Batch data processing method and device suitable for database, equipment and medium

Abstract

The invention discloses a batch data processing method and device suitable for a database, equipment and a medium, relates to the technical field of data processing, and is applied to a processor. Monitoring whether a target instruction meeting a preset stride condition exists in a data processing instruction stream corresponding to the preset database in the target assembly line or not, if yes, entering an instruction pre-execution mode, vectorizing the target instruction and a subsequent instruction having a dependency relationship with a register of the target instruction, and outputting the vectorized instruction; performing instruction pre-execution based on the vectorized instruction and a first execution unit, and storing an instruction pre-execution result to a first physical register file and a result cache region; and when the data processing instruction stream in the target assembly line reaches the input end of the second execution unit, matching the instruction pre-execution result in the result cache region, and completing batch data processing operation based on an information matching result. According to the invention, the efficiency and accuracy of batch data processing are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a batch data processing method and device suitable for a database, equipment and a medium. BACKGROUND

[0002] In the traditional batch data processing scheme, instructions are usually executed in sequence, which cannot fully utilize the parallel computing capability of modern processors.

[0003] Although vectorization technology has been applied to batch data processing, in the existing related schemes: (1) hardware acceleration-based vectorization scheme: data is processed by hardware parallel computing capability, but this scheme has the problem of insufficient instruction scheduling flexibility when processing complex data dependency computing tasks; (2) software optimization-based vectorization scheme: scalar code is automatically converted to vector code by compiler optimization, but it cannot fully exploit all parallel opportunities in the code, and if there is a circular dependency, the compiler may not be able to correctly vectorize the code, or complex dependency analysis is required, which increases the complexity and error probability of the compiler.

[0004] It can be seen that how to solve the problems existing in the related prior art and improve the efficiency and accuracy of batch data processing is a problem to be solved by those skilled in the art. SUMMARY

[0005] The embodiments of the present application provide a batch data processing method and device suitable for a database, equipment and a medium, which can solve the problems existing in the related prior art and improve the efficiency and accuracy of batch data processing. The specific scheme is as follows: In the first aspect, the present application provides a batch data processing method suitable for a database, applied to a processor, comprising: After starting the batch data processing corresponding to the preset database, based on the preset detector, whether there is a target instruction meeting the preset step condition in the data processing instruction stream corresponding to the preset database in the target pipeline is monitored to obtain a step detection result; wherein the preset step condition is that it belongs to the same program counter, repeatedly appears and the memory access step changes regularly; If the step detection result indicates that there is, enter the instruction pre-execution mode, and based on the vectorization execution engine, the target instruction and the subsequent instruction in the data processing instruction stream which has a dependency relationship with the register of the target instruction are processed to determine the vectorized instruction; Based on the vectorized instruction, the first launch queue and the first execution unit, the instruction pre-execution is performed, and the preset result storage strategy is used to save the corresponding instruction pre-execution result to the first physical register stack and the result cache area; When the data processing instruction flow in the target pipeline reaches the input end of the second execution unit, the instruction pre-execution result in the result cache area is matched based on instruction information corresponding to the data processing instruction flow to determine an information matching result; the instruction information includes program counter information, source operands and destination operands; Based on the information matching result, the data processing instruction flow and the second execution unit, a batch data processing operation corresponding to the preset database is completed.

[0006] Optionally, based on the preset detector, it is monitored whether there is a target instruction meeting a preset stride condition in the data processing instruction flow corresponding to the preset database in the target pipeline to obtain a stride detection result, including: Based on the preset detector and the stride information corresponding to each data processing instruction in the data processing instruction flow, change monitoring of the stride is performed to determine a monitoring result; the stride information includes instruction addresses in the program counter, stride values and stride confidence degrees; Based on the preset detector and the monitoring result, it is judged whether there is a target instruction meeting a preset stride condition in the data processing instruction flow to obtain a stride detection result.

[0007] Optionally, based on the vectorization execution engine, the target instruction and a subsequent instruction in the data processing instruction flow having a register dependency relationship with the target instruction are subjected to vectorization processing to determine a vectorized instruction, including: In the instruction pre-execution mode, the target instruction is subjected to vectorization processing based on the vectorization execution engine and the corresponding stride value to determine a first vectorized instruction; Based on the vectorization execution engine and the corresponding stride value, a data processing instruction in the data processing instruction flow having a register dependency relationship with the target instruction and having an execution sequence after the target instruction is subjected to vectorization processing to determine a second vectorized instruction.

[0008] Optionally, based on the vectorized instruction, the first emission queue and the first execution unit, instruction pre-execution is performed, including: The vectorized instruction is subjected to renaming to determine a renamed instruction; Based on the first renaming table and the first physical register stack, the renamed instruction is subjected to register reassignment to determine a register reassignment result; The renamed instruction is stored to the first emission queue; Based on the first emission queue, it is checked whether the renamed instruction meets a preset instruction execution condition to determine a checking result; If the checking result shows that it is met, the renamed instruction is sent to the first execution unit based on the first emission queue; Based on the first execution unit, the renamed instruction and the register reassignment result, instruction pre-execution is performed to determine an instruction pre-execution result corresponding to the renamed instruction.

[0009] Optionally, the instruction pre-execution result is saved to the first physical register file and the result cache area according to a preset result storage strategy, including: For any renamed instruction, the instruction pre-execution result corresponding to the current renamed instruction is saved to the first physical register file. The operation type of the current renamed instruction is determined to be a preset operation type to determine a type determination result; the preset operation type includes floating point operation, multiplication operation and division operation. If the type determination result indicates that it belongs to, the instruction pre-execution result corresponding to the current renamed instruction is saved to the result cache area.

[0010] Optionally, the instruction pre-execution result in the result cache area is matched based on the instruction information corresponding to the data processing instruction stream to determine an information matching result, including: For any data processing instruction corresponding to the preset database in the target pipeline, the instruction information corresponding to the current data processing instruction is obtained. The instruction pre-execution result in the result cache area is matched based on the program counter information, the source operand, the destination operand and the operation type corresponding to the current data processing instruction to determine the information matching result.

[0011] Optionally, the batch data processing operation corresponding to the preset database is completed based on the information matching result, the data processing instruction stream and the second execution unit, including: If the information matching result indicates that there is a vectorized instruction identical to the current data processing instruction information in the result cache area, the instruction pre-execution result corresponding to the vectorized instruction is bypassed to the output end of the second execution unit. If the information matching result indicates that there is no vectorized instruction identical to the current data processing instruction information in the result cache area, the current data processing instruction is executed based on the second execution unit.

[0012] In a second aspect, the present application provides a batch data processing device suitable for a database, applied to a processor, including: The stride detection module is configured to monitor whether there is a target instruction meeting a preset stride condition in the data processing instruction stream corresponding to the preset database in the target pipeline based on a preset detector after starting the batch data processing corresponding to the preset database to obtain a stride detection result; wherein the preset stride condition is that the target instruction belongs to the same program counter, repeatedly appears and the memory access stride changes regularly. The instruction vectorization module is configured to enter an instruction pre-execution mode if the stride detection result indicates that there is, and perform vectorization processing on the target instruction and a subsequent instruction in the data processing instruction stream that has a register dependency with the target instruction based on a vectorization execution engine, to determine a vectorized instruction. The instruction pre-execution module is configured to perform instruction pre-execution based on the vectorized instruction, the first launch queue, and the first execution unit, and save corresponding instruction pre-execution results to the first physical register file and the result cache area using a preset result storage strategy. The result cache matching module is configured to, when the data processing instruction stream in the target pipeline reaches an input end of the second execution unit, match the instruction pre-execution results in the result cache area based on instruction information corresponding to the data processing instruction stream, to determine an information matching result. The instruction information includes program counter information, a source operand, and a destination operand. The processing operation completion module is configured to complete a batch data processing operation corresponding to the preset database based on the information matching result, the data processing instruction stream, and the second execution unit.

[0013] In a third aspect, the present application provides an electronic device, comprising: A memory configured to save a computer program. A processor configured to execute the computer program to implement the steps of the batch data processing method for a database.

[0014] In a fourth aspect, the present application provides a computer readable storage medium configured to save a computer program, which, when executed by a processor, implements the steps of the batch data processing method for a database.

[0015] It can be seen that, in the present application, the processor is applied to, after starting the batch data processing corresponding to the preset database, based on the preset detector, whether there is a target instruction in the data processing instruction stream corresponding to the preset database in the target pipeline that meets the preset stride condition, to obtain a stride detection result; wherein the preset stride condition is that it belongs to the same program counter, repeatedly appears and the memory access stride changes regularly; if the stride detection result indicates that there is, enter the instruction pre-execution mode, and based on the vector execution engine, the target instruction and the subsequent instruction in the data processing instruction stream that has a dependency relationship with the register of the target instruction are subjected to vector processing to determine the post-vector instruction; based on the post-vector instruction, the first launch queue and the first execution unit, the instruction pre-execution is carried out, and the preset result storage strategy is used to save the corresponding instruction pre-execution result to the first physical register stack and the result cache area; when the data processing instruction stream in the target pipeline reaches the input end of the second execution unit, based on the instruction information corresponding to the data processing instruction stream, the instruction pre-execution result in the result cache area is matched to determine the information matching result; the instruction information includes the program counter information, the source operand and the destination operand; based on the information matching result, the data processing instruction stream and the second execution unit, the batch data processing operation corresponding to the preset database is completed.

[0016] From the above technical solution, it can be seen that, in the present application, the processor is applied to, first, after starting the batch data processing corresponding to the preset database, based on the preset detector, whether there is a target instruction in the data processing instruction stream corresponding to the preset database that belongs to the same program counter, repeatedly appears and the memory access stride changes regularly, to obtain a stride detection result; then, if the stride detection result indicates that there is, enter the instruction pre-execution mode, based on the vector execution engine, the target instruction and the subsequent instruction in the instruction stream that has a dependency relationship with the register of the target instruction are subjected to vector processing; then, based on the corresponding post-vector instruction, the first launch queue and the first execution unit, the instruction pre-execution result is determined and saved to the first physical register stack and the result cache area; then, when the data processing instruction stream in the target pipeline reaches the input end of the second execution unit, based on the instruction information corresponding to the data processing instruction stream, the instruction pre-execution result in the result cache area is matched, and the corresponding information matching result and the second execution unit are used to complete the batch data processing operation corresponding to the preset database. In this way, the problems existing in the related solutions can be solved, thereby improving the efficiency and accuracy of batch data processing, improving the parallelism of instruction execution, improving the cache hit rate during target pipeline execution and reducing repeated calculation. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following embodiments are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0018] Figure 1 A batch data processing system framework suitable for a database provided by the present application; Figure 2 A specific batch data processing flow framework diagram suitable for a database provided by the present application; Figure 3 A preset detector design diagram provided by the present application; Figure 4 An instruction vectorization implementation diagram provided by the present application; Figure 5 An instruction pre-execution result storage diagram provided by the present application; Figure 6 A batch data processing device structure diagram suitable for a database provided by the present application; Figure 7 An electronic device structure diagram provided by the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.

[0020] The terms "include" and "have" and any variations in the specification and above drawings of the present application, and any variations related to "include" and "have", are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can include steps or units not listed.

[0021] In order to make the person skilled in the art better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0022] In a traditional batch data processing scheme, instructions are usually executed in sequence, which cannot fully utilize the parallel computing capability of modern processors. Although vectorization technology has been applied to the processing of batch data, in existing related schemes: (1) hardware acceleration-based vectorization scheme: data is processed by hardware parallel computing capability, but this scheme has the problem of insufficient instruction scheduling flexibility when processing complex data dependency computing tasks; (2) software optimization-based vectorization scheme: scalar code is automatically converted to vector code by compiler optimization, but it cannot fully exploit all parallel opportunities in the code, and if there is a circular dependency, the compiler may not be able to correctly vectorize the code, or complex dependency analysis is required, which increases the complexity and error probability of the compiler.

[0023] Therefore, the present application provides a batch data processing scheme suitable for a database, which can solve the problems existing in the related art, thereby improving the efficiency and accuracy of batch data processing, improving the parallelism of instruction execution, and improving the cache hit rate during target pipeline execution and reducing repeated computation.

[0024] Referring to Figure 1 The embodiment of the present application discloses a batch data processing method suitable for a database, applied to a processor, comprising: Step S11, after starting the batch data processing corresponding to the preset database, based on the preset detector, monitoring whether there is a target instruction in the data processing instruction stream corresponding to the preset database in the target pipeline that meets the preset stride condition to obtain a stride detection result; wherein the preset stride condition is that it belongs to the same program counter, repeatedly appears and the memory access stride changes regularly.

[0025] In this embodiment, after starting the batch data processing corresponding to the preset database by using the flow framework as shown in Figure 2 In the data processing process, the stride in the decoded data processing instruction stream is monitored in real time to determine whether it needs to enter the instruction pre-execution mode, specifically: based on the preset detector and the stride information corresponding to each data processing instruction in the data processing instruction stream, the change of the stride is monitored to determine the monitoring result; the stride information includes the instruction address in the program counter, the stride value and the stride confidence; based on the preset detector and the monitoring result, it is judged whether there is a target instruction in the data processing instruction stream that meets the preset stride condition to obtain a stride detection result. It can be understood that, in this embodiment, the preset detector (i.e. Figure 2The stride detector (Stride Detector) in the processor detects in real time whether the stride satisfies a specific condition (i.e., a preset stride condition), which can be set or adjusted according to specific data processing requirements and processor performance, for example, the stride reaches a certain value or the change rule of the stride conforms to a certain mode.

[0026] It should be understood that, regarding the design of the stride detector, in combination with Figure 3 shown in the figure, in the embodiment, after the decoding operation of the instruction is completed at the front end of the processor, the stride detector is added to detect in real time whether there is a stride with access regularity under the same instruction PC in the instruction stream, and if so, the instruction is converted into a vector instruction and a corresponding vector logical register is allocated. The specific implementation of the detector is as follows: The stride detector contains 32 entries (i.e., a maximum of 32 different instruction access strides) in total, each entry contains instruction PC (Program Counter), stride, and conf (confidence) in total 4 items, wherein the instruction PC represents the PC address of the instruction; , stride, and conf (confidence) in total 4 items, wherein the instruction PC represents the PC address of the instruction; The memory address accessed last time when the instruction with the PC address is executed; stride is the difference between the instruction with the PC address this time and the memory address accessed last time; conf represents the confidence of the stride, that is, the value of conf is increased by 1 when the current calculated stride is the same as the stored stride. When conf reaches the set threshold, it is considered that the vectorization condition is reached, and the instruction needs to be vectorized.

[0027] The following for loop program segment is taken as an example, in which the value of i is stored in the a array, and the value in the a array is added to the value in the P array and stored in the b array, wherein the P array is a known array. The program segment is as follows: .

[0028] The pseudo-instruction stream converted from the above program segment is shown below, the loop starts at , and the loop ends at .

[0029] MOV R1, 0; initialize i to 0; MOV R2, 0; initialize the address of a; MOV R3, P; initialize the address of P; MOV R4, N; transfer the value of N to R4; : CMP R1, R4 ; compare i and N JGE ; if i >= N, jump to ; MOV [R2], R1 ; store value of i into a[i] MOV R5, [R2] ; load value of a[i] into R5 MOV R6, [R3] ; load value of P[i] into R6 ADD R7, R5, R6 ; compute sum of a[i] + P[i] and store into R7 MOV [R2+ ], R7 ; store result into b[i] (assuming size of each element of P array) INC R1 ; increment i ADD R2, 1 ; add 1 to current address of a, assuming 1 byte per element ADD R3, ; add 1 to current address of P ; ADD R2, ; add 1 to current address of b (because a and b are separate) JMP loop_start ; jump back to ; ; During the execution of the instructions, the step detector detects the step change in real time, for example, the third instruction MOV [R2], R1 in , where the variable R1 stores the value of i, and the variable R2 is the first address of the a array, and the value of i is stored into the a array, and the step detector tracks that the value of R1 changes according to the rule of constantly adding 1, and thus is identified as a regular step change. And the instruction is vectorized to obtain MOV [V2], V1, where V1 and V2 are vector registers. Similarly, for the fifth instruction MOV R6, [R3] in , the address of the variable R3 also presents a step change rule, and thus the instruction also needs to be vectorized.

[0030] In this way, for the common for loop, while loop and other operations in the program, the step detector can find that the instructions of the same PC repeatedly appear and the access address presents a step rule, and then enters the instruction pre-execution mode for subsequent processing.

[0031] Step S12, if the step detection result indicates that there is, enter the instruction pre-execution mode, and based on the vector execution engine, perform vectorization on the target instruction and the subsequent instruction in the data processing instruction stream which has a register dependency with the target instruction, to determine the vectorized instruction.

[0032] In this embodiment, when the step satisfies the specific condition, the instruction pre-execution mode is entered, and the vectorizer in the vector execution engine, i.e. Figure 2 , is used to perform instruction vectorization, to convert the originally sequentially executed scalar instruction into a vector instruction capable of processing multiple data elements at the same time, so as to fully utilize the vector processing unit of the processor and improve the parallelism of data processing. Specifically, in the instruction pre-execution mode, based on the vector execution engine and the corresponding step value, the target instruction is vectorized to determine the first vectorized instruction; and based on the vector execution engine and the corresponding step value, the data processing instruction in the data processing instruction stream which has a register dependency with the target instruction and whose execution order is after the target instruction is vectorized to determine the second vectorized instruction.

[0033] It should be understood that, as to the implementation of the vectorizer, in this embodiment, the role of the vectorizer is to vectorize the instruction with the regularly changing step detected by the step detector, and also vectorize the subsequent instruction which has a register dependency with the instruction, so as to realize vectorization execution of a large number of subsequent instructions in a for loop or the like. In combination with Figure 4 , the specific implementation of the instruction vectorization process is as follows: Taking the for loop program segment listed in the foregoing steps as an example, first, the instruction with the regularly changing step is vectorized. For example, in the above program segment, the third instruction MOV [R2], R1 can be vectorized, and the value of R1 changes regularly by one, so the instruction is converted into the corresponding vectorized instruction VMOV [V2], V1, and the corresponding vector registers V1 and V2 are allocated, wherein V1 corresponds to the value of R1 as the source register, and V1 can be expressed as V1={R1+1, R1+2, R1+3, R1+4}. Similarly, the MOV R6, [R3] instruction in the above program segment can also be vectorized, and the obtained vectorized instruction is VMOV [V6], V3, wherein V3={R3+1, R3+2, R3+3, R3+4}. is the array P address change step.

[0034] ​​​​Secondly, the subsequent instruction which has a dependency relationship with the register of the target instruction is also vectorized to ensure that the subsequent instruction in the loop program can continue to be executed in a vectorized manner. As in the above program segment, the third instruction MOV R5, [R2] can also be vectorized because the MOV [R2], R1 instruction has been vectorized to VMOV [V2], V1, and the value of the vector register V2 can be obtained after the execution of VMOV [V2], V1. Therefore, the vectorized instruction VMOV V5, [V2] can be executed. Similarly, the addition instruction ADD R7, R5, R6 in the loop program segment can still be continued to be vectorized, and the vectorized instruction is VADD V7, V5, V6. Since the values of the registers V5 and V6 have been completed by the foregoing vector instruction, VADD V7, V5, V6 can be executed.

[0035] In this way, not only the target instruction is vectorized, but also the instruction output by the register of the target instruction is vectorized, thereby expanding the range of vectorization and ensuring that the instructions related to the register can be executed in a vector manner, thereby improving the overall execution efficiency.

[0036] In step S13, the instruction pre-execution is performed based on the vectorized instruction, the first launch queue, and the first execution unit, and the corresponding instruction pre-execution result is saved to the first physical register file and the result cache area by using the preset result storage strategy.

[0037] In the embodiment, after the instruction vectorization is completed and the vectorized instruction is obtained, the obtained vectorized instruction is executed, but before the execution, the renaming and the vector register re-allocation are also needed. Specifically, the vectorized instruction is renamed to determine a renamed instruction; the register of the renamed instruction is re-allocated based on the first renaming table and the first physical register file to determine a register re-allocation result; the renamed instruction is stored to the first launch queue; whether the renamed instruction meets a preset instruction execution condition is checked based on the first launch queue to determine a checking result; if the checking result indicates that the condition is met, the renamed instruction is sent to the first execution unit based on the first launch queue; and the instruction pre-execution is performed based on the first execution unit, the renamed instruction, and the register re-allocation result to determine an instruction pre-execution result corresponding to the renamed instruction. That is, in the embodiment, first, the vectorized instruction is subjected to a vector renaming operation, and then the vector register is re-allocated to avoid the register conflict, optimize the order of instruction execution and resource allocation, and improve the execution efficiency of the processor. Finally, the vector calculation is executed: after the foregoing preparation work is completed, the vector calculation operation is executed. The vectorized data is calculated by using the vector operation unit of the processor to quickly process a large amount of data.

[0038] As we can understand, the issue queue is a buffer in the CPU (Central Processing Unit) used to temporarily store instructions awaiting execution. When an instruction is fetched from the instruction cache and undergoes certain preprocessing, it is placed in the issue queue. The issue queue checks the instruction to determine if it meets the execution conditions, such as whether the required operands are ready. When the execution conditions are met, the instruction is issued from the issue queue to the corresponding execution unit for processing. The rename table (also known as the register rename table, RAT) is used to handle dependencies between instructions. When the processor executes instructions, to avoid conflicts such as register conflicts, it uses the rename table to map the logical registers used in the instructions to physical registers. In this way, the processor can adjust the execution order of instructions without changing the instruction semantics, improving the parallelism of instruction execution. The execution unit (EXU) is the functional module in the processor responsible for executing specific instruction operations.

[0039] It is important to understand that after vectorization, the normal pipeline, i.e. the target pipeline, continues to issue and execute instructions normally. After vectorization, the instructions are issued to the vector execution unit (represented by VEXU, i.e. the first execution unit) through a separate renaming table (represented by VRAT, also known as the first renaming table) and a separate issue queue (represented by Vector IQ, also known as the first issue queue) to complete the operation.

[0040] Furthermore, after obtaining the computation result (i.e., the instruction pre-execution result), since the vectorized instruction is pre-executed, the complete correctness of the result cannot be guaranteed. Therefore, the computation result is saved to a separate physical register file (i.e., the pre-execution physical register file, or Pre-execution PRF (Physical Register File)), instead of being written back to the general physical register file, and certainly not to the cache. Specifically: for any renamed instruction, the instruction pre-execution result corresponding to the current renamed instruction is saved to the first physical register file; it is determined whether the operation type of the current renamed instruction belongs to a preset operation type to determine the type judgment result; the preset operation types include floating-point operations, multiplication operations, and division operations; if the type judgment result indicates that it belongs to the preset operation type, the instruction pre-execution result corresponding to the current renamed instruction is saved to the result cache. In this way, it is prevented that the pre-executed instruction may have speculative errors that affect the normal result.

[0041] As to the processing of the pre-execution result of the instruction, the part includes a pre-execution physical register file and a result cache area. Since the instruction is pre-executed, the result cannot be guaranteed to be completely correct, and thus the operation result is saved to the separate pre-execution register file instead of being written back to the normal register file, and even less to the cache. However, the pre-execution can read the data required by the operation from the memory to the cache, thereby improving the cache hit rate. In addition, in the implementation, the result of the pre-executed complex operation is saved to the separate result cache. When it is found that the pre-executed instruction is completely correct, the result can be directly read out, thereby avoiding repeated calculation.

[0042] In combination with Figure 5 As shown in the figure, first, when the pre-executed vectorized instruction completes the operation, the operation result is saved to the separate pre-execution physical register file. At the same time, the operation type of the instruction is judged. If the instruction type is a complex calculation instruction such as floating point operation, multiplication and division, the calculation result is saved to the result cache area. The result cache area includes 8 entries, each of which stores the operation result of a complex vector instruction. Assuming that the vector instruction is the vectorization of 4 normal executions, the PC value common to the 4 instructions, the source operand and the operation result of each instruction, and a V bit are saved in each entry. When the result is used, the V bit is 0, and a new pre-execution result can be written to the entry.

[0043] In this way, the result stored in the pre-execution register file can be used by the subsequent pre-execution instruction. In the process of execution, part of the operation result is stored to the result cache. When the normally executed instruction reaches the input end of the execution unit, the cache is checked. If the source operand, the destination operand and the operation instruction are all the same, the calculation result is directly bypassed to the output end of the execution unit, thereby avoiding repeated operation. In the result cache, only the result of the complex instruction such as multiplication, division and floating point operation is stored. Such operation often needs many cycles to complete. The result of other simple operation (such as addition and subtraction) is not stored, thereby reducing the space occupation of data storage.

[0044] In step S14, when the data processing instruction flow in the target pipeline reaches the input end of the second execution unit, the pre-execution result of the instruction in the result cache area is matched based on the instruction information corresponding to the data processing instruction flow, to determine the information matching result. The instruction information includes program counter information, source operand and destination operand.

[0045] In the embodiment, in combination with Figure 2As shown, when the instructions in the normal pipeline get the values of the source operands and the destination operands, the PC is checked in the result cache area to match the corresponding operation result. Specifically, for any data processing instruction in the target pipeline corresponding to the preset database, the instruction information corresponding to the current data processing instruction is obtained; based on the program counter information, the source operand, the destination operand, and the operation type corresponding to the current data processing instruction, the instruction pre-execution result in the result cache area is subjected to instruction matching to determine the information matching result.

[0046] In step S15, based on the information matching result, the data processing instruction stream, and the second execution unit, the batch data processing operation corresponding to the preset database is completed.

[0047] In this embodiment, it can be understood that when the operation type, the source operand, and the destination operand of the instruction are completely consistent, the operation result in the result cache area is bypassed to the output end of the second execution unit (denoted as EXU), that is, if the information matching result indicates that there is the same vectorized instruction as the current data processing instruction information in the result cache area, the corresponding instruction pre-execution result is bypassed to the output end of the second execution unit; if the information matching result indicates that there is no same vectorized instruction as the current data processing instruction information in the result cache area, the current data processing instruction is executed based on the second execution unit.

[0048] In this way, time-consuming complex calculations are avoided, and the execution efficiency is improved.

[0049] In summary, the scheme provided in this embodiment has the following beneficial effects: (1) Dynamic stride detection mechanism: the stride detector is used to monitor whether the decoded instructions have a regular change in stride in real time, to identify the instructions of the loop program, and to provide a basis for vectorization processing.

[0050] (2) Vectorization processing: the stride detected by the stride detector is used to vectorize the normal instructions, allocate vector registers to them, and vectorize the instructions having a dependency relationship with the instructions, to improve the vectorization degree. In this way, the instructions of the loop program are vectorized and pre-executed, and the parallel degree of instruction execution is improved.

[0051] (3) By executing the vectorized instructions in advance, the required data is read into the cache in advance, and the cache hit rate during normal pipeline execution is improved.

[0052] (4) Pre-execution operation result saving: the execution result is saved in a separate pre-execution physical register stack, to provide data for the execution of subsequent vectorized instructions.

[0053] (5), the result buffer area is used to save the operation result of the pre-executed part of the complex instruction, so that the result is directly read when the normal pipeline instruction is executed, and repeated calculation is avoided.

[0054] It can be seen that, in the embodiment of the application, firstly, after starting the batch data processing corresponding to the preset database, whether there is a target instruction belonging to the same program counter and repeatedly appearing and having a regular change in memory access stride in the data processing instruction stream corresponding to the preset database is monitored based on a preset detector to obtain a stride detection result; then, if the stride detection result indicates that there is, an instruction pre-execution mode is entered, and the target instruction and a subsequent instruction in the instruction stream having a register dependency relationship with the target instruction are processed based on a vectorization execution engine; then, an instruction pre-execution result is determined based on the corresponding vectorized instruction, the first launch queue and the first execution unit, and the instruction pre-execution result is saved to the first physical register file and the result buffer area; then, when the data processing instruction stream in the target pipeline reaches the input end of the second execution unit, the instruction pre-execution result in the result buffer area is matched based on the instruction information corresponding to the data processing instruction stream, and the second execution unit is used to complete the batch data processing operation corresponding to the preset database according to the corresponding information matching result. In this way, the problems in the prior art can be solved, the efficiency and accuracy of batch data processing are improved, the parallelism of instruction execution is improved, the cache hit rate during execution of the target pipeline is improved, and repeated calculation is reduced.

[0055] As a preferred embodiment, since the overhead of frequently entering / leaving the instruction pre-execution mode may offset the vectorization benefit, an adaptive pre-execution control mechanism is further added in the embodiment, by which, when it is detected by the stride detector that the target instruction needs to enter the instruction pre-execution mode, a predictor is used to estimate the performance benefit and the overhead of this time of pre-execution, then, the estimated benefit and the overhead are compared with corresponding thresholds, and according to the comparison result of the thresholds and the current processor state, it is autonomously decided whether to enter the pre-execution and the strength of the pre-execution of the instruction, and after it is decided to enter the pre-execution mode, the pre-execution is monitored to actively exit when the benefit is insufficient, so that the overall performance is maximized.

[0056] Referring to Figure 6 The embodiment of the application also discloses a batch data processing device suitable for a database and applied to a processor, comprising: The step detection module 11 is configured to, after starting the batch data processing corresponding to the preset database, monitor whether there is a target instruction meeting a preset step condition in a data processing instruction stream corresponding to the preset database in the target pipeline based on a preset detector to obtain a step detection result, wherein the preset step condition is that the target instruction belongs to the same program counter and repeatedly appears and a memory access step is regularly changed. The instruction vectorization module 12 is configured to, if the step detection result indicates that there is the target instruction, enter an instruction pre-execution mode, and perform vectorization processing on the target instruction and a subsequent instruction in the data processing instruction stream that has a register dependency relationship with the target instruction based on a vectorization execution engine to determine a post-vectorization instruction. The instruction pre-execution module 13 is configured to perform instruction pre-execution based on the post-vectorization instruction, the first launch queue and the first execution unit, and save a corresponding instruction pre-execution result to the first physical register file and the result cache area by using a preset result storage strategy. The result cache matching module 14 is configured to, when the data processing instruction stream in the target pipeline reaches an input end of the second execution unit, match the instruction pre-execution result in the result cache area based on instruction information corresponding to the data processing instruction stream to determine an information matching result, wherein the instruction information includes program counter information, a source operand and a destination operand. The processing operation completion module 15 is configured to complete a preset database corresponding batch data processing operation based on the information matching result, the data processing instruction stream and the second execution unit.

[0057] The more specific working processes of the above modules can be referred to the corresponding contents disclosed in the foregoing embodiments, and will not be described here.

[0058] Further, the embodiment of the present application further discloses an electronic device, Figure 7 The electronic device shown in FIG. 1 is not considered as any limitation on the use range of the present application. The electronic device can specifically include at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26. The memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to realize the related steps in the batch data processing method for database disclosed in any of the foregoing embodiments. In addition, the electronic device in the embodiment can be an electronic computer.

[0059] In this embodiment, the power supply 23 is configured to provide operating voltage for each hardware device on the electronic device; the communication interface 24 is configured to create a data transmission channel between the electronic device and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which will not be specifically limited herein; the input / output interface 25 is configured to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which will not be specifically limited herein.

[0060] In addition, the memory 22 as a carrier for storing resources can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0061] The operating system 221 is configured to manage and control each hardware device on the electronic device and the computer program 222, and can be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program applicable to the database batch data processing method executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 can further include a computer program capable of completing other specific work.

[0062] Further, the present application further discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by the processor to realize the foregoing disclosed database batch data processing method. For the specific steps of the method, reference can be made to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

[0063] Further, the present application further discloses a computer program product comprising computer programs / instructions; wherein the computer programs / instructions are executed by the processor to realize the foregoing disclosed database batch data processing method. For the specific steps of the method, reference can be made to the corresponding contents disclosed in the foregoing embodiments, which will not be repeated here.

[0064] In the present specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts between each embodiment can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the method part.

[0065] Those skilled in the art will further appreciate that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various examples have been described herein in terms of their functionality, which has been described generally and symbolically in flow charts. Having thus described the functionality of the examples, a person of ordinary skill in the art will be able to implement such functions in hardware and / or software, using the means and methods available to those skilled in the art. The examples described herein are not meant to limit the scope of the application, but merely to provide examples of the methods and systems being described.

[0066] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0067] Finally, it should be noted that the terms "first", "second", and the like, herein do not denote any order, quantity, combination, or importance, but rather are used to distinguish one element from another, and are not necessarily intended to denote the order, quantity, combination, or importance of such elements. Also, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0068] The above has introduced the technical solutions provided by the present application in detail, and the principles and implementation manners of the present application have been described by applying specific examples. The above description of the examples is only applicable to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and application range will have changes, and in summary, the content of the specification should not be understood as limiting the present application.

Claims

1. A batch data processing method suitable for databases, characterized in that, Applied to processors, including: After starting the batch data processing corresponding to the preset database, based on the preset detector, monitor whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset step size conditions, so as to obtain the step size detection result; wherein, the preset step size conditions are that they belong to the same program counter, appear repeatedly, and the memory access step size changes regularly. If the stride detection result indicates that the target instruction exists, the system enters the instruction pre-execution mode and, based on the vectorized execution engine, performs vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction, in order to determine the vectorized instruction. Based on the vectorized instructions, the first launch queue, and the first execution unit, instruction pre-execution is performed, and the corresponding instruction pre-execution results are saved to the first physical register file and the result cache using a preset result storage strategy. When the data processing instruction stream in the target pipeline reaches the input of the second execution unit, the pre-execution result of the instruction in the result buffer is matched based on the instruction information corresponding to the data processing instruction stream to determine the information matching result; the instruction information includes program counter information, source operands, and destination operands; Based on the information matching results, the data processing instruction stream, and the second execution unit, the batch data processing operation corresponding to the preset database is completed.

2. The batch data processing method for databases according to claim 1, characterized in that, The step of monitoring whether there are target instructions that meet preset stride conditions in the data processing instruction stream corresponding to the preset database in the target pipeline based on a preset detector, in order to obtain stride detection results, includes: Based on the stride information corresponding to each data processing instruction in the preset detector and the data processing instruction stream, stride changes are monitored to determine the monitoring results; the stride information includes the instruction address, stride value, and stride confidence level in the program counter. Based on the preset detector and the monitoring results, it is determined whether there is a target instruction in the data processing instruction stream that meets the preset stride conditions, so as to obtain the stride detection result.

3. The batch data processing method for databases according to claim 2, characterized in that, The vectorized execution engine performs vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have register dependencies on the target instruction, in order to determine the vectorized instruction, including: In instruction pre-execution mode, the target instruction is vectorized based on the vectorized execution engine and the corresponding step value to determine the first vectorized instruction; Based on the vectorized execution engine and the corresponding step value, the data processing instructions in the data processing instruction stream that have a register dependency relationship with the target instruction and whose execution order is after the target instruction are vectorized to determine the second vectorized instruction.

4. The batch data processing method for databases according to claim 1, characterized in that, The instruction pre-execution based on the vectorized instructions, the first launch queue, and the first execution unit includes: The vectorized instructions are renamed to determine the renamed instructions; Based on the first renaming table and the first physical register file, the renamed instructions are reassigned to determine the register reassignment result. The renamed instruction is stored in the first launch queue; Based on the first transmission queue, check whether the renamed instruction meets the preset instruction execution conditions to determine the check result; If the check result is satisfactory, then the renamed instruction is sent to the first execution unit based on the first transmission queue; Based on the first execution unit, the renamed instruction, and the register reallocation result, instruction pre-execution is performed to determine the instruction pre-execution result corresponding to the renamed instruction.

5. The batch data processing method for databases according to claim 4, characterized in that, The step of using a preset result storage strategy to save the corresponding instruction pre-execution results to the first physical register file and the result cache includes: For any of the renamed instructions, the instruction pre-execution result corresponding to the current renamed instruction is saved to the first physical register file; Determine whether the operation type of the currently renamed instruction belongs to a preset operation type to determine the type determination result; the preset operation types include floating-point operations, multiplication operations, and division operations; If the type determination result indicates that it belongs to the category, then the pre-execution result of the instruction corresponding to the currently renamed instruction is saved to the result cache area.

6. The batch data processing method for databases according to any one of claims 1 to 5, characterized in that, The step of matching the instruction pre-execution results in the result cache with the instruction information corresponding to the data processing instruction stream to determine the information matching result includes: For any data processing instruction in the target pipeline that corresponds to the preset database, obtain the instruction information corresponding to the current data processing instruction; Based on the program counter information, source operands, destination operands, and operation type corresponding to the current data processing instruction, the instruction pre-execution result in the result buffer is matched to determine the information matching result.

7. The batch data processing method for databases according to claim 6, characterized in that, The step of completing the batch data processing operation corresponding to the preset database based on the information matching result, the data processing instruction stream, and the second execution unit includes: If the information matching result indicates that there is a vectorized instruction in the result cache that is identical to the current data processing instruction information, then the corresponding instruction pre-execution result is bypassed to the output of the second execution unit; If the information matching result indicates that there is no vectorized instruction in the result cache that is identical to the current data processing instruction information, then the current data processing instruction is executed based on the second execution unit.

8. A batch data processing device suitable for databases, characterized in that, Applied to processors, including: The stride detection module is used to monitor, based on a preset detector, whether there are target instructions in the data processing instruction stream corresponding to the preset database in the target pipeline that meet the preset stride conditions after the batch data processing corresponding to the preset database is started, so as to obtain the stride detection result; wherein, the preset stride conditions are that they belong to the same program counter, appear repeatedly, and the memory access stride changes regularly. The instruction vectorization module is used to enter the instruction pre-execution mode if the stride detection result indicates that the target instruction exists, and to perform vectorization processing on the target instruction and subsequent instructions in the data processing instruction stream that have a dependency relationship with the register of the target instruction based on the vectorization execution engine, so as to determine the vectorized instruction. The instruction pre-execution module is used to perform instruction pre-execution based on the vectorized instruction, the first issue queue and the first execution unit, and to save the corresponding instruction pre-execution results to the first physical register file and the result cache area using a preset result storage strategy. The result cache matching module is used to match the pre-execution results of the instructions in the result cache area based on the instruction information corresponding to the data processing instruction stream in the target pipeline when the data processing instruction stream arrives at the input of the second execution unit, so as to determine the information matching result; the instruction information includes program counter information, source operands and destination operands; The processing operation completion module is used to complete the batch data processing operation corresponding to the preset database based on the information matching result, the data processing instruction stream, and the second execution unit.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the batch data processing method for a database as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the batch data processing method for a database as described in any one of claims 1 to 7.

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