A satellite-borne optical switching system, method and related device based on superframe time slot mechanism

Abstract

This invention discloses a spaceborne optical switching system, method, and related apparatus based on a superframe time slot mechanism. The system includes several spaceborne nodes interconnected via inter-satellite laser links. Each spaceborne node comprises a master control node and slave nodes. The master control node maintains a global time reference, periodically collects service status information from each slave node, performs time slot and resource allocation calculations, and sends the optical switching configuration results to the execution layer. The slave nodes perform local service access, status acquisition and reporting, time synchronization locking, and transmit optical pulses or optical data signals according to a unified time system within their allocated time slots. This system, method, and related apparatus can overcome the bottlenecks in rate, power consumption, and latency caused by traditional electrical switching and software control methods, improving the speed, parallelism, and stability of the optical switching control process, thereby increasing the resource utilization of inter-satellite optical links and the overall throughput of the system.

Description

Technical Field

[0001] This invention belongs to the field of information interaction technology and relates to a spaceborne optical switching system, method and related devices based on superframe time slot mechanism. Background Technology

[0002] In terrestrial data centers and high-performance computing networks, optical switching nodes are typically combined with hierarchical network architectures and centralized control mechanisms. Network topology changes are relatively controllable, switching reconfiguration cycles are relatively long, and the requirements for real-time control are relatively low. However, the operating environment of spaceborne networks differs significantly from that of terrestrial networks. Influenced by orbital motion, attitude changes, and visibility constraints, the establishment and disconnection of inter-satellite links exhibit significant time-varying and uncertainties, and the network topology is in a state of continuous dynamic change. This characteristic requires spaceborne optical switching nodes to possess higher agility and lower reconfiguration latency to achieve rapid switching and real-time reconfiguration of inter-satellite links. Simultaneously, due to inter-satellite visibility limitations, the number of optical links that each satellite can establish at any given time is limited, resulting in a relatively low demand for port size per node, but placing higher demands on the real-time performance, determinism, and reliability of switching control.

[0003] To meet the needs of spaceborne applications, existing research and engineering explorations have begun to explore the introduction of optical switching technology into the space environment, conducting a series of exploratory works at both the device and system levels. For example, engineering optimizations of MEMS optical switch arrays, such as vibration and thermal deformation resistance, have been implemented to adapt them to the on-orbit operating environment; dynamic beam calibration and power stabilization control have been achieved by introducing tunable optical components; and at the system architecture level, the use of a hierarchical constellation structure and a centralized-distributed control approach has been explored to achieve collaborative management of cross-orbit optical links. These studies indicate that spaceborne optical switching has a certain foundation in terms of device feasibility and system architecture, but many challenges remain in its engineering implementation.

[0004] From a node implementation perspective, existing spaceborne optical switching solutions still have significant shortcomings in hardware architecture and control mechanisms. On the one hand, some solutions rely on general-purpose processors or software during the switching control process, resulting in substantial latency and uncertainty between scheduling calculations, control decisions, and switching execution. Under the constraints of spaceborne computing power and power consumption, it is difficult to achieve deterministic responses at the microsecond or even nanosecond level. On the other hand, since the optical switching system itself lacks buffering and queuing capabilities, the timing coordination requirements between control signaling processing, time slot switching, and optical switching execution are extremely high. Existing solutions still need improvement in terms of timing consistency, disturbance rejection capabilities, and anomaly handling mechanisms. Furthermore, existing spaceborne optical switching nodes generally have low module integration and hardware resource utilization efficiency, and insufficient coordination between control logic and the optical switching matrix makes it difficult to achieve high-concurrency and high-reliability switching control capabilities under limited hardware resources.

[0005] Against this backdrop, while existing technologies have made some progress in areas such as the performance of optical switching devices, verification of spaceborne optical communication, and exploration of network architecture, they still lack an overall design scheme for optical switching nodes that is engineering-featured for spaceborne application scenarios. In particular, a mature and unified implementation path has not yet been formed in areas such as full hardware control, high real-time scheduling, and high-reliability operation.

[0006] Against the backdrop of rapid development in satellite internet, inter-satellite laser links have gradually become the main method for carrying high-speed, high-capacity data transmission in spaceborne communication systems. The processing capacity and control performance of spaceborne switching nodes directly determine the overall operational efficiency of the space network. However, from the current engineering implementation and research status, existing spaceborne switching technologies still have many limitations in terms of architecture, hardware implementation, and control mechanisms, making it difficult to meet the application requirements of inter-satellite laser links under ultra-high-speed, highly dynamic, and highly reliable conditions. Existing spaceborne switching systems mostly use traditional electrical switching or optoelectronic hybrid switching architectures. Data needs to undergo frequent optical-electrical-optical conversions during the switching process, which not only makes it difficult to match the physical transmission capacity of laser links in terms of rate and bandwidth, but also significantly increases system power consumption and processing latency. Under the constraints of spaceborne platform power, heat dissipation, and size, it is difficult to achieve long-term stable operation. In addition, the method of electrical switching and software-based scheduling has problems of uncertain response and lengthy processing paths when handling concurrent services. It is easy to form a switching bottleneck under high load or sudden service scenarios, which restricts the further improvement of the switching capacity of spaceborne nodes.

[0007] In optical switching research, although various optical switching structures based on MEMS, MZI, and silicon photonics integrated devices have been proposed, much research remains at the device-level performance verification or small-scale experimental stage, lacking a systematic node design and engineering implementation path for spaceborne applications. Existing optical switching nodes generally suffer from deficiencies in structural integration and control architecture. The coordination between the optical switching matrix and control logic is not tight, and the control process often relies on external processing units or software, resulting in significant control delays and insufficient timing determinism, making it difficult to support the high-speed switching requirements of frequent inter-satellite link establishment and termination. Furthermore, since optical switching systems themselves lack buffering and queuing capabilities, deviations in control signaling processing, time slot switching, or drive timing can easily lead to optical path conflicts, incorrect switching, or service interruptions, placing extremely high demands on system stability and reliability. Current technologies still fall short of fully meeting the requirements of spaceborne operation in terms of control accuracy, timing consistency, and disturbance rejection capabilities.

[0008] From a control mechanism perspective, some existing spaceborne optical switching solutions still employ CPU- or software-based scheduling and control models. Significant time decoupling and resource contention exist between scheduling calculations, control decisions, and switching execution. On spaceborne platforms with limited computing power and controlled clock frequencies, achieving microsecond- or even nanosecond-level deterministic control responses is difficult. Furthermore, existing scheduling mechanisms are prone to generating empty time slots or invalid switching during resource allocation, resulting in wasted valuable inter-satellite optical link resources and low overall system bandwidth utilization and throughput efficiency. Some solutions do not adequately consider the parallelism between scheduling calculations and optical switching execution. When scheduling calculations are not yet complete, the switching matrix cannot be updated in a timely manner, further amplifying the impact of control latency on system performance.

[0009] At the engineering implementation level, existing spaceborne optical switching nodes generally lack hardware architecture optimized for the spaceborne environment. The control module, interface management module, and optical switching matrix are loosely coupled, resulting in low hardware resource utilization efficiency and difficulty in achieving high-concurrency, high-real-time switching control capabilities within limited logic resources and power budgets. Furthermore, existing solutions rely heavily on external systems or simple mechanisms for time synchronization, time slot boundary control, and link alignment. Faced with long-distance inter-satellite propagation delays, high-speed node movement, and environmental disturbances, the system's timing robustness is insufficient, affecting the stable operation of optical switching nodes in complex space environments. Summary of the Invention

[0010] The purpose of this invention is to overcome the shortcomings of the prior art and provide a spaceborne optical switching system, method and related apparatus based on superframe time slot mechanism. This system, method and related apparatus can solve the bottlenecks of rate, power consumption and latency caused by traditional electrical switching and software control methods, improve the speed, parallelism and stability of optical switching control process, and thus improve the resource utilization of inter-satellite optical links and the overall throughput of the system.

[0011] To achieve the above objectives, this invention discloses a spaceborne optical switching system based on a superframe time slot mechanism, comprising several spaceborne nodes, wherein the spaceborne nodes are interconnected via inter-satellite laser links. The spaceborne nodes include a master control node and slave nodes. The master control node is used to maintain a global time reference, periodically collect service status information of each slave node, complete time slot and resource allocation calculations, and send the optical switching configuration results to the execution layer. The slave nodes are used to complete local service access, status acquisition and reporting, time synchronization locking, and send optical pulses or optical data signals according to a unified time system within the allocated time slots.

[0012] Furthermore, the master control node includes: A global superframe timer is used to maintain the loop count and generate the superframe start trigger signal, signaling window indication signal, and data time slot index signal, which are used to uniformly drive signaling transmission, demand acquisition, scheduling writing, and optical switching execution. The signaling receiving and parsing module is used to identify and parse the REQ control frames reported by the subordinate nodes. After completing the extraction of key fields, it enters the waiting end state. The scheduling and bandwidth allocation engine is used to aggregate demand information within the signaling window and perform work conservation scheduling calculations to generate time slot mapping results. The demand information writing process is restricted by the signaling window gating signal. A double-buffered ping-pong storage structure is used to achieve pipelined collaboration between scheduling computation and optical switching execution.

[0013] This invention discloses a spaceborne optical switching method based on a superframe time slot mechanism, comprising: The master node generates a superframe initiation event and enters the signaling window; Beacon control frames are constructed and broadcast through the master node; The Beacon control frames are captured by the Always-on resolver in the slave node, and cold start synchronization is completed. Propagation delay compensation is performed and the transmission window is calculated through the subordinate node; The slave node generates a REQ control frame within the signaling window and sends the REQ control frame for reporting. The master control node parses the REQ control frame and writes the parsing result into the demand table within the signaling window; The master control node performs scheduling calculations at the end of the signaling window and generates time slot mapping information, which is then written into the Shadow Bank storage area. The data exchange window begins, and the master node drives the optical switching matrix according to the time slot mapping information in the Shadow Bank storage area. The slave node opens a transmission window and sends out optical data signals within the allocated time slot.

[0014] Furthermore, the specific process of generating a superframe initiation event and entering the signaling window through the master control node is as follows: The global superframe timer in the master node counts cyclically according to a preset superframe period. When the count value reaches the superframe period boundary, the global superframe timer outputs a superframe start trigger signal, sets the signaling window indicator signal, and initializes or resets the current data slot index counter. The process of constructing and broadcasting Beacon control frames through the master node is as follows: After detecting the superframe start trigger signal, the master node constructs a Beacon control frame based on the current global superframe timer count value and broadcasts the Beacon control frame so that each slave node can obtain the latest time base and control information at the beginning of each superframe cycle.

[0015] Furthermore, the process of capturing Beacon control frames and completing cold start synchronization through the Always-on resolver in the slave node is as follows: The Always-on frame parser performs frame header detection on the received Beacon control frames. When a Beacon control frame with a predefined EtherType and frame type identifier is identified, the global timestamp field is extracted, and the local superframe counter is forcibly reset or calibrated to ensure that the local time of the slave node is consistent with the global time of the master node.

[0016] Furthermore, the process of performing propagation delay compensation and calculating the sending window through the subordinate node is as follows: The slave node introduces a propagation delay compensation mechanism, which combines the local superframe time with the pre-estimated or measured inter-satellite propagation delay parameters to generate a virtual time for controlling the transmission behavior. The slave node performs a lookup operation on the locally stored Bitmap or time slot mapping information based on the virtual time to determine the position of the data time slot allocated to its own node in the current superframe. When a slave node detects that it is about to enter its own data time slot, it raises the transmit window control signal in advance.

[0017] Furthermore, the process of generating a REQ control frame within the signaling window through the subordinate node and sending the REQ control frame for reporting is as follows: When a slave node determines that the signaling window has entered its edge or has already been reached based on the synchronization result, the slave node reads the amount of data to be sent from its local FIFO, buffer, or service queue in real time, and encapsulates the amount of data to be sent as the service requirement value together with the node identification information into a REQ control frame. The REQ control frame is then sent to the master node in a high-priority manner through the sending arbitration module to ensure that the reporting is completed within the effective time of the signaling window, providing accurate requirement input for the centralized scheduling of the master node.

[0018] Furthermore, the process by which the master node drives the optical switching matrix according to the data time slot mapping information in the Shadow Bank storage area at the start of the data exchange window is as follows: At each data time slot boundary, the optical switching execution module in the master node reads the corresponding time slot mapping information from the Active Bank storage area according to the current time slot index, converts the mapping information into a control signal for the optical switching matrix, and then applies the control signal of the optical switching matrix to the optical switching matrix or optical switch array, so that the optical switching matrix or optical switch array completes optical path conduction, disconnection or path selection operations within the time slot boundary.

[0019] This invention discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the spaceborne optical switching method based on the superframe time slot mechanism.

[0020] The present invention discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the spaceborne optical switching method based on the superframe time slot mechanism.

[0021] The present invention has the following beneficial effects: The spaceborne optical switching system, method, and related devices based on the superframe time slot mechanism described in this invention, in specific operation, maintain a global time reference through the master control node, periodically collect service status information of each subordinate node, complete time slot and resource allocation calculations, and send the optical switching configuration results to the execution layer; the subordinate nodes are used to complete local service access, status acquisition and reporting, and time synchronization locking, and send optical pulses or optical data signals according to a unified time system within the allocated time slots, so as to solve the bottlenecks of rate, power consumption, and latency caused by traditional electrical switching and software control methods, improve the speed, parallelism, and stability of the optical switching control process, and thereby improve the resource utilization of inter-satellite optical links and the overall throughput of the system, which is highly practical. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the spaceborne all-optical switching system of the present invention; Figure 2 This is a schematic diagram of the superframe-slot time organization structure; Figure 3 A schematic diagram of control plane signaling and frame structure; Figure 4Design diagram for a lightweight control frame structure; Figure 5 This is a structural diagram of an FPGA; Figure 6 This is a system structure diagram of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0027] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0028] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0029] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0031] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] Example 1 refer to Figure 1 The spaceborne optical switching system based on the superframe time slot mechanism described in this invention includes several spaceborne nodes, which are interconnected via inter-satellite laser links. Each spaceborne node is equipped with an optical switching node capable of switching, scheduling, and control. This allows the inter-satellite laser link to not only perform physical layer transmission functions but also become a switching resource that can be configured and dynamically reconfigured on demand. Furthermore, considering the strict constraints of the spaceborne platform in terms of power consumption, size, computing power, and reliability, and taking into account the frequent changes in the topology of the inter-satellite laser link due to orbital motion, this invention adopts a hierarchical / master-slave collaborative structure in its system organization. The optical switching master node with global control capabilities undertakes system-level control functions, while multiple access / slave nodes undertake service access and execution functions.

[0033] Specifically, the master node is used to maintain the global time base, periodically collect the service status information of each slave node, complete the time slot and resource allocation calculation, and send the optical switching configuration results to the execution layer; Slave nodes are used to complete local service access, status collection and reporting, time synchronization locking, and send optical pulses or optical data signals in accordance with a unified time system within the allocated time slots.

[0034] Through the above architecture design, while ensuring centralized control and timing consistency, the control overhead caused by complex negotiations between nodes is reduced, which can effectively support the requirements of high bandwidth, low latency, reconfigurability and adaptive spatial optical interconnection.

[0035] Each onboard node (including master and slave nodes) adopts a functional division of "optical forwarding plane + control plane" in its internal structure. The optical forwarding plane handles the physical access, forwarding, and output of inter-satellite laser signals, primarily including optical interface modules, optical switching matrices or equivalent high-speed optical switch arrays, and high-speed execution circuits to drive the optical switching devices. The control plane handles all functions related to time, signaling, scheduling, and control, mainly including time reference and timing control modules, control signaling parsing and generation modules, scheduling and control engines, and interface and state management modules. This structure functionally decouples high-speed optical signal processing from complex control logic, while achieving close collaboration between the two through on-chip high-speed interconnects. The control structure, centered on the optical switching control engine and composed of units for time synchronization, interface control, and configuration generation, achieves refined and deterministic control of the optical switching matrix through logical coupling and strict timing coordination.

[0036] The system implements time organization, superframes, and time slot structures through a control plane. Specifically, a unified superframe-time slot time organization structure is established in the control plane to adapt to engineering characteristics in spaceborne scenarios, such as non-negligible propagation delays, highly dynamic link states, and the lack of buffering capabilities in optical domain switching systems. The system uses a fixed-frequency clock as the global operating reference. In a typical embodiment, the control logic operates under a 100MHz clock condition. Based on this clock reference, the superframe period length, signaling window duration, and basic granularity of data time slots are defined, ensuring that all nodes in the system perform synchronization, reporting, scheduling, and switching actions based on the same time scale. Through this unified time organization method, high-precision timing alignment between spaceborne nodes is achieved without relying on complex software time synchronization protocols.

[0037] Within a complete superframe cycle, time is explicitly divided into two consecutive phases: a signaling window and a data exchange window. The signaling window, located in a fixed interval at the beginning of the superframe, is used by the master node to broadcast time synchronization and optical switching mapping information to subordinate nodes, while also providing a time window for subordinate nodes to report service requests. The data exchange window consists of several consecutive data time slots, each corresponding to a deterministic optical switching execution process. Within the data exchange window, the master node controls the conduction state of the optical switching matrix according to a pre-generated time slot mapping table, while subordinate nodes send optical pulses or optical data signals within their assigned data time slots. By confining control actions to the signaling window and data forwarding actions to the data exchange window, strict boundaries are established between control and forwarding in the time dimension, providing a reliable timing basis for subsequent gating protection, anti-crosstalk design, and deterministic optical switching execution.

[0038] like Figure 4 As shown, this invention employs a lightweight control frame structure design during inter-satellite control information interaction to meet the engineering implementation requirements of parallel parsing, high-speed processing, and fixed word alignment for onboard FPGAs. In a typical embodiment, the system defines two types of key control frames: Beacon frames periodically sent by the master node, and REQ control frames sent by slave nodes within the signaling window. Beacon frames are used to send global timestamp information to slave nodes and, in some implementations, carry time slot mappings or control parameters related to the current or next superframe; REQ control frames are used by slave nodes to report node identification information and the current service queue depth or service demand to the master node.

[0039] To adapt to the full hardware parsing method, the control frame is standardized in terms of field length, field position and byte alignment. For example, by fixing the EtherType identifier and packet type field, the parsing module can complete high-speed recognition and field capture by feature word matching and fixed offset extraction, avoiding the timing uncertainty caused by complex variable length parsing, thereby improving the stability and reliability of the control plane.

[0040] Specifically, the master control node includes a global superframe timer, a scheduling and bandwidth allocation engine, a signaling reception and parsing module, and a double-buffered ping-pong storage structure. The global superframe timer maintains a loop count and generates a superframe start trigger signal, a signaling window indication signal, and a data time slot index signal, driving signaling transmission, demand acquisition, scheduling writing, and optical switching execution in a unified manner. The signaling reception and parsing module identifies and parses REQ control frames reported by subordinate nodes. After extracting key fields, it enters a waiting state to consume frame tail filling data, avoiding repeated triggering. The scheduling and bandwidth allocation engine summarizes demand information within the signaling window and performs work-conserving scheduling calculations to generate time slot mapping results. To prevent crosstalk or false triggering during the data phase from introducing false demand information, the demand writing process is strictly limited by the signaling window gating signal. The double-buffered ping-pong storage structure enables pipelined collaboration between scheduling calculations and optical switching execution.

[0041] The slave node employs an Always-on frame parser design, enabling it to capture Beacon frames and complete cold start synchronization even in unsynchronized or link reconfiguration states. After synchronization, the slave node generates a virtual time using a propagation delay compensation mechanism and determines the opening time of the transmission window based on the virtual time and time slot mapping information. Within the signaling window, the slave node generates and sends REQ control frames to report service requirements; within the data exchange window, the slave node transmits optical signals within its allocated data time slots.

[0042] Example 2 This embodiment discloses a spaceborne optical switching method based on a superframe time slot mechanism. The method forms a complete control and switching closed loop sequentially within a superframe cycle. The closed loop process is completed collaboratively by the master control node and slave nodes under a unified time reference, and specifically includes stages such as time synchronization, service requirement collection, scheduling calculation, optical switching execution, and cycle switching.

[0043] Specifically, the spaceborne optical switching method based on the superframe time slot mechanism includes the following steps: 1) The master node generates a superframe start event and enters the signaling window; During normal system operation, the global superframe timer in the master control node counts cyclically according to the preset superframe period. When the count value reaches the superframe period boundary, the global superframe timer outputs a superframe start trigger signal, sets the signaling window indicator signal, and initializes or resets the current data slot index counter.

[0044] The superframe start trigger signal serves as the unified time starting point for various control actions within the current superframe period, driving subsequent operations such as control signaling transmission, service request collection, and scheduling calculation. The signaling window indication signal serves as a hardware gating condition, explicitly limiting service request writing and scheduling calculation to only be allowed within the signaling window, thereby establishing a clear and stable time boundary at the hardware level.

[0045] 2) The master node constructs and broadcasts Beacon frames.

[0046] After detecting the superframe start trigger signal, the control signaling generation module in the master node is activated, and a Beacon control frame is constructed based on the current global superframe timer count value. The Beacon control frame is then broadcast through the optical interface module of the master node, enabling each slave node to obtain the latest time reference and control information at the beginning of each superframe cycle.

[0047] The Beacon control frame contains at least a global timestamp field for time synchronization, and in some implementations may also carry time slot mapping information or control parameters related to the current or next superframe.

[0048] 3) The Always-on resolver in the slave node captures the Beacon and completes cold start synchronization; An Always-on frame parser is configured within the slave node. This Always-on frame parser remains in a continuous listening state during system operation, unaffected by the local time counter or signaling window position. The Always-on frame parser performs frame header detection on the received optical signal. When it identifies a Beacon control frame with a predetermined EtherType and frame type identifier, it immediately extracts the global timestamp field and triggers the time synchronization module to forcibly reset or calibrate the local superframe counter, ensuring that the slave node's local time is consistent with the master node's global time. Even if the slave node is in its initial power-on state or loses synchronization due to a link interruption, the Always-on frame parser can still guarantee cold-start synchronization upon first receiving a Beacon control frame.

[0049] 4) The subordinate node performs propagation delay compensation and calculates the sending window.

[0050] After time synchronization is completed, the time synchronization and compensation module in the slave node introduces a propagation delay compensation mechanism. This mechanism combines the local superframe time with pre-estimated or measured inter-satellite propagation delay parameters to generate a virtual time for controlling transmission behavior. The slave node then performs a lookup operation on the locally stored Bitmap or time slot mapping information based on this virtual time to determine the position of the data time slot allocated to itself in the current superframe.

[0051] When the slave node detects that it is about to enter its own data time slot, it raises the transmission window control signal in advance to provide time preparation for the accurate transmission of subsequent optical signals, thereby ensuring that the optical signals can be aligned with the conduction window of the master node's optical switching matrix after inter-satellite propagation.

[0052] 5) The slave node generates a REQ control frame within the signaling window and sends it up for reporting.

[0053] When a slave node determines that the signaling window has reached its edge or has been reached based on the synchronization result, the service status acquisition and signaling generation module within the slave node is triggered. This module reads the amount of data to be sent from the local FIFO, buffer, or service queue in real time, and encapsulates this amount of data, along with node identification information, into a REQ control frame. The REQ control frame is then sent to the master node with high priority via the transmission arbitration module, ensuring that the report is completed within the effective time of the signaling window and providing accurate demand input for centralized scheduling by the master node.

[0054] 6) The master control node parses the REQ control frame and writes it into the demand table in the signaling window.

[0055] During the signaling window, the master node continuously receives REQ control frames from each slave node. The signaling receiving and parsing module performs EtherType and packet type matching on the received REQ control frames. When a valid REQ control frame is identified, the node identifier field and service requirement field are extracted from it. After the node identifier field and service requirement field are extracted, the signaling receiving and parsing module enters a waiting state to consume Ethernet frame end padding data, avoiding duplicate triggering caused by the minimum frame length mechanism. Simultaneously, under the gating condition of the signaling window indication signal, the scheduling and control engine writes the service requirement field into the internal requirement table. This writing operation is only allowed within the signaling window, thereby preventing the introduction of false requirement information due to crosstalk or false triggering during the data exchange phase.

[0056] 7) The master node completes the scheduling calculation and generates the time slot mapping table at the end of the signaling window.

[0057] As the signaling window is about to close, the scheduling and bandwidth allocation engine in the master node initiates the scheduling calculation process based on the demand information of each node in the demand table. The engine uses a hardware state machine to poll and traverse the demands of each slave node. When a slave node's demand is zero, it skips that node without allocating a data time slot. When a slave node has a demand, it allocates the corresponding data time slot and updates the demand count synchronously. After the scheduling calculation is complete, the generated data time slot mapping result is written to the Shadow Bank storage area for data exchange execution in the next superframe cycle.

[0058] 8) When the data exchange window starts, the master node uses Active Bank to look up the table and drive the optical switching matrix.

[0059] As the signaling window ends, the system enters the data exchange window. At each data time slot boundary, the optical switching execution module in the master node reads the corresponding data time slot mapping information from the Active Bank storage area according to the current time slot index, converts the mapping information into control signals for the optical switching matrix, and then applies the control signals of the optical switching matrix to the optical switching matrix or optical switch array via a high-speed drive interface. This enables the optical switching matrix or optical switch array to complete optical path conduction, disconnection, or path selection operations within the time slot boundary, thereby ensuring the determinism and continuity of the optical switching execution process.

[0060] 9) The slave node opens the transmission window and sends out optical data signals within the allocated time slot.

[0061] During the data exchange window, the slave node determines the current data time slot ownership based on the virtual time and time slot mapping information. When it detects that the current data time slot has been allocated to its own node, the slave node pulls up the transmission window signal and drives the optical transmitter to output optical pulses or optical data signals. Since the present invention introduces a propagation delay compensation mechanism, the optical signal emitted by the slave node can be precisely aligned with the conduction window of the optical exchange matrix in the master node in time after inter-satellite propagation, thereby completing reliable data forwarding under buffer-free conditions.

[0062] 10) Superframe switching, ping-pong buffer flips and enters the next cycle closed loop.

[0063] When the current superframe cycle ends and the next superframe start trigger signal arrives, the ping-pong buffer control logic inside the master node is triggered, causing an instantaneous switch between the Active Bank and Shadow Bank roles. The scheduling results previously written to the Shadow Bank immediately become the new execution mapping table, used to drive data exchange in the next superframe cycle; the original Active Bank then enters an idle state to store the next round of scheduling calculation results. Through this ping-pong buffer flipping mechanism, scheduling calculation and optical switching execution are fully pipelined in time, allowing the system to seamlessly enter the next superframe cycle and repeat the closed-loop process described above.

[0064] Example 3 refer to Figure 5 This embodiment implements a protocol parsing pipeline, scheduling state machine, ping-pong buffer mechanism, and time compensation logic on an FPGA platform, enabling the system to achieve high real-time response and stable operation under limited onboard resources. Simultaneously, an experimental verification platform for onboard application scenarios can be constructed to conduct system testing and evaluation of node functional correctness, the coordination between the control plane and forwarding plane, stability under dynamic load conditions, and system lightweight indicators, thereby forming a verification framework with engineering feasibility.

[0065] It should be noted that the present invention has the following characteristics: 1) Existing spaceborne communication systems mostly rely on electrical switching or employ hybrid optical-electrical-optical switching methods. Constrained by high-speed analog-to-digital conversion, electrical domain processing speed, and power consumption, these systems struggle to match the ultra-high bandwidth capabilities of inter-satellite laser links, easily creating "switching bottlenecks" at nodes. While some existing optical switching research has achieved high-speed switching at the device level, it lacks a control system adapted to spaceborne scenarios, making it difficult to stably leverage its capacity advantages in practical systems. This invention constructs a spaceborne all-optical switching system that completely avoids optical-electrical-optical conversion during data forwarding, directly performing path selection and forwarding control of optical signals within the optical domain, thus eliminating the rate and power consumption bottlenecks caused by electrical switching at the system level. Simultaneously, by introducing a deterministic scheduling mechanism based on superframes and time slots in the control plane, the conduction state of the optical switching matrix is ​​strictly aligned with the inter-satellite optical link, thereby achieving effective matching of switching capacity and laser link transmission capacity at the system level. Therefore, this invention can significantly improve the effective throughput that a single node can carry under limited node scale conditions, providing crucial support for constructing inter-satellite "high-speed optical information channels."

[0066] 2) Existing spaceborne optical switching solutions often borrow from the centralized scheduling approach of terrestrial data centers or backbone networks, relying on complex software control or cross-node negotiation mechanisms. In space environments with highly dynamic topologies and link states, scheduling failures are easily caused by control delays, state inconsistencies, or link mutations. Furthermore, optical switching systems inherently lack buffering and queuing capabilities; any time deviation between control and execution can easily lead to data loss. This invention introduces a unified time-base superframe-timeslot organization method in its system design, strictly separating control actions from data forwarding actions in the time dimension: all demand collection and scheduling calculations occur only within the signaling window, while optical switching execution occurs only within the data switching window. In this way, this invention forms a clear control boundary at the hardware level, making the conduction behavior of the optical switching matrix highly deterministic. Simultaneously, through propagation delay compensation of subordinate nodes and virtual time calculation mechanisms, it ensures that optical signals under long-distance inter-satellite propagation conditions can still be precisely aligned with the optical switching conduction window, thereby significantly improving the system's stability and robustness in highly dynamic orbital environments.

[0067] 3) In existing research, some optical switching control schemes rely on CPUs or software-defined network (SDN) controllers for centralized computation and distribution. While theoretically flexible, these schemes struggle to meet the combined constraints of power consumption, computing power, and real-time performance in a spaceborne environment. Furthermore, software control methods are prone to unpredictable scheduling delays under bursty traffic or high-concurrency scenarios. This invention employs a fully hardware-based FPGA implementation, embedding key functions such as time synchronization, frame parsing, demand collection, scheduling computation, and optical switching execution into a hardware logic pipeline. Through hardware parallel processing and state machine-driven approaches, nanosecond-level response and microsecond-level scheduling capabilities are achieved, effectively avoiding the uncertainties introduced by software control. Simultaneously, the introduction of a ping-pong buffered scheduling structure completely decouples scheduling computation from optical switching execution in time, masking scheduling delays within the superframe period, thus achieving zero-wait switching. This design significantly improves the system's real-time performance and engineering feasibility, making it more suitable for long-term stable operation under resource-constrained spaceborne conditions.

[0068] 4) Existing polling or statically allocated optical switching scheduling schemes often generate a large number of empty time slots when facing uneven node service loads, resulting in the waste of valuable optical link resources. Especially in spaceborne environments, the link availability window is limited, and the reduction in resource utilization will directly affect the overall system performance. This invention introduces a work-conserving time slot allocation strategy into the scheduling mechanism, implementing a dynamic judgment and skipping mechanism for node demand at the hardware level: when a node has no service demand, no data time slot is allocated to it, and the process directly switches to the next node; idle time slots are only introduced when all nodes have no demand. Through this mechanism, this invention can significantly reduce the proportion of empty time slots without increasing scheduling complexity, improve the effective utilization of optical links, and thus achieve higher system throughput under the same hardware conditions.

[0069] 5) In spaceborne optical communication systems, optical switch crosstalk, false triggering, and physical layer noise are unavoidable. Existing solutions lack effective logical isolation mechanisms, making it easy to mistakenly collect control information during the data phase, affecting the accuracy of scheduling results. This invention introduces a strict gating mechanism based on a signaling window in the control plane, allowing only the parsing and writing of REQ requests within the signaling window. Even if crosstalk or false triggering signals occur during the data exchange phase, they will not affect the scheduling logic. By constructing a "time firewall" at the logical level, this invention significantly improves the control system's tolerance to physical layer disturbances, thereby enhancing the overall reliability and engineering robustness of the system.

[0070] Example 4 refer to Figure 6 The spaceborne optical switching method based on the superframe time slot mechanism of the present invention includes: The generation module is used to generate a superframe initiation event through the master control node and enter the signaling window; The building module is used to build and broadcast Beacon control frames through the master node; The synchronization module is used to capture Beacon control frames and complete cold start synchronization through the Always-on resolver in the slave node; The calculation module is used to perform propagation delay compensation and calculate the transmission window through the slave node; The generation module is used to generate REQ control frames within the signaling window through the slave node and send the REQ control frames for reporting. The writing module is used to parse the REQ control frame through the master control node and write the parsing result into the demand table within the signaling window; The scheduling module is used to perform scheduling calculations at the end of the signaling window through the master control node, generate time slot mapping information, and write the time slot mapping information into the Shadow Bank storage area. The driver module is used to start the data exchange window and drive the optical switching matrix through the master node based on the time slot mapping information in the Shadow Bank storage area. The activation module is used to open a transmission window and send optical data signals through the slave node within the allocated time slot.

[0071] In this embodiment, the specific process of generating a superframe initiation event and entering the signaling window through the master control node is as follows: The global superframe timer in the master node counts cyclically according to a preset superframe period. When the count value reaches the superframe period boundary, the global superframe timer outputs a superframe start trigger signal, sets the signaling window indicator signal, and initializes or resets the current data slot index counter. The process of constructing and broadcasting Beacon control frames through the master node is as follows: After detecting the superframe start trigger signal, the master node constructs a Beacon control frame based on the current global superframe timer count value and broadcasts the Beacon control frame so that each slave node can obtain the latest time base and control information at the beginning of each superframe cycle.

[0072] In this embodiment, the process of capturing Beacon control frames and completing cold start synchronization through the Always-on resolver in the slave node is as follows: The Always-on frame parser performs frame header detection on the received Beacon control frames. When a Beacon control frame with a predefined EtherType and frame type identifier is identified, the global timestamp field is extracted, and the local superframe counter is forcibly reset or calibrated to ensure that the local time of the slave node is consistent with the global time of the master node.

[0073] In this embodiment, the process of performing propagation delay compensation and calculating the sending window through the subordinate node is as follows: The slave node introduces a propagation delay compensation mechanism, which combines the local superframe time with the pre-estimated or measured inter-satellite propagation delay parameters to generate a virtual time for controlling the transmission behavior. The slave node performs a lookup operation on the locally stored Bitmap or time slot mapping information based on the virtual time to determine the position of the data time slot allocated to its own node in the current superframe. When a slave node detects that it is about to enter its own data time slot, it raises the transmit window control signal in advance.

[0074] In this embodiment, the process of generating a REQ control frame within the signaling window by the subordinate node and sending the REQ control frame for reporting is as follows: When a slave node determines that the signaling window has entered its edge or has already been reached based on the synchronization result, the slave node reads the amount of data to be sent from its local FIFO, buffer, or service queue in real time, and encapsulates the amount of data to be sent as the service requirement value together with the node identification information into a REQ control frame. The REQ control frame is then sent to the master node in a high-priority manner through the sending arbitration module to ensure that the reporting is completed within the effective time of the signaling window, providing accurate requirement input for the centralized scheduling of the master node.

[0075] In this embodiment, the process of the master node driving the optical switching matrix according to the data time slot mapping information in the Shadow Bank storage area at the start of the data exchange window is as follows: At each data time slot boundary, the optical switching execution module in the master node reads the corresponding time slot mapping information from the Active Bank storage area according to the current time slot index, converts the mapping information into a control signal for the optical switching matrix, and then applies the control signal of the optical switching matrix to the optical switching matrix or optical switch array, so that the optical switching matrix or optical switch array completes optical path conduction, disconnection or path selection operations within the time slot boundary.

[0076] The module division in this embodiment is illustrative and represents only one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in each embodiment of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0077] Example 5 A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the spaceborne optical switching method based on a superframe time slot mechanism. For example, the steps include: generating a superframe start event and entering a signaling window via a master node; constructing and broadcasting a Beacon control frame via the master node; capturing the Beacon control frame and completing cold start synchronization via an Always-on parser in a slave node; performing propagation delay compensation and calculating a transmission window via a slave node; generating a REQ control frame within the signaling window via a slave node and sending the REQ control frame for reporting; parsing the REQ control frame via the master node and writing the parsing result into a demand table within the signaling window; performing scheduling calculations at the end of the signaling window via the master node and generating time slot mapping information, and writing the time slot mapping information into a Shadow Bank storage area; starting a data exchange window and driving an optical switching matrix via the master node according to the time slot mapping information in the Shadow Bank storage area; and opening a transmission window and sending optical data signals via a slave node within an allocated time slot. The memory may include main memory, such as high-speed random access memory (RAM), or non-volatile memory, such as at least one disk storage device. The processor, network interface, and memory are interconnected via an internal bus, which may be an industry-standard architecture bus, a peripheral component interconnection standard bus, or an extended industry-standard architecture bus. The bus can be categorized as an address bus, data bus, or control bus. The memory stores programs; specifically, the program may include program code, which includes computer operation instructions. The memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0078] Example 6 A computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the spaceborne optical switching method based on a superframe time slot mechanism. For example, the steps include: generating a superframe start event and entering a signaling window via a master node; constructing and broadcasting a Beacon control frame via the master node; capturing the Beacon control frame and completing cold start synchronization via an Always-on parser in a slave node; performing propagation delay compensation and calculating a transmission window via a slave node; generating a REQ control frame within the signaling window via a slave node and sending the REQ control frame for reporting; parsing the REQ control frame via the master node and writing the parsing result into a demand table within the signaling window; performing scheduling calculations at the end of the signaling window via the master node and generating time slot mapping information, and writing the time slot mapping information into a Shadow Bank storage area; starting a data exchange window and driving an optical switching matrix via the master node based on the time slot mapping information in the Shadow Bank storage area; and opening a transmission window and sending optical data signals via a slave node within an allocated time slot. Specifically, the computer-readable storage medium includes, but is not limited to, volatile memory and / or non-volatile memory. The volatile memory may include random access memory (RAM) and / or cache memory, etc. The non-volatile memory may include read-only memory (ROM), hard disk, flash memory, optical disk, magnetic disk, etc.

[0079] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0080] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0081] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0082] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0083] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0084] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

[0085] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A spaceborne optical switching system based on a superframe time slot mechanism, characterized in that, It includes several onboard nodes, which are connected to each other via inter-satellite laser links. The onboard nodes include a master control node and slave nodes. The master control node is used to maintain a global time reference, periodically collect service status information of each slave node, complete time slot and resource allocation calculations, and send the optical switching configuration results to the execution layer. The slave nodes are used to complete local service access, status acquisition and reporting, time synchronization locking, and send optical pulses or optical data signals according to a unified time system within the allocated time slots.

2. The spaceborne optical switching system based on the superframe time slot mechanism according to claim 1, characterized in that, The master control node includes: A global superframe timer is used to maintain the loop count and generate the superframe start trigger signal, signaling window indication signal, and data time slot index signal, which are used to uniformly drive signaling transmission, demand acquisition, scheduling writing, and optical switching execution. The signaling receiving and parsing module is used to identify and parse the REQ control frames reported by the subordinate nodes. After completing the extraction of key fields, it enters the waiting end state. The scheduling and bandwidth allocation engine is used to aggregate demand information within the signaling window and perform work conservation scheduling calculations to generate time slot mapping results. The demand information writing process is restricted by the signaling window gating signal. A double-buffered ping-pong storage structure is used to achieve pipelined collaboration between scheduling computation and optical switching execution.

3. A spaceborne optical switching method based on a superframe time slot mechanism, characterized in that, include: The master node generates a superframe initiation event and enters the signaling window; Beacon control frames are constructed and broadcast through the master node; The Beacon control frames are captured by the Always-on resolver in the slave node, and cold start synchronization is completed. Propagation delay compensation is performed and the transmission window is calculated through the subordinate node; The slave node generates a REQ control frame within the signaling window and sends the REQ control frame for reporting. The master control node parses the REQ control frame and writes the parsing result into the demand table within the signaling window; The master control node performs scheduling calculations at the end of the signaling window and generates time slot mapping information, which is then written into the Shadow Bank storage area. The data exchange window begins, and the master node drives the optical switching matrix according to the time slot mapping information in the Shadow Bank storage area. The slave node opens a transmission window and sends out optical data signals within the allocated time slot.

4. The spaceborne optical switching method based on the superframe time slot mechanism according to claim 3, characterized in that, The specific process of generating a superframe initiation event and entering the signaling window through the master control node is as follows: The global superframe timer in the master node counts cyclically according to a preset superframe period. When the count value reaches the superframe period boundary, the global superframe timer outputs a superframe start trigger signal, sets the signaling window indicator signal, and initializes or resets the current data slot index counter. The process of constructing and broadcasting Beacon control frames through the master node is as follows: After detecting the superframe start trigger signal, the master node constructs a Beacon control frame based on the current global superframe timer count value and broadcasts the Beacon control frame so that each slave node can obtain the latest time base and control information at the beginning of each superframe cycle.

5. The spaceborne optical switching method based on the superframe time slot mechanism according to claim 3, characterized in that, The process of capturing Beacon control frames and completing cold start synchronization through the Always-on resolver in the slave node is as follows: The Always-on frame parser performs frame header detection on the received Beacon control frames. When a Beacon control frame with a predefined EtherType and frame type identifier is identified, the global timestamp field is extracted, and the local superframe counter is forcibly reset or calibrated to ensure that the local time of the slave node is consistent with the global time of the master node.

6. The spaceborne optical switching method based on the superframe time slot mechanism according to claim 3, characterized in that, The process of performing propagation delay compensation and calculating the transmission window through the subordinate node is as follows: The slave node introduces a propagation delay compensation mechanism, which combines the local superframe time with the pre-estimated or measured inter-satellite propagation delay parameters to generate a virtual time for controlling the transmission behavior. The slave node performs a lookup operation on the locally stored Bitmap or time slot mapping information based on the virtual time to determine the position of the data time slot allocated to its own node in the current superframe. When a slave node detects that it is about to enter its own data time slot, it raises the transmit window control signal in advance.

7. The spaceborne optical switching method based on superframe time slot mechanism according to claim 3, characterized in that, The process of generating a REQ control frame within the signaling window through the subordinate node and sending the REQ control frame for reporting is as follows: When a slave node determines that the signaling window has entered its edge or has already been reached based on the synchronization result, the slave node reads the amount of data to be sent from its local FIFO, buffer, or service queue in real time, and encapsulates the amount of data to be sent as the service requirement value together with the node identification information into a REQ control frame. The REQ control frame is then sent to the master node in a high-priority manner through the sending arbitration module to ensure that the reporting is completed within the effective time of the signaling window, providing accurate requirement input for the centralized scheduling of the master node.

8. The spaceborne optical switching method based on the superframe time slot mechanism according to claim 3, characterized in that, The process by which the master node drives the optical switching matrix based on the data time slot mapping information in the Shadow Bank storage area at the start of the data exchange window is as follows: At each data time slot boundary, the optical switching execution module in the master node reads the corresponding time slot mapping information from the ActiveBank storage area according to the current time slot index, converts the mapping information into a control signal for the optical switching matrix, and then applies the control signal of the optical switching matrix to the optical switching matrix or optical switch array, so that the optical switching matrix or optical switch array completes optical path conduction, disconnection or path selection operations within the time slot boundary.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the spaceborne optical switching method based on the superframe time slot mechanism as described in any one of claims 3-8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the spaceborne optical switching method based on the superframe time slot mechanism as described in any one of claims 3-8.

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