A testing method, device, equipment and medium for a system on a chip

Abstract

The present application discloses a method, device, equipment and medium for testing a system on a chip, relating to the field of system-on-chip testing. The method includes: obtaining, through a preset information acquisition interface, attribute information saved in a preset format and corresponding to a debug access port in the system to be tested; generating an error corrector based on the attribute information and using a preset error corrector generation template; when connection success information indicating that the error corrector has successfully connected to the target host and the system to be tested is obtained, generating a test case through the error corrector and the attribute information; testing the system to be tested by the error corrector using the test case, and supervising and recording the data reading and writing process in the system to be tested during the testing process to obtain corresponding test logs, and then printing the test logs to a preset page by using a preset log printing function. This solution supervises and records the read and written data during the testing process through the created error corrector, improving the system verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of system - on - chip testing, and particularly to a testing method, device, equipment and medium for a system on a chip. Background Art

[0002] The Debug Access Port (DAP) is a typical way and component to access the debug function of a system on a chip. In recent years, it has been applied to various chips, especially more frequently in the Arm - series processors commonly used in embedded systems. It is usually composed of a Debug Port (DP) and an Access Port (AP). The former is mainly used to receive instructions from a host (usually outside the chip), and the latter is mainly used to access on - chip resources. Verification personnel perform read - write operations on the system on a chip through the debug access port passed in by the host and receive the return data from the system on a chip.

[0003] Currently, the most widely used in the market is the debug access port integrated based on the ADI specification of Arm (Acorn RISC Machine). However, during the application of the debug access port, many errors will occur. For example, when the host sends instructions too fast, the system on a chip receives the next instruction before the previous instruction that has not been executed yet, which will cause the next instruction to overwrite the previous unexecuted instruction and then lead to data - transmission errors. Or when the return value of the system on a chip has not been sent to the debug access port, the host requests data, which will also cause the return of incorrect data and then affect the reliability and integrity of verification. For these problems of data errors caused by unreasonable data - processing procedures in the debug access port, verification personnel can only choose the inefficient methods of increasing delay and trial - and - error to avoid the occurrence of such problems. However, inaccurate delays will reduce the performance of the system, and the trial - and - error process also wastes a lot of energy and time of verification personnel, thus resulting in low efficiency in the verification process of the system on a chip.

[0004] As can be seen from the above, in the process of verifying a system on a chip, how to avoid data errors caused by unreasonable data - processing procedures in the debug access port, and thus avoid the low efficiency of the verification process of the system on a chip is a problem to be solved in this field. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a testing method, device, equipment and medium for a system on a chip, which can create an error corrector between the system on a chip to be tested and the target host, and use the error corrector to optimize the data - processing procedure of the debug access port. The whole process greatly improves the correctness and rationality of data interaction and data transmission between the system to be tested and the target host, and thus improves the verification efficiency of the system to be tested. The specific solutions are as follows:

[0006] In a first aspect, the present application discloses a method for testing a system on a chip, including:

[0007] Obtaining, through a preset information acquisition interface, attribute information saved in a preset format and corresponding to a debug access port in the system to be tested;

[0008] Based on the attribute information, generating an error corrector by using a preset error corrector generation template;

[0009] When connection success information indicating that the error corrector has successfully connected to the target host and the system to be tested is obtained, generating a test case through the error corrector and the attribute information;

[0010] Testing the system to be tested by using the test case through the error corrector, and supervising and recording the data reading and writing process in the system to be tested during the test process to obtain corresponding test logs, and then printing the test logs to a preset page by using a preset log printing function.

[0011] Optionally, the obtaining, through a preset information acquisition interface, attribute information saved in a preset format and corresponding to a debug access port in the system to be tested includes:

[0012] Obtaining a target table file through a preset information acquisition interface;

[0013] Reading the target table file to obtain attribute information corresponding to a debug access port in the system to be tested; wherein the attribute information includes version information of the debug access port, attribute information of the debug port, and attribute information of the access port.

[0014] Optionally, the generating an error corrector based on the attribute information and using a pre-obtained error corrector generation template includes:

[0015] Generating an error corrector including a standard access function based on the attribute information and using a pre-obtained error corrector generation template;

[0016] Correspondingly, the generating a test case through the error corrector and the attribute information includes:

[0017] Generating a test case based on the attribute information and through the error corrector using the standard access function.

[0018] Optionally, the testing the system to be tested by using the test case through the error corrector, and supervising and recording the data reading and writing process in the system to be tested during the test process to obtain corresponding test logs includes:

[0019] Determine the operating mode of the error corrector; the operating mode of the error corrector includes a bypass mode or an in-depth mode;

[0020] Use the error corrector to test the system under test with the test case, and monitor and record the data reading and writing processes in the system under test during the test based on the operating mode to obtain corresponding test logs.

[0021] Optionally, monitoring and recording the data reading and writing processes in the system under test during the test based on the operating mode to obtain corresponding test logs, and then using a preset log printing function to print the test logs to a preset page, includes:

[0022] If the operating mode of the error corrector is the bypass mode, then when the error corrector monitors a target read / write instruction sent by the target host to the system under test, record the instruction information of the target read / write instruction, and forward the target read / write instruction to the system under test;

[0023] When the error corrector monitors the return data corresponding to the target read / write instruction returned by the system under test to the target host, record the return data, and forward the return data to the target host;

[0024] Based on the instruction information and return data of the target read / write instruction, determine abnormal execution instructions from all the target read / write instructions, generate abnormal instruction execution information based on the instruction information and return data of the abnormal execution instructions, and add the abnormal instruction execution information to a preset first test log;

[0025] Use a preset log printing function to print the first test log to a preset page.

[0026] Optionally, monitoring and recording the data reading and writing processes in the system under test during the test based on the operating mode to obtain corresponding test logs, and then using a preset log printing function to print the test logs to a preset page, includes:

[0027] If the operating mode of the error corrector is the in-depth mode, then when the error corrector monitors a target read / write instruction sent by the target host to the system under test, intercept the target read / write instruction, and store the instruction information of the target read / write instruction in the preset temporary storage space of the error corrector in chronological order;

[0028] If there is no currently executing instruction, extract a target instruction to be executed from all the target read / write instructions in the preset temporary storage space through the error corrector, and determine the operation type of the target instruction to be executed; the target instruction to be executed is the earliest deposited instruction in the preset temporary storage space;

[0029] Transmit the target instruction to be executed to the system under test through the error corrector, and perform signal detection on the system under test to determine whether the target instruction to be executed is successfully executed;

[0030] If the target instruction to be executed is successfully executed, determine the execution information generation rule of the target instruction to be executed based on the operation type of the target instruction to be executed, generate the instruction execution information of the target instruction to be executed, and then add the instruction execution information to a preset second test log;

[0031] Use a preset log printing function to print the second test log to a preset page.

[0032] Optionally, after adding the instruction execution information to the preset second test log, it further includes:

[0033] Redetermine and extract a target instruction to be executed from all the current target read / write instructions in the preset temporary storage space in the error corrector through the error corrector, determine the target instruction to be executed as the current target instruction to be executed, and then jump to the step of determining the operation type of the target instruction to be executed.

[0034] Optionally, determining the execution information generation rule of the target instruction to be executed based on the operation type of the target instruction to be executed to generate the instruction execution information of the target instruction to be executed includes:

[0035] If the operation type is a read operation, generate a read signal for reading the return data corresponding to the target instruction to be executed in the debug access port through the error corrector, so that after the debug access port receives the read signal, it sends the return data to the target host, and then generate the instruction execution information of the current target instruction to be executed according to the instruction information and the return data of the target instruction to be executed through the error corrector;

[0036] If the operation type is a write operation, generate the instruction execution information of the current target instruction to be executed according to the instruction information of the target instruction to be executed through the error corrector.

[0037] Optionally, the test method of the system on chip further includes:

[0038] Use the error corrector to detect the host frequencies of the target host and the system to be tested respectively, and determine the difference between the host frequencies of the target host and the system to be tested;

[0039] If the difference between the host frequencies of the target host and the system to be tested is greater than a preset difference threshold, generate a corresponding prompt message according to a preset prompt message generation rule, and display the prompt message in the test log.

[0040] In a second aspect, the present application discloses a test device for a system-on-chip, including:

[0041] An information acquisition module, configured to acquire attribute information saved in a preset format and corresponding to a debug access port in the system to be tested through a preset information acquisition interface;

[0042] An error corrector generation module, configured to generate an error corrector based on the attribute information and using a preset error corrector generation template;

[0043] A test case generation module, configured to generate a test case through the error corrector and the attribute information when connection success information indicating that the error corrector is successfully connected to the target host and the system to be tested is obtained;

[0044] A system test module, configured to test the system to be tested through the error corrector using the test case, and supervise and record the data reading and writing process in the system to be tested during the test process to obtain a corresponding test log, and then print the test log to a preset page using a preset log printing function.

[0045] In a third aspect, the present application discloses an electronic device, including:

[0046] A memory, configured to save a computer program;

[0047] A processor, configured to execute the computer program to implement the foregoing test method for a system-on-chip.

[0048] In a fourth aspect, the present application discloses a computer storage medium, configured to save a computer program; wherein, when the computer program is executed by a processor, the steps of the foregoing disclosed test method for a system-on-chip are implemented.

[0049] This application obtains attribute information corresponding to the debug access port in the system to be tested and saved in a preset format through a preset information acquisition interface; based on the attribute information, a corrector is generated using a preset corrector generation template; after obtaining the connection success information used to characterize that the corrector is successfully connected to the target host and the system to be tested, a test case is generated through the corrector and the attribute information; the system to be tested is tested using the test case through the corrector, and the data reading and writing process in the system to be tested during the test is supervised and recorded to obtain a corresponding test log, and then the test log is printed to a preset page using a preset log printing function. In this way, this solution creates a corrector between the system on chip to be tested and the target host, and uses the corrector to supervise and record the read and write data during the test, and then generates and displays the recorded test results in the form of a log to the verification personnel. The error corrector in this method is automatically generated for different systems to be tested. Users do not need to modify internal parameters by themselves. They only need to connect the automatically generated error corrector between the host end and the debug access port, which greatly improves the test efficiency of the system to be tested and reduces the time spent by the verification personnel to perform error correction on the debug access port for each different design to be tested. At the same time, this method is convenient for management and maintenance, improves the flexibility and efficiency of verification, and realizes the rapid integration and implementation of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0051] Figure 1 A flow chart of a system-on-chip testing method provided in this application;

[0052] Figure 2 An overall structural diagram provided for this application;

[0053] Figure 3 An implementation flow chart provided for this application;

[0054] Figure 4 A flowchart of a specific system-on-chip testing method provided in this application;

[0055] Figure 5 An implementation flow chart provided for this application;

[0056] Figure 6 A schematic diagram of the structure of a system-on-chip test device provided in this application;

[0057] Figure 7 A structural diagram of an electronic device provided for this application. Specific implementation manners

[0058] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0059] In the prior art, during the verification process of a system on a chip, data errors may occur due to unreasonable data processing in the debug access port, which may further lead to low efficiency in the verification process of the system on a chip. In this application, a test method for optimizing the data processing of the debug access port of the system on a chip is proposed, which can greatly improve the test efficiency of the system to be tested and reduce the large amount of time spent by verification engineers to correct errors in the debug access port for each different design to be tested.

[0060] An embodiment of the present invention discloses a test method for a system on a chip. Refer to Figure 1 As described, the method includes:

[0061] Step S11: Obtain, through a preset information acquisition interface, attribute information that is saved in a preset format and corresponds to the debug access port in the system to be tested.

[0062] In this embodiment, Figure 2 This is an overall structural diagram proposed by the present invention. The figure shows the connection relationship between the external host, error corrector, debug access port and the system to be tested in the present invention. The user mounts the error corrector defined and generated by the table file and script between the external host and the debug access port, so that it receives instructions from the host, return values of the debug access port, and partial port data of the access ports in the debug access port. The external host sends correct stimuli to the debug access port through the error corrector to complete the reading and writing of different resources in the system, so as to achieve the corresponding verification target.

[0063] It should be noted that the attribute information in this embodiment can be initially defined by the architecture engineer according to his own assumptions and requirements and then handed over to the design engineer and verification engineer. The design engineer integrates and connects the corresponding debug access ports in the system to be tested according to this information. After re-organizing and modifying, this information is handed over to the verification personnel for filling.

[0064] In this embodiment, obtaining, through a preset information acquisition interface, the attribute information saved in a preset format and corresponding to the debug access port in the system under test may include: obtaining a target table file through the preset information acquisition interface; reading the target table file to obtain the attribute information corresponding to the debug access port in the system under test in the target table file; where the attribute information includes the version information of the debug access port, the attribute information of the debug port, and the attribute information of the access port. It can be understood that the preset format in this embodiment may be a table format, including but not limited to the CSV format. In a specific implementation manner, the attribute information in this embodiment may include the version information of the debug access port, the attribute information of the debug port, and the attribute information of the access port. Table 1 is a table file of a debug access port. The attribute information of the debug access port in this table is filled in by the verification personnel. The debug access port includes a debug port of type JTAG-DP (JTAG: Joint Test Action Group), and two access ports, AP1 and AP2, which are AHB-AP and APB-AP respectively. The length of the IR is 4 respectively. And other information related to IDCODE and IDR.

[0065] Table 1

[0066]

[0067]

[0068] Step S12: Based on the attribute information, generate an error corrector using a preset error corrector generation template.

[0069] In this embodiment, the attribute information input by the verification personnel can be automatically obtained, and different error correctors can be generated based on a predefined template. The entire process is automatically completed based on a preset script tool without any manual intervention.

[0070] In a specific implementation manner, if the attribute information corresponding to the debug access port exists in a table format, the table file can be automatically read and analyzed, and then an error corrector can be generated in the form of a.v file using the table file and a predefined template. It should be noted that the preset script tool can be implemented using any scripting language. This tool will first read the table file predefined by us, and then generate an error corrector based on the attribute information in the table file and the predefined template.

[0071] Step S13: When connection success information indicating that the error corrector has been successfully connected to the target host and the system under test is obtained, generate a test case through the error corrector and the attribute information.

[0072] It should be noted that, in this embodiment, after the error corrector is generated, the user needs to connect the error corrector to the debugging access port of the target host and the system to be tested, that is, integrate it into the verification environment. After obtaining the connection success information indicating that the error corrector has been successfully connected to the target host and the system to be tested, it indicates that the current verification environment has been successfully integrated, and then test cases are generated through the error corrector and the attribute information. In a specific embodiment, the test cases can be reading and writing of different registers, accessing different addresses in the design under test through the debugging access port, setting the transmission mode, or reading IDCODE, etc. In a specific embodiment, the test cases are generated in the format of a.c file.

[0073] Step S14: Use the test cases to test the system to be tested through the error corrector, and supervise and record the data reading and writing processes in the system to be tested during the test process to obtain corresponding test logs, and then use a preset log printing function to print the test logs to a preset page.

[0074] It can be understood that after the test cases are generated by the error corrector, the error corrector will automatically execute the test cases. The test cases contain multiple data interaction commands between the system to be tested and the target host. During these data interactions, the error corrector will supervise and record the data reading and writing operations during these data interaction processes, and generate corresponding test logs.

[0075] Specifically, in this embodiment, the error corrector contains a set of standard access functions. By default, the error corrector can generate a set of basic use cases applicable to the current debugging access port and the current test system and covering all basic functions of the test, and these standard access functions will not make mistakes. In addition, after the test logs are generated, the verification personnel can also modify the test cases according to the test information in the test logs for the next test, so as to complete the debugging of the subsequent system to be tested. As Figure 3 shown is the flowchart of the automated implementation of the above process.

[0076] It should be noted that the test cases in this embodiment can also be pre-set by the user, that is, they do not need to be automatically generated by the error corrector in this embodiment. Instead, the pre-set test cases are directly input into the error corrector. At this time, the error corrector will no longer generate the basic use cases, but use the pre-set test cases to complete the user's targeted custom system test. Moreover, after the verification personnel perform a test on the system to be tested once, they can also create test cases according to the standard access functions in the error corrector to continue to complete the custom system test of the system to be tested.

[0077] In this embodiment, the method for testing the system on a chip may further include: using the error corrector to respectively detect the host frequencies of the target host and the system to be tested, and determining the difference between the host frequencies of the target host and the system to be tested; if the difference between the host frequencies of the target host and the system to be tested is greater than a preset difference threshold, generating corresponding prompt information according to a preset prompt information generation rule, and displaying the prompt information in the test log.

[0078] It can be understood that in this embodiment, the host frequencies of the target host and the system to be tested may also be detected, and when the difference between the host frequencies of the target host and the system to be tested is greater than a preset difference threshold, a prompt information is generated in the log to remind the user to modify relevant use cases and designs.

[0079] Figure 4 It is a flowchart of a specific method for testing a system on a chip provided by an embodiment of the present application. Refer to Figure 4 As shown, the method includes:

[0080] Step S21: Obtain a target table file through a preset information acquisition interface, and read the target table file to obtain attribute information corresponding to a debug access port in the system to be tested; wherein, the attribute information includes version information of the debug access port, attribute information of the debug port, and attribute information of the access port.

[0081] The preset format in this embodiment may be a table format, including but not limited to the CSV (i.e., Comma-Separated Values) format. In a specific implementation manner, the attribute information in this embodiment may include version information of the debug access port, attribute information of the debug port, and attribute information of the access port.

[0082] Step S22: Based on the attribute information, generate an error corrector including standard access functions by using a pre-obtained error corrector generation template.

[0083] It can be understood that in this embodiment, an error corrector including standard access functions can be generated by using a pre-obtained error corrector generation template.

[0084] Step S23: When connection success information indicating that the error corrector has successfully connected to the target host and the system to be tested is obtained, then based on the attribute information, generate test cases through the error corrector by using the standard access functions.

[0085] Such as Figure 5A flowchart of an implementation proposed in this embodiment is shown in the figure, which shows the relevant processes of generating test cases in this embodiment. Among them, after the verifier fills in the form, the form will be automatically read, and then an error corrector will be automatically generated according to the attribute information in the form. After waiting for the user to integrate the generated error corrector into the verification environment, the standard access function in the debug access port will be called, and test cases will be generated in combination with the attribute information in the form.

[0086] Step S24: Determine the operating mode of the error corrector; the operating modes of the error corrector include a bypass mode or an in-depth mode.

[0087] It should be noted that the error corrector in this embodiment can have two operating modes, namely, a bypass mode or an in-depth mode.

[0088] Step S25: Use the test cases to test the system under test through the error corrector, and supervise and record the data reading and writing processes in the system under test during the test based on the operating mode to obtain corresponding test logs, and then use a preset log printing function to print the test logs to a preset page.

[0089] For a typical debug access port that complies with the Arm-based ADI standard, it usually receives instructions from an external host as stimuli through the debug port. The debug port can be of two types, JTAG and Serial Wire, or both. Then, it accesses the resources in the system under test with different bus protocols through the corresponding access ports (such as AHB (i.e., Advanced High performance Bus), AXI (i.e., Advanced eXtensible Interface), APB (i.e., Advanced Peripheral Bus)).

[0090] In this embodiment, monitoring and recording the data reading and writing process in the system under test during the test based on the operating mode to obtain corresponding test logs, and then using a preset log printing function to print the test logs to a preset page may include: If the operating mode of the error corrector is the bypass mode, when the error corrector monitors a target read / write instruction sent by a target host to the system under test, record the instruction information of the target read / write instruction, and forward the target read / write instruction to the system under test; when the error corrector monitors the system under test returning return data corresponding to the target read / write instruction to the target host, record the return data, and forward the return data to the target host; based on the instruction information and return data of the target read / write instruction, determine an abnormally executed instruction from all the target read / write instructions, generate abnormal instruction execution information based on the instruction information and return data of the abnormally executed instruction, and add the abnormal instruction execution information to a preset first test log; use a preset log printing function to print the first test log to a preset page.

[0091] It can be understood that when the error corrector is in the bypass mode, the error corrector will not modify any commands from an external host, nor will it modify the data returned by the debug access port to the external host, but directly release the received interaction data. However, it should be noted that the error corrector will detect whether there are transmission errors in the interaction instructions based on the collected data. For example, if the host-side input instructions are too fast, the debug access port is forced to execute the next instruction before receiving the return value from the design under test, resulting in the situation where the previous instruction is not correctly executed. And in the bypass mode, the test logs generated by the error corrector record the discarded read / write instructions, that is, the instructions with abnormal execution. After determining the abnormal instructions, their matching simulation time will be added, and they will be printed out through the uvm_info function or the log file path specified by the user for the user to view. The user can judge whether the current test case has insufficient reliability and the specific location where it occurs based on these log files, and then make targeted modifications to avoid misjudgment caused by the recurrence of such errors. It should be noted that the functions for printing logs in this embodiment include but are not limited to the uvm_info function.

[0092] In this embodiment, monitoring and recording the data reading and writing process in the system under test based on the operating mode to obtain corresponding test logs, and then using a preset log printing function to print the test logs to a preset page may include: If the operating mode of the error corrector is the in-depth mode, when the error corrector monitors a target read / write instruction sent by a target host to the system under test, intercept the target read / write instruction, and store the instruction information of the target read / write instruction in the preset temporary storage space of the error corrector in chronological order; If there is no currently executing instruction, extract a target instruction to be executed from all the target read / write instructions in the preset temporary storage space through the error corrector, and determine the operation type of the target instruction to be executed; The target instruction to be executed is the instruction earliest stored in the preset temporary storage space; Transmit the target instruction to be executed to the system under test through the error corrector, and perform signal detection on the system under test to determine whether the target instruction to be executed is successfully executed; If the target instruction to be executed is successfully executed, determine the execution information generation rule of the target instruction to be executed based on the operation type of the target instruction to be executed, generate the instruction execution information of the target instruction to be executed, and then add the instruction execution information to a preset second test log; Use a preset log printing function to print the second test log to a preset page.

[0093] It can be understood that in this embodiment, when the error corrector mode is the in-depth mode, regardless of whether the operation type of the target instruction to be executed is a read operation or a write operation, it will be judged by comprehensively detecting signals related to the transmission correctness of the corresponding protocol (such as slverr, hready, etc.) whether the instruction is normally transmitted by the access port to the corresponding bus. At this time, it can also be used to reconfirm whether the current error corrector is compatible with the current version of the debug access port, that is, whether the attribute information input by the verifier is correct. If there is an error in the attribute information setting, corresponding log information will also be printed for reminder. Specifically, in this embodiment, the signal detection may specifically use the signal of MEM-AP for judgment.

[0094] In this embodiment, after adding the instruction execution information to the preset second test log, it may further include: Re-determine and extract a target instruction to be executed from all the current target read / write instructions in the preset temporary storage space of the error corrector through the error corrector, and determine the target instruction to be executed as the current target instruction to be executed, and then jump to the step of determining the operation type of the target instruction to be executed.

[0095] It can be understood that in this embodiment, when the error corrector mode is the in-depth mode, commands from the external host and data returned by the debug access port to the external host are intercepted, and the execution of each piece of data and command is monitored. After the execution of the previous command to be executed ends, the next instruction is sent and executed. When there is an instruction being executed currently, the received instructions are stored in the temporary storage area in the order of time. This can avoid the situation in the prior art where the host inputs instructions too quickly, causing the debug access port to be forced to execute the next instruction before receiving the return value from the design under test, resulting in the incorrect execution of the previous instruction, and also avoid the problem of incorrect data processing flow in accessing the debug port in the prior art, which easily leads to errors in data transmission. The error corrector in the in-depth mode ensures the correctness of data transmission and data interaction. And it is easy to understand that when the error corrector is in the in-depth mode, abnormal execution instructions such as those in the bypass mode will not appear in the test log because each instruction is executed completely. The following is an example of the integration of the error corrector and the error corrector print log in the in-depth mode proposed by the present invention:

[0096]

[0097]

[0098]

[0099] According to the test log, it can assist the verification personnel to accurately judge the test results of the system under test. And after obtaining the test log, the verification personnel can intuitively understand the data interaction process, which can assist the verification personnel to modify the test cases, and thus the improvement of the test cases can be achieved.

[0100] Determining the execution information generation rule of the target instruction to be executed based on the operation type of the target instruction to be executed to generate the instruction execution information of the target instruction to be executed, including: if the operation type is a read operation, using the error corrector to generate a read signal for reading the return data corresponding to the target instruction to be executed in the debug access port, so that after the debug access port receives the read signal, it sends the return data to the target host, and then the error corrector generates the instruction execution information of the current target instruction to be executed according to the instruction information and the return data of the target instruction to be executed; if the operation type is a write operation, using the error corrector to generate the instruction execution information of the current target instruction to be executed according to the instruction information of the target instruction to be executed.

[0101] It can be understood that during the data interaction between the system under test and the target host in this embodiment, the instructions sent by the target host to the system under test may be read operations or write operations. When the target instruction to be executed is a read operation command, the read operation command will be received by the debug port in the debug access port, and the access port in the debug access port will access the data inside the system under test to read the target data to be returned to the target host, and read the return value into the debug access port. At this time, when the error corrector monitors that the return data has been transmitted to the debug access port, it will simulate and generate a signal for the target host to read the return value, and send this read signal to the debug access port. When the debug access port receives this read signal, it will send the return value to the target host, finally complete the processing of the current target instruction to be executed, and then generate the corresponding test log. When the target instruction to be executed is a write operation command, the write operation command will be received by the debug port in the debug access port, and the access port will write the corresponding data to the target write location. At this time, no data will be returned to the debug access port, and the error corrector can directly generate the instruction execution information of the current target instruction to be executed according to the instruction information of the target instruction to be executed.

[0102] It should be noted that when the current target instruction to be executed is being executed, the remaining target read and write instructions will be temporarily stored in the error corrector. If the instruction temporary storage space is about to overflow, an error will be reported, and the specific error reason will be pointed out in the log, and the verification personnel will be reminded to modify the frequency or use cases.

[0103] In this embodiment, the error corrector generated by the automation script can be used to uniformly cover and solve the errors of the use cases related to the debug access port. Secondly, the present invention also provides standard access functions to allow users to generate more reliable use cases. Automatically generating the error corrector through the obtained table file reduces the requirements for the technical level of the verification personnel and the energy and events required to verify this function point. And the use cases developed for the debug access port can be quickly transplanted into the new design under test without modification for timing and delay, and can help the verification personnel detect whether there are such risks or errors in the existing system. The present invention also proposes a set of basic standard access functions for configuring and reading and writing the debug access port, which are placed in the header file. Used in combination with the error corrector, it can completely eliminate the errors caused by the delay of data transmission in the front-end verification. Through the above two points, use cases can be quickly established and tested, the testing of the debug access port can be accelerated, and the efficiency of relevant verification can be guaranteed. Finally, the present invention has strong extensibility and reusability, all of which are automatically generated by scripts. Users can generate the error corrector and test cases that meet the requirements according to the parameter definition and configuration file modification, which greatly saves the time for use case development. The application of the template makes the structure of the test cases more reasonable and standard.

[0104] SeeFigure 6 As shown in Figure 6 , an embodiment of the present application discloses a test device for a system on a chip, which may specifically include:

[0105] An information acquisition module 11, configured to acquire attribute information saved in a preset format and corresponding to a debug access port in the system to be tested through a preset information acquisition interface;

[0106] An error corrector generation module 12, configured to generate an error corrector based on the attribute information and by using a preset error corrector generation template;

[0107] A test case generation module 13, configured to generate a test case through the error corrector and the attribute information when connection success information for characterizing successful connection of the error corrector to a target host and the system to be tested is acquired;

[0108] A system test module 14, configured to test the system to be tested through the error corrector by using the test case, and supervise and record the data reading and writing process in the system to be tested during the test process to obtain a corresponding test log, and then print the test log to a preset page by using a preset log printing function.

[0109] The present application acquires attribute information saved in a preset format and corresponding to a debug access port in the system to be tested through a preset information acquisition interface; generates an error corrector based on the attribute information and by using a preset error corrector generation template; generates a test case through the error corrector and the attribute information when connection success information for characterizing successful connection of the error corrector to a target host and the system to be tested is acquired; tests the system to be tested through the error corrector by using the test case, and supervises and records the data reading and writing process in the system to be tested during the test process to obtain a corresponding test log, and then prints the test log to a preset page by using a preset log printing function. In this way, the present solution creates an error corrector between the system on a chip to be tested and a target host, uses the error corrector to supervise and record the read and write data during the test process, and then generates and displays the recorded test results in the form of a log to the verification personnel. The error corrector in this method is automatically generated for different systems to be tested. The user does not need to modify the internal parameters by himself / herself, and only needs to connect the automatically generated error corrector between the host end and the debug access port, which greatly improves the test efficiency of the system to be tested and reduces the large amount of time spent by the verification personnel on correcting the debug access port for each different design to be tested. At the same time, this method is convenient for management and maintenance, improves the flexibility and efficiency of verification, and realizes the rapid integration and implementation of verification.

[0110] Furthermore, an embodiment of the present application also discloses an electronic device, Figure 7It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment, and the content in the figure should not be regarded as any limitation on the scope of use of this application.

[0111] Figure 7 This is a schematic structural diagram of an electronic device 20 provided by an embodiment of this application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a display screen 24, an input / output port 25, a communication port 26, and a communication bus 27. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the test method of the system-on-chip disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0112] In this embodiment, the power supply 23 is used to provide working voltages for the various hardware devices on the electronic device 20; the communication port 26 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed on it here; the input / output port 25 is used to obtain external input data or output data to the outside, and its specific port type can be selected according to specific application requirements, and no specific limitation is made here.

[0113] In addition, as a carrier for resource storage, the memory 22 may be a read-only memory, a random access memory, a magnetic disk, or an optical disc, etc., and the resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0114] Among them, the operating system 221 is used to manage and control the various hardware devices and the computer program 222 on the electronic device 20, and it may be Windows Server, Netware, Unix, Linux, etc. In addition to the computer program that can be used to complete the test method of the system-on-chip executed by the electronic device 20 disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program that can be used to complete other specific tasks.

[0115] Furthermore, the present application also discloses a computer-readable storage medium, which includes a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, magnetic disks, optical disks, or any other form of storage medium known in the art. Among them, when the computer program is executed by a processor, it implements the on-chip system testing method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0116] The various embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and reference can be made to the method part for relevant details. Professionals can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professionals can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0117] The steps of the method or algorithm described in combination with the embodiments disclosed in this article can be directly implemented by hardware, a software module executed by a processor, or a combination of both. The software module can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0118] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0119] The above has introduced in detail the test method, device, equipment, and storage medium of the system on chip provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A test method for a system on a chip, characterized in that, Including: Obtaining, through a preset information acquisition interface, property information that is saved in a preset format and corresponds to a debugging access port in the system under test; Based on the property information, and using a preset error corrector generation template, generating an error corrector including standard access functions; After obtaining connection success information indicating that the error corrector has successfully connected to the target host and the system under test, based on the property information, and using the standard access functions through the error corrector, generating test cases; Using the error corrector to test the system under test with the test cases, and supervising and recording the data reading and writing processes in the system under test during the test process to obtain corresponding test logs, and then using a preset log printing function to print the test logs to a preset page.

2. The test method of the system on chip according to claim 1, characterized in that, The obtaining, through a preset information acquisition interface, of property information that is saved in a preset format and corresponds to a debugging access port in the system under test includes: Obtaining a target table file through a preset information acquisition interface; Reading the target table file to obtain property information corresponding to the debugging access port in the system under test in the target table file; wherein, the property information includes version information of the debugging access port, property information of the debugging port, and property information of the access port.

3. The test method for the system on chip according to claim 1, wherein The using the error corrector to test the system under test with the test cases, and supervising and recording the data reading and writing processes in the system under test during the test process to obtain corresponding test logs includes: Determining the operating mode of the error corrector; the operating mode of the error corrector includes a bypass mode or an in-depth mode; Using the error corrector to test the system under test with the test cases, and supervising and recording the data reading and writing processes in the system under test during the test process based on the operating mode to obtain corresponding test logs.

4. The test method for the system on a chip according to claim 3, wherein The supervising and recording the data reading and writing processes in the system under test during the test process based on the operating mode to obtain corresponding test logs, and then using a preset log printing function to print the test logs to a preset page includes: If the operating mode of the error corrector is the bypass mode, then when the error corrector monitors a target read / write instruction sent by the target host to the system under test, recording the instruction information of the target read / write instruction, and forwarding the target read / write instruction to the system under test; When the error corrector monitors return data corresponding to the target read / write instruction returned by the system under test to the target host, recording the return data, and forwarding the return data to the target host; Based on the instruction information and return data of the target read / write instruction, determining an abnormal execution instruction from all the target read / write instructions, and generating abnormal instruction execution information based on the instruction information and return data of the abnormal execution instruction, and adding the abnormal instruction execution information to a preset first test log; Using a preset log printing function to print the first test log to a preset page.

5. The test method of the system on chip according to claim 3, characterized in that Monitoring and recording the data reading and writing process in the system under test during the test based on the operating mode to obtain corresponding test logs, and then using a preset log printing function to print the test logs to a preset page, including: If the operating mode of the error corrector is the in-depth mode, when the error corrector monitors a target read / write instruction sent by the target host to the system under test, intercept the target read / write instruction and store the instruction information of the target read / write instruction in the preset temporary storage space of the error corrector in chronological order; If there is no instruction in execution currently, extract a target instruction to be executed from all the target read / write instructions in the preset temporary storage space through the error corrector, and determine the operation type of the target instruction to be executed; the target instruction to be executed is the instruction that was stored earliest in the preset temporary storage space; Transmit the target instruction to be executed to the system under test through the error corrector, and perform signal detection on the system under test to determine whether the target instruction to be executed is successfully executed; If the target instruction to be executed is successfully executed, determine the generation rule of the execution information of the target instruction to be executed based on the operation type of the target instruction to be executed, to generate the instruction execution information of the target instruction to be executed, and then add the instruction execution information to a preset second test log; Use a preset log printing function to print the second test log to a preset page.

6. The test method for the system on chip according to claim 5, characterized in that, After adding the instruction execution information to the preset second test log, it further includes: Redetermine and extract a target instruction to be executed from all the current target read / write instructions in the preset temporary storage space of the error corrector through the error corrector, and determine the target instruction to be executed as the current target instruction to be executed, and then jump to the step of determining the operation type of the target instruction to be executed.

7. The test method of the system on chip according to claim 5, characterized in that Determining the generation rule of the execution information of the target instruction to be executed based on the operation type of the target instruction to be executed to generate the instruction execution information of the target instruction to be executed includes: If the operation type is a read operation, use the error corrector to generate a read signal for reading the return data corresponding to the target instruction to be executed in the debug access port, so that after the debug access port receives the read signal, it sends the return data to the target host, and then use the error corrector to generate the instruction execution information of the current target instruction to be executed according to the instruction information and the return data of the target instruction to be executed; If the operation type is a write operation, use the error corrector to generate the instruction execution information of the current target instruction to be executed according to the instruction information of the target instruction to be executed.

8. The testing method of the system on chip according to any one of claims 1 to 7, characterized in that, It further includes: Use the error corrector to detect the host frequencies of the target host and the system under test respectively, and determine the difference between the host frequencies of the target host and the system under test; If the difference between the host frequency of the target host and that of the system under test is greater than a preset difference threshold, a corresponding prompt message is generated according to a preset prompt message generation rule, and the prompt message is displayed in the test log.

9. A test device for a system-on-chip, characterized in that Including: An information acquisition module, configured to acquire, through a preset information acquisition interface, attribute information saved in a preset format and corresponding to a debugging access port in the system under test; An error corrector generation module, configured to generate an error corrector including a standard access function based on the attribute information and by using a preset error corrector generation template; A test case generation module, configured to, when connection success information indicating that the error corrector has successfully connected to the target host and the system under test is acquired, generate a test case based on the attribute information and by using the standard access function through the error corrector; A system test module, configured to test the system under test by using the test case through the error corrector, supervise and record the data reading and writing process in the system under test during the test to obtain a corresponding test log, and then print the test log to a preset page by using a preset log printing function.

10. An electronic device, characterized in that, Including a processor and a memory; wherein, when the processor executes a computer program saved in the memory, the test method of the system on chip according to any one of claims 1 to 8 is implemented.

11. A computer-readable storage medium, characterized in that, For storing a computer program; wherein, when the computer program is executed by a processor, the test method of the system on chip according to any one of claims 1 to 8 is implemented.

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