Data pre-fetching method, processor and electronic device

Abstract

The present application relates to the field of chip technology, and discloses a data pre-fetching method, a processor and an electronic device. The processor includes a computing unit, a cache unit and a pre-fetcher; the pre-fetcher includes: a pre-fetch address generation circuit, which is used to assign multiple historical access addresses of the computing unit to multiple preset groups according to preset rules, and record the number of matches between multiple historical access addresses and the step distances recorded in each preset group, and when the number of matches meets the preset conditions, obtain the pre-fetch address based on the historical access address recorded in the first preset group, wherein the first preset group is one of the multiple preset groups, and the historical access address recorded in the first preset group is an equally spaced address sequence; the pre-fetch circuit is used to obtain data corresponding to the pre-fetch address from a memory outside the processor, and store the obtained data in the cache unit. In this way, it is beneficial to reduce the circuit area occupied by the processor while ensuring the pre-fetching function of the processor.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a data pre-fetching method, a processor and an electronic device. Background Art

[0002] With the development of chip technology, memory access latency has gradually become an important factor limiting processor performance and efficiency. In order to improve the latency of processor access to memory, a cache and a prefetcher are usually set in the processor. The prefetcher predicts the prefetch address that the processor may access based on the historical access address of the processor to the off-chip memory (i.e., the memory outside the processor), and stores the data corresponding to the prefetch address from the off-chip memory in the cache. Therefore, when the processor accesses the data corresponding to the prefetch address, it can directly read the data from the cache. Since the speed at which the processor accesses the cache is much higher than the speed at which it accesses the off-chip memory, the memory access latency is reduced.

[0003] However, the prefetcher can usually only give a prefetch address when the historical access address includes multiple consecutive equally spaced addresses. For example, when the historical access address includes three consecutive addresses X, X+A, and X+2A, it can be predicted that the processor may access address X+3A next, and the prefetcher gives a prefetch address X+3A. However, when the historical access address includes multiple groups of equally spaced address sequences, but there are other addresses between the same group of equally spaced address sequences, the prefetcher cannot predict the prefetch address. For example, when the historical access address is X, Y, X+B, Y+C, X+2B, X+3B, and Y+2C, although the historical access address includes two groups of equally spaced address sequences (X, X+2B, X+3B and Y, Y+C, and Y+2C), the prefetcher cannot identify the equally spaced address sequence, resulting in the prefetcher being unable to give a prefetch address, so that the processor can only read data from the off-chip memory, affecting the performance of the processor. Summary of the invention

[0004] The embodiments of the present application provide a prefetch method, a processor and an electronic device. Based on a prefetcher, an evenly spaced address sequence in multiple historical access addresses of a processor can be identified, and data prefetching is performed based on the identified evenly spaced address sequence, which is beneficial to reducing the circuit area occupied by the processor.

[0005] In a first aspect, an embodiment of the present application provides a data pre-fetching method, which is applied to an electronic device, the electronic device comprising: a processor and a memory arranged outside the processor, wherein the processor comprises a cache unit; and the method comprises:

[0006] Get multiple historical access addresses of the processor;

[0007] Allocate multiple historical access addresses to multiple preset groups according to preset rules, and record the number of matches between the multiple historical access addresses and the step distance recorded in each preset group, wherein the step distance is used to indicate the difference between the two most recently allocated historical access addresses of the preset group;

[0008] When the number of matches meets a preset condition, obtaining a pre-fetch address based on a historical access address recorded in a first preset group, wherein the first preset group is one of a plurality of preset groups, and the historical access address recorded in the first preset group is an equally spaced address sequence;

[0009] The data corresponding to the pre-fetch address is obtained from the memory, and the obtained data is stored in the cache unit.

[0010] Through the method provided by the embodiment of the present application, multiple historical access addresses of the processor (i.e., memory addresses hereinafter) are grouped according to preset rules, and the number of matches (e.g., confidence count values ​​hereinafter) between multiple historical access addresses and the step distances recorded in each preset grouping (i.e., address stream grouping hereinafter) is recorded. When the number of matches meets the preset conditions, the pre-fetch address is obtained based on the historical access address in the preset grouping of the recorded historical access address in the multiple preset groups as an evenly spaced address sequence, and the data corresponding to the pre-fetch address is stored in the cache unit. In this way, the processor does not need to increase the number of pre-fetchers, and only one pre-fetcher is used to realize the identification of the evenly spaced address sequence in the multiple historical access addresses, but the evenly spaced address sequence is not a connected access, and pre-fetching is performed based on the identified evenly spaced address sequence, which not only ensures the pre-fetching function of the processor, but also does not need to increase the number of pre-fetchers, which is beneficial to reducing the circuit area occupied by the processor.

[0011] It can be understood that in some embodiments, the above-mentioned preset condition may include the number of matches reaching a preset number of matches.

[0012] It can be understood that, in some embodiments, the pre-fetch address can be obtained by adding the previous address recorded in the first preset group to the step distance.

[0013] In a possible implementation of the first aspect, each preset group includes a previous address, a step distance, a step distance identifier, an address identifier, and a pre-fetch identifier; wherein,

[0014] The previous address is used to indicate the most recently allocated historical access address in the preset group.

[0015] When the step size mark is valid, it is used to indicate that the step size is a valid step size, wherein the valid step size refers to the step size whose absolute value is less than the preset step size value;

[0016] When the address identifier is valid, it is used to indicate that the preset group has recorded the memory address.

[0017] When the pre-fetch flag is valid, it is used to indicate that a pre-fetch address has been generated based on a preset grouping.

[0018] In a possible implementation of the first aspect, allocating the multiple historical access addresses to multiple preset groups according to a preset rule includes:

[0019] In a case where the first historical access address matches a second preset group among the plurality of preset groups, allocating the first historical access address to the second preset group, wherein the first historical access address is any one of the plurality of historical access addresses;

[0020] In the absence of a preset group matching the first historical access address, the first historical access address is assigned to a third preset group, where the third preset group is one of the preset groups with the lowest priority among multiple preset groups, wherein the priority of the preset group is determined by the step identifier, address identifier and prefetch identifier in the preset group.

[0021] In a possible implementation of the first aspect, allocating the first historical access address to the second preset group includes:

[0022] updating the step size of the second preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded in the second preset group, and setting the step size flag of the second preset group to be valid if the updated step size is a valid step size;

[0023] The previous address of the second preset group is updated to the first historical access address.

[0024] In a possible implementation of the first aspect, allocating the first historical access address to the third preset group includes:

[0025] Update the step size of the third preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded in the third preset group, and set the step size flag of the third preset group to be valid if the updated step size is a valid step size, and set the step size flag of the third preset group to be invalid if the updated step size is an invalid step size;

[0026] Updating the previous address of the third preset group to the first historical access address;

[0027] The address identifier of the third preset group is updated to be valid.

[0028] In a possible implementation of the first aspect, when the step length of the first historical access address matches the second preset group record, determining that the first historical access address matches the second preset group record;

[0029] Alternatively, when the first historical access address does not match the step length of any preset group record, the second preset group record has a previous address, the step length identifier of the second preset group is invalid, and the difference between the first historical address and the previous address in the second preset group is a valid step length, it is determined that the first historical access address matches the second preset group;

[0030] When the difference between the first historical access address and the previous address recorded in the preset group is the same as the step length recorded in the preset group, the first historical access address matches the step length recorded in the preset group.

[0031] In a possible implementation of the first aspect, the priority of the preset group is determined by a step identifier, an address identifier, and a pre-fetch identifier in the preset group, including:

[0032] The preset group with a valid pre-fetch identifier has the first priority;

[0033] The preset group whose pre-fetching identifier is invalid but whose step identifier is valid has the second priority;

[0034] The preset group whose pre-fetch identifier and step identifier are invalid but whose address identifier is valid has the third priority;

[0035] The preset group whose pre-fetch identifier, step identifier and address identifier are all invalid has the fourth priority;

[0036] Among them, the priorities are, from high to low, the first priority, the second priority, the third priority, and the fourth priority.

[0037] In a possible implementation of the first aspect, the recording of the number of matches between the plurality of historical access addresses and the step lengths of each preset group record includes:

[0038] When the first historical access address matches the step length of the second preset group record, the number of matches is increased;

[0039] When the first historical access address matches the step length recorded in the second preset group, and the pre-fetch flag of the second preset group is valid, the number of matches is reset.

[0040] In a possible implementation of the first aspect, the method further includes:

[0041] Recording the number of resets, where the number of resets indicates the number of times that the plurality of historical access addresses do not match the step lengths of any preset groupings, and the number of resets increases when the first historical access address does not match the step lengths of any preset grouping records, and is reset when the first historical access address matches the step lengths of any preset grouping records;

[0042] When the reset times reach the preset reset times, the data, reset times, and matching times in each preset group are reset.

[0043] In an embodiment of the present application, the electronic device can record the number of reset times (for example, the reset count value mentioned below) among multiple historical access addresses. If a preset number of consecutive historical access addresses do not match each preset grouping, it means that no equally spaced address sequence is recorded in each current preset grouping, or the equally spaced address sequence has ended. Re-identification can be achieved by resetting the data, reset times, and match times in each preset grouping, which is beneficial to improving the speed at which the electronic device recognizes the next equally spaced address sequence.

[0044] In a possible implementation of the first aspect, obtaining the pre-fetch address based on the historical access address recorded in the first preset group includes:

[0045] The previous address recorded in the first preset group is added to the step size to obtain a pre-fetch address.

[0046] In a possible implementation of the first aspect, obtaining the pre-fetch address based on the historical access address recorded in the first preset group further includes:

[0047] The pre-fetch flag recorded in the first preset group is set to be valid.

[0048] In a possible implementation of the first aspect, the preset condition includes: the number of matches reaches a preset number of matches.

[0049] In a second aspect, an embodiment of the present application provides a processor, the processor comprising a computing unit, a cache unit and a prefetcher; wherein the prefetcher comprises:

[0050] A pre-fetch address generation circuit is used to allocate multiple historical access addresses of the computing unit to multiple preset groups according to a preset rule, and record the number of matches between the multiple historical access addresses and the step distance recorded in each preset group, wherein the step distance is used to indicate the difference between the two most recently allocated historical access addresses of the preset group.

[0051] and obtaining a pre-fetch address based on a historical access address recorded in a first preset group when the number of matches meets a preset condition, wherein the first preset group is one of a plurality of preset groups, and the historical access address recorded in the first preset group is an equally spaced address sequence;

[0052] The prefetch circuit is used to obtain data corresponding to the prefetch address from a memory outside the processor and store the obtained data in a cache unit.

[0053] Through the processor provided by the embodiment of the present application, the pre-fetch address generation circuit groups multiple historical access addresses of the processor (i.e., the memory address hereinafter) by preset rules, records the number of matches between the multiple historical access addresses and the step distances recorded in each preset group (i.e., the address stream group hereinafter), and when the number of matches meets the preset conditions, obtains the pre-fetch address based on the historical access addresses in the preset group of the recorded historical access addresses as the equal-spaced address sequence in the multiple preset groups, and uses the pre-fetch circuit (e.g., the pre-fetch instruction generation circuit hereinafter) to store the data corresponding to the pre-fetch address in the cache unit. In this way, the processor does not need to increase the number of pre-fetchers, and only uses one pre-fetcher to realize the case where the equal-spaced address sequence is included in multiple historical access addresses, but the equal-spaced address sequence is not a connected access, identifies the equal-spaced address sequence, and performs pre-fetching based on the identified equal-spaced address sequence, which not only ensures the pre-fetching function of the processor, but also does not need to increase the number of pre-fetchers, which is conducive to reducing the circuit area occupied by the processor.

[0054] In a possible implementation of the second aspect, the prefetcher further includes:

[0055] A storage unit is used to store a plurality of preset groups, and each preset group includes a prior address, a step distance, a step distance identifier, an address identifier and a pre-fetch identifier; wherein,

[0056] The previous address is used to indicate the most recently allocated historical access address in the preset group.

[0057] When the step size mark is valid, it is used to indicate that the step size is a valid step size, wherein the valid step size refers to the step size whose absolute value is less than the preset step size value;

[0058] When the address identifier is valid, it is used to indicate that the preset group has recorded the memory address.

[0059] When the pre-fetch flag is valid, it is used to indicate that a pre-fetch address has been generated based on a preset grouping.

[0060] In a possible implementation of the second aspect, the pre-fetch address generation circuit allocates the multiple historical access addresses to the multiple preset groups according to the preset rule in the following manner:

[0061] The pre-fetch address generation circuit allocates the first historical access address to the second preset group when the first historical access address matches a second preset group among the plurality of preset groups, wherein the first historical access address is any one of the plurality of historical access addresses;

[0062] In the absence of a preset group matching the first historical access address, the first historical access address is assigned to a third preset group, where the third preset group is one of the preset groups with the lowest priority among multiple preset groups, wherein the priority of the preset group is determined by the step identifier, address identifier and prefetch identifier in the preset group.

[0063] In a possible implementation of the second aspect, the pre-fetch address generation circuit assigns the first historical access address to the second preset group, including:

[0064] The pre-fetch address generation circuit updates the step size of the second preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded in the second preset group, and sets the step size flag of the second preset group to be valid if the updated step size is a valid step size;

[0065] The pre-fetch address generation circuit updates the previous address of the second preset group to the first historical access address.

[0066] In a possible implementation of the second aspect, the pre-fetch address generation circuit assigns the first historical access address to the third preset group, including:

[0067] The pre-fetch address generation circuit updates the step size of the third preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded in the third preset group, and sets the step size identifier of the third preset group to be valid if the updated step size is a valid step size, and sets the step size identifier of the third preset group to be invalid if the updated step size is an invalid step size;

[0068] The pre-fetch address generation circuit updates the previous address of the third preset group to the first historical access address;

[0069] The pre-fetch address generation circuit updates the address identifier of the third preset group to be valid.

[0070] In a possible implementation of the second aspect, the pre-fetch address generation circuit determines that the first historical access address matches the second preset grouping when the step length of the first historical access address matches the step length of the second preset grouping record;

[0071] Alternatively, when the first historical access address does not match the step length of any preset group record, the second preset group record has a previous address, the step length identifier of the second preset group is invalid, and the difference between the first historical address and the previous address in the second preset group is a valid step length, it is determined that the first historical access address matches the second preset group;

[0072] The pre-fetch address generation circuit determines that the first historical access address matches the step length recorded in the preset group when the difference between the first historical access address and the previous address recorded in the preset group is the same as the step length recorded in the preset group.

[0073] In a possible implementation of the second aspect, the priority of the preset group is determined by a step identifier, an address identifier, and a pre-fetch identifier in the preset group, including:

[0074] The preset group with a valid pre-fetch identifier has the first priority;

[0075] The preset group whose pre-fetching identifier is invalid but whose step identifier is valid has the second priority;

[0076] The preset group whose pre-fetch identifier and step identifier are invalid but whose address identifier is valid has the third priority;

[0077] The preset group whose pre-fetch identifier, step identifier and address identifier are all invalid has the fourth priority;

[0078] Among them, the priorities are, from high to low, the first priority, the second priority, the third priority, and the fourth priority.

[0079] In a possible implementation of the second aspect, the prefetcher further includes a first counter, and the prefetch address generation circuit records the number of matches between the plurality of historical access addresses and the step lengths of each preset group record through the first counter; and

[0080] The pre-fetch address generation circuit increases the count value of the first counter when the first historical access address matches the step length of the second preset group record;

[0081] The pre-fetch address generating circuit resets the count value of the first counter when the first historical access address matches the step length of the second preset group record and the pre-fetch flag of the second preset group is valid.

[0082] In the embodiment of the present application, the processor records the number of matches between the multiple historical access addresses and the step distances of each preset group record through a first counter (eg, a confidence counter referred to below).

[0083] In a possible implementation of the second aspect, the prefetcher further includes a second counter, the second counter being used to record the number of times that the first historical access address does not match the step length of any preset grouping; and

[0084] The pre-fetch address generation circuit is further used to increase the count value of the second counter when the first historical access address does not match the step length of any preset group record, and reset the count value of the second counter when the first historical access address matches the step length of any preset group record;

[0085] And when the count value of the second counter reaches a preset reset number of times, the data in each preset group, the count value of the first counter, and the count value of the second counter are reset.

[0086] In an embodiment of the present application, the processor uses a second counter (such as the reset counter mentioned below) to record the number of times that the first historical access address does not match the step size of any preset group, and when the count value of the second counter reaches the preset reset number, the data in each preset group, the count value of the first counter, and the count value of the second counter are reset, which is beneficial to improving the speed at which the processor recognizes the next equally spaced address sequence.

[0087] In a possible implementation of the second aspect, the pre-fetch address generation circuit obtains the pre-fetch address based on the historical access address recorded in the first preset group in the following manner:

[0088] The pre-fetch address generation circuit adds the previous address recorded in the first preset group to the step distance to obtain the pre-fetch address.

[0089] In a possible implementation of the second aspect, the pre-fetch address generation circuit is further configured to set the pre-fetch flag recorded in the first preset group as valid when the pre-fetch address is obtained based on the historical access address recorded in the first preset group.

[0090] In a possible implementation of the second aspect, the preset condition includes: the number of matches reaches a preset number of matches.

[0091] In a third aspect, an embodiment of the present application provides an electronic device including a memory, and the second aspect and any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] Figure 1 According to some embodiments of the present application, a schematic diagram of the structure of a processor 1 is shown;

[0093] Figure 2 According to some embodiments of the present application, a schematic diagram of a process in which the prefetcher 13 performs data prefetching based on a memory address sequence is shown;

[0094] Figure 3 According to some embodiments of the present application, a schematic diagram of the structure of a processor 1' is shown;

[0095] Figure 4 According to some embodiments of the present application, a schematic diagram of a process in which the address allocation unit 17 uses the prefetchers 13A to 13D to prefetch data based on a memory address sequence is shown;

[0096] Figure 5 According to some embodiments of the present application, a schematic diagram of prioritizing address flow packets is shown;

[0097] Figure 6 According to some embodiments of the present application, a schematic diagram of a process in which a pre-fetch address generation circuit generates a pre-fetch address based on a memory address sequence is shown;

[0098] Figure 7 According to some embodiments of the present application, a schematic diagram of the structure of a prefetcher 2 is shown;

[0099] Figure 8 According to some embodiments of the present application, a schematic diagram of the structure of a processor 1" is shown;

[0100] Fig. 9 According to some embodiments of the present application, a schematic diagram of a process of data prefetching by a processor 1" is shown;

[0101] Fig.10 According to some embodiments of the present application, a schematic structural diagram of an electronic device 100 is shown. DETAILED DESCRIPTION

[0102] Illustrative embodiments of the present application include, but are not limited to, a data pre-fetching method, a processor, and an electronic device.

[0103] The technical solution of the embodiments of the present application is described below in conjunction with the accompanying drawings.

[0104] Figure 1 According to some embodiments of the present application, a schematic structural diagram of a processor 1 is shown.

[0105] like Figure 1 As shown, the processor 1 includes a computing unit 11, an access unit 12, a prefetcher 13, a prefetch cache 14, a bus interface 15 and a cache unit 16. The prefetcher 13 includes an equally spaced address sequence recognition circuit 131, a state cache unit 132 and a prefetch instruction generation circuit 133.

[0106] The calculation unit 11 is used to send an instruction address sequence to the access unit 12 according to the execution instruction and the demand for data in the executed instruction, when the data accessed by the instruction is batch data.

[0107] The load store unit (LSU) 12 is used to convert the instruction address in the instruction address sequence sent by the computing unit into a memory address sequence and send it to the prefetcher 13 .

[0108] The equally spaced address sequence recognition circuit 131 is used to recognize the equally spaced address sequence in the memory address sequence, and generate a pre-fetch address according to the last address and interval of the recognized equally spaced address sequence, and send the pre-fetch address to the pre-fetch instruction generation circuit 133. Generally, the equally spaced address sequence recognition circuit 131 records the difference between two adjacent received memory addresses (i.e., stride), and the hit count (i.e., the number of times the stride is the same continuously), and gives a pre-fetch address (the sum of the most recently received memory address and the stride) when the hit count is greater than or equal to the preset hit count. For example, assuming that the preset hit count is 2, when the received memory address is X, X+A, X+2A (A is the stride), the pre-fetch address X+3A can be given. In other words, the equally spaced address sequence recognition circuit 131 can only recognize the equally spaced address sequence when there are no other addresses between the addresses of the equally spaced address sequence in the memory address sequence.

[0109] It can be understood that the equally spaced address sequence refers to an address sequence consisting of a plurality of addresses forming an arithmetic progression.

[0110] The status cache unit 132 is used to store the type corresponding to each memory address, such as security data or normal data.

[0111] The prefetch instruction generation circuit 133 is used to determine whether the received prefetch address meets the prefetch condition according to the received prefetch address, and send the prefetch instruction to the bus interface 15 through the prefetch cache 14 if the prefetch address meets the prefetch condition.

[0112] It can be understood that the pre-fetch condition includes: the address pointed to by the pre-fetch address is the address of the off-chip memory, the data corresponding to the pre-fetch address is not stored in the cache unit 16, and the data corresponding to the pre-fetch address and each memory address in the memory address sequence are of the same type (all are secure data or ordinary data). In other embodiments, the pre-fetch condition may also include other conditions, which are not limited here.

[0113] The prefetch cache 14 is used to store prefetched data obtained from the bus interface 15, and when the prefetched data obtained reaches a preset data amount, the prefetched data is sent to the cache unit 16 through the bus interface 15, or when the interval from the last time the prefetched data was sent to the cache unit 16 reaches a preset time length, the prefetched data is sent to the cache unit 16 through the bus interface 15.

[0114] The bus interface 15 is a communication interface between the prefetcher 13, the prefetch cache 14, the cache unit 16 and the off-chip memory SC.

[0115] When the instruction executed by the computing unit 11 needs to access a large amount of data, the address to be accessed by the instruction (instruction address sequence) can be sent to the LSU 12, and the LSU 12 converts the instruction address sequence into a memory address sequence and sends it to the prefetcher 13; the prefetch address generation circuit 13 predicts the address that the processor may access (hereinafter referred to as the prefetch address) according to each address sequence in the memory address sequence, when the memory address sequence stores connected addresses with equal intervals, and sends the prefetch address to the prefetch instruction generation circuit 133; after receiving the prefetch address, the prefetch instruction generation circuit 133 sends a prefetch instruction to the prefetch cache 14 when the prefetch address meets the prefetch condition; the prefetch cache 14 can obtain the prefetch data corresponding to the prefetch instruction from the off-chip memory SC, store the prefetch data in the prefetch cache 14, and when the obtained prefetch data reaches a preset data amount, or when the interval from the last time the prefetch data was sent to the cache unit 16 reaches a preset time length, the prefetch data is sent to the cache unit 16 through the bus interface 15. In this way, when the computing unit 11 executes an instruction, if it needs to access the data corresponding to the prefetch address, it can directly obtain the prefetched data from the cache unit 16, thereby reducing the delay for the computing unit to obtain the data corresponding to the prefetch address and improving the performance and efficiency of the processor.

[0116] However, in general, the storage address sequence corresponding to the instruction address sequence sent by the computing unit 11 is usually not a continuous access to an equally spaced address sequence (for example, the computing unit 11 executes multiple instructions in parallel, or the data corresponding to the instruction includes multiple groups of equally spaced address sequences but the same group of equally spaced address sequences includes other addresses), resulting in the equally spaced address sequence recognition circuit 131 being unable to recognize the equally spaced address sequence, and unable to predict the pre-fetch address based on the recognized equally spaced address sequence, thereby resulting in the computing unit 11 being able to only obtain data from the off-chip memory SC, affecting the performance and efficiency of the processor. For example, when the computing unit 11 executes instructions related to image processing, since a pixel in an image usually includes multiple color channels, and data of a color channel is usually stored in adjacent storage spaces, and instructions related to image processing usually need to process data of multiple color channels, resulting in the instruction address sequence sent by the computing unit 11 usually including multiple groups of equally spaced address sequences, but each group of equally spaced address sequences usually includes addresses in other equally spaced address sequences.

[0117] For example, refer to Figure 2, assuming that the memory address sequence corresponding to the instruction address sequence sent by the computing unit 11 is 0-1000-2-1001-4-500-13-1002-14-50-15-501-502-6, the memory address sequence includes four groups of equally spaced address sequences, namely, equally spaced address sequence 0-2-4-6, equally spaced address sequence 1000-1001-1002, equally spaced address sequence 500-501-502 and equally spaced address sequence 13-14-15. The equally spaced address sequence recognition circuit 131 determines the corresponding address, step size and hit count when each memory address is received by comparing two adjacent memory addresses. Since there are no continuous equally spaced addresses in the memory address sequence, the hit count cannot reach the preset hit count value. As a result, even if the memory address sequence includes four groups of equally spaced address sequences, the equally spaced address sequence recognition circuit 131 cannot recognize the equally spaced address sequence, and thus cannot provide a prefetch address, resulting in the computing unit 11 being able to read data only from the off-chip memory SC, which increases the delay in the processor 1 reading data and affects the performance and efficiency of the processor.

[0118] In order to solve the above problem, in some embodiments, the number of prefetchers in the processor can be increased and an address allocation unit can be added to the processor, so that the address allocation unit can allocate addresses belonging to the same equally spaced address sequence in the memory address sequence to the same prefetcher, so that when the memory address sequence includes an equally spaced address sequence but the addresses of the equally spaced address sequence include other addresses, the equally spaced address sequence can be identified, and data prefetching can be performed based on the identified equally spaced address sequence, thereby improving the performance and efficiency of the processor.

[0119] For example, Figure 3 According to an embodiment of the present application, a schematic structural diagram of a processor 1 ′ including multiple prefetchers is shown.

[0120] like Figure 3 As shown, the processor 1' includes a computing unit 11, an access unit 12, a prefetcher 13A, a prefetcher 13B, a prefetcher 13C, a prefetcher 13D, a prefetch cache 14, a bus interface 15, a cache unit 16 and an address allocation unit 17. The structure of each prefetcher can refer to the structure of the aforementioned prefetcher 13, and the functions and effects of the computing unit 11, the access unit 12, the prefetch cache 14, the bus interface 15 and the cache unit 16 can refer to the description of the aforementioned processor 1, which will not be repeated here.

[0121] The address allocation unit 17 is used to allocate each address in the memory address sequence received from the LSU 12 to each prefetcher, so that a prefetcher can give a prefetch address based on the allocated memory address. Specifically, assuming that the memory address sequence corresponding to the instruction address sequence sent by the computing unit 11 is 0-1000-2-1001-4-500-13-1002-14-50-15-501-502-6, refer to Figure 4 The address allocation unit 17 receives and allocates the processing cycles of each address in the address sequence from T1 to T14.

[0122] Specifically, the address allocation unit 17 can allocate the received memory address to any prefetcher when none of the prefetchers have stored the previous address. For example, the address allocation unit 17 allocates address 0 to the prefetcher 13A in the T1 processing cycle, so that the previous address, stride, and hit count recorded by the prefetcher 13A are 0, 0, and 0, respectively.

[0123] The address allocation unit 17 can allocate the received address to the prefetcher that does not store the previous address when the difference between the received memory address and the previous address in each prefetcher is greater than the preset value, and the difference is different from the step size in the corresponding prefetcher, and there is a prefetcher that does not store the previous address. For example, the address allocation unit 17 compares the address 1000 with the previous address in each prefetcher in the T2 processing cycle. Since only the prefetcher 0 has the previous address 0, and the difference between the address 1000 and the address 0 is greater than the preset value (for example, 100), the address 0 is allocated to the prefetcher 13B, so that the previous address, step size, and hit count recorded by the prefetcher 13B are 1000, 0, and 0, respectively. Similarly, the address allocation unit 17 allocates the address 500 to the prefetcher 13C in the T6 processing cycle and allocates the address 13 to the prefetcher 13C in the T7 processing cycle.

[0124] The address allocation unit 17 can allocate the received address to the prefetcher with the smallest difference between the received address and the previous address when the difference between the received memory address and the previous address recorded by each prefetcher is different from the stride recorded by the corresponding prefetcher, and there is no prefetcher that does not store the previous address. For example, the address allocation unit 17 compares address 2 with the previous address recorded by each prefetcher in the T3 processing cycle, determines that the difference between address 2 and the previous address recorded by each prefetcher is different from the stride recorded by the corresponding prefetcher, and the difference between address 2 and the previous address 0 recorded by prefetcher 13A is less than a preset value (for example, 100), and allocates address 2 to prefetcher 13A, so that the previous address, stride, and hit count recorded by prefetcher 13A are 2, 2, and 1, respectively. Similarly, the address assigning unit 17 assigns the address 1001 to the prefetcher 13B in the T4 processing cycle, assigns the address 501 to the prefetcher 13C in the T12 cycle, and assigns the address 14 to the prefetcher 13D in the T9 processing cycle.

[0125] For another example, in the T10 processing cycle, the address allocation unit 17 determines that the difference between the address 50 and the previous address recorded by each prefetcher is different from the step recorded by the corresponding prefetcher, and the previous address has been recorded in each recorder, and the difference between the address 50 and the previous address 14 recorded in the prefetcher 13D is the smallest, and the address 50 is allocated to the prefetcher 13D, so that the previous address, step, and hit count recorded by the prefetcher 13D are 50, 36, and 1, respectively. Similarly, the address allocation unit 17 allocates the address 15 to the prefetcher 13D in the T10 processing cycle.

[0126] The address allocation unit 17 may allocate the received address to the prefetcher when there is a prefetcher whose difference between the received memory address and the previous address is the same as the stride recorded by the corresponding prefetcher. For example, the address allocation unit 17 compares address 4 with the previous address recorded by each prefetcher in the T5 processing cycle, and determines that the difference between address 4 and the previous address recorded by prefetcher 13A is 2, and the difference is the same as the stride recorded by prefetcher 13A, and allocates address 4 to prefetcher 13A, so that the previous address, stride, and hit count recorded by prefetcher 13A are 4, 2, and 2, respectively. At this time, the prefetch address generation unit in prefetcher 13A determines that the hit count 2 reaches the preset hit count value (for example, 2), and generates a prefetch address 6. Similarly, the address allocation unit 17 allocates address 1002 to prefetcher 13B in the T8 processing cycle, and the prefetch address generation unit in prefetcher 13B generates prefetch address 1003; allocates address 502 to prefetcher 13C in the T13 processing cycle, and the prefetch address generation unit in prefetcher 13C generates prefetch address 503; allocates address 6 to prefetcher 13A in the T14 cycle, and the prefetch address generation unit in prefetcher 13A generates prefetch address 8.

[0127] Based on the allocation relationship of each address by the address allocation unit 17 as mentioned above, the prefetcher 13A can generate prefetch address 6 in the T5 processing cycle and prefetch address 8 in the T14 processing cycle respectively, and when it is determined that prefetch address 6 and prefetch address 8 do not correspond to the memory in the processor 1' and the data corresponding to prefetch address 6 and prefetch address 8 are not stored in the cache 16, it generates corresponding estimated fetch instructions; the prefetcher 13B can generate prefetch address 1003 in the T8 processing cycle respectively, and when it is determined that prefetch address 1003 does not correspond to the memory in the processor 1' and the data corresponding to prefetch address 1003 are not stored in the cache 16, it generates corresponding estimated fetch instructions; the prefetcher 13C can generate prefetch address 503 in the T13 processing cycle respectively, and when it is determined that prefetch address 503 does not correspond to the memory in the processor 1' and the data corresponding to prefetch address 503 are not stored in the cache 16, it generates corresponding estimated fetch instructions. In this way, processor 1' can prefetch three equally spaced address sequences in the memory address sequence, reducing the delay of the processor in acquiring data corresponding to prefetch address 6, prefetch address 8, prefetch address 103, and prefetch address 503, thereby improving the efficiency and performance of the processor.

[0128] However, for processors in some application scenarios, such as processors used in wearable devices, IoT devices, smart home devices, etc., there are high restrictions on the power consumption and area occupied by the processors. In the above-mentioned scheme of increasing the number of preprocessors, since the circuit area occupied by the state cache unit and the prefetch instruction generation circuit is large, it will greatly increase the circuit area occupied by the processor and the power consumption of the processor, which is not suitable for such scenarios. In addition, in the scheme of using multiple prefetchers, it is possible that multiple prefetchers issue prefetch instructions at the same time, and the bus interface bandwidth of the processor corresponding to the above-mentioned application scenario is limited. Since the prefetch instruction has a low priority in the bus interface, the bus interface can usually only respond to one prefetch instruction at the same time, resulting in the inability to prefetch even though the prefetch instruction is generated.

[0129] In order to solve the above problems, an embodiment of the present application provides a prefetcher, which replaces the equally spaced address sequence identification circuit 131 in the aforementioned prefetcher 13 with a prefetch address generation circuit to realize the identification of the equally spaced address sequence in the memory address sequence, and performs data prefetching based on the identified equally spaced address sequence. Specifically, the prefetch address generation circuit divides the received memory address into multiple address stream groups, and sets a priority for each address stream group. When the received memory address matches a certain address stream group, the received memory address is assigned to the matching address stream group and the data and priority in the matching address stream group are updated. When the received memory address does not match any address stream group, the received memory address is assigned to the address stream group with the lowest priority and the data and priority in the address stream group with the lowest priority are updated. Furthermore, the prefetch address generation circuit can record the number of matches between the received memory address and the step size of each address stream grouping for which the prefetch address has not been generated. When the number of matches reaches a preset number of matches, the prefetch address is obtained based on the step size and memory address of the last match, and then the prefetch data corresponding to the prefetch address is obtained from the off-chip memory based on the prefetch address, and the obtained prefetch data is stored in the cache unit of the processor.

[0130] It is understood that the number of address stream groups into which the pre-fetch address generation circuit divides the memory address can be any number greater than 2, and the present application embodiment does not limit this. For ease of description, the following examples are introduced as follows: the pre-fetch address generation circuit divides the memory address into 3 address stream groups.

[0131] It can be understood that the data in the address stream group includes an address identifier, a step identifier, a pre-fetch identifier, a previous address and a step, which are used to indicate the memory address, step, and priority of each address stream group recorded by each address stream group.

[0132] The previous address is used to indicate the memory address of the most recent record of the address stream packet.

[0133] The step distance is used to indicate the difference between the memory addresses of the two most recent records of the address stream packet. Specifically, the step distance = ADD K -ADD K-1 , where ADD K Refers to the memory address of the Kth (most recent) record of the address stream packet, ADD K-1 The memory address recorded for the K-1th time (the last time before the most recent time).

[0134] The address identifier is used to indicate whether the address stream group has recorded the memory address. For example, if the address stream group has recorded the memory address, the address identifier is 1, otherwise the address identifier is 0.

[0135] The step identifier is used to indicate whether the step recorded in the address stream group is a valid step. If the recorded step is a valid step, the step identifier is 1, otherwise the step identifier is 0. The valid step refers to a step whose absolute value is greater than 0 but less than the preset step value. For example, in some embodiments, the preset step value may be 3, and when the difference between the received memory address and the previous address is -2, -1, 1, or 2, the step identifier is 1. It can be understood that the size of the preset step value can be any integer greater than 1, and is not limited here. The larger the preset step value, the larger the interval of the equally spaced address sequence that the prefetcher can recognize, but the worse the stability.

[0136] The pre-fetch flag is used to indicate whether the historical address recorded in the address stream group has generated a pre-fetch address. If yes, the pre-fetch flag is 1, otherwise the pre-fetch flag is 0. It can be understood that the pre-fetch flag is 1 in at most only one address stream group.

[0137] It can be understood that the priority of the address stream group is determined by the step identifier, address identifier and pre-fetch identifier in the address stream group. The higher the priority, the higher the possibility of data pre-fetching according to the address sequence corresponding to the address stream group. Figure 5 The address stream group with a prefetch identifier of 1 has the first priority, the address stream group with a step size of 1 but a prefetch identifier of 0 has the second priority, the address stream group with an address identifier of 1 but a step size identifier and a prefetch identifier of 0 has the third priority, and the address stream group with an address identifier, a step size identifier and a prefetch identifier of 0 has the fourth priority, where the smaller the priority number, the higher the priority.

[0138] It can be understood that the step matching of the memory address and the address stream group means that the difference between the memory address and the previous address recorded in the address stream group is the effective step, and the difference is the same as the step in the address stream group. In some embodiments, the pre-fetch address generation circuit can use a confidence count value to represent the number of matches between the memory address and the step of each address stream group for which the pre-fetch address has not been generated. When the memory address and the step of each address stream group for which the pre-fetch address has not been generated match, the confidence count value increases, and when the memory address and the step of the address stream group for which the pre-fetch address has been generated match, the confidence count value is reset. When the confidence count value reaches the preset number of matches, the pre-fetch address generation circuit obtains the pre-fetch address according to the memory address that makes the confidence calculation number reach the preset number of matches and the step of the matching address stream group, and sets the pre-fetch flag of the matching address stream group to 1, and sets the pre-fetch flags of other address stream groups to 0. For example, in some embodiments, the pre-fetch address can be the sum of the memory address that makes the confidence calculation number reach the preset number of matches and the step of the matching address stream group.

[0139] It can be understood that the address stream grouping that matches the memory address refers to the address stream grouping in which the step distance of the memory address and the address stream grouping matches (hereinafter referred to as the first type of matching grouping), or the address stream grouping in which the address identifier is 1 and the step distance identifier is 0 when there is no first type of matching grouping for the memory address, but the absolute value of the difference between the memory address and the previous address is less than the preset step distance value (hereinafter referred to as the second type of matching grouping).

[0140] In some embodiments, when there are multiple address stream packets with the lowest priority, the pre-fetch address generation circuit can assign the received memory address to the address stream packet with the lowest priority and the address stream packet that is sorted first when the received memory address does not match any of the address stream packets. The received memory address can also be assigned to the address stream packet with the smallest interval between the previous address and the received memory address in the address stream packet with the lowest priority. Furthermore, when there are multiple address stream packets with the smallest interval between the previous address and the received memory address, the pre-fetch address generation circuit can also randomly assign the memory address to any one of the multiple address stream packets with the smallest interval between the previous address and the received memory address, which is not limited here.

[0141] In some embodiments, the pre-fetch address generation circuit can also use a reset count value to indicate the number of times the received memory address does not match the step size of each address stream grouping in a row. The reset count value increases when the received memory address does not match the step size of each address stream grouping, and resets when the received memory address matches the step size of any address stream grouping. When the reset count value reaches a preset reset number of times, the pre-fetch address generation circuit resets the data in each address stream grouping and resets the count value. This can avoid waiting for the memory address that satisfies the identified equally spaced address sequence when the identified equally spaced address sequence has ended, thereby improving the timeliness of the pre-fetch address generation circuit in identifying the next equally spaced address sequence.

[0142] The following describes the process of generating prefetch addresses by the prefetch address generation circuit in conjunction with a specific memory address sequence.

[0143] Specifically, Figure 6 According to some embodiments of the present application, a schematic diagram of a process of generating a prefetch address by a prefetch address generating circuit is shown.

[0144] refer to Figure 6, assuming that the memory address sequence received by the pre-fetch address generation circuit is 0-1000-2-1001-4-500-13-1002-14-50-15-501-502-6, the pre-fetch address generation circuit divides the memory address sequence into 3 address stream groups (address stream group 1, address stream group 2, address stream group 3), the preset number of matches is 2, the preset number of resets is 5, and the processing cycles of the pre-fetch address generation circuit operating on each address in the memory address sequence are T1 to T14, and the preset step value is 3. Therefore, the process of the pre-fetch address generation circuit performing data preset based on the memory address sequence may include:

[0145] In the T1 processing cycle, the pre-fetch address generation circuit receives address 0. Since none of the three address stream groups have received any memory address at this time, address 0 does not match any of the three address stream groups, and the priority is level 4. The pre-fetch address generation circuit assigns address 0 to the address stream group 1 that is arranged first, and updates the previous address 1 of the address stream group 1 to 0, the address identifier 1 to 1, and the reset count value to 1.

[0146] In the T2 processing cycle, the pre-fetch address generation circuit obtains address 1000. Since address 1000 does not match any of the three address stream groups, and the priority of address stream group 1 is level 3, and the priority of address stream group 2 and address stream group 3 is level 4, the pre-fetch address generation circuit assigns address 1000 to address stream group 2, which is in the front of the arrangement order, and updates the previous address 2 of address stream group 2 to 1000, the address identifier 1 to 1, and the reset count value to 2.

[0147] In the T3 processing cycle, the pre-fetch address generation circuit obtains address 2. Since address 2 does not match the step size of any of the three address stream groups, but the absolute value of the difference between address 2 and the previous address 1 (address 0) in address stream group 1 is 2, which is less than the preset step size, the pre-fetch address generation circuit assigns address 2 to address stream group 1, and updates the previous address 1 of address stream group 1 to 2, and the step size 1 to 2. Since 2 is a valid step size, the pre-fetch address generation circuit updates the step size identifier 1 of address stream group 1 to 1, and updates the reset count value to 3.

[0148] In the T4 processing cycle, the pre-fetch address generation circuit obtains address 1001. Since there is no step size of address stream group 1 that matches address 1001, but the absolute value of the difference between address 1001 and the previous address 2 (address 1000) in address stream group 2 is 1, which is less than the preset step size, the pre-fetch address generation circuit assigns address 1001 to address stream group 2, updates the previous address 2 of address stream group 2 to 1001, updates the step size 2 to 1, and updates the reset count value to 4. Since 1 is a valid step size, the pre-fetch address generation circuit updates the step size identifier 2 of address stream group 2 to 1.

[0149] In the T5 processing cycle, the pre-fetch address generation circuit obtains address 4. The difference (2) of address 4 minus the previous address 1 (2) in address stream group 1 is the same as the step 1 (2) in address stream group 1. Address 4 matches the step of address stream group 1, and the pre-fetch address generation circuit assigns address 4 to address stream group 1. The pre-fetch address generation circuit updates the previous address 1 of address stream group 1 to 4, the step 1 remains unchanged, resets the reset count value to 0, and updates the confidence count value to 1.

[0150] In the T6 processing cycle, the pre-fetch address generation circuit obtains address 500. Since address 500 does not match any of the three address stream groups, and the priority of address stream group 1 is level 1, the priority of address stream group 2 is level 2, and the priority of address stream group 3 is level 4, the pre-fetch address generation circuit assigns address 500 to address stream group 3 with the lowest priority, and updates the previous address 3 of address stream group 3 to 500, the address identifier 3 to 1, and the reset count value to 1.

[0151] In the T7 processing cycle, the pre-fetch address generation circuit obtains address 13, because address 13 does not match any of the three address stream groups, and the priority of address stream group 1 is level 1, the priority of address stream group 2 is level 2, and the priority of address stream group 3 is level 3. The pre-fetch address generation circuit assigns address 13 to the address stream group 3 with the lowest priority, and updates the previous address 3 of address stream group 3 to 13, the address identifier 3 to 1, the step distance to -487, and the reset count value to 2. Since the absolute value of the step distance -487 is greater than the preset step distance value, the step distance identifier is kept at 0.

[0152] In the T8 processing cycle, the pre-fetch address generation circuit obtains address 1002. The difference (1) of address 1002 minus the previous address 2 (address 1001) in address stream group 2 is the same as the step 2 (1) in address stream group 2. Address 1002 matches the step 2 of address stream group 2. The pre-fetch address generation circuit assigns address 1002 to address stream group 2. The pre-fetch address generation circuit updates the previous address 2 of address stream group 2 to 1002, the step 2 remains unchanged, resets the reset count value to 0, and updates the confidence count value to 2. Since the confidence count value reaches the preset number of matches (2), the pre-fetch address generation circuit updates the pre-fetch flag 1 of address stream group 2 to 1, and obtains the pre-fetch address 1003 based on the addition of address 1002 and step 2 (1), and then resets the confidence count value to 0.

[0153] In the T9 processing cycle, the pre-fetch address generation circuit obtains address 14. Since address 14 does not match the step size of the three address stream groups, but the absolute value of the difference between address 14 and the previous address 3 (address 13) in address stream group 3 is 1, which is less than the preset step size, the pre-fetch address generation circuit assigns address 14 to address stream group 3, and updates the previous address 3 of address stream group 3 to 14, and the step size 3 to 1. Since 1 is a valid step size, the pre-fetch address generation circuit updates the step size identifier 3 of address stream group 3 to 1, and updates the reset count value to 1.

[0154] In the T10 processing cycle, the pre-fetch address generation circuit obtains address 50. Since address 50 does not match any of the three address stream groups, and the priority of address stream group 1 is level 2, the priority of address stream group 2 is level 1, and the priority of address stream group 3 is level 2, the pre-fetch address generation circuit assigns address 50 to the address stream group 1 that is sorted first, and updates the previous address 1 of address stream group 1 to 50, the step size is updated to 46, and the reset count value is updated to 2. Since the absolute value of the step size 46 is greater than the preset step size value, the pre-fetch address generation circuit sets the step size identifier of address stream group 1 to 0.

[0155] In the T11 processing cycle, the pre-fetch address generation circuit obtains address 15. The difference (1) of address 15 minus the previous address 3 (address 14) in address stream group 3 is the same as the step 3 (1) in address stream group 3. Address 15 matches the step of address stream group 3, and the pre-fetch address generation circuit assigns address 15 to address stream group 3. The pre-fetch address generation circuit updates the previous address 3 of address stream group 3 to 15, the step 3 remains unchanged, resets the reset count value to 0, and updates the confidence count value to 1.

[0156] In the T12 processing cycle, the pre-fetch address generation circuit obtains address 501. Since address 501 does not match any of the three address stream groups, and the priority of address stream group 1 is level 3, the priority of address stream group 2 is level 1, and the priority of address stream group 3 is level 2, the pre-fetch address generation circuit assigns address 501 to address stream group 1, updates the previous address 1 of address stream group 1 to 501, updates the step size to 451, and updates the reset count value to 1. Since the absolute value of the step size 451 is greater than the preset step size value, the pre-fetch address generation circuit keeps the step size identifier of address stream group 1 at 0.

[0157] In the T13 processing cycle, the pre-fetch address generation circuit obtains address 502. Since address 2 does not match the step size of the three address stream groups, but the absolute value of the difference between address 502 and the previous address 1 (address 501) in address stream group 1 is 1, which is less than the preset step size value, the pre-fetch address generation circuit assigns address 502 to address stream group 1, and updates the previous address 1 of address stream group 1 to 502, and the step size 1 is updated to 1. Since 1 is a valid step size, the pre-fetch address generation circuit updates the step size identifier 1 of address stream group 1 to 1, and updates the reset count value to 2.

[0158] In the T14 processing cycle, the pre-fetch address generation circuit obtains address 6, because address 6 does not match any of the three address stream groups, and the priority of address stream group 1 is level 2, the priority of address stream group 2 is level 1, and the priority of address stream group 3 is level 2. The pre-fetch address generation circuit assigns address 501 to the address stream group 1 that is sorted first, and updates the previous address 1 of address stream group 1 to 6, the step size to -496, and the reset count value to 3. Since the absolute value of the step size -496 is greater than the preset step size value, the pre-fetch address generation circuit updates the step size identifier of address stream group 1 to 0.

[0159] Through the above processing, it can be known that the prefetch address generation circuit can obtain the prefetch address 1003 based on the equally spaced address sequences 1000, 1001, and 1002 in the T8 cycle. That is to say, through a prefetcher, it is possible to recognize the equally spaced address sequence in the above memory address sequence, and generate a prefetch address based on the recognized interval address sequence, so that the prefetcher can store the data corresponding to the prefetch address in the cache unit of the processor based on the prefetch address.

[0160] Based on the logic of generating a prefetch address by the above-mentioned prefetch address generation circuit, an embodiment of the present application provides a prefetcher, which includes the above-mentioned estimated fetch address generation circuit.

[0161] Specifically, Figure 7 According to some embodiments of the present application, a schematic structural diagram of a prefetcher 2 is shown.

[0162] like Figure 7 As shown, the prefetcher 2 includes a prefetch address generation circuit 21, a state cache unit 22 and a prefetch instruction generation circuit 23. The functions of the state cache unit 22 and the prefetch instruction generation circuit 23 can refer to the related description of the state cache unit 132 and the prefetch instruction generation circuit 133, which will not be repeated here.

[0163] The pre-fetch address generation circuit 21 is any circuit that can implement the operation logic of the pre-fetch address generation circuit. Exemplarily, the pre-fetch address generation circuit 21 may include a control circuit 211, a reset counter 212, a confidence counter 213, and a register group.

[0164] Among them, the register group is used to store the data of each address stream group. The number of register groups included in the pre-fetch address generation circuit 21 can be determined based on the number of address stream groups into which the pre-fetch address generation circuit 21 divides the memory address. For example, one register group can be used to store the data in one address stream group (i.e., address identifier, step identifier, pre-fetch identifier, previous address and step identifier), so that the pre-fetch address generation circuit 21 can include three register groups (register group 1, register group 2, register group 3). It should be understood that in other embodiments, one register group can also be used to store the data of all address stream groups, which is not limited here.

[0165] The reset counter 212 is used to record the aforementioned reset count value.

[0166] The confidence counter 213 is used to record the aforementioned confidence count value.

[0167] The control circuit 211 is used to store the received memory address in each register group, generate a prefetch address, and reset or update the reset counter 212, reset the confidence counter 213, the data in each register group, etc. according to the address identifier, step identifier, prefetch identifier, previous address, step identifier, reading of the reset counter 212, reading of the confidence counter 213, etc. in each register group.

[0168] Specifically, the control circuit 211 is used to assign the memory address to the matching register group when the received memory address matches the address stream group corresponding to a register group, and to assign the memory address to the register group with the lowest priority when the received memory address does not match the address stream group corresponding to each register group, wherein the priority of the register group is the same as the priority of the address stream group stored in the register group. After assigning the memory address to a register group, the control circuit 211 updates the step size in the register group to the difference between the received memory address and the previous address of the register, updates the register group address identifier to 1, and updates the step size identifier in the register group according to the updated step size, for example, when the updated step size is a valid step size, the step size identifier is updated to 1, otherwise the step size identifier is updated to 0.

[0169] The control circuit 211 is also used to increase the count value of the confidence counter 213, for example, by 1, when the received memory address matches the step size of the address stream grouping corresponding to any register group with a prefetch identifier of 0; or reset the count value of the confidence counter 213, for example, to 0, when the received memory address matches the step size of the address stream grouping corresponding to the register group with a prefetch identifier of 1; or when the count value of the confidence counter 213 reaches a preset number of confidences, based on the memory address and the step size that make the count value of the confidence counter 213 reach the preset number of confidences, obtain the prefetch address, send the prefetch address to the prefetch instruction generation circuit 23, and set the prefetch identifier of the register group that makes the count value of the confidence counter 213 reach the preset number of confidences to 1, set the prefetch identifiers of other register groups to 0, and reset the confidence counter 213.

[0170] The control circuit 211 is also used to increase the count value of the reset counter 212, for example, by 1, when the received memory address does not match the step size of the address stream grouping corresponding to any register group; or when the count value of the reset counter 212 reaches a preset reset number of times, reset the data in each register group, the count value of the reset counter 212, and the count value of the confidence counter 213.

[0171] Based on the above-mentioned estimated address generation circuit 21, after the estimated address generation circuit 21 determines the prefetch address, the estimated instruction generation circuit 23 can determine whether the prefetch address meets the prefetch condition based on the prefetch address, and output the prefetch instruction if the prefetch address meets the prefetch condition.

[0172] It is understandable that the aforementioned Figure 7 The structure of the prefetcher 2 shown is only an example. In other embodiments, the prefetcher 2 may include more or fewer modules, and some modules may be merged or split, which is not limited here.

[0173] The above-mentioned prefetcher 2 can utilize the control circuit 211, 3 register groups and 2 counters to identify an equally spaced address sequence in a memory address sequence including an equally spaced address sequence, generate a prefetch address based on the equally spaced address sequence, and output a prefetch instruction when the prefetch address meets the prefetch condition. Since the number of status cache units and prefetch instruction generation circuits is not increased, it is beneficial to reduce the circuit area occupied by the prefetcher, thereby reducing the circuit area occupied by the processor.

[0174] Furthermore, an embodiment of the present application provides a processor, which includes the aforementioned prefetcher 2.

[0175] Specifically, Figure 8 According to some embodiments of the present application, a schematic structural diagram of a processor 1" is shown.

[0176] like Figure 8 As shown, the processor 1" includes a computing unit 11, an access unit 12, a prefetcher 2, a prefetch cache 14, a bus interface 15 and a cache unit 16. The roles and functions of the computing unit 11, the access unit 12, the prefetch cache 14, the bus interface 15 and the cache unit 16 can refer to the relevant description of the corresponding modules in the aforementioned processor 1, and the functions and roles of the prefetcher 2 can refer to the aforementioned Figures 5 to 7 The description of prefetcher 2 is not repeated here.

[0177] When the memory addresses obtained from the access unit 12 by the prefetcher 2 include at least one group of equally spaced address sequences, but there are other addresses between the addresses in each equally spaced address sequence, a group of equally spaced address sequences can be identified, and based on the identified equally spaced address sequence, the address (i.e., the prefetch address) that the computing unit 11 may access is predicted, and the data corresponding to the prefetch address is stored in the cache unit 16 from the off-chip memory SC through the bus interface 15, which can reduce the delay of the computing unit reading the data corresponding to the prefetch address, and is conducive to improving the performance and efficiency of the processor 1". In addition, since only one prefetcher is used, the number of state cache units and prefetch instruction generation circuits is not increased, which is conducive to reducing the circuit area occupied by the processor.

[0178] Combine the following Figure 6 The processing process shown, Figure 7 The structure of the prefetcher 2 shown, Figure 8 The structure of the processor 1" is shown, and the detailed process of data prefetching by the processor 1" is introduced.

[0179] Specifically, Fig. 9 According to some embodiments of the present application, a schematic diagram of a process of a processor 1" performing data prefetching is shown. Fig. 9 As shown, the process includes the following steps.

[0180] S901: The computing unit 11 sends an instruction address sequence to the access unit 12.

[0181] When the executed instruction needs to access a large amount of data, the computing unit 11 sends an instruction address sequence corresponding to the instruction to the access unit 12 .

[0182] S902 : The access unit 12 converts the instruction address sequence into a memory address sequence and sends it to the pre-fetch address generation circuit 21 .

[0183] After receiving the instruction address sequence, the access unit 12 converts the instruction address sequence into a memory address sequence and sends it to the pre-fetch address generation circuit 21 .

[0184] It is understood that in some embodiments, the access unit 12 may send the addresses in the memory address sequence to the pre-fetch address generation circuit 21 one by one, or may send multiple memory addresses at a time, which is not limited here. Figure 6 , the access unit 12 can send each memory address in the memory address sequence 0-1000-2-1001-4-500-13-1002-14-50-15-501-502-6 to the pre-fetch address generation circuit 21 one by one in 14 processing cycles.

[0185] It can be understood that in some embodiments, the processing cycle can be the time from when the prefetch address generation circuit 21 receives a memory address to when it determines the prefetch address based on the memory address, for example, the time from when the prefetch address generation circuit 21 executes steps S904 to S909 below.

[0186] S903: The pre-fetch address generation circuit 21 determines whether there is an address stream packet matching the memory address.

[0187] Exemplarily, the pre-fetch address generation circuit 21 can determine whether there is an address stream group matching the memory address based on the control circuit 211. If so, the memory address should be assigned to the existing address stream group and go to step S904; if not, the memory address should be assigned to the address stream group with the lowest priority.

[0188] For example, the pre-fetch address generation circuit 21 may determine that there is an address stream packet matching the memory address when the step length of the memory address matches that of any address stream packet. Figure 6 In the T5 processing cycle, the absolute value of the difference between address 4 and the previous address 2 in address stream group 1 is 2, which is the same as the step 1 recorded in address stream group 1. Address 4 matches the step of address stream group 1.

[0189] For another example, the pre-fetch address generation circuit 21 can determine that there is an address stream group that matches the memory address when the memory address and the step size of any address stream group do not match, but there is an address stream group with an address identifier of 1 and a step size of 0, and the absolute value of the difference between the memory address and the previous address is less than the preset step size. Specifically, for example, referring to the T3 processing cycle in 6, address 2 does not match the step size of the three address stream groups, but the absolute value of the difference between address 2 and the previous address 1 in address stream group 1 is 2, which is less than the preset step size 3, and it is determined that there is an address stream group that matches the memory address.

[0190] S904: The pre-fetch address generation circuit 21 updates the data in the register group corresponding to the existing address stream group based on the memory address and resets the count value and the confidence count value.

[0191] Exemplarily, when the memory address matches the step size of the existing address stream group, the pre-fetch address generation circuit 21 may update the previous address in the register group corresponding to the existing address stream group to the memory address, increase the confidence count value, and reset the reset count value. Figure 6 In the T5 processing cycle, the existing address stream grouping is address stream grouping 1, and the memory address 4 matches the step size of address stream grouping 1. The pre-fetch address generation circuit 21 can update the previous address 1 in the register corresponding to address stream grouping 1 to 4, increase the confidence count value by 1, and reset the reset count value to 0.

[0192] Exemplarily, when the memory address does not match the step of the existing address stream group, the pre-fetch address generation circuit 21 may update the step in the register group corresponding to the existing address stream group to the difference between the memory address and the previous address, update the previous address to the memory address, update the step identifier to 1, and increase the reset count value. Figure 6 In the T3 processing cycle, the existing address stream group is address stream group 1, and address 2 does not match the step size in the three address stream groups 1. The pre-fetch address generation circuit 21 can update 1 in the address stream group to 2, the previous address 1 to 2, the step size flag to 1, and increase the reset count value to 1.

[0193] S905: The pre-fetch address generation circuit 21 updates the data in the register group corresponding to the lowest priority address stream group based on the memory address and resets the count value.

[0194] Exemplarily, the prefetch address generation circuit 21 can assign the memory address to the address stream group with the lowest priority when there is no address stream group matching the memory address, and update the address identifier in the address stream group with the lowest priority to 1, the step identifier to 0, the step size to the difference between the memory address and the previous address, and increase the value of the reset counter.

[0195] Specifically, for example, refer to Figure 6 In processing cycle T7, there is no address stream group matching memory address 13, and the address stream group with the lowest priority is address stream group 3. The pre-fetch address generation circuit 21 can update the address identifier 3 in the register group corresponding to address stream group 3 to 1, the step identifier 3 to 0, the step 3 to 13-500=-487, and increase the reset count value to 2.

[0196] S906: The prefetch address generation circuit 21 determines whether the prefetch address generation condition is satisfied.

[0197] After updating the confidence count value, the pre-fetch address generation circuit 21 determines whether the pre-fetch address generation condition is met. If yes, it means that the pre-fetch address can be generated, and the process goes to step S907; otherwise, it means that the pre-fetch address cannot be generated, and the process goes to step S908.

[0198] Exemplarily, the pre-fetch address generation condition may include: the confidence count value reaches a preset confidence number, or the pre-fetch flag of the existing address flow packet is 1. In other embodiments, the pre-fetch address generation condition may also include other conditions, which are not limited here.

[0199] It is understandable that the preset number of transmissions may be preset in the processor by a developer of the processor, or may be set as an adjustable parameter, so that the processor may adjust the preset number of transmissions according to different scenarios to meet pre-fetching requirements in different scenarios.

[0200] S907 : the prefetch address generation circuit 21 updates the prefetch flag of each address stream group, resets the reset count value and the confidence count value, generates a prefetch address, and sends the prefetch address to the prefetch instruction generation circuit 23 .

[0201] When determining that the prefetch address generation condition is met, the prefetch address generation circuit 21 updates the prefetch flag of each address stream group, resets the reset count value and the confidence count value, generates a prefetch address, and sends the prefetch address to the prefetch instruction generation circuit 23 .

[0202] Exemplarily, when the confidence count value reaches the preset confidence number, the pre-fetch address generation circuit 21 may set the pre-fetch flag in the register group corresponding to the above-mentioned existing address stream group to 1, set the pre-fetch flags in other register groups to 0, reset the reset count value and the confidence count value to 0, and add the memory address and the step size of the above-mentioned existing address stream group to obtain the pre-fetch address and send the pre-fetch address to the pre-fetch instruction generation circuit 23. Specifically, for example, refer to Figure 6 In processing cycle T8, the confidence count value is 2, reaching the preset confidence count. The pre-fetch address generation circuit 21 can set the pre-fetch flag of address stream group 2 to 1, and the pre-fetch flags in other address stream groups to 0, reset the reset count value and the confidence count value to 0, and add the address 1002 to the step size 2 (1) to obtain the pre-fetch address 1003.

[0203] Exemplarily, when the prefetch flag of an existing address stream group is 1, it means that the existing address stream group has generated a prefetch address. The prefetch address generation circuit 21 can directly reset the reset count value and the confidence count value to 0, and add the memory address and the step size of the above-mentioned existing address stream group to obtain the prefetch address and send the prefetch address to the prefetch instruction generation circuit 23.

[0204] S908: The pre-fetch address generation circuit 21 determines whether the reset count value reaches a preset reset number of times.

[0205] When the pre-fetch address generation condition is not met, the pre-fetch address generation circuit 21 determines whether the reset count value reaches the preset reset number. If the reset count value reaches the preset reset number, it means that the equally spaced address sequence is not currently recognized or the recognized equally spaced address sequence has ended, and it is necessary to restart the recognition, and go to step S909; otherwise, it means that the equally spaced address sequence can continue to be recognized, and go to step S903 to perform pre-fetch based on the next memory address.

[0206] It is understandable that the preset reset number can be preset in the processor by the developer of the processor, or can be set as an adjustable parameter, so that the processor can adjust the preset reset number according to different scenarios to meet the pre-fetching requirements in different scenarios.

[0207] S909: The pre-fetch address generation circuit 21 resets the data of each register group, resets the count value and the confidence count value.

[0208] When the reset count value reaches the preset reset times, the pre-fetch address generation circuit 21 resets the data of each register group, the reset count value and the confidence count value, and then proceeds to step S903 to perform pre-fetch based on the next memory address.

[0209] S910: The prefetch instruction generation circuit 23 determines whether the prefetch address satisfies the prefetch condition.

[0210] The prefetch instruction generation circuit 23 determines whether the prefetch address meets the prefetch condition. If so, it means that the data corresponding to the prefetch address can be prefetched into the processor, and the process goes to step S911; otherwise, it means that the data corresponding to the prefetch address is already in the processor or cannot be prefetched, and the process goes to step S903 to prefetch based on the next memory address.

[0211] Exemplarily, the prefetch conditions may include: the address pointed to by the prefetch address is the address of the off-chip memory, the data corresponding to the prefetch address is not stored in the cache unit 16, and the data corresponding to the prefetch address and each address in the corresponding equally spaced address sequence are of the same type (all are security data or ordinary data).

[0212] In other embodiments, the prefetch condition may also include more or fewer conditions. For example, the prefetch instruction generation circuit 23 may determine that the prefetch address satisfies the prefetch condition when the address pointed to by the prefetch address is the address of the off-chip memory and the data corresponding to the prefetch address is not stored in the cache unit 16. This is not limited here.

[0213] Specifically, refer to Figure 6 In the T8 processing cycle, the prefetch address is 1003. The prefetch instruction generation circuit 23 can determine that the prefetch address meets the prefetch condition when the address pointed to by address 1003 is not the address of other memories (such as registers) inside the processor, the cache unit 16 does not store data corresponding to address 1003, and the data type of the address pointed to by address 1003 is the same as the data type recorded in the status cache unit 22.

[0214] S911 : the prefetch instruction generation circuit 23 obtains the prefetch data corresponding to the prefetch address from the off-chip memory SC through the bus 15 interface, and stores the prefetch data in the prefetch cache 14 .

[0215] When the prefetch address satisfies the prefetch condition, the prefetch instruction generation circuit 23 generates a prefetch instruction for obtaining data from the prefetch address, obtains the prefetch data corresponding to the prefetch address from the off-chip memory SC through the bus 15 interface, and stores the prefetch data in the prefetch cache 14.

[0216] S912: The pre-fetch cache 14 determines whether the data in the pre-fetch cache 14 reaches a preset data amount.

[0217] After receiving the prefetch data, the prefetch cache 14 determines whether the data in the prefetch cache 14 reaches the preset data amount. If so, it means that the prefetch data of the preset data amount can be stored in the cache unit 16, and the process goes to step S913; otherwise, it means that it is necessary to wait for more prefetch data, and the process goes to step S903 to prefetch based on the next memory address.

[0218] It is understandable that the preset data volume can be preset in the processor by the developer, or it can be a parameter set by the processor according to the scenario. The larger the preset data volume, the lower the frequency of data exchange between the pre-fetch cache 14 and the cache unit 16, the slower the pre-fetch speed, but it can also occupy less bandwidth of the bus interface 15; the smaller the preset data volume, the higher the frequency of data exchange between the pre-fetch cache 14 and the cache unit 16, the faster the pre-fetch speed, but it will also occupy more bandwidth of the bus interface 15.

[0219] S913 : The pre-fetch cache 14 stores the cache data of a preset data volume in the cache unit 16 .

[0220] After the pre-fetch cache 14 determines that the data in the pre-fetch cache 14 reaches the preset data amount, it stores the cache data of the preset data amount in the cache unit 16, and goes to step S903 to perform pre-fetch based on the next memory address.

[0221] It can be understood that in some embodiments, when the amount of data in the pre-fetch cache 14 does not reach the preset data amount within the preset time, the data in the pre-fetch cache 14 can be stored in the cache unit 16 so that the computing unit can access the pre-fetched data more timely.

[0222] It can be understood that the execution order of the aforementioned steps S901 to S913 is only an example. In other embodiments, the order of some steps can be changed, and some steps can be split or combined, which is not limited here. For example, in some embodiments, steps S903 to S909 corresponding to a certain memory address can be executed in parallel with steps S910 to S913 corresponding to the memory address before the memory address.

[0223] An embodiment of the present application further provides an electronic device, which includes the aforementioned prefetcher 2 .

[0224] Specifically, Fig.10 According to some embodiments of the present application, a schematic diagram of the structure of an electronic device 100 is shown. Fig.10As shown, the electronic device 100 includes one or more processors 101, a system memory 102, a non-volatile memory (NVM) 103, a communication interface 104, an input / output (I / O) device 105, and a system control logic 106 for coupling the processor 101, the system memory 102, the non-volatile memory 103, the communication interface 104 and the input / output (I / O) device 105. Among them:

[0225] The computing unit of the processor 101 includes one or more processing units, for example, a central processing unit CPU (Central Processing Unit), a graphics processor GPU (Graphics Processing Unit), a digital signal processor DSP (Digital Signal Processor), a microprocessor MCU (Micro-programmed Control Unit), an AI (Artificial Intelligence) processor or a programmable logic device FPGA (Field Programmable Gate Array), a neural network processor (Neural-network Processing Unit, NPU), etc. The processor 101 is used to execute instructions (for example, instructions 107 stored in the system memory 102 or the non-volatile memory 103). In some embodiments, the processor 101 may be the aforementioned processor 1". In other embodiments, the processor 101 may include the aforementioned prefetcher 2, so that the processor 101 can use the prefetcher 2 to prefetch data from the system memory 102 or the non-volatile memory 103 when executing instructions.

[0226] The system memory 102 is a volatile memory, such as a random-access memory (RAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc. The system memory is used to temporarily store data and / or instructions. For example, in some embodiments, the system memory 102 can be used to store data or instructions.

[0227] The non-volatile memory 103 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, the non-volatile memory 103 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as a hard disk drive (HDD), a compact disc (CD), a digital versatile disc (DVD), a solid-state drive (SSD), etc. In some embodiments, the non-volatile memory 103 may also be a removable storage medium, such as a secure digital (SD) memory card, etc. In other embodiments, the non-volatile memory 103 may be used to store data or instructions.

[0228] The communication interface 104 may include a transceiver for providing a wired or wireless communication interface for the electronic device 100, thereby communicating with any other suitable device through one or more networks. In some embodiments, the communication interface 104 may be integrated into other components of the electronic device 100, for example, the communication interface 104 may be integrated into the processor 101. In some embodiments, the electronic device 100 may communicate with other devices through the communication interface 104.

[0229] The input / output (I / O) device 105 may include input devices such as a keyboard, a mouse, etc., and output devices such as a display, etc. A user may interact with the electronic device 100 via the input / output (I / O) device 105 .

[0230] The system control logic 106 may include any suitable interface controller to provide any suitable interface with other modules of the electronic device 100. For example, in some embodiments, the system control logic 106 may include one or more memory controllers to provide an interface for the processor to access the system memory 102 and the non-volatile memory 103 through a bus interface.

[0231] In some embodiments, at least one of the processors 101 may be packaged together with the logic of one or more controllers for the system control logic 106 to form a system in package (SiP). In other embodiments, at least one of the processors 101 may also be integrated with the logic of one or more controllers for the system control logic 106 on the same chip to form a system-on-chip (SoC).

[0232] Understandably, Fig.10The structure of the electronic device 100 shown is only an example. In other embodiments, the electronic device 100 may include more or fewer components than shown, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0233] The various embodiments of the mechanism disclosed in the present application can be implemented in hardware, software, firmware or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system, which includes at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device and at least one output device.

[0234] Program code can be applied to input instructions to perform the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0235] Program code can be implemented with high-level programming language or object-oriented programming language to communicate with the processing system. When necessary, program code can also be implemented with assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any specific programming language. In either case, the language can be a compiled language or an interpreted language.

[0236] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, instructions may be distributed over a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine (e.g., computer) readable form, including, but not limited to, floppy disks, optical disks, optical disks, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROM), random access memories (RAM), erasable programmable read-only memories (EPROM), electrically erasable programmable read-only memories (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable memories for transmitting information (e.g., carrier waves, infrared signal digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Accordingly, machine-readable media include any type of machine-readable media suitable for storing or transmitting electronic instructions or information in a form readable by a machine (eg, a computer).

[0237] In the accompanying drawings, some structural or method features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be required. Instead, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of structural or method features in a particular figure does not mean that such features are required in all embodiments, and in some embodiments, these features may not be included or may be combined with other features.

[0238] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation method of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed by the present application. In addition, in order to highlight the innovative part of the present application, the above-mentioned device embodiments of the present application do not introduce units / modules that are not closely related to solving the technical problems proposed by the present application, which does not mean that there are no other units / modules in the above-mentioned device embodiments.

[0239] It should be noted that in the examples and description of this patent, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element defined by the sentence "comprises one" does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0240] Although the present application has been illustrated and described with reference to certain preferred embodiments thereof, it will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.

Claims

1. A data pre-fetching method, applied to an electronic device, characterized in that: The electronic device comprises: a processor and a memory arranged outside the processor, wherein the processor comprises a cache unit; and The method comprises: Acquire multiple historical access addresses of the processor; Allocate the multiple historical access addresses to multiple preset groups according to a preset rule, and record the number of matches between the multiple historical access addresses and the step lengths recorded in each preset group, wherein the step length is used to indicate the difference between the two most recently allocated historical access addresses of the preset group, each of the preset groups includes a previous address, the step length, a step length identifier, an address identifier, and a pre-fetch identifier, the previous address is used to indicate the most recently allocated historical access address in the preset group, the step length identifier is used to indicate that the step length is a valid step length when it is valid, the valid step length refers to a step length whose absolute value is less than a preset step length value, the address identifier is used to indicate that the preset group has recorded a memory address when it is valid, and the pre-fetch identifier is used to indicate that a pre-fetch address has been generated based on the preset group when it is valid; When the number of matches meets a preset condition, obtaining a pre-fetch address based on a historical access address recorded in a first preset group, wherein the first preset group is one of the plurality of preset groups, and the historical access address recorded in the first preset group is an equally spaced address sequence; Acquire data corresponding to the pre-fetch address from the memory, and store the acquired data in the cache unit; Furthermore, allocating the plurality of historical access addresses to a plurality of preset groups according to a preset rule includes: In a case where the first historical access address matches a second preset group among the plurality of preset groups, allocating the first historical access address to the second preset group, wherein the first historical access address is any one of the plurality of historical access addresses; In the absence of a preset group matching the first historical access address, the first historical access address is assigned to a third preset group, wherein the third preset group is one of the preset groups with the lowest priority among the multiple preset groups, wherein the priority of the preset group is determined by the step identifier, address identifier and prefetch identifier in the preset group.

2. The method according to claim 1, characterized in that: The allocating the first historical access address to the second preset group includes: updating the step size of the second preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded by the second preset group, and setting the step size flag of the second preset group to be valid if the updated step size is a valid step size; The previous address of the second preset group is updated to the first historical access address.

3. The method according to claim 1, characterized in that The allocating the first historical access address to the third preset group includes: updating the step size of the third preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded by the third preset group, and setting the step size flag of the third preset group to valid if the updated step size is a valid step size, and setting the step size flag of the third preset group to invalid if the updated step size is an invalid step size; Updating the previous address of the third preset group to the first historical access address; The address identifier of the third preset group is updated to be valid.

4. The method according to claim 1, characterized in that In the case where the step length of the first historical access address matches the step length of the second preset group record, determining that the first historical access address matches the second preset group; Alternatively, when the first historical access address does not match the step length of any preset group record, the second preset group record has a previous address, the step length identifier of the second preset group is invalid, and the difference between the first historical address and the previous address in the second preset group is a valid step length, it is determined that the first historical access address matches the second preset group; When the difference between the first historical access address and the previous address recorded in the preset group is the same as the step length recorded in the preset group, the first historical access address matches the step length recorded in the preset group.

5. The method according to claim 1, characterized in that The method further comprises: Recording a reset count, the reset count being used to indicate the number of times the multiple historical access addresses do not match the step length of any preset grouping record, and the reset count is increased when the first historical access address does not match the step length of any preset grouping record, and is reset when the first historical access address matches the step length of any preset grouping record; When the number of reset times reaches the preset number of reset times, the data in each of the preset groups, the number of reset times, and the number of matches are reset.

6. A processor, characterized in that: The processor includes a computing unit, a cache unit and a prefetcher; wherein the prefetcher includes: A pre-fetch address generation circuit is used to allocate multiple historical access addresses of the computing unit to multiple preset groups according to a preset rule, and record the number of matches between the multiple historical access addresses and the step distance recorded in each preset group, wherein the step distance is used to indicate the difference between the two most recently allocated historical access addresses of the preset group, and obtaining a pre-fetch address based on a historical access address recorded in a first preset group when the number of matches meets a preset condition, wherein the first preset group is one of the plurality of preset groups, and the historical access address recorded in the first preset group is an equally spaced address sequence; A prefetch circuit, used for acquiring data corresponding to the prefetch address from a memory outside the processor, and storing the acquired data in the cache unit; A storage unit, used to store the plurality of preset groups, and each of the preset groups includes a previous address, the step distance, a step distance identifier, an address identifier and a pre-fetch identifier; wherein the previous address is used to indicate the historical access address most recently allocated in the preset group, and the step distance identifier is used to indicate that the step distance is a valid step distance when it is valid, wherein the valid step distance refers to a step distance whose absolute value is less than the preset step distance value, and the address identifier is used to indicate that the preset group has recorded the memory address when it is valid, and the pre-fetch identifier is used to indicate that the pre-fetch address has been generated based on the preset group when it is valid; Furthermore, the pre-fetch address generation circuit allocates the plurality of historical access addresses to a plurality of preset groups according to a preset rule in the following manner: The pre-fetch address generation circuit allocates the first historical access address to the second preset group when the first historical access address matches a second preset group among the plurality of preset groups, wherein the first historical access address is any one of the plurality of historical access addresses; In the absence of a preset group matching the first historical access address, the first historical access address is assigned to a third preset group, wherein the third preset group is one of the preset groups with the lowest priority among the multiple preset groups, wherein the priority of the preset group is determined by the step identifier, address identifier and prefetch identifier in the preset group.

7. The processor according to claim 6, characterized in that The pre-fetch address generation circuit assigns the first historical access address to the second preset group, including: The pre-fetch address generating circuit updates the step size of the second preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded by the second preset group, and sets the step size flag of the second preset group to be valid if the updated step size is a valid step size; The pre-fetch address generation circuit updates the previous address of the second preset group to the first historical access address.

8. The processor according to claim 7, characterized in that The pre-fetch address generation circuit assigns the first historical access address to the third preset group, including: The pre-fetch address generating circuit updates the step size of the third preset group to the difference between the first historical access address and the first historical access address minus the previous address currently recorded by the third preset group, and sets the step size flag of the third preset group to be valid if the updated step size is a valid step size, and sets the step size flag of the third preset group to be invalid if the updated step size is an invalid step size; The pre-fetch address generation circuit updates the previous address of the third preset group to the first historical access address; The pre-fetch address generation circuit updates the address identifier of the third preset group to be valid.

9. The processor according to claim 6, characterized in that: The pre-fetch address generating circuit determines that the first historical access address matches the second preset grouping when the step length of the first historical access address matches the step length of the second preset grouping record; Alternatively, when the first historical access address does not match the step length of any preset group record, the second preset group record has a previous address, the step length identifier of the second preset group is invalid, and the difference between the first historical address and the previous address in the second preset group is a valid step length, it is determined that the first historical access address matches the second preset group; The pre-fetch address generation circuit determines that the first historical access address matches the step size recorded in the preset group when the difference between the first historical access address and the previous address recorded in the preset group is the same as the step size recorded in the preset group.

10. The processor according to claim 6, characterized in that The priority of the preset group is determined by the step identifier, address identifier and pre-fetch identifier in the preset group, including: The preset group with a valid pre-fetch identifier has the first priority; The preset group whose pre-fetching identifier is invalid but whose step identifier is valid has the second priority; The preset group whose pre-fetch identifier and step identifier are invalid but whose address identifier is valid has the third priority; The preset group whose pre-fetch identifier, step identifier and address identifier are all invalid has the fourth priority; Among them, the priorities are, from high to low, the first priority, the second priority, the third priority, and the fourth priority.

11. The processor according to claim 6, characterized in that The prefetcher further includes a first counter, and the prefetch address generation circuit records the number of matches between the plurality of historical access addresses and the step lengths of each of the preset group records through the first counter; and The pre-fetch address generation circuit increases the count value of the first counter when the first historical access address matches the step length of the second preset group record; The pre-fetch address generation circuit resets the count value of the first counter when the first historical access address matches the step length of the second preset group record and the pre-fetch flag of the second preset group is valid.

12. The processor according to claim 11, characterized in that The prefetcher further includes a second counter, the second counter being used to record the number of times that the first historical access address does not match the step length of any preset grouping; and The pre-fetch address generation circuit is further used to increase the count value of the second counter when the first historical access address does not match the step length of any preset group record, and reset the count value of the second counter when the first historical access address matches the step length of any preset group record; And when the count value of the second counter reaches a preset reset number of times, the data in each of the preset groups, the count value of the first counter, and the count value of the second counter are reset.

13. The processor according to claim 6, characterized in that The pre-fetch address generation circuit obtains the pre-fetch address based on the historical access address recorded in the first preset group in the following manner: The pre-fetch address generation circuit adds the previous address recorded in the first preset group to the step distance to obtain the pre-fetch address.

14. The processor according to claim 6, characterized in that The pre-fetch address generation circuit is further configured to set the pre-fetch flag recorded in the first preset group to be valid when the pre-fetch address is obtained based on the historical access address recorded in the first preset group.

15. The processor according to claim 6, characterized in that The preset condition includes: the number of matches reaches a preset number of matches.

16. An electronic device, characterized in that: The electronic device comprises a memory and the processor according to any one of claims 6 to 15.

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