Inverter and pixel circuit

Abstract

The present invention discloses an inverter and a pixel circuit, wherein the inverter includes a diode and a switching thin-film transistor. The diode includes a first semiconductor channel structure, a first electrode, a second electrode, and a third electrode. The first electrode overlaps and is separated from a first channel region of the first semiconductor channel structure. The second electrode and the third electrode are respectively electrically connected to the first semiconductor channel structure. The second electrode is electrically connected to the first electrode. The switching thin-film transistor includes a second semiconductor channel structure, a gate electrode, a drain electrode, and a source electrode. The gate electrode overlaps and is separated from a second channel region of the second semiconductor channel structure. The carrier mobility of the first channel region is greater than that of the second channel region. The drain electrode is electrically connected to the third electrode of the diode.

Description

Technical Field

[0001] The present invention relates to an inverter and a pixel circuit. Background Art

[0002] In a common display device, a pixel circuit includes a switching element and a driving element. The switching element is used to control the gate of the driving element and adjust the gate voltage of the driving element to control the output current of the driving element. The current is transmitted through the driving element to the light-emitting element to turn on the light-emitting element. Generally, if the light-emitting element is to be maintained in the on state for a long time, the driving element must output current for a long time. However, this will cause the driving element to deteriorate due to long-term current stress, thereby affecting the brightness of the light-emitting element. Summary of the Invention

[0003] The present invention provides an inverter whose output current magnitude is easy to adjust.

[0004] The present invention provides a pixel circuit that can improve the degradation problem of the driving transistor.

[0005] At least one embodiment of the present invention provides an inverter. The inverter includes a diode and a switching thin-film transistor. The diode includes a first semiconductor channel structure, a first electrode, a second electrode, and a third electrode. The first electrode overlaps and is separated from the first channel region of the first semiconductor channel structure. The second electrode and the third electrode are respectively electrically connected to the first semiconductor channel structure. The second electrode is electrically connected to the first electrode. The switching thin-film transistor includes a second semiconductor channel structure, a gate, a drain, and a source. The gate overlaps and is separated from the second channel region of the second semiconductor channel structure. The carrier mobility of the first channel region is greater than the carrier mobility of the second channel region. The drain and the source are respectively electrically connected to the second semiconductor channel structure, and the drain is electrically connected to the third electrode of the diode.

[0006] At least one embodiment of the present invention provides a pixel circuit. The pixel circuit includes a switching element, an inverter, a first driving transistor, and a second driving transistor. The switching element is electrically connected to a scan line and a data line. The inverter includes a diode and a switching thin-film transistor. The switching thin-film transistor is electrically connected to the diode. The carrier mobility of the first channel region of the first semiconductor channel structure of the diode is greater than the carrier mobility of the second channel region of the second semiconductor channel structure of the switching thin-film transistor. The first gate of the first driving transistor is electrically connected to the switching element. The second gate of the second driving transistor is electrically connected to the switching element through the inverter. Description of the Drawings

[0007] Figure 1A is an equivalent circuit schematic diagram of an inverter according to an embodiment of the present invention;

[0008] Figure 1B It is a cross-sectional schematic diagram of an inverter according to an embodiment of the present invention;

[0009] Figure 2A It is an equivalent circuit schematic diagram of a pixel circuit according to an embodiment of the present invention;

[0010] Figure 2B It is a cross-sectional schematic diagram of a switching element, a first driving transistor, and a second driving transistor of a pixel circuit according to an embodiment of the present invention;

[0011] Figure 2C It is a cross-sectional schematic diagram of a reset transistor of a pixel circuit according to an embodiment of the present invention;

[0012] Figure 3 It is an operation signal timing diagram of a pixel circuit according to an embodiment of the present invention;

[0013] Figure 4 It is a graph of the input voltage and output voltage of an inverter of a pixel circuit according to an embodiment of the present invention.

[0014] Symbol Explanation

[0015] 100: Substrate

[0016] 112: First buffer layer

[0017] 114: Second buffer layer

[0018] 120: Gate dielectric layer

[0019] 130: Interlayer dielectric layer

[0020] a: First node

[0021] b: Second node

[0022] C1: First storage capacitor

[0023] C2: Second storage capacitor

[0024] c: Third node

[0025] d: Fourth node

[0026] ch1~ch6: Channel region

[0027] D1: Second electrode

[0028] D2: Drain

[0029] EL: Light-emitting diode

[0030] G1: First electrode

[0031] G2: Gate

[0032] GND: Ground voltage

[0033] IVT: Inverter

[0034] ND: Normal direction

[0035] OS1: First metal oxide layer

[0036] OS2: Second metal oxide layer

[0037] OS3: Third metal oxide layer

[0038] OS4: Fourth metal oxide layer

[0039] OS5: Fifth metal oxide layer

[0040] OS6: Sixth metal oxide layer

[0041] OS7: Seventh metal oxide layer

[0042] OS8: Eighth metal oxide layer

[0043] OS9: Ninth metal oxide layer

[0044] PX: Pixel circuit

[0045] S1: Third electrode

[0046] S2: Source electrode

[0047] SM1: First semiconductor channel structure

[0048] SM2: Second semiconductor channel structure

[0049] SMsw, SMdr1, SMdr2, SMse: Semiconductor channel structure

[0050] sr1~sr6: Source regions

[0051] Tse: Reset transistor

[0052] Tload: Diode

[0053] Tsw1: Switch thin film transistor

[0054] Tsw2: Switch element

[0055] Tdr1: First driving transistor

[0056] Tdr2: Second driving transistor

[0057] t1, t2: Thickness

[0058] VDD1, VDD2, Vsus, Vdr1, Vdr2, Vgs: Voltages

[0059] Vdata: Data line voltage

[0060] Vdata+: High voltage level

[0061] Vdata-: Low voltage level

[0062] Vin: Input voltage

[0063] Vref: Reference voltage level

[0064] Vreset: Reset voltage

[0065] Vout: Output voltage

[0066] Vscan: Scan line voltage

[0067] V1: First contact hole

[0068] V2: Second contact hole

[0069] V3: Third contact hole

[0070] V4: Fourth contact hole

[0071] V5: Fifth contact hole

[0072] V6: Sixth contact hole

[0073] V7: Seventh contact hole

[0074] V8: Eighth contact hole

[0075] V9: Ninth contact hole

[0076] V10: Tenth contact hole

[0077] V11: Eleventh contact hole

[0078] V12: Twelfth contact hole

[0079] V13: Thirteenth contact hole

[0080] V14: Fourteenth contact hole

[0081] V15: Fifteenth contact hole Detailed implementation manners

[0082] Figure 1A is a schematic equivalent circuit diagram of an inverter according to an embodiment of the present invention. Figure 1B is a schematic cross-sectional view of an inverter according to an embodiment of the present invention.

[0083] Please refer toFigure 1A And Figure 1B , the inverter IVT includes a diode Tload and a switching thin-film transistor Tsw1. In this embodiment, the inverter IVT further includes a substrate 100, a first buffer layer 112, a second buffer layer 114, a gate dielectric layer 120, and an interlayer dielectric layer 130.

[0084] The material of the substrate 100 can be glass, quartz, organic polymer, or light-impermeable / reflection material (e.g., conductive material, metal, wafer, ceramic, or other applicable materials) or other applicable materials. If a conductive material or metal is used, an insulating layer (not shown) is covered on the substrate 100 to avoid short-circuit problems. In some embodiments, the substrate 100 is a flexible substrate, and the material of the substrate 100 is, for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethyl methacrylate (PMMA), polycarbonate (PC), polyimide (PI), or metal foil or other flexible materials.

[0085] The first buffer layer 112 is located on the substrate 100. The second buffer layer 114 is located on the first buffer layer 112. The materials of the first buffer layer 112 and the second buffer layer 114 can include silicon nitride, silicon oxide, silicon oxynitride, or other suitable materials or a stacked layer of the above materials, but the present invention is not limited thereto.

[0086] The diode Tload and the switching thin-film transistor Tsw1 are located above the substrate 100. In this embodiment, the diode Tload and the switching thin-film transistor Tsw1 are located on the second buffer layer 114.

[0087] The diode Tload includes a first semiconductor channel structure SM1, a first electrode G1, a second electrode D1, and a third electrode S1, wherein the first semiconductor channel structure SM1 includes a stack of a first metal oxide layer OS1 and a second metal oxide layer OS2. The switching thin-film transistor Tsw1 includes a second semiconductor channel structure SM2, a gate G2, a drain D2, and a source S2, wherein the second semiconductor channel structure SM2 includes a third metal oxide layer OS3.

[0088] The first metal oxide layer OS1 is located above the substrate 100. In this embodiment, the first metal oxide layer OS1 is located on the second buffer layer 114. In some embodiments, the material of the first metal oxide layer OS1 includes quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), etc. or oxides composed of ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W). In some embodiments, the thickness t1 of the first metal oxide layer OS1 is 5 nanometers to 25 nanometers.

[0089] The second metal oxide layer OS2 and the third metal oxide layer OS3 are located above the first metal oxide layer OS1 and the substrate 100. In this embodiment, the second metal oxide layer OS2 and the third metal oxide layer OS3 are located on the first metal oxide layer OS1 and the second buffer layer 114. The second metal oxide layer OS2 covers the top surface and the side walls of the first metal oxide layer OS1 and extends outward from the side walls of the first metal oxide layer OS1. In some embodiments, the materials of the second metal oxide layer OS2 and the third metal oxide layer OS3 include quaternary metal compounds such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), aluminum zinc tin oxide (AZTO), indium tungsten zinc oxide (IWZO), etc. or oxides composed of ternary metals containing any three of gallium (Ga), zinc (Zn), indium (In), tin (Sn), aluminum (Al), and tungsten (W). In some embodiments, the second metal oxide layer OS2 and the third metal oxide layer OS3 belong to the same patterned film layer. In other words, the second metal oxide layer OS2 and the third metal oxide layer OS3 are defined in the same patterning process. In some embodiments, the thickness t2 of the second metal oxide layer OS2 and the third metal oxide layer OS3 is 15 nanometers to 25 nanometers.

[0090] In some embodiments, the first semiconductor channel structure SM1 includes a source region sr1, a drain region dr1, and a channel region ch1 located between the source region sr1 and the drain region dr1. The channel region ch1 includes an overlapping portion of a first metal oxide layer OS1 and a second metal oxide layer OS2, while the source region sr1 and the drain region dr1 include portions of the second metal oxide layer OS2 that do not overlap with the first metal oxide layer OS1. Accordingly, the thickness of the channel region ch1 is greater than the thicknesses of the source region sr1 and the drain region dr1. In some embodiments, the source region sr1 and the drain region dr1 are doped to have a lower resistivity than the channel region ch1. In some embodiments, the first metal oxide layer OS1 in the channel region ch1 has a higher carrier mobility than the second metal oxide layer OS2. For example, both the first metal oxide layer OS1 and the second metal oxide layer OS2 include indium gallium zinc oxide, and the indium concentration in the first metal oxide layer OS1 is greater than the indium concentration in the second metal oxide layer OS2.

[0091] The second semiconductor channel structure SM2 includes a source region sr2, a drain region dr2, and a channel region ch2 located between the source region sr2 and the drain region dr2. In some embodiments, the source region sr2 and the drain region dr2 are doped to have a lower resistivity than the channel region ch2. In this embodiment, due to the provision of the first metal oxide layer OS1, the carrier mobility of the channel region ch1 of the first semiconductor channel structure SM1 is greater than the carrier mobility of the channel region ch2 of the second semiconductor channel structure SM2.

[0092] The gate dielectric layer 120 covers the first semiconductor channel structure SM1 and the second semiconductor channel structure SM2. In some embodiments, the material of the gate dielectric layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials. In some embodiments, the thickness of the gate dielectric layer 120 is from 50 nanometers to 200 nanometers.

[0093] The first electrode G1 and the gate G2 are located on the gate dielectric layer 120 and respectively overlap the channel region ch1 of the first semiconductor channel structure SM1 and the channel region ch2 of the second semiconductor channel structure SM2 in the normal direction ND of the top surface of the substrate 100. The gate dielectric layer 120 is located between the first semiconductor channel structure SM1 and the first electrode G1 and between the second semiconductor channel structure SM2 and the gate G2. The first electrode G1 is separated from the channel region ch1 of the first semiconductor channel structure SM1, and the gate G2 is separated from the channel region ch2 of the second semiconductor channel structure SM2.

[0094] In some embodiments, the materials of the first electrode G1 and the gate G2 may include metals such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The first electrode G1 and the gate G2 may also use other conductive materials, such as: nitrides of metals, oxides of metals, oxynitrides of metals, stacks of metals and other conductive materials, or other materials with conductive properties.

[0095] The interlayer dielectric layer 130 is located on the gate dielectric layer 120, the gate G2, and the first electrode G1. In some embodiments, the material of the interlayer dielectric layer 130 includes silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, or other insulating materials. In some embodiments, the thickness of the interlayer dielectric layer 130 is 100 nanometers to 600 nanometers.

[0096] The second electrode D1, the third electrode S1, the drain D2, and the source S2 are located on the interlayer dielectric layer 130. The second electrode D1 and the third electrode S1 are electrically connected to the drain region dr1 and the source region sr1 of the first semiconductor channel structure SM1 through the first contact hole V1 and the second contact hole V2 that penetrate the interlayer dielectric layer 130 and the gate dielectric layer 120, respectively. The drain D2 and the source S2 are electrically connected to the drain region dr2 and the source region sr2 of the second semiconductor channel structure SM2 through the third contact hole V3 and the fourth contact hole V4 that penetrate the interlayer dielectric layer 130 and the gate dielectric layer 120, respectively. The second electrode D1 is electrically connected to the first electrode G1 through the fifth contact hole V5 that penetrates the interlayer dielectric layer 130. The drain D2 is electrically connected to the third electrode S1. For example, the drain D2 and the third electrode S1 are electrically connected to the first node a. In this embodiment, the drain D2 and the third electrode S1 are integrated.

[0097] In some embodiments, the materials of the second electrode D1, the third electrode S1, the drain D2, and the source S2 may include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but the present invention is not limited thereto. The second electrode D1, the third electrode S1, the drain D2, and the source S2 may also use other conductive materials, such as: nitrides of metals, oxides of metals, oxynitrides of metals, stacks of metals and other conductive materials, or other materials with conductive properties.

[0098] The first electrode G1 and the second electrode D1 of the diode Tload are electrically connected to the signal line and electrically connected to the voltage VDD1 through the signal line. The source S2 of the switching thin-film transistor Tsw1 is electrically connected to the ground voltage GND. The input voltage Vin is applied to the gate G2 of the switching thin-film transistor Tsw1 to control the turning on or off of the switching thin-film transistor Tsw1. The source S1 of the diode Tload has an output voltage Vout.

[0099] In this embodiment, since the carrier mobility of the channel region ch1 of the first semiconductor channel structure SM1 of the diode Tload is greater than the carrier mobility of the channel region ch2 of the second semiconductor channel structure SM2 of the switching thin-film transistor Tsw1, the ratio of the resistance value of the diode Tload to the resistance value of the switching thin-film transistor Tsw1 is small. Furthermore, the magnitude of the output voltage Vout can be easily changed by adjusting the input voltage Vin, and even the inverter IVT can output an analog signal.

[0100] Figure 2A It is a schematic equivalent circuit diagram of a pixel circuit according to an embodiment of the present invention. Figure 2B It is a cross-sectional schematic diagram of a switching element, a first driving transistor, and a second driving transistor of a pixel circuit according to an embodiment of the present invention. Figure 2C It is a cross-sectional schematic diagram of a reset transistor of a pixel circuit according to an embodiment of the present invention. It must be noted here that Figures 2A to 2C The embodiment of Figure 1A and Figure 1B adopts the component labels and partial contents of the embodiments of

[0101] Please refer to Figures 2A to 2C , the pixel circuit PX includes a switching element Tsw2, an inverter IVT, a first driving transistor Tdr1, and a second driving transistor Tdr2. In this embodiment, the pixel circuit PX further includes a light-emitting diode EL, a first storage capacitor C1, a second storage capacitor C2, and a reset transistor Tse.

[0102] The switching element Tsw2, the first driving transistor Tdr1, the second driving transistor Tdr2, and the reset transistor Tse are located on the substrate 100. In this embodiment, the switching element Tsw2, the first driving transistor Tdr1, the second driving transistor Tdr2, and the reset transistor Tse are located on the second buffer layer 114.

[0103] The switching element Tsw2 includes a semiconductor channel structure SMsw, a gate Gsw, a drain Dsw, and a source Ssw, where the semiconductor channel structure SMsw includes a fourth metal oxide layer OS4. The first driving transistor Tdr1 includes a semiconductor channel structure SMdr1, a gate Gdr1, a drain Ddr1, and a source Sdr1, where the semiconductor channel structure SMdr1 includes a stack of a fifth metal oxide layer OS5 and a sixth metal oxide layer OS6. The second driving transistor Tdr2 includes a semiconductor channel structure SMdr2, a gate Gdr2, a drain Ddr2, and a source Sdr2, where the semiconductor channel structure SMdr2 includes a stack of a seventh metal oxide layer OS7 and an eighth metal oxide layer OS8. The reset transistor Tse includes a semiconductor channel structure SMse, a gate Gse, a drain Dse, and a source Sse, where the semiconductor channel structure SMse includes a ninth metal oxide layer OS9.

[0104] The fifth metal oxide layer OS5 and the seventh metal oxide layer OS7 are located above the substrate 100. In this embodiment, the fifth metal oxide layer OS5 and the seventh metal oxide layer OS7 are located on the second buffer layer 114. In some embodiments, the fifth metal oxide layer OS5, the seventh metal oxide layer OS7, and the first metal oxide layer OS1 (please refer to Figure 1B ) belong to the same patterned film layer. In other words, the fifth metal oxide layer OS5, the seventh metal oxide layer OS7, and the first metal oxide layer OS1 are defined in the same patterning process. In some embodiments, the fifth metal oxide layer OS5, the seventh metal oxide layer OS7, and the first metal oxide layer OS1 have the same material and the same thickness.

[0105] The fourth metal oxide layer OS4, the sixth metal oxide layer OS6, the eighth metal oxide layer OS8, and the ninth metal oxide layer OS9 are located above the fifth metal oxide layer OS5, the seventh metal oxide layer OS7, and the substrate 100. In this embodiment, the fourth metal oxide layer OS4, the sixth metal oxide layer OS6, the eighth metal oxide layer OS8, and the ninth metal oxide layer OS9 are located on the fifth metal oxide layer OS5, the seventh metal oxide layer OS7, and the second buffer layer 114. The sixth metal oxide layer OS6 covers the top surface and the sidewalls of the fifth metal oxide layer OS5 and extends outward from the sidewalls of the fifth metal oxide layer OS5. The eighth metal oxide layer OS8 covers the top surface and the sidewalls of the seventh metal oxide layer OS7 and extends outward from the sidewalls of the seventh metal oxide layer OS7. In some embodiments, the second metal oxide layer OS2 (please refer to Figure 1B ), the third metal oxide layer OS3 (please refer to Figure 1B) The fourth metal oxide layer OS4, the sixth metal oxide layer OS6, the eighth metal oxide layer OS8, and the ninth metal oxide layer OS9 belong to the same patterned film layer. In other words, the second metal oxide layer OS2, the third metal oxide layer OS3, the fourth metal oxide layer OS4, the sixth metal oxide layer OS6, the eighth metal oxide layer OS8, and the ninth metal oxide layer OS9 are defined in the same patterning process. In some embodiments, the second metal oxide layer OS2, the third metal oxide layer OS3, the fourth metal oxide layer OS4, the sixth metal oxide layer OS6, the eighth metal oxide layer OS8, and the ninth metal oxide layer OS9 have the same material and the same thickness.

[0106] The semiconductor channel structure SMsw includes a source region sr3, a drain region dr3, and a channel region ch3 located between the source region sr3 and the drain region dr3. In some embodiments, the source region sr3 and the drain region dr3 are doped to have a lower resistivity than the channel region ch3.

[0107] In some embodiments, the semiconductor channel structure SMdr1 includes a source region sr4, a drain region dr4, and a channel region ch4 located between the source region sr4 and the drain region dr4, where the channel region ch4 includes an overlapping portion of the fifth metal oxide layer OS5 and the sixth metal oxide layer OS6, and the source region sr4 and the drain region dr4 include portions of the sixth metal oxide layer OS6 that do not overlap with the fifth metal oxide layer OS5. Accordingly, the thickness of the channel region ch4 is greater than the thickness of the source region sr4 and the drain region dr4. In some embodiments, the source region sr4 and the drain region dr4 are doped to have a lower resistivity than the channel region ch4. In some embodiments, the fifth metal oxide layer OS5 in the channel region ch4 has a higher carrier mobility than the sixth metal oxide layer OS6.

[0108] In some embodiments, the semiconductor channel structure SMdr2 includes a source region sr5, a drain region dr5, and a channel region ch5 located between the source region sr5 and the drain region dr5, where the channel region ch5 includes an overlapping portion of the seventh metal oxide layer OS7 and the eighth metal oxide layer OS8, and the source region sr5 and the drain region dr5 include portions of the eighth metal oxide layer OS8 that do not overlap with the seventh metal oxide layer OS7. Accordingly, the thickness of the channel region ch5 is greater than the thickness of the source region sr5 and the drain region dr5. In some embodiments, the source region sr5 and the drain region dr5 are doped to have a lower resistivity than the channel region ch5. In some embodiments, the seventh metal oxide layer OS7 in the channel region ch5 has a higher carrier mobility than the eighth metal oxide layer OS8.

[0109] The semiconductor channel structure SMse includes a source region sr6, a drain region dr6, and a channel region ch6 located between the source region sr6 and the drain region dr6. In some embodiments, the source region sr6 and the drain region dr6 are doped to have a lower resistivity than the channel region ch6.

[0110] In this embodiment, the semiconductor channel structures SMsw, SMdr1, SMdr2, and SMse include metal oxide semiconductor materials, but the present invention is not limited thereto. In other embodiments, the semiconductor channel structures SMsw, SMdr1, SMdr2, and SMse include polysilicon, amorphous silicon, microcrystalline silicon, organic semiconductors, or other suitable semiconductor materials. In this embodiment, the semiconductor channel structures SMdr1 and SMdr2 are both multi-layer structures, but the present invention is not limited thereto. In other embodiments, the semiconductor channel structures SMdr1 and SMdr2 can be single-layer structures, for example, only having a fifth metal oxide layer OS5 and a seventh metal oxide layer OS7 respectively, or only having a sixth metal oxide layer OS6 and an eighth metal oxide layer OS8 respectively.

[0111] The gate dielectric layer 120 covers the semiconductor channel structures SMsw, SMdr1, SMdr2, and SMse.

[0112] The gates Gsw, Gdr1, Gdr2, and Gse are located on the gate dielectric layer 120 and respectively overlap the channel regions ch3 of the semiconductor channel structure SMsw, the channel region ch4 of the semiconductor channel structure SMdr1, the channel region ch5 of the semiconductor channel structure SMdr2, and the channel region ch6 of the semiconductor channel structure SMse in the normal direction ND of the top surface of the substrate 100.

[0113] In some embodiments, the gates Gsw, Gdr1, Gdr2, Gse, the first electrode G1 (please refer to Figure 1B ) and the gate G2 (please refer to Figure 1B)Belong to the same patterned film layer. In other words, the gate Gsw, the gate Gdr1, the gate Gdr2, the gate Gse, the first electrode G1, and the gate G2 are defined in the same patterning process. In some embodiments, the gate Gsw, the gate Gdr1, the gate Gdr2, the gate Gse, the first electrode G1, and the gate G2 have the same material. The gate Gsw of the switching element Tsw2 is electrically connected to a scan line (not shown) and is electrically connected to the scan line voltage Vscan through the scan line. The gate Gse of the reset transistor Tse is electrically connected to a reset signal line (not shown) and is electrically connected to the reset voltage Vreset through the reset signal line.

[0114] The interlayer dielectric layer 130 is located on the gate dielectric layer 120, the gate Gsw, the gate Gdr1, the gate Gdr2, and the gate Gse.

[0115] The drain Dsw, the source Ssw, the drain Ddr1, the source Sdr1, the drain Ddr2, the source Sdr2, the drain Dse, and the source Sse are located on the interlayer dielectric layer 130. The drain Dsw and the source Ssw are electrically connected to the drain region dr3 and the source region sr3 of the semiconductor channel structure SMsw through the sixth contact hole V6 and the seventh contact hole V7 that penetrate through the interlayer dielectric layer 130 and the gate dielectric layer 120, respectively. The drain Ddr1 and the source Sdr1 are electrically connected to the drain region dr4 and the source region sr4 of the semiconductor channel structure SMdr1 through the eighth contact hole V8 and the ninth contact hole V9 that penetrate through the interlayer dielectric layer 130 and the gate dielectric layer 120, respectively. The drain Ddr2 and the source Sdr2 are electrically connected to the drain region dr5 and the source region sr5 of the semiconductor channel structure SMdr2 through the tenth contact hole V10 and the eleventh contact hole V11 that penetrate through the interlayer dielectric layer 130 and the gate dielectric layer 120, respectively.

[0116] The drain Dsw of the switching element Tsw2 is electrically connected to a data line (not shown) and is electrically connected to the data line voltage Vdata through the data line.

[0117] The source Ssw of the switching element Tsw2, the gate G of the switching thin film transistor Tsw1 (please refer to Figure 1B ), one end of the first storage capacitor C1, and the gate Gdr1 of the first driving transistor Tdr1 are electrically connected to the second node b. For example, the source Ssw is electrically connected to the gate Gdr1 through the twelfth contact hole V12 that penetrates through the interlayer dielectric layer 130 and is electrically connected to the gate G of the switching thin film transistor Tsw1 (please refer to Figure 1B ) through other contact holes (not shown) that penetrate through the interlayer dielectric layer 130.

[0118] The first node a, one end of the second storage capacitor C2, and the gate Gdr2 of the second driving transistor Tdr2 are electrically connected to the third node c. For example, the third electrode S1 of the diode and / or the drain D2 of the switching thin film transistor are electrically connected to the gate Gdr2 through the thirteenth contact hole V13 passing through the interlayer dielectric layer 130. Based on the foregoing, the gate Gdr2 of the second driving transistor Tdr2 is electrically connected to the source Ssw of the switching element Tsw2 through the inverter IVT.

[0119] The drain Dse and the source Sse are electrically connected to the drain region dr6 and the source region sr6 of the semiconductor channel structure SMse through the fourteenth contact hole V14 and the fifteenth contact hole V15 passing through the interlayer dielectric layer 130 and the gate dielectric layer 120, respectively.

[0120] In some embodiments, the second electrode D1 (please refer to Figure 1B ), the third electrode S1 (please refer to Figure 1B ), the drain D2 (please refer to Figure 1B ), the source S2 (please refer to Figure 1B ), the drain Dsw, the source Ssw, the drain Ddr1, the source Sdr1, the drain Ddr2, the source Sdr2, the drain Dse, and the source Sse belong to the same patterned film layer. In other words, the second electrode D1, the third electrode S1, the drain D2, the source S2, the drain Dsw, the source Ssw, the drain Ddr1, the source Sdr1, the drain Ddr2, the source Sdr2, the drain Dse, and the source Sse are defined in the same patterning process. In some embodiments, the second electrode D1, the third electrode S1, the drain D2, the source S2, the drain Dsw, the source Ssw, the drain Ddr1, the source Sdr1, the drain Ddr2, the source Sdr2, the drain Dse, and the source Sse have the same material.

[0121] The drain Ddr1 of the first driving transistor Tdr1 and the drain Ddr2 of the second driving transistor Tdr2 are electrically connected to each other. The drain Ddr1 and the drain Ddr2 are electrically connected to the signal line and are electrically connected to the voltage VDD2 through the signal line. In some embodiments, the voltage VDD1 is substantially equal to the voltage VDD2. The source Sdr1 of the first driving transistor Tdr1, the source Sdr2 of the second driving transistor Tdr2, the other end of the first storage capacitor C1, the other end of the second storage capacitor C2, the drain Dse of the reset transistor Tse, and one end of the light emitting diode are electrically connected to the fourth node d.

[0122] The first storage capacitor C1 is electrically connected to the gate Gdr1 and the source Sdr1 of the first driving transistor Tdr1. The second storage capacitor C2 is electrically connected to the gate Gdr2 and the source Sdr2 of the second driving transistor Tdr2. The light-emitting diode EL is electrically connected to the source Sdr1 of the first driving transistor Tdr1 and the source Sdr2 of the second driving transistor Tdr2. The drain Dse of the reset transistor Tse is electrically connected to the source Sdr1 of the driving transistor Tdr1 and the source Sdr2 of the second driving transistor Tdr2. The source Sse of the reset transistor Tse is electrically connected to the voltage Vsus. The light-emitting diode EL is, for example, a micro light-emitting diode, an organic light-emitting diode, or other light-emitting elements.

[0123] Figure 3 is an operation signal timing diagram of a pixel circuit according to an embodiment of the present invention. In Figure 3 , the horizontal axis represents time, and the vertical axis represents the magnitude of the voltage. Additionally, Figure 3 the voltage Vd in

[0124] Please refer to Figure 2A and Figure 3 simultaneously. First, reset the signals of the pixel circuit PX. Specifically, increase the scan line voltage Vscan and the reset voltage Vreset to turn on the gate Gsw of the switching element Tsw2 and the gate Gse of the reset transistor Tse. At the same time, adjust the data line voltage Vdata to the reference voltage level Vref. At this time, the gates Gdr1 of the first driving transistor Tdr1 and the gate Gdr2 of the second driving transistor Tdr2 are both in the off state, where the voltage Vdr1 on the gate Gdr1 is substantially equal to the input voltage Vin of the inverter IVT, and the voltage Vdr2 on the gate Gdr2 is substantially equal to the output voltage Vout of the inverter IVT. In some embodiments, when resetting the signals of the pixel circuit PX, the input voltage Vin of the inverter IVT is equal to the output voltage Vout.

[0125] Next, charge the first storage capacitor C1. Specifically, lower the reset voltage Vreset to turn off the gate Gse of the reset transistor Tse. At the same time, continuously turn on the gate Gsw of the switching element Tsw2 and adjust the data line voltage Vdata to a high voltage level Vdata+ (e.g., a positive voltage), thereby boosting the voltage Vdr1 on the gate Gdr1 of the first driving transistor Tdr1 to turn on the gate Gdr1 of the first driving transistor Tdr1. At the same time, the input voltage Vin of the inverter IVT is also boosted, so the gate G of the switching thin-film transistor Tsw1 will be turned on and the output voltage Vout of the inverter IVT will drop. This causes the voltage Vdr2 on the gate Gdr2 of the second driving transistor Tdr2 to drop and turns off the gate Gdr2 of the second driving transistor Tdr2. After such an operation, there is a voltage difference across the first storage capacitor C1, whereby the first storage capacitor C1 can be charged.

[0126] Then, lower the scan line voltage Vscan and lower the data line voltage Vdata to the reference voltage level Vref. Since the first storage capacitor C1 is electrically connected to the gate Gdr1 of the first driving transistor Tdr1, even if the gate Gsw of the switching element Tsw2 is turned off, the gate Gdr1 of the first driving transistor Tdr1 can remain turned on for a period of time. Since the gate Gdr1 of the first driving transistor Tdr1 has been turned on, the light-emitting diode EL can be lit by the current passing through the first driving transistor Tdr1. At the same time, since the gate Gdr2 of the second driving transistor Tdr2 has been turned off, current will not pass through the second driving transistor Tdr2 (or only a very small amount of current can pass through).

[0127] Next, reset the signals of the pixel circuit PX again. Specifically, raise the scan line voltage Vscan and the reset voltage Vreset to turn on the gate Gsw of the switching element Tsw2 and the gate Gse of the reset transistor Tse. At the same time, maintain the data line voltage Vdata at the reference voltage level Vref. At this time, both the gate Gdr1 of the first driving transistor Tdr1 and the gate Gdr2 of the second driving transistor Tdr2 are in the off state.

[0128] Then, charge the second storage capacitor C2. Specifically, lower the reset voltage Vreset to turn off the gate Gse of the reset transistor Tse. At the same time, continuously turn on the gate Gsw of the switching element Tsw2 and adjust the data line voltage Vdata to a low voltage level Vdata- (for example, a negative voltage), thereby reducing the voltage Vdr1 on the gate Gdr1 of the first driving transistor Tdr1 and turning off the gate Gdr1 of the first driving transistor Tdr1. At the same time, the input voltage Vin of the inverter IVT is also reduced. Therefore, the gate G of the switching thin film transistor Tsw1 will be turned off, and the output voltage Vout of the inverter IVT will increase. This causes the voltage Vdr2 on the gate Gdr2 of the second driving transistor Tdr2 to rise and turns on the gate Gdr2 of the second driving transistor Tdr2. After such an operation, there is a voltage difference across the second storage capacitor C2, whereby the second storage capacitor C2 can be charged.

[0129] Then, lower the scan line voltage Vscan and raise the data line voltage Vdata to the reference voltage level Vref. Since the second storage capacitor C2 is electrically connected to the gate Gdr2 of the second driving transistor Tdr2. Since the gate Gdr2 of the second driving transistor Tdr2 has been turned on, the light-emitting diode EL can be lit by the current passing through the second driving transistor Tdr2. At the same time, since the gate Gdr1 of the first driving transistor Tdr1 has been turned off, current will not pass through the first driving transistor Tdr1 (or only a very small amount of current can pass through). In some embodiments, the voltage VDD1 becomes 0 potential after the second driving transistor Tdr2 is turned on. At this time, the gate of the diode Tload is turned off, and together with the switching thin film transistor Tsw1 being turned off, the inverter does not work at this time. Since the second storage capacitor C2 is electrically connected to the gate Gdr2 of the second driving transistor Tdr2, even if the inverter is turned off, the gate Gdr2 of the second driving transistor Tdr2 can remain turned on for a period of time. In other embodiments, the voltage VDD1 is a fixed potential, and when the second driving transistor Tdr2 is turned on, the second storage capacitor C2 only serves to stabilize the gate voltage of the second driving transistor Tdr2.

[0130] Based on the above, since the light-emitting diode EL is lit alternately through the first driving transistor Tdr1 and the second driving transistor Tdr2, the time during which the first driving transistor Tdr1 and the second driving transistor Tdr2 are each subjected to current stress can be reduced, thereby improving the degradation problems of the first driving transistor Tdr1 and the second driving transistor Tdr2.

[0131] Figure 4It is a graph showing the input voltage and output voltage of an inverter of a pixel circuit according to an embodiment of the present invention. For the specific structure of the pixel circuit, reference can be made to the foregoing embodiments, which will not be elaborated herein. Table 1 shows the input voltage Vin, output voltage Vout, voltage Vsus, and voltage Vgs of the inverter when the brightness of the light-emitting diode EL is L0 and L255, where the voltage Vgs is the voltage difference between the gate and the source of the first driving transistor Tdr1 or the voltage difference between the gate and the source of the second driving transistor Tdr2.

[0132] Table 1

[0133]

[0134] Please refer to Figure 2A 、 Figure 3 、 Figure 4 and Table 1. During the period when the data line voltage is at the low voltage level Vdata-, the input voltage Vin of the inverter IVT is negative and the output voltage Vout is positive. At this time, the gate of the first driving transistor Tdr1 is closed and the gate of the second driving transistor Tdr2 is open. When the output voltage Vout is 5V and the input voltage Vin is -10V, the current provided by the second driving transistor Tdr2 makes the brightness of the light-emitting diode EL L255.

[0135] When the output voltage Vout is 0V and the input voltage Vin is 0V, the light-emitting diode EL does not emit light (brightness is L0).

[0136] During the period when the data line voltage is at the high voltage level Vdata+, the input voltage Vin of the inverter IVT is positive and the output voltage Vout is negative. At this time, the gate of the second driving transistor Tdr2 is closed and the gate of the first driving transistor Tdr1 is open. When the output voltage Vout is -3V and the input voltage Vin is 5V, the current provided by the first driving transistor Tdr1 makes the brightness of the light-emitting diode EL L255.

[0137] In some embodiments, the data line voltage Vdata is -10V to 5V, the output voltage Vout of the inverter IVT is -3V to 5V, and the voltage difference Vgs between the gate and the source of the first driving transistor Tdr1 and the voltage difference between the gate and the source of the second driving transistor Tdr1 are -4V to 4V.

Claims

1. A pixel circuit, comprising: A switching element electrically connected to a scan line and a data line, a gate of the switching element being electrically connected to a scan line voltage Vscan through the scan line, and a drain of the switching element being electrically connected to a data line voltage Vdata through the data line; An inverter, comprising: A transistor acting as a diode, electrically connected to a voltage VDD1, the transistor acting as a diode having an output voltage Vout; and A switching thin-film transistor electrically connected to the transistor acting as a diode, a source of the switching thin-film transistor being electrically connected to a ground voltage GND, a source of the switching element providing an input voltage Vin applied to a gate of the switching thin-film transistor to control turning on or off of the switching thin-film transistor, wherein a carrier mobility of a first channel region of a first semiconductor channel structure of the transistor acting as a diode is greater than a carrier mobility of a second channel region of a second semiconductor channel structure of the switching thin-film transistor; A first driving transistor, a first gate of the first driving transistor being electrically connected to the source of the switching element and the gate of the switching thin-film transistor; A second driving transistor, a second gate of the second driving transistor being electrically connected to the source of the switching element through the inverter, a drain of the first driving transistor and a drain of the second driving transistor being electrically connected to each other and electrically connected to a voltage VDD2; and A light-emitting diode electrically connected to the source of the first driving transistor and the source of the second driving transistor.

2. The pixel circuit according to claim 1, further comprising: A first storage capacitor, one end of the first storage capacitor being electrically connected to the source of the switching element, the gate of the switching thin-film transistor, and the gate of the first driving transistor, and the other end of the first storage capacitor being electrically connected to the source of the first driving transistor and the source of the second driving transistor; And A second storage capacitor, one end of the second storage capacitor being electrically connected to the gate of the second driving transistor, and the other end of the second storage capacitor being electrically connected to the other end of the first storage capacitor and the source of the second driving transistor.

3. The pixel circuit according to claim 2, further comprising: A reset transistor, a gate of the reset transistor being electrically connected to a reset voltage Vreset through a reset signal line, a source of the reset transistor being electrically connected to a voltage Vsus, and a drain of the reset transistor being electrically connected to the source of the first driving transistor and the source of the second driving transistor.

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