Memory and method of programming the same, storage system

Abstract

This application provides a memory and its programming method and storage system, belonging to the field of storage technology. The memory provided by this application can provide a programming voltage to the select word line and a pass voltage to the first non-select word line through a first voltage generation circuit. Therefore, when leakage occurs in the first non-select word line, the programming voltage provided by the first voltage generation circuit will decrease, or the time required for the voltage provided by the first voltage generation circuit to reach the programming voltage will increase, thereby causing the memory cell coupled to the select word line to fail to program. Since the control circuit can promptly stop the programming operation on the memory cell in the memory block when it detects a programming failure in the memory cell coupled to the select word line, it can effectively prevent the written data from being incorrectly read due to leakage in the first non-select word line.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, its programming method, and a storage system. Background Technology

[0002] A 3D memory is a type of memory that arranges multiple memory strings in an array. Each memory string includes at least one up select transistor, multiple memory cells, and at least one down select transistor connected in sequence. Furthermore, memory cells located in the same layer can be coupled to the same word line (WL).

[0003] Due to manufacturing processes, the bottom layer (WL) of a memory chip (near the lower select transistor) is more prone to leakage. When reverse programming the memory (programming the memory cells coupled to each WL sequentially from the upper select transistor to the lower select transistor), a phenomenon occurs where the memory cells coupled to the top WL can still be programmed even if the bottom WL has leakage. However, when programming to the memory cells coupled to a WL adjacent to the bottom WL, leakage in the bottom WL may cause several adjacent WLs to burn out, resulting in the data in the programmed memory cells being unreadable. Summary of the Invention

[0004] This application provides a memory, its programming method, and a storage system, which can solve the technical problem that leakage current in the memory's WL (Wastewater) layer causes data in the programmed memory cells to be unable to be read correctly. The technical solution is as follows:

[0005] In a first aspect, a memory is provided, the memory comprising: a memory block, a word line selection circuit, a first voltage generation circuit, a second voltage generation circuit, and a control circuit;

[0006] The memory block includes multiple memory cells coupled to different word lines, and the multiple output terminals of the word line selection circuit are connected one-to-one with the multiple word lines in the memory block;

[0007] The first voltage generating circuit and the second voltage generating circuit are respectively connected to different output terminals of the word line selection circuit. The first voltage generating circuit is used to provide programming voltage and first pass voltage, and the second voltage generating circuit is used to provide second pass voltage.

[0008] The control circuit is connected to the word line selection circuit, and the control circuit is used for:

[0009] The word line selection circuit is controlled to apply the programming voltage to the selected word line in the memory block, apply the first through voltage to the first non-selected word line in the memory block, and apply the second through voltage to the second non-selected word line in the memory block;

[0010] If a programming failure is detected in the memory cell coupled to the select word line, the programming operation on the memory cell in the memory block is stopped.

[0011] Optionally, the first voltage generating circuit includes: a first charge pump circuit and at least one first voltage regulating circuit;

[0012] The first charge pump circuit is connected to the input terminal of the word line selection circuit and is used to provide the programming voltage;

[0013] Each of the at least one first voltage regulation circuits is connected to the input terminals of the first charge pump circuit and the word line selection circuit, respectively, and is used to provide the first pass voltage under the drive of the first charge pump circuit.

[0014] Optionally, the first charge pump circuit includes: a first charge pump and a second voltage regulation circuit;

[0015] The first charge pump is used to provide a first initial voltage;

[0016] The second voltage regulation circuit is connected to the input terminals of the first charge pump and the word line selection circuit, respectively, and is used to convert the first initial voltage into the programming voltage;

[0017] The first voltage regulation circuit is connected to the second voltage regulation circuit and is used to convert the programming voltage into the first pass voltage;

[0018] Alternatively, the first voltage regulation circuit is connected to the first charge pump and is used to convert the first initial voltage into the first pass voltage.

[0019] Optionally, the first voltage generating circuit includes a plurality of first voltage regulating circuits, and the first pass voltages provided by the plurality of first voltage regulating circuits are different from each other.

[0020] Optionally, the first voltage generating circuit further includes a current limiting circuit;

[0021] The current limiting circuit is connected between the input terminals of the first charge pump circuit and the word line selection circuit, and the current limiting circuit is used to limit the current output by the first charge pump circuit.

[0022] Optionally, the first voltage generating circuit further includes at least one current amplification circuit corresponding to the at least one first voltage regulating circuit;

[0023] Each of the current amplification circuits is connected in series with a corresponding first voltage regulation circuit between the input terminals of the first charge pump circuit and the word line selection circuit, and is used to amplify the current.

[0024] Optionally, the second voltage generating circuit includes: a second charge pump and at least one third voltage regulating circuit;

[0025] The second charge pump is used to provide a second initial voltage;

[0026] Each of the at least one third voltage regulation circuit is connected to the input terminals of the second charge pump and the word line selection circuit, respectively, and is used to convert the second initial voltage into the second pass voltage;

[0027] The second pass voltage obtained by different third voltage regulation circuits is different from each other.

[0028] Optionally, the first non-select word line is closer to the lower select tube in the memory block than the second non-select word line.

[0029] Optionally, the control circuit is further configured to: control a plurality of memory cells in the memory block to be programmed in a direction from the upper select transistor to the lower select transistor.

[0030] Optionally, the control circuit is further configured to: mark the memory block as a bad block if a programming failure is detected in the memory cell coupled to the select word line.

[0031] Optionally, the control circuit is further configured to: if the number of programming pulses loaded onto the select word line is greater than a threshold number, determine that the memory cell coupled to the select word line has failed to be programmed.

[0032] Secondly, a method for programming a memory is provided, the memory including a storage block, a first voltage generation circuit, and a second voltage generation circuit; the method includes:

[0033] The first voltage generating circuit applies a programming voltage to the select word line in the memory block and applies a first pass voltage to the first non-select word line in the memory block.

[0034] A second pass voltage is applied to the second non-select word line in the memory block through the second voltage generation circuit;

[0035] If a programming failure is detected in the memory cell coupled to the select word line, the programming operation on the memory cell in the memory block is stopped.

[0036] Optionally, leakage current in the first non-select word line can cause the programming voltage provided by the first voltage generation circuit to decrease; the method further includes: if a programming failure of the memory cell coupled to the select word line is detected, then marking the memory block as a bad block.

[0037] Optionally, the method further includes:

[0038] If the number of programming pulses loaded onto the select word line is greater than a threshold, it is determined that the memory cell coupled to the select word line has failed to be programmed.

[0039] Optionally, the first non-select word line is closer to the lower select transistor in the memory block than the second non-select word line. The programming directions of the plurality of memory cells in the memory block are opposite.

[0040] Thirdly, a storage system is provided, the storage system comprising: a memory controller, and at least one memory as provided in the first aspect above.

[0041] The technical solution provided in this application may include the following beneficial effects:

[0042] This application provides a memory, its programming method, and a storage system. The memory provided by this application can provide a programming voltage to the select word line and a pass voltage to the first non-select word line via a first voltage generation circuit. Therefore, when leakage occurs on the first non-select word line, the programming voltage provided by the first voltage generation circuit will decrease, leading to programming failure of the memory cell coupled to the select word line. Since the control circuit can promptly stop programming operations on the memory cells in the memory block when it detects programming failure of the memory cell coupled to the select word line, it can effectively prevent written data from being incorrectly read due to leakage on the first non-select word line. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is a schematic diagram of the structure of a storage system provided in an embodiment of this application;

[0045] Figure 2This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0046] Figure 3 This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0047] Figure 4 This is a schematic diagram of a storage string structure provided in an embodiment of this application;

[0048] Figure 5 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0049] Figure 6 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0050] Figure 7 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0051] Figure 8 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0052] Figure 9 This is a leakage current distribution diagram between the bottom WL and CH provided in an embodiment of this application;

[0053] Figure 10 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0054] Figure 11 This is a flowchart illustrating a memory programming method provided in an embodiment of this application;

[0055] Figure 12 This is a flowchart of another memory programming method provided in an embodiment of this application. Detailed Implementation

[0056] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0057] The solutions provided in this application can be applied to electronic devices. These electronic devices can be mobile terminals, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality devices, augmented reality devices, or any other suitable electronic device having memory.

[0058] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 1As shown, the electronic device includes a storage system 1000 and a host 2000. The host 2000 can be a central processing unit (CPU) or a system-on-chip (SOC) of the electronic device. The host 2000 is used to send data to the storage system 1000 for storage, or to read data from the storage system 1000.

[0059] refer to Figure 1 The storage system 1000 includes a memory controller 200 and at least one memory 100 for storing data, for example... Figure 1 Multiple memories 100 are shown. Each memory 100 can be a three-dimensional (3D) memory, such as a 3D NAND flash memory. A memory controller 200 is connected to both the memory 100 and the host 2000. The memory controller 200 is used to manage the data stored in the memory 100 and to communicate with the host 2000.

[0060] In this embodiment, the memory controller 200 and at least one memory 100 can be integrated, meaning the storage system 1000 can be integrated into a single storage device. As a possible example, the memory controller 200 and a single memory 100 can be integrated into a memory card. This memory card may include PCMCIA cards, compact flash (CF) cards, smart media (SM) cards, memory sticks, multimedia cards (MMC), secure digital (SD) cards, and universal flash storage (UFS), etc. As another possible example, the memory controller 200 and multiple memories 100 can be integrated into a solid-state disk (SSD).

[0061] Figure 2 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 2 As shown, the memory 100 includes peripheral circuitry 110 and a memory array 120. The peripheral circuitry 110 is used to write data to and read data from the memory array 120. The memory array 120 may include at least one memory block 121, for example... Figure 2 Multiple storage blocks 121 are shown in the figure. Figure 3 This is a schematic diagram of a storage block structure provided in an embodiment of this application, with reference to... Figure 3 Each memory block 121 in the memory array 120 may include a plurality of memory strings 1211, which are arranged along a bearing surface parallel to the substrate (i.e., Figure 3 The memory cells are arranged in the XY plane of the substrate. Each memory string 1211 includes multiple memory cells connected in series, which are arranged in a direction perpendicular to the bearing surface of the substrate (i.e., the XY plane of the substrate). Figure 3 The memory cells are arranged in the Z-direction. Each memory cell can be a floating-gate field-effect transistor or a charge-trap field-effect transistor.

[0062] like Figure 3 As shown, each memory string 1211 further includes at least one upper select transistor connected to the first pole of the first memory cell, and at least one lower select transistor connected to the second pole of the last memory cell. The upper select transistor is also called a top select gate (TSG) or drain select transistor, and the lower select transistor is also called a bottom select gate (BSG) or source select transistor.

[0063] Each TSG's gate is connected to the drain select line (DSL), and the second terminal of each TSG is connected to the first terminal of the first memory cell in its memory string. The first terminal of each TSG is also connected to the bit line (BL). Each BSG's gate is connected to the source select line (SSL), and the first terminal of each BSG is connected to the second terminal of the last memory cell in its memory string. The second terminal of each BSG is also connected to the source line (SL). It is understood that the first terminal mentioned above can refer to either the source or the drain, and the second terminal can refer to the other. For example, the first terminal could refer to the drain, and the second terminal could refer to the source.

[0064] from Figure 3 As can be seen, the storage array 120 includes n BLs (BL1 to BLn) arranged along direction X, x DSLs (DSL1 to DSLx) arranged along direction Y, and x SSLs (SSL1 to SSLx) arranged along direction Y. Here, n and x are both integers greater than 1. Each DSL is connected to the gate of the n TSGs arranged along direction X, each BL is connected to the first electrode of the x TSGs arranged along direction Y, and each SSL is connected to the gate of the n BSGs arranged along direction X. Furthermore, the second electrode of each BSG is connected to the same SL.

[0065] Continue to refer to Figure 3 Each memory cell in a memory string 1211 shares a set of memory lines (WLs) with memory cells in other memory strings 1211. Assuming each memory string 121 includes m memory cells, each memory block 121 in the memory array 120 can include m WLs arranged along the Z direction: WL1 to WLm. m is an integer greater than 1. For example, m can be 64 or 128. Each WL is connected to each memory cell located on the same layer (i.e., having the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell on the same layer, and the gate connection lines between the control gates, constitute a WL.

[0066] Peripheral circuitry 110 can be connected to the memory cells in memory array 120 via BL, WL, DSL, SSL, and SL. For example... Figure 2 As shown, the peripheral circuit 110 may include a voltage generator 111, a data buffer (also known as a page buffer or sense amplifier) ​​112, a column decoder (also known as a bit line driver) 113, a row decoder (also known as a word line driver circuit or word line selection circuit) 114, and a control logic circuit 115.

[0067] The voltage generator 111 is connected to the control logic circuit 115 and, under the control of the control logic circuit 115, generates word line voltages (e.g., read voltage, programming voltage, pass voltage, and verification voltage), bit line voltages, and source line voltages for application to the memory array 120. The voltage generator 111 in related technologies generally includes multiple voltage generation circuits, each used to provide a word line voltage, or to provide a bit line voltage or a source line voltage. For example, the voltage generator 111 in related technologies includes a voltage generation circuit dedicated to providing a programming voltage and a voltage generation circuit dedicated to providing a pass voltage.

[0068] Data buffer 112 is used to read data from memory array 120 under the control of control logic circuitry 115. In one example, data buffer 112 may store data to be programmed into memory array 120. In another example, data buffer 112 may perform a programming verification operation to ensure that data has been correctly programmed into the memory cell connected to the selected word line. In yet another example, data buffer 112 may also sense voltage signals from bit lines representing data bits stored in the memory cell and amplify the sensed voltage signals to a recognizable logic level.

[0069] The column decoder 113 is connected to each bit line of the memory array 120 and is used to apply bit line voltages from the voltage generator 111 to each bit line of the memory array 120 under the control of the control logic circuit 115.

[0070] The row decoder 114 is connected to each row line of the memory array 120 and, under the control of the control logic circuit 115, applies row line voltages from the voltage generator 111 to each row line of the memory array 120. Each row line of the memory array 120 includes a word line, a drain select line, a source select line, and a source line. For example, during the programming phase, the row decoder 114, under the control of the control logic circuit 115, can apply a programming voltage to the selected word line and a pass voltage to the non-selected word line.

[0071] Figure 4 This is a schematic diagram of a storage string structure provided in an embodiment of this application. (Combined with...) Figure 3 and Figure 4 As can be seen, each storage string 1211 can also include at least one dummy (DMY) storage unit between its TSG and storage cells, between storage cells, and between a storage cell and its BSG. The dummy storage unit can be connected to dummy storage units in other storage strings via a dummy word line (DWL).

[0072] The programming methods for memory 100 generally include forward programming and reverse programming. Forward programming refers to programming the memory cells coupled to each WL sequentially from BSG to TSG. Reverse programming refers to programming the memory cells coupled to each WL sequentially from TSG to BSG. Because reverse programming effectively reduces programming disturbance, it is more widely used.

[0073] When programming the memory cell coupled to the selected WL, a programming voltage needs to be applied to the selected WL, and a pass voltage needs to be applied to other WLs (i.e., non-selected WLs), which is less than the programming voltage. Furthermore, in related technologies, the programming voltage and the pass voltage are provided by different voltage generation circuits in the voltage generator 111.

[0074] Understandably, due to the limitations of the memory manufacturing process, the bottom WL (i.e., the WL closest to the BSG) in each memory block 121 has relatively poor performance. Therefore, this bottom WL typically reaches end-of-life (EOL) first, meaning it is usually the first to fail or damage. Furthermore, the bottom WL is also a significant factor affecting the defective parts per million (DPPM) rate of the memory 100.

[0075] In forward programming scenarios, since programming starts from the memory cell coupled to the bottom WL, even if the bottom WL is damaged and leakage occurs between it and the channel hole (CH) or other WLs, it will only cause the memory cell coupled to that bottom WL to fail to program, and will not cause the data already programmed in the memory block to be lost.

[0076] In reverse programming scenarios, since programming begins with the memory cell coupled to the top write-level (WL) (i.e., the WL closest to the TSG), even if the bottom write-level is damaged and leaks current with the core communication (CH) or other write-levels (WLs), it will not affect the normal programming of the memory cell coupled to the top write-level. That is, the memory cell coupled to the top write-level can still be programmed successfully (programpass). However, when programming reaches the memory cell coupled to a WL adjacent to the bottom write-level, due to the leakage current in the bottom write-level and the higher programming voltage applied to that adjacent WL, a large voltage difference will occur. This large voltage difference will cause that adjacent WL, as well as other WLs adjacent to it that have already been programmed, to burn out. Consequently, the data in the memory cell coupled to the programmed WL cannot be read correctly, that is, it will cause an uncorrectable error correction code (UECC) in the memory cell.

[0077] Example, reference Figure 4 Suppose that WLm, located at the bottom of memory block 121, is burned out during an erase operation, causing leakage between it and CH. When programming the memory cell coupled to WL0, a higher programming voltage Vpe is applied to WL0, and a pass voltage Vpass is applied to other non-selected WLs, including WLm. Since WLm is far from WL0 and is powered by different voltage generation circuits, the leakage of WLm only affects the pass voltage Vpass applied to WLm, and does not affect the programming voltage Vpe applied to WL0. Accordingly, the memory cell coupled to WL0 can be programmed. Similarly, the memory cells coupled to WL1 to WLm-2 can also be programmed sequentially.

[0078] When programming the memory cells coupled to WLm-1, leakage between WLm and CH will cause WLm-1, WLm-2, and WLm-3 to burn out. This will lead to programming failure of WLm-1, and the data in the memory cells coupled to WLm-2 and WLm-3 will be unreadable, resulting in data loss in these memory cells.

[0079] Based on the above analysis, it can be seen that in reverse programming scenarios, even if there is leakage in the bottom WL, the memory cell coupled to the top WL can still be programmed. However, when programming reaches the memory cell coupled to a WL adjacent to the bottom WL, it will cause leakage in several WLs adjacent to the bottom WL, which will lead to UECC in the programmed memory cell.

[0080] It is understandable that if there is leakage in the top WL of storage block 121, in the scenario of forward programming, it will also cause several WL adjacent to the top WL to leak, which will lead to UECC in the memory cell that has been programmed.

[0081] Figure 5 This is a schematic diagram of another memory structure provided in an embodiment of this application. This memory 100 can solve the technical problem of data loss in programmed memory cells within a memory block due to WL leakage. (Reference) Figure 5 The memory 100 includes: a memory block 101, a word line selection circuit 102, a first voltage generation circuit 103, a second voltage generation circuit 104, and a control circuit 105.

[0082] The memory block 101 includes multiple memory cells coupled to different word lines (WLs). The word line selection circuit 102 has multiple output terminals, which are connected one-to-one with each WL in the memory block 101. The structure of the memory block 101 can be referred to... Figure 3 The word line selection circuit 102 can be Figure 2 The line decoder 114 in the middle. Combined with... Figure 2 As can be seen, the memory 100 provided in this application embodiment may include multiple memory blocks. Figure 5 The storage block 101 shown can be any one of the plurality of storage blocks.

[0083] like Figure 5 As shown, the first voltage generating circuit 103 and the second voltage generating circuit 104 are respectively connected to different output terminals of the word line selection circuit 102. The first voltage generating circuit 103 is used to provide the programming voltage Vpe and the first pass voltage Vpass1, and the second voltage generating circuit 104 is used to provide the second pass voltage Vpass2. It can be understood that both the first voltage generating circuit 103 and the second voltage generating circuit 104 can belong to... Figure 2 Voltage generator 111 in memory 100 shown.

[0084] In this system, both the second pass voltage Vpass2 and the first pass voltage Vpass1 are less than the programming voltage Vpe, and the second pass voltage Vpass2 may be equal to or unequal to the first pass voltage Vpass1. For example, the programming voltage Vpe may be around 24V or 25V, and the values ​​of the first pass voltage Vpass1 and the second pass voltage Vpass2 may range from 5V to 7V, for example, around 6V.

[0085] Continue to refer to Figure 5 The control circuit 105 is connected to the word line selection circuit 102, and the control circuit 105 can be used for:

[0086] The control word line selection circuit 102 loads the programming voltage Vpe provided by the first voltage generation circuit 103 into the select word line sel_WL in the storage block 101, loads the first pass voltage Vpass1 provided by the first voltage generation circuit 103 into the first non-select word line unsel_WL1 in the storage block 101, and loads the second pass voltage Vpass2 provided by the second voltage generation circuit 104 into the second non-select word line unsel_WL2 in the storage block 101.

[0087] Furthermore, if programming of the memory cell coupled to the select word line sel_WL fails, programming operations on the memory cell in memory block 101 are stopped.

[0088] In this embodiment, the select word line sel_WL refers to the word line coupled to the memory cell to be programmed. All other WLs in memory block 101 besides the select word line sel_WL are non-selectable WLs, and these non-selectable WLs can be divided into a first non-selectable word line unsel_WL1 and a second non-selectable word line unsel_WL2, meaning the second non-selectable word line unsel_WL2 is any non-selectable WL other than the first non-selectable word line unsel_WL1.

[0089] Specifically, the first unselectable word line unsel_WL1 can be a relatively poor-performing word line (WL) in memory block 101, meaning a WL that is more prone to leakage. Alternatively, it can be understood as: the first unselectable word line unsel_WL1 can be a WL in memory block 101 whose leakage probability exceeds a probability threshold. Furthermore, the first unselectable word line unsel_WL1 can be determined after testing the performance of each WL in each memory block 101 before the memory 100 leaves the factory.

[0090] Optionally, the first unselect word line unsel_WL1 can be one or more WLs in storage block 101 that are close to the BSG. That is, the first unselect word line unsel_WL1 is closer to the BSG in storage block 101 than the second unselect word line unsel_WL2. Of course, if the performance test results of the WLs show that the performance of other WLs in storage block 101 (e.g., the WLs close to the TSG) is relatively poor, then the first unselect word line unsel_WL1 can also be one of those other WLs (e.g., the WLs close to the TSG).

[0091] Understandably, if there is leakage between the first non-selection word line unsel_WL1 and CH (or other WL), a leakage path will be formed between the first voltage generation circuit 103 and CH (or other WL) when the first voltage generation circuit 103 applies the first pass voltage Vpass1 to the first non-selection word line unsel_WL1. This leakage path will reduce the power supply capability of the first voltage generation circuit 103 to the selection word line sel_WL, thereby reducing the programming voltage Vpe applied by the first voltage generation circuit 103 to the selection word line sel_WL, or increasing the time required for the first voltage generation circuit 103 to apply the voltage to the selection word line sel_WL to reach the specified programming voltage Vpe. Both the decrease in programming voltage Vpe and the increase in the time required to apply programming voltage Vpe will cause the memory cell coupled to the selection word line sel_WL to fail to program.

[0092] Based on the above analysis, if the control circuit 105 detects a programming failure in the memory cell coupled to the select word line sel_WL, it can determine that there is leakage in the first non-select word line unsel_WL1 in the memory block 101. At this time, the control circuit 105 can promptly stop the programming operation on the memory cell in the memory block 101 to prevent subsequent data written to the memory block 101 from being read incorrectly. For example, after detecting a programming failure in the memory cell coupled to the select word line sel_WL, the control circuit 105 can store the data to be written to other memory blocks in the memory to ensure the reliability of data storage and retrieval.

[0093] In summary, the memory provided in this application embodiment can provide a programming voltage to the select word line and a pass voltage to the first non-select word line through a first voltage generation circuit. Therefore, when leakage occurs in the first non-select word line, the programming voltage provided by the first voltage generation circuit will decrease, or the time required for the voltage provided by the first voltage generation circuit to reach the programming voltage will increase, thereby causing the memory cell coupled to the select word line to fail to program. Since the control circuit can promptly stop programming operations on the memory cells in the memory block when it detects programming failure in the memory cell coupled to the select word line, it can effectively prevent already written data and subsequently written data from being incorrectly read due to leakage in the first non-select word line.

[0094] Optionally, the word line selection circuit 102 may include multiple selection switches. These switches can connect the first voltage generation circuit 103 and the second voltage generation circuit 104 to the global word line (GWL), and can connect the GWL to the local word line (LWL) of the memory block 101. The control circuit 105 can control the on / off state of these multiple selection switches to apply the voltages provided by the first voltage generation circuit 103 and the second voltage generation circuit 104 to different LWLs. The control circuit 105 may be... Figure 2 The control logic circuit 115 in the memory 100 shown.

[0095] Each selection switch in the word line selection circuit 102 may have a control terminal, and the control circuit 105 may be connected to the control terminals of the plurality of selection switches respectively.

[0096] In this embodiment, incremental step pulse programming (ISPP) can be used to program the memory cell coupled to the select word line sel_WL. This programming operation includes multiple programming cycles, each cycle comprising a step of applying a programming voltage and a verification step. In the step of applying the programming voltage, a programming pulse with a voltage of Vpe is applied to the select word line sel_WL. In the verification step, a verification voltage is applied to the select word line sel_WL to verify whether the memory cell coupled to the select word line sel_WL has been programmed to the specified state. Furthermore, as the number of programming cycles increases, the programming voltage Vpe applied in each programming cycle gradually increases.

[0097] During the programming operation of the memory cell coupled to the select word line sel_WL, the control circuit 105 can count the number of programming pulses loaded onto the select word line sel_WL (i.e., count the number of times the programming loop is executed). If the number of times exceeds the threshold, and the programming of the memory cell coupled to the select word line sel_WL is still not completed, the control circuit 105 can determine that the programming has failed.

[0098] The threshold number can be determined based on the number of programming pulses required to program the memory cell coupled to the select word line sel_WL when there is no leakage in any WL in the memory block 101.

[0099] Optionally, after determining that the memory cell coupled to the select word line sel_WL has failed to program, the control circuit 105 can also mark the memory block 101 to which the select word line sel_WL belongs as a bad block (BB). This avoids writing data to the memory block 101 in the future, ensuring the reliability of data writing.

[0100] Figure 6 This is a schematic diagram of another memory structure provided in the embodiments of this application, such as... Figure 6 As shown, the first voltage generating circuit 103 may include: a first charge pump circuit 1031 and at least one first voltage regulating circuit 1032. Figure 6 The diagram schematically illustrates a first voltage regulation circuit 1032.

[0101] The first charge pump circuit 1031 is connected to the input of the word line selection circuit 102 and is used to provide the programming voltage Vpe. Each of the at least one first voltage regulation circuit 1032 is connected to the input of the first charge pump circuit 1031 and the word line selection circuit 102 respectively, and is used to provide a first pass voltage Vpass1 under the drive of the first charge pump circuit 1031.

[0102] Understandably, when programming the memory cell coupled to the select word line sel_WL, the control circuit 105 can control the word line selection circuit 102 to connect the first charge pump circuit 1031 to sel_WL and connect at least one first voltage regulation circuit 1032 to the first non-select word line unsel_WL1.

[0103] If leakage occurs on the first non-select word line unsel_WL1, a leakage path will form between the first voltage regulation circuit 1032 and the first non-select word line unsel_WL1. This leakage path will cause charge shunting at the output of the first charge pump circuit 1031, thereby reducing the charge supply capability of the first charge pump circuit 1031 to the select word line sel_WL. This will result in a decrease in the programming voltage Vpe applied to the select word line sel_WL by the first charge pump circuit 1031, or an increase in the time required for the voltage applied to the select word line sel_WL to reach the specified programming voltage Vpe, i.e., a slower voltage ramping speed. Both of these situations will cause the programming pulses provided by the first charge pump circuit 1031 to fail to bring the voltage on the select word line sel_WL to the specified programming voltage within a finite number of pulses (i.e., the number threshold), leading to programming failure.

[0104] Optionally, continue to refer to Figure 6 The first charge pump circuit 1031 may include: a first charge pump 10311 and a second voltage regulation circuit 10312.

[0105] The first charge pump 10311 provides a first initial voltage. A second voltage regulation circuit 10312 is connected to the inputs of both the first charge pump 10311 and the word line selection circuit 102, and is used to convert the first initial voltage into a programming voltage Vpe. This programming voltage Vpe is less than the first initial voltage. For example, the first initial voltage can be approximately 30 volts (V), and the programming voltage Vpe can be approximately 24V or 25V.

[0106] As a possible example, such as Figure 6 As shown, the first voltage regulation circuit 1032 can be connected to the second voltage regulation circuit 10312 and is used to convert the programming voltage Vpe output by the second voltage regulation circuit 10312 into the first pass voltage Vpass1.

[0107] In this example, the output of the second voltage regulation circuit 10312 is connected to the inputs of the first voltage regulation circuit 1032 and the word line selection circuit 102, respectively. When a leakage path is formed between the first voltage regulation circuit 1032 and the first unselected word line unsel_WL1, this leakage path causes charge shunting at the output of the second voltage regulation circuit 10312. This results in a decrease in the programming voltage Vpe applied to the select word line sel_WL by the second voltage regulation circuit 10312, or an increase in the time required for the voltage applied to the select word line sel_WL to reach the specified programming voltage Vpe.

[0108] As another possible example, Figure 7As shown, the first voltage regulation circuit 1032 can be connected to the first charge pump 10311 and is used to convert the first initial voltage output by the first charge pump 10311 into a first pass voltage Vpass1.

[0109] In this example, the output of the first charge pump 10311 is connected to the first voltage regulation circuit 1032 and the second voltage regulation circuit 10312, respectively. When a leakage path is formed between the first voltage regulation circuit 1032 and the first non-select word line unsel_WL1, this leakage path causes charge shunting at the output of the first charge pump 10311, thereby reducing the driving capability of the first charge pump 10311 for each voltage regulation circuit. Consequently, this can lead to a decrease in the programming voltage Vpe applied to the select word line sel_WL by the second voltage regulation circuit 10312, or an increase in the time required for the voltage applied to the select word line sel_WL to reach the specified programming voltage Vpe.

[0110] Optionally, such as Figure 7 As shown, the first voltage generating circuit 103 may include a plurality of first voltage regulating circuits 1032. Furthermore, the first pass voltage Vpass1 provided by the plurality of first voltage regulating circuits 1032 are all different.

[0111] When programming the memory cell coupled to the select word line sel_WL, the control circuit 105 can control the word line selection circuit 102 to connect the plurality of first voltage adjustment circuits 1032 to different first non-select word lines unsel_WL1, thereby applying different first pass voltages Vpass1 to different first non-select word lines unsel_WL1.

[0112] For example, refer to Figure 7 Assuming the first voltage generating circuit 103 includes j first voltage regulating circuits 1032, the first pass voltages provided by these j first voltage regulating circuits 1032 can be Vpass1_1 to Vpass1_j, where j is an integer greater than 1. Furthermore, the first pass voltage provided by each first voltage regulating circuit 1032 is less than the programming voltage Vpe.

[0113] It is understandable that if the driving capability of the first charge pump 10311 in the first charge pump circuit 1031 is strong, then even if a leakage path is formed between the first voltage regulation circuit 1032 and the first non-selection word line unsel_WL1, the first charge pump circuit 1031 can still output a relatively stable programming voltage Vpe. That is, the leakage of the first non-selection word line unsel_WL1 will not have a significant impact on the programming voltage Vpe applied to the selection word line sel_WL1, and thus will not cause the memory cell coupled to the selection word line sel_WL1 to fail to program.

[0114] Based on this, as the first optional implementation method, such as Figure 8 As shown, the first voltage generation circuit 103 may further include a current limiting circuit 1033. This current limiting circuit 1033 is connected between the input terminals of the first charge pump circuit 1031 and the word line selection circuit 102, and is used to limit the current output by the first charge pump circuit 1031. This reduces the driving capability of the first charge pump circuit 1031, ensuring that leakage current in the first non-selected word line unsel_WL1 does not affect the programming voltage Vpe applied to the select word line sel_WL1.

[0115] Optionally, the current limiting circuit 1033 may include at least one transistor, which may be a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0116] In this embodiment, the current limiting capability of the current limiting circuit 1033 can be determined based on the driving capability of the first charge pump 10311 in the memory block 101. Through the current limiting of the current limiting circuit 1033, it can be ensured that when there is no leakage current on the first non-selection word line unsel_WL1, the programming voltage Vpe applied to the selection word line sel_WL1 can ensure that the memory cell coupled to the selection word line sel_WL1 can be programmed successfully. Furthermore, it can be ensured that when there is leakage current on the first non-selection word line unsel_WL1, the effect of the leakage current on the programming voltage Vpe applied to the selection word line sel_WL1 is sufficient to cause the memory cell coupled to the selection word line sel_WL1 to fail to program.

[0117] Figure 9 This is a distribution diagram of leakage current between the bottom WL and CH provided in an embodiment of this application. The vertical axis in the figure represents the magnitude of leakage current between the bottom WL and CH, and the unit is nanoampere (nA). The horizontal axis has no actual meaning. Figure 9 The leakage current between different bottom WLs and CHs is detected during the programming process. During the test, a test voltage is applied to the bottom WL being tested, and a pass voltage Vpass is applied to the WL adjacent to the bottom WL being tested. The voltages applied to other WLs are the same as the voltages actually applied during the programming process. The test voltage and the pass voltage Vpass can be equal, for example, both 6V.

[0118] refer to Figure 9It can be seen that the leakage current between the bottom WL and CH is approximately between 10,000 nA and 60,000 nA. After labeling the leakage current of multiple bottom WLs using a box plot, it can be seen that the leakage current of most bottom WLs is between 10,000 nA and 20,000 nA. In this embodiment, the impact of the leakage current on the programming voltage Vpe can be determined based on the statistically obtained leakage current of the bottom WLs and the driving capability of the first charge pump 10311, thereby allowing for a reasonable configuration of the current limiting capability of the current limiting circuit 1033.

[0119] Understandable, Figure 9 The leakage current shown is for illustrative purposes only. Due to differences in manufacturing processes and performance, the magnitude of the leakage current in the WL of different memories will vary.

[0120] For scenarios where the first charge pump 10311 has strong driving capability, as a second optional implementation method, such as Figure 10 As shown, the first voltage generating circuit 103 may further include at least one current amplification circuit 1034 corresponding to at least one first voltage regulating circuit 1032. Figure 10 The diagram schematically illustrates a current amplifier circuit 1034.

[0121] The current amplification circuit 1034 and a corresponding first voltage regulation circuit 1032 are connected in series between the input terminals of the first charge pump circuit 1031 and the word line selection circuit 102, and are used to amplify the current.

[0122] Understandably, when leakage occurs in the first non-select word line unsel_WL1, a leakage path will be formed between the first charge pump circuit 1031 and the first non-select word line unsel_WL1. This leakage path passes through the current amplification circuit 1034 and the first voltage regulation circuit 1032, and the current amplification circuit 1034 can amplify the leakage current in this leakage path. Therefore, the impact of the leakage current of the first non-select word line unsel_WL1 on the driving capability of the first charge pump 10311 can be effectively increased, thereby ensuring that the programming voltage Vpe applied to the select word line sel_WL by the first charge pump 10311 is not affected.

[0123] In this embodiment, the current amplification capability of the current amplification circuit 1034 can also be determined based on the statistically obtained leakage current of the bottom WL and the driving capability of the first charge pump 10311.

[0124] It is also understood that the memory 100 is obtained by packaging dies in a wafer. Due to the influence of manufacturing process precision, the driving capability of the first charge pump 10311 in different dies will vary. By adding a current limiting circuit 1033 or a current amplification circuit 1034, it can be ensured that the solution provided in this application embodiment can flexibly adapt to the first charge pump 10311 with different driving capabilities.

[0125] Optionally, refer to Figures 6 to 8 ,as well as Figure 10 The second voltage generating circuit 104 may include a second charge pump 1041 and at least one third voltage regulating circuit 1042. The second charge pump 1041 may be used to provide a second initial voltage, which may be less than the first initial voltage provided by the first charge pump 10311.

[0126] Each of the at least one third voltage regulation circuit 1042 is connected to the input terminals of the second charge pump 1041 and the word line selection circuit 102, respectively, and is used to convert the second initial voltage into a second pass voltage Vpass2. Furthermore, the second pass voltage Vpass2 obtained by different third voltage regulation circuits 1042 are different from each other.

[0127] For example, refer to Figure 7 Assuming the second voltage generating circuit 104 includes k third voltage regulating circuits 1042, the second pass voltages provided by these k third voltage regulating circuits 1042 can be successively Vpass2_1 to Vpass2_k, where k is an integer greater than 1. Furthermore, the second pass voltage provided by each third voltage regulating circuit 1042 is less than the programming voltage Vpe.

[0128] When programming the memory cell coupled to the select word line sel_WL, the control circuit 105 can control the word line selection circuit 102 to connect multiple third voltage adjustment circuits 1042 to different second non-select word lines unsel_WL2, thereby applying different second pass voltages Vpass2 to different second non-select word lines unsel_WL2.

[0129] Optionally, the first voltage regulation circuit, the second voltage regulation circuit, and the third voltage regulation circuit described above can all be circuits that include multiple transistors (e.g., MOS) and are capable of precisely regulating the voltage.

[0130] It is understood that the memory provided in this application embodiment can be programmed using forward programming or reverse programming. For example, the control circuit 105 can control multiple memory cells in the memory block to be programmed in the direction from TSG to BSG, that is, the memory can be programmed using reverse programming.

[0131] In summary, the memory provided in this application embodiment can provide a programming voltage to the select word line and a pass voltage to the first non-select word line through a first voltage generation circuit. Therefore, when leakage occurs in the first non-select word line, the programming voltage provided by the first voltage generation circuit will decrease, or the time required for the voltage provided by the first voltage generation circuit to reach the programming voltage will increase, thereby causing the memory cell coupled to the select word line to fail to program. Since the control circuit can promptly stop programming operations on the memory cells in the memory block when it detects programming failure in the memory cell coupled to the select word line, it can effectively prevent the written data from being incorrectly read due to leakage in the first non-select word line. That is, it effectively avoids UECC (Uninterrupted User Code Correction) in the memory cells of the memory block.

[0132] Figure 11 This is a flowchart illustrating a memory programming method provided in an embodiment of this application. This method can be applied to the memory provided in the above embodiment. Figure 11 As shown, the method includes:

[0133] Step 201: Apply programming voltage to the select word line in the memory block through the first voltage generation circuit, and apply a first pass voltage to the first non-select word line in the memory block.

[0134] In this embodiment of the application, the control circuit in the memory can control the word line selection circuit to connect the first voltage generation circuit to the selected word line and the first non-selected word line respectively, so that the first voltage generation circuit applies a programming voltage to the selected word line and applies a first pass voltage to the first non-selected word line.

[0135] The first non-select word line can be a relatively poor-performing word line in the memory block, that is, a word line that is more prone to leakage.

[0136] Step 202: Apply a second pass voltage to the second non-select word line in the memory block through the second voltage generation circuit.

[0137] The control circuit can control the word line selection circuit to connect the second voltage generation circuit to the second non-selectable word line, so that the second voltage generation circuit applies a second pass voltage to the second non-selectable word line. The second non-selectable word line is any non-selectable word line in the memory block other than the first non-selectable word line.

[0138] Optionally, the first non-select word line can be one or more WLs located near the BSG in the memory block. That is, the first non-select word line is closer to the BSG in the memory block than the second non-select word line.

[0139] Step 203: If programming of the memory cell coupled to the select word line fails, stop programming the memory cell in the memory block.

[0140] If the control circuit detects a programming failure in the memory cell coupled to the select word line, it can determine that there is leakage on the first non-select word line in the memory block, and thus promptly stop the programming operation on the memory cell in that memory block. This effectively prevents the loss of data subsequently written to the memory block.

[0141] Figure 12 This is a flowchart of another memory programming method provided in an embodiment of this application, which can be applied to the memory provided in the above embodiments. Figure 12 As shown, the method includes:

[0142] Step 301: Apply programming voltage to the select word line in the memory block through the first voltage generation circuit, and apply a first pass voltage to the first non-select word line in the memory block.

[0143] Step 302: Apply a second pass voltage to the second non-select word line in the memory block through the second voltage generation circuit.

[0144] The implementation process of steps 301 and 302 above can be... Figure 11 The relevant descriptions of steps 201 and 202 in the illustrated embodiment will not be repeated here.

[0145] Step 303: Detect whether the number of programming pulses loaded onto the select word line is greater than the number threshold.

[0146] The first charge pump circuit in the memory can apply programming pulses to the select word line to bring its voltage to the programming voltage. During the application of programming pulses, if leakage occurs on the first non-select word line, this leakage can cause the programming voltage provided by the first voltage generation circuit to decrease, thereby increasing the number of programming pulses that the first charge pump circuit needs to apply to the select word line.

[0147] In this embodiment of the application, during the programming of the memory cell coupled to the select word line, the control circuit can count the number of programming pulses applied to the select word line by the first charge pump circuit and detect whether the number of pulses is greater than the number threshold.

[0148] If the control circuit detects that the number of programming pulses loaded is greater than the threshold, step 304 can be executed; if the control circuit detects that the number of programming pulses loaded is not greater than the threshold, step 301 can be executed, that is, the first charge pump circuit is controlled to continue loading programming pulses onto the select word line.

[0149] Step 304: Determine that the memory cell coupled to the select word line has failed to program, and stop programming operations on the memory cells in the memory block.

[0150] If the control circuit detects that the number of programming pulses applied to the select word line by the first charge pump circuit exceeds a threshold, it can determine that the memory cell coupled to that select word line has failed to be programmed. Consequently, the control circuit can stop programming operations on the memory cells in the memory block.

[0151] Step 305: Mark the storage block as a bad block.

[0152] After determining that the memory cell coupled to the select word line has failed to program, the control circuit can mark the memory block as bad. This prevents further data from being written to that memory block. For example, the control circuit can store the data to be written in another memory block.

[0153] It is understood that the implementation process of the memory programming method provided in the embodiments of this application can refer to the relevant description in the above memory embodiments, and will not be repeated here.

[0154] It is also understood that the order of steps in the memory programming method provided in this application embodiment can be appropriately adjusted, and steps can be added or removed as needed. For example, step 305 can be deleted as needed, or it can be executed synchronously with step 304.

[0155] In summary, this application provides a memory programming method. This method provides a programming voltage to the select word line and a pass voltage to the first non-select word line via a first voltage generation circuit. Therefore, when leakage occurs on the first non-select word line, the programming voltage provided by the first voltage generation circuit decreases, or the time required for the voltage provided by the first voltage generation circuit to reach the programming voltage increases, thereby causing programming failure of the memory cell coupled to the select word line. Since the method provided in this application can promptly stop programming operations on the memory cells in the memory block when programming failure of the memory cell coupled to the select word line is detected, it can effectively prevent written data from being incorrectly read due to leakage on the first non-select word line.

[0156] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0157] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory (100), characterized in that, The memory (100) includes: a memory block (101), a word line selection circuit (102), a first voltage generation circuit (103), a second voltage generation circuit (104), and a control circuit (105). The memory block (101) includes multiple memory cells coupled to different word lines, and the multiple output terminals of the word line selection circuit (102) are connected one-to-one with the multiple word lines in the memory block (101); The first voltage generating circuit (103) and the second voltage generating circuit (104) are respectively connected to different input terminals of the word line selection circuit (102). The first voltage generating circuit (103) is used to provide programming voltage and first pass voltage, and the second voltage generating circuit (104) is used to provide second pass voltage. The control circuit (105) is connected to the word line selection circuit (102), and the control circuit (105) is used for: The word line selection circuit (102) is controlled to apply the programming voltage to the selected word line in the memory block (101), apply the first through voltage to the first non-selected word line in the memory block (101), and apply the second through voltage to the second non-selected word line in the memory block (101), wherein the probability of leakage current in the first non-selected word line is greater than that in the second non-selected word line. If a programming failure is detected in the memory cell coupled to the select word line, the programming operation on the memory cell in the memory block (101) is stopped. The first voltage generating circuit (103) includes: a first charge pump circuit (1031) and at least one first voltage regulating circuit (1032). The first charge pump circuit (1031) is connected to the input terminal of the word line selection circuit (102) and is used to provide the programming voltage; Each of the at least one first voltage regulation circuit (1032) is connected to the input terminals of the first charge pump circuit (1031) and the word line selection circuit (102), respectively, and is used to provide the first pass voltage under the drive of the first charge pump circuit (1031); If there is leakage in the first non-select word line, a leakage path is formed between the first voltage regulation circuit (1032) and the first non-select word line, causing the first charge pump circuit (1031) to generate charge shunting.

2. The memory (100) according to claim 1, characterized in that, The first charge pump circuit (1031) includes: a first charge pump (10311) and a second voltage regulation circuit (10312); The first charge pump (10311) is used to provide a first initial voltage; The second voltage regulation circuit (10312) is connected to the input terminals of the first charge pump (10311) and the word line selection circuit (102) respectively, and is used to convert the first initial voltage into the programming voltage; The first voltage regulation circuit (1032) is connected to the second voltage regulation circuit (10312) and is used to convert the programming voltage into the first pass voltage; Alternatively, the first voltage regulation circuit (1032) is connected to the first charge pump (10311) and is used to convert the first initial voltage into the first pass voltage.

3. The memory (100) according to claim 1, characterized in that, The first voltage generating circuit (103) includes a plurality of first voltage regulating circuits (1032), and the first pass voltages provided by the plurality of first voltage regulating circuits (1032) are different from each other.

4. The memory (100) according to claim 1, characterized in that, The first voltage generating circuit (103) also includes a current limiting circuit (1033); The current limiting circuit (1033) is connected between the input terminals of the first charge pump circuit (1031) and the word line selection circuit (102), and the current limiting circuit (1033) is used to limit the current output by the first charge pump circuit (1031).

5. The memory (100) according to claim 1, characterized in that, The first voltage generating circuit (103) further includes at least one current amplification circuit (1034) corresponding to the at least one first voltage regulating circuit (1032). Each of the current amplification circuits (1034) is connected in series with a corresponding first voltage regulation circuit (1032) between the input terminals of the first charge pump circuit (1031) and the word line selection circuit (102) and is used to amplify the current.

6. The memory (100) according to any one of claims 1 to 5, characterized in that, The second voltage generating circuit (104) includes: a second charge pump (1041) and at least one third voltage regulating circuit (1042). The second charge pump (1041) is used to provide a second initial voltage; Each of the at least one third voltage regulation circuit (1042) is connected to the input terminals of the second charge pump (1041) and the word line selection circuit (102), respectively, and is used to convert the second initial voltage into the second pass voltage; The second pass voltage obtained by different third voltage regulation circuits (1042) is different from each other.

7. The memory (100) according to any one of claims 1 to 5, characterized in that, The first nonselect word line is closer to the lower select tube in the memory block (101) than the second nonselect word line.

8. The memory (100) according to claim 7, characterized in that, The control circuit (105) is also used to control a plurality of memory cells in the memory block (101) to be programmed in the direction from the upper selector to the lower selector.

9. The memory (100) according to any one of claims 1 to 5, characterized in that, The control circuit (105) is also used to mark the memory block (101) as a bad block if it is detected that the memory cell coupled to the select word line has failed to be programmed.

10. The memory (100) according to any one of claims 1 to 5, characterized in that, The control circuit (105) is further configured to: if the number of programming pulses loaded onto the select word line is greater than a threshold number, determine that the memory cell coupled to the select word line has failed to be programmed.

11. A method for programming a memory, characterized in that, The memory includes a memory block, a first voltage generation circuit, and a second voltage generation circuit. The first voltage generation circuit includes a first charge pump circuit and at least one first voltage regulation circuit. The method includes: The first charge pump circuit applies a programming voltage to the select word line in the memory block, and the first voltage regulation circuit applies a first pass voltage to the first non-select word line in the memory block. A second pass voltage is applied to the second non-select word line in the memory block through the second voltage generation circuit, wherein the probability of leakage current in the first non-select word line is greater than that in the second non-select word line. If a programming failure is detected in the memory cell coupled to the select word line, the programming operation on the memory cell in the memory block is stopped. If there is leakage in the first non-select word line, a leakage path is formed between the first voltage regulation circuit and the first non-select word line, causing the first charge pump circuit to generate charge shunting.

12. The method according to claim 11, characterized in that, The method further includes: If a programming failure is detected in the memory cell coupled to the select word line, the memory block is marked as a bad block.

13. The method according to claim 11, characterized in that, Leakage in the first non-select word line can cause a decrease in the programming voltage provided by the first charge pump circuit; the method further includes: If the number of programming pulses loaded onto the select word line is greater than a threshold, it is determined that the memory cell coupled to the select word line has failed to be programmed.

14. The method according to any one of claims 11 to 13, characterized in that, The first nonselect word line is closer to the lower select tube in the memory block than the second nonselect word line.

15. A storage system (1000), characterized in that, The storage system (1000) includes: a memory controller (200), and at least one memory (100) as described in any one of claims 1 to 10.

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