Display panel and display device

Abstract

The application provides a display panel and a display device, comprising a non-display area, the display panel comprising a test line and at least two signal lines, the display panel located in the non-display area comprising a base layer, at least part of the two adjacent signal lines being arranged on the base layer, and the test line being located between the two adjacent signal lines; the test line comprising a first test line, when the base layer has metal residues and the two adjacent signal lines are short-circuited through the metal residues, the first test line and any one of the two adjacent signal lines forming a partial test loop. The first test line tests the metal residues between the two adjacent signal lines, which can improve the metal residues in the preparation process of the signal lines, save the module materials, and reduce the preparation cost of the display panel. Therefore, the display panel and the display device provided by the application can detect the preparation defects of the signal lines of the display panel in time, thereby being beneficial to the preparation of the display panel.

Description

Display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are characterized by active light emission, high contrast, ultra-thinness, low temperature resistance, fast response speed, low power consumption, wide viewing angle, and strong shock resistance, which has led to their increasing use.

[0003] In related technologies, a display panel may include a display area and a non-display area. The non-display area is provided with multiple signal traces. One end of the signal trace can be electrically connected to the integrated circuit (IC) in the non-display area, and the other end of the signal trace is electrically connected to the display panel in the display area, thereby providing various signals to the display panel in the display area.

[0004] However, the manufacturing defects of the aforementioned signal traces cannot be detected in time, which is detrimental to the manufacturing of the display panel. Summary of the Invention

[0005] In view of at least one of the above-mentioned technical problems, embodiments of this application provide a display panel and a display device that can detect manufacturing defects in the signal lines of the display panel in a timely manner, thereby facilitating the manufacturing of the display panel.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] A first aspect of this application provides a display panel including a non-display area. The display panel includes a test line and at least two signal lines. The display panel located in the non-display area includes a substrate. At least a portion of two adjacent signal lines are spaced apart on the substrate. The test line is located between the two adjacent signal lines. The test line includes a first test line. When there is metal residue on the substrate and the two adjacent signal lines are short-circuited through the metal residue, either the first test line or the two adjacent signal lines form a partial test circuit.

[0008] The display panel provided in this application embodiment may include a non-display area, a test line, and at least two signal lines. The display panel located in the non-display area includes a substrate. At least a portion of two adjacent signal lines are spaced apart on the substrate, and the test line is located between the two adjacent signal lines. The test line includes a first test line. When there is metal residue on the substrate, and two adjacent signal lines are short-circuited through the metal residue, the first test line and either of the two adjacent signal lines form a partial test circuit, thereby testing for the metal residue between the two adjacent signal lines. If metal residue is found, it can be improved during the signal line fabrication process, and a metal residue-free display panel can be formed without discarding the display panel, thus saving module materials, reducing the manufacturing cost of the display panel, and benefiting the fabrication of the display panel.

[0009] In one possible implementation, a display area is also included, which is adjacent to a non-display area. The base layer includes a first side closer to the display area and a second side farther away from the display area, which are disposed opposite to each other. The orthographic projection of the test end of the first test line on the plane of the base layer is located on the side of the second side farther away from the display area. The orthographic projection of the first test line on the plane of the base layer coincides with a portion of the base layer.

[0010] In this way, the test end of the first test lead can be easily connected to external test equipment.

[0011] In one possible implementation, at least a portion of the connection end of the first test line has its orthographic projection on the plane where the base layer is located between the first side and the second side.

[0012] In this way, the first test line can be used to detect metal residue on the second side.

[0013] In one possible implementation, at least a portion of the connection end of the first test line has its orthographic projection on the plane of the substrate located on the side of the first side closest to the display area.

[0014] In this way, the first test line can be used to detect metal residues at the first and second sides.

[0015] In one possible implementation, multiple fan-out lines are spaced apart in the non-display area. The fan-out lines are located on the side of the base layer away from the signal lines, and at least a portion of the orthographic projection of the fan-out lines on the plane of the base layer is located between the orthographic projections of two adjacent signal lines on the plane of the base layer. The orthographic projection of the connection end on the plane of the base layer partially coincides with the orthographic projection of the fan-out lines on the plane of the base layer.

[0016] In this way, the first test lead can be used to detect metal residue caused by the fan-out line.

[0017] In one possible implementation, the non-display area includes a bending area, the base layer includes a buffer layer located at least in the bending area, the first test line includes a power test line, the signal lines include a high-level signal line and a low-level signal line, both of which are located on the buffer layer, and the power test line is located between the high-level signal line and the low-level signal line.

[0018] In this way, the power test leads are used to detect metallic residue between high-level and low-level signal lines.

[0019] In one possible implementation, the non-display area includes a bend area, the base layer includes a dam, the first test line includes a touch test line, the dam is located between the bend area and the display area, and the signal line includes multiple touch lines, with the touch test line located between two adjacent touch lines.

[0020] In this way, the touch test line is used to detect metal residue between two adjacent touch lines.

[0021] In one possible implementation, the test line includes at least two second test lines located on the side of the signal line away from the substrate. The connection ends of the two second test lines are connected to each other to form a partial test loop. The edge of the signal line is provided with a protrusion, and the orthographic projection of either of the two second test lines on the plane of the protrusion coincides with a portion of the protrusion.

[0022] In this way, the second test line is used to detect over-etching of the metal layer where the signal line is located.

[0023] In one possible implementation, the protrusion includes a first protrusion and a second protrusion, the first protrusion being located on one of at least two signal lines, the second protrusion being located on the other of at least two signal lines, the orthographic projection of one of the two second test lines on the plane where the first protrusion is located coincides with a portion of the first protrusion, and the orthographic projection of the other of the two second test lines on the plane where the second protrusion is located coincides with a portion of the second protrusion.

[0024] A second aspect of this application provides a display device, including the display panel described in the first aspect.

[0025] The display device provided in this application includes a display panel, which may include a non-display area. The display panel may include test lines and at least two signal lines. The display panel located in the non-display area includes a substrate. At least a portion of two adjacent signal lines are spaced apart on the substrate, and the test lines are located between the two adjacent signal lines. The test lines include a first test line. When there is metal residue on the substrate, and two adjacent signal lines are short-circuited through the metal residue, the first test line and either of the two adjacent signal lines form a partial test circuit, thereby testing the metal residue between the two adjacent signal lines. If metal residue is found, it can be improved during the signal line manufacturing process, and a display panel without metal residue can continue to be manufactured, eliminating the need to discard the display panel, thus saving module materials, reducing the manufacturing cost of the display panel, and benefiting the manufacturing of the display panel.

[0026] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 is a top view of the display panel provided in an embodiment of this application;

[0029] Figure 2 is a schematic diagram of the structure of the touch test line provided in an embodiment of this application;

[0030] Figure 3 is a schematic diagram of the power test line provided in an embodiment of this application;

[0031] Figure 4 is another structural schematic diagram of the touch test line provided in an embodiment of this application;

[0032] Figure 5 is another structural schematic diagram of the power test line provided in an embodiment of this application;

[0033] Figure 6 is another structural schematic diagram of the power test line provided in an embodiment of this application;

[0034] Figure 7 is a schematic diagram of the structure of the second test line provided in an embodiment of this application;

[0035] Figure 8 is another structural schematic diagram of part A in Figure 7.

[0036] Explanation of reference numerals in the attached figures:

[0037] 100 - Display panel; 100a - Display area;

[0038] 100b - Non-display area; 100c - Bending area;

[0039] 110 - Power cable; 111 - ELVDD signal cable;

[0040] 112 - ELVSS signal line; 1121 - First extension;

[0041] 1122 - Second extension section; 120 - Touch line;

[0042] 130 - Base layer; 131 - First side edge;

[0043] 132 - Second side; 140 - Buffer layer;

[0044] 141 - First organic side; 142 - Second organic side;

[0045] 150 - Embankment; 151 - Side of the first embankment;

[0046] 152 - Side of the second embankment; 160 - First test line;

[0047] 161 - Power supply test cable; 162 - Touch test cable;

[0048] 170 - Second test line; 180 - Raised line;

[0049] 181 - First protrusion; 182 - Second protrusion;

[0050] 191 - Fan-out cable; 192 - Connecting cable;

[0051] 193 - Test pin. Detailed Implementation

[0052] In related technologies, a display panel includes adjacent display and non-display areas. The non-display area has a bending area and a bonding area, with the bending area located between the bonding area and the display area. The display panel includes a substrate. In the bending area, multiple inorganic films on the substrate are removed using a multi-step etching process to form a groove. An organic film with lower stress is deposited in the groove to replace the inorganic film, thereby improving the bending performance of the product. A metal material layer is formed on the side of the organic film layer facing away from the substrate. Photoresist is formed on the metal material layer, and the photoresist is exposed, developed, and etched to form a mask. Then, the metal material layer is etched to form multiple signal lines that extend from the display area to the bonding area.

[0053] Along the direction from the display area to the non-display area, the organic film layer includes two oppositely positioned sides. The thickness of the organic film layer at the sides is greater than that of the rest of the area, resulting in a step in the organic film layer at the sides. During the exposure process of forming the mask, the step on the side of the organic film layer creates shadows, leading to insufficient exposure. This makes it easy for metal residues to remain on the side of the organic film layer, causing short circuits between multiple signal lines covering the side of the organic film layer, thus affecting the performance of the display panel.

[0054] However, this metal residue cannot be detected during the signal line fabrication process, leading to defects in the subsequently manufactured display panels. If a defective display panel is discovered due to metal residue during the testing phase, it must be discarded, resulting in a waste of module materials, increased manufacturing costs, and hindering the production of display panels.

[0055] Based on at least one of the aforementioned technical problems, embodiments of this application provide a display panel and a display device. The display panel may include a non-display area, a test line, and at least two signal lines. The display panel located in the non-display area includes a substrate. At least a portion of two adjacent signal lines are spaced apart on the substrate, and the test line is located between the two adjacent signal lines. The test line includes a first test line. When there is metal residue on the substrate, and two adjacent signal lines are short-circuited through the metal residue, the first test line and either of the two adjacent signal lines form a partial test circuit, thereby testing the metal residue between the two adjacent signal lines. If metal residue is found, it can be improved during the signal line manufacturing process, and a display panel without metal residue can continue to be manufactured, eliminating the need for waste disposal of the display panel, thus saving module materials, reducing the manufacturing cost of the display panel, and benefiting the manufacturing of the display panel.

[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0057] The display device provided in the embodiments of this application will be described below with reference to Figures 1-8.

[0058] This application provides a display device, which includes a display panel 100. The display device can be a mobile or fixed terminal with a display panel 100, such as an electronic paper device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, supercomputer, or navigator.

[0059] The display panel 100 provided in the embodiments of this application will be described in detail below.

[0060] The display panel 100 can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED or μLED) display panel, or a liquid crystal display (LCD) display panel.

[0061] The display panel 100 includes a light-emitting side and a backlight side arranged opposite to each other along the thickness direction. The light-emitting side is used to display images, and the backlight side is the other side arranged opposite to the light-emitting side.

[0062] As shown in Figures 1 and 2, the display panel 100 includes a display area 100a and a non-display area 100b, with the non-display area 100b potentially located on one side of the display area 100a. The non-display area 100b may include a bending area 100c and a bonding area, with the bending area 100c located between the display area 100a and the bonding area. By bending the bending area 100c, the bonding area can be bent to the backlight side of the display panel 100, thus reducing the bezel width of the display device. The display panel 100 located within the bonding area can be used to bond a driver chip, thereby enabling signal transmission between the driver chip and the display panel 100.

[0063] It should be noted that, as shown in Figure 1, the display panel 100 may include a first direction X, which can be the width direction of the display panel 100; the display panel 100 may include a second direction Y, which can be the length direction of the display panel 100; and the display panel 100 may include a third direction Z, which can be the thickness direction of the display panel 100. The length, width, and thickness in the embodiments of this application are merely for descriptive convenience and do not imply any limitation on the dimensions. For example, the width may be greater than, equal to, or less than the length. The first direction X, the second direction Y, and the third direction Z are all different.

[0064] The display panel 100 may include an array substrate and a light-emitting layer located on the array substrate. The array substrate has multiple driving units arranged in an array, and the driving units are electrically connected to the light-emitting layer. The driving units are used to control the light emission of the light-emitting layer. The driving units may include thin-film transistors (TFTs) and capacitor structures; thin-film transistors may also be simply referred to as transistors.

[0065] The light-emitting layer includes an anode layer, a light-emitting material layer, and a cathode layer stacked sequentially, as well as an electron blocking layer and a hole transport layer located between the anode layer and the light-emitting material layer, and a hole blocking layer and an electron transport layer located between the cathode layer and the light-emitting material layer. The specific structure of the light-emitting layer is not limited in the embodiments of this application.

[0066] An encapsulation layer is disposed on the side of the light-emitting layer facing away from the substrate. The encapsulation layer can employ thin film encapsulation (TFE) technology and may include multiple encapsulation sub-film layers. The encapsulation layer may include inorganic layers and / or organic layers. For example, the encapsulation layer may adopt a film structure of overlapping inorganic / organic / inorganic layers. The inorganic layers are used to effectively block water and oxygen, while the organic layers are used to buffer the stress within the inorganic layers.

[0067] The display panel 100 also includes a dam 150, which can be arranged around the outer periphery of the display area 100a. The dam 150 can be annular. As shown in Figure 2, part of the dam 150 is located between the display area 100a and the bending area 100c. The dam 150 is located on the side of the encapsulation layer facing the array substrate. During the film formation process of the encapsulation layer, the dam 150 can block and prevent overflow. The organic layer in the encapsulation layer extends from the display area 100a to the non-display area 100b and terminates at the dam 150. The inorganic layer in the encapsulation layer crosses the dam 150 and continues to extend towards the edge of the display panel 100. The dam 150 can prevent material from the organic layer in the encapsulation layer from overflowing to the outside of the dam 150, thus improving the encapsulation effect.

[0068] A touch layer is disposed on the side of the encapsulation layer opposite to the array substrate. The touch layer is used to implement touch functionality. The touch layer may include multiple signal lines, as shown in Figure 2. These signal lines can be touch lines 120, which are used to transmit touch signals to the touch layer. The touch lines 120 are located in the display area 100a and the non-display area 100b, and can extend from the display area 100a to the bonding area of ​​the non-display area 100b.

[0069] The array substrate provided in the embodiments of this application will be described below.

[0070] The array substrate includes a substrate that provides support for subsequent structural layers. In some examples, the substrate may be a rigid substrate, for example, the substrate material may be glass. In other examples, the substrate may be a flexible substrate, and the substrate material may include at least one of polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0071] The array substrate may include a semiconductor layer, a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer sequentially stacked on a substrate. An insulating layer is disposed between each adjacent pair of the semiconductor layer, the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer. This insulating layer may be an inorganic insulating layer, and its material may be silicon nitride or silicon oxide. The insulating layer may include a first insulating layer located between the semiconductor layer and the first metal layer, a second insulating layer between the first metal layer and the second metal layer, a third insulating layer between the second metal layer and the third metal layer, and a fourth insulating layer between the third metal layer and the fourth metal layer.

[0072] The semiconductor layer includes an active layer of multiple transistors. The first metal layer may include a scan line, a first electrode of a capacitor structure, a light-emitting control line, and the gate of a transistor. The second metal layer may include a reference line and a second electrode of a capacitor structure. The third metal layer may include the source and drain electrodes of multiple transistors. The fourth metal layer may include data lines.

[0073] Multiple signal lines can be provided in the array substrate. These signal lines can be power lines 110 (Figure 3), which are used to provide voltage signals to the light-emitting layer to control its light emission. As shown in Figure 3, the power line 110 can include a high-level (ELVDD) signal line and a low-level (ELVSS) signal line. The ELVDD signal line 111 provides a high-level signal to the anode layer, and the ELVSS signal line 112 provides a low-level signal to the cathode layer. Both the ELVDD signal line 111 and the ELVSS signal line 112 can be located in the display area 100a and the non-display area 100b of the display panel 100, and both can extend from the display area 100a to the bonding area. The power line 110 can be formed by a third metal layer and / or a fourth metal layer.

[0074] As shown in Figure 3, in the non-display area 100b, the ELVSS signal line 112 includes a first extension 1121 and a second extension 1122 that are spaced apart along the first direction X. Both the first extension 1121 and the second extension 1122 extend along the second direction Y. The first extension 1121 and the second extension 1122 are located on opposite sides of the ELVDD signal line 111 along the first direction X, and are spaced apart from the ELVDD signal line 111.

[0075] It should be noted that the signal line in this embodiment can also be a data line or other signal line. One end of the signal line is connected to the display area 100a, and the other end of the signal line passes through the bending area 100c and extends to the bonding area. For example, the material of the signal line can include titanium / aluminum / titanium, which has good ductility.

[0076] This application embodiment uses the formation of a power line 110 on the fourth metal layer as an example for illustration. The first, second, third, and fourth insulating layers in the bending region 100c can be removed using a multi-step etching process to form a groove, and a low-stress organic material is deposited in the groove to form a buffer layer 140, thereby improving the bending performance of the bending region 100c. The buffer layer 140 may be located only in the bending region 100c, or it may extend from the bending region 100c towards the bonding area and the display area 100a, with the extension length of the buffer layer 140 along the second direction Y greater than the extension length of the bending region 100c.

[0077] The buffer layer 140 includes two opposing sides along the second direction Y. The power line 110 is located on the side of the buffer layer 140 away from the substrate. The power line 110 extends from the display area 100a through the buffer layer 140 to the bonding area. There are steps on the two sides of the buffer layer 140, which makes it easy for metal residues to be generated on the two sides of the power line 110, resulting in a short circuit between the ELVDD signal line 111 and the ELVSS signal line 112. In addition, since the dam 150 has a large thickness along the thickness direction of the display panel 100, the touch line 120 is located on the side of the dam 150 away from the array substrate. The touch line 120 extends from the display area 100a through the dam 150 to the bonding area. There are steps on the two opposing sides of the dam 150 along the second direction Y, which makes it easy for metal residues to be generated on the two sides of adjacent touch lines 120, resulting in a short circuit between adjacent touch lines 120.

[0078] The buffer layer 140 and the dam 150 located in the non-display area 100b can be collectively referred to as the base layer 130 (Figure 4). That is, there are steps on the two opposite sides of the base layer 130 along the second direction Y, which makes it easy for metal residues to exist on these sides, resulting in a short circuit between two adjacent signal lines.

[0079] In this embodiment, the display panel 100 further includes test lines. At least a portion of two adjacent signal lines are spaced apart on the substrate 130, and the test lines are located between the two adjacent signal lines. The test lines include a first test line 160 (FIG. 2). When there are metal residues on the substrate 130, and two adjacent signal lines are short-circuited through the metal residues, the first test line 160 and either of the two adjacent signal lines form a partial test circuit, thereby testing the metal residues between the two adjacent signal lines. If metal residues are found, they can be improved during the signal line fabrication process, and the display panel 100 without metal residues can continue to be fabricated, eliminating the need for waste disposal of the display panel 100. This saves module materials, reduces the fabrication cost of the display panel 100, and is beneficial to the fabrication of the display panel 100. For example, the first test line 160 can be disposed in the same layer and with the same material as the signal lines, thereby simplifying the fabrication process of the first test line 160.

[0080] It should be noted that "same layer, same material" in the embodiments of this application refers to forming a base film layer from the same material, and then, after patterning and / or other processing of the base film layer, forming various structural film layers from different parts of the base film layer. The processing processes for the different structural film layers can be the same or different, and the different structural film layers can have the same or different thicknesses, and can also be on the same horizontal plane or different horizontal planes.

[0081] The test line includes a test end and a connection end arranged opposite each other along the second direction Y (Figure 3). The test end is used to connect to external test equipment and is located on the side of the bend area 100c away from the display area. For example, the test end can be located in the bonding area. The connection end is the other end arranged opposite to the test end. The end of the signal line away from the display area 100a and the test end of the test line can be provided with a test pin 193 (Figure 2). The test pin 193 is used for electrical connection to external test equipment.

[0082] The first test line 160 provided in the embodiments of this application will be described below.

[0083] As shown in Figure 2, the base layer 130 includes a first side 131 and a second side 132 disposed opposite to each other. The first side 131 is disposed closer to the display area 100a, and the second side 132 is disposed further away from the display area 100a. The orthographic projection of the test end of the first test line 160 onto the plane of the base layer 130 is located on the side of the second side 132 that is further away from the display area 100a. The test end of the first test line 160 can be used to connect to external testing equipment. The connection end of the first test line 160 extends along the second side 132 toward the first side 131. The orthographic projection of the first test line 160 onto the plane of the base layer 130 partially coincides with the base layer 130.

[0084] As shown in Figure 3, the first test line 160 may include a power test line 161. The power test line 161 is fabricated in the same layer and with the same material as the power line 110. Both the power test line 161 and the power line 110 are located on the side of the buffer layer 140 away from the substrate. The power test line 161 is used to detect metal residues between the ELVSS signal line 112 and the ELVDD signal line 111. The first side 131 and the second side 132 of the buffer layer 140 are respectively the first organic side 141 and the second organic side 142.

[0085] As shown in Figure 2, the first test line 160 may include a touch test line 162. The touch test line 162 is fabricated in the same layer and material as the touch line 120. Both the touch test line 162 and the touch line 120 are located on the side of the dam 150 away from the substrate. The touch test line 162 is used to detect metal residues between two adjacent touch lines 120. Specifically, a touch test line 162 may be provided between every two adjacent touch lines 120, or a touch test line 162 may be provided between some of two adjacent touch lines 120, while no touch test line 162 is provided between other adjacent touch lines 120. The first side 131 and the second side 132 of the dam 150 are respectively the first dam side 151 and the second dam side 152.

[0086] In an embodiment where the base layer 130 is a buffer layer 140, the signal line is a power line 110, and the first test line 160 is a power test line 161, as shown in FIG3, the power test line 161 is disposed between adjacent ELVSS signal lines 112 and ELVDD signal lines 111. For example, the power test line 161 can be disposed between the first extension 1121 and the ELVDD signal line 111. Alternatively, the power test line 161 can also be disposed between the second extension 1122 and the ELVDD signal line 111. When there are metal residues at the first organic side 141 and / or the second organic side 142, for example, by testing parameters such as current, voltage, or resistance between the power test line 161 and the ELVSS signal line 112 and comparing the test values ​​with the values ​​when there is no short circuit, it can be determined whether there is a short circuit between the power test line 161 and the ELVSS signal line 112, thereby determining whether there are metal residues between the power test line 161 and the ELVSS signal line 112. By testing the current, voltage, or resistance between the power test line 161 and the ELVDD signal line 111, and comparing the test values ​​with those when there is no short circuit, it can be determined whether there is a short circuit between the power test line 161 and the ELVDD signal line 111, and thus whether there are any metal residues between the power test line 161 and the ELVDD signal line 111.

[0087] For example, when fabricating power lines 110 and power test lines 161, a metal material layer is first formed on the side of the buffer layer 140 and the fourth insulation layer away from the substrate, and a mask is formed on the metal material layer. After etching the metal material layer, power lines 110 and power test lines 161 are formed. If metal residue is found between ELVSS signal line 112 and ELVDD signal line 111 after testing with power test line 161, the mask can be removed, and the exposure during the mask fabrication process can be adjusted to form an improved mask. The metal material layer is then etched again to remove the metal residue. By improving the metal residue during the fabrication of power lines 110 and continuing to fabricate a display panel 100 free of metal residue, the entire display panel 100 does not need to be discarded, saving module materials, reducing the fabrication cost of the display panel 100, and facilitating the fabrication of the display panel 100.

[0088] In an embodiment where the base layer 130 is the dam 150, the signal line is the touch line 120, and the first test line 160 is the touch test line 162, as shown in Figure 2, the touch test line 162 is positioned between two adjacent touch lines 120, which can be the first touch line and the second touch line. The touch test line 162 is located between the first touch line and the second touch line. For example, by testing parameters such as current, voltage, or resistance between the touch test line 162 and the first touch line, and comparing the test values ​​with those when there is no short circuit, it can be determined whether the touch test line 162 and the first touch line are short-circuited, thereby determining whether there is any metal residue between the touch test line 162 and the first touch line. By testing parameters such as current, voltage, or resistance between the touch test line 162 and the second touch line, and comparing the test values ​​with those before a short circuit, it can be determined whether there is a short circuit between the touch test line 162 and the second touch line, thereby determining whether there are metal residues between them. This allows for the mitigation of metal residues during the fabrication of the touch line 120, enabling the continued fabrication of a metal residue-free display panel 100. This eliminates the need for discarding the entire display panel 100, saving module materials, reducing the fabrication cost of the display panel 100, and facilitating its production.

[0089] In a first embodiment of the first test line 160, at least a portion of the connection end of the first test line 160 has its orthographic projection on the plane of the substrate 130 located between the first side 131 and the second side 132. The first test line 160 covers the side of the second side 132 facing away from the substrate and passes through the second side 132. The first test line 160 can detect metal residues at the second side 132.

[0090] In an embodiment where the substrate 130 is a buffer layer 140, the signal line is a power line 110, and the first test line 160 is a power test line 161, as shown in FIG3, at least a portion of the connection end of the power test line 161 has its orthographic projection on the plane of the buffer layer 140 located between the first organic side 141 and the second organic side 142 of the buffer layer 140. The power test line 161 covers the side of the second organic side 142 facing away from the substrate and passes through the second organic side 142. The power test line 161 can detect metal residues between the ELVDD signal line 111 and the ELVSS signal line 112 at the second organic side 142.

[0091] In an embodiment where the base layer 130 is a dam 150, the signal line is a touch line 120, and the first test line 160 is a touch test line 162, as shown in FIG4, at least a portion of the connection end of the touch test line 162 has its orthographic projection on the plane where the dam 150 is located between the first dam side 151 and the second dam side 152. The touch test line 162 covers the side of the substrate facing away from the second dam side 152, and the touch test line 162 passes through the second dam side 152. The touch test line 162 can detect metal residue between the first touch line and the second touch line at the second dam side 152.

[0092] In a second embodiment of the first test line 160, at least a portion of the connection end of the first test line 160 has its orthographic projection on the plane of the substrate 130 located on the side of the first side 131 closest to the display area 100a. That is, the first test line 160 extends from the side of the second side 132 away from the first side 131 to the side of the first side 131 away from the second side 132, passing through the first side 131 and the second side 132 of the substrate 130, and covering the sides of the first side 131 and the second side 132 away from the substrate. The first test line 160 can detect metal residues on the first side 131 and the second side 132.

[0093] It is understandable that when the metal residue is located on the first side 131, the metal residue is located on the second side 132, or the metal residue is located on both the first side 131 and the second side 132, the parameter values ​​obtained by the signal line and the first test line 160 are different, thus the specific location of the metal residue can be distinguished.

[0094] In the embodiment where the base layer 130 is a buffer layer 140, the signal line is a power line 110, and the first test line 160 is a power test line 161, as shown in FIG5, the connection end of the power test line 161 is located on the side of the first organic side 141 that is away from the second organic side 142. The power test line 161 passes through the first organic side 141 and the second organic side 142, and the power test line 161 can detect metal residues on the first organic side 141 and the second organic side 142.

[0095] In the embodiment where the base layer 130 is the dam 150, the signal line is the touch line 120, and the first test line 160 is the touch test line 162, as shown in Figure 2, the connection end of the touch test line 162 is located on the side of the first dam side 151 away from the second dam side 152. The touch test line 162 passes through the first dam side 151 and the second dam side 152, and the touch test line 162 can detect metal residues on the first dam side 151 and the second dam side 152.

[0096] In a third embodiment of the first test line 160, as shown in FIG6, multiple fan-out lines 191 are spaced apart within the non-display area 100b. The fan-out lines 191 are located on the side of the buffer layer 140 facing the substrate, and the orthogonal projection of the fan-out lines 191 on the substrate can be located between the orthogonal projection of the buffer layer 140 on the substrate and the display area 100a. The fan-out lines 191 can be formed by at least one of the first metal layer and the second metal layer. The surface flatness of the portion of the fourth insulating layer corresponding to the fan-out lines 191 is poor, which makes it easy for metal residues to appear on the surface of the portion of the fourth insulating layer corresponding to the fan-out lines 191, which may lead to short circuits in some signal lines.

[0097] For example, at least a portion of the fan-out line 191's orthographic projection on the plane of the buffer layer 140 lies between the orthographic projections of the ELVDD signal line 111 and the ELVSS signal line 112 on the plane of the buffer layer 140. Metal residue is prone to accumulate in the portion of the ELVDD signal line 111 and the ELVSS signal line 112 corresponding to the fan-out line 191, potentially leading to a short circuit between these two lines. The orthographic projection of the connection end of the power test line 161 on the plane of the buffer layer 140 partially coincides with the orthographic projection of the fan-out line 191 on the plane of the buffer layer 140. The power test line 161 can detect the metal residue caused by the fan-out line 191. For example, the power test line 161 can detect the metal residue caused by the fan-out line 191 between the ELVDD signal line 111 and the ELVSS signal line 112.

[0098] In some embodiments, during the etching process, over-etching may occur on the sidewalls of the signal line, affecting its performance. The edges of the signal line may be provided with protrusions 180 at intervals (Figure 7). During the etching process, over-etching will first occur on the protrusions 180, thereby reducing or avoiding over-etching at the protrusions 180 and protecting the signal line. Multiple protrusions 180 can be provided at intervals along the edges of the signal line.

[0099] As shown in Figure 7, the test line may include at least two second test lines 170. The second test lines 170 are located on the side of the signal line away from the substrate. The connection ends of the two second test lines 170 are connected to each other to form a partial test loop. For example, the connection ends of the two second test lines 170 can be connected by a connecting wire 192. The orthographic projection of either of the two second test lines 170 onto the plane of the protrusion 180 partially coincides with the protrusion 180. The second test line 170 covers the side of the protrusion 180 away from the substrate. If the sidewall of the protrusion 180 is over-etched, the sidewall of the protrusion 180 will be recessed. The recess makes it easy for the second test line 170 to break when it covers the sidewall of the protrusion 180, causing the two second test lines 170 to be disconnected. By comparing the detection parameters with those when they are not disconnected, it can be determined whether the two second test lines 170 are disconnected, and whether the sidewall of the protrusion 180 is over-etched in time. The manufacturing process of the signal line and the protrusion 180 can be improved to avoid wasting module materials in subsequent processes, which is beneficial to the manufacturing of the display panel 100.

[0100] The protrusion 180 includes a first protrusion 181 and a second protrusion 182 (Figure 8). The first protrusion 181 is located on one of at least two signal lines, and the second protrusion 182 is located on the other of at least two signal lines. The orthographic projection of one of the two second test lines 170 on the plane of the first protrusion 181 partially coincides with that of the first protrusion 181, and the orthographic projection of the other of the two second test lines 170 on the plane of the second protrusion 182 partially coincides with that of the second protrusion 182. If at least one of the sidewalls of the first protrusion 181 and the second protrusion 182 is over-etched, at least one second test line 170 will break, causing a break between the two second test lines 170, in order to determine whether the sidewall of the protrusion 180 is over-etched, thereby improving the manufacturing process of the signal lines and the protrusion 180, which is beneficial to the manufacturing of the display panel 100.

[0101] Taking the protrusion 180 as an example, the protrusion 180 can be located on the ELVSS signal line 112, and the protrusion 180 can also be located on the ELVDD signal line 111.

[0102] For example, as shown in FIG7, the protrusion 180 may be located on the ELVSS signal line 112. Part of the protrusion 180 is located at the edge of the first extension 1121, and part of the protrusion 180 is located at the edge of the second extension 1122. One of the two connected second test lines 170 covers the side of the protrusion 180 in the first extension 1121 that is away from the substrate, and the other of the two connected second test lines 170 covers the side of the protrusion 180 in the second extension 1122 that is away from the substrate. At least part of the connecting line 192 covers the side of the ELVDD signal line 111 that is away from the substrate. If the protrusion 180 is over-etched, the two second test lines 170 and the connecting line 192 will be disconnected, thereby indicating that the sidewall of the fourth metal layer where the protrusion 180 is located has been over-etched, and the fabrication process of the power line 110 and the protrusion 180 can be improved in time, which is beneficial to the fabrication of the display panel 100. For example, the protrusion 180 may be located on the edge of the ELVSS signal line 112 facing the ELVDD signal line 111. At least one of the second test line 170 and the ELVSS signal line 112, and the connecting line 192 and the ELVDD signal line 111, is provided with an insulating layer to prevent short circuits between the ELVSS signal line 112 and the ELVDD signal line 111.

[0103] For example, the protrusion 180 may be located at the edge of the ELVDD signal line 111. At least one of the two connected second test lines 170 covers the side of the protrusion 180 of the ELVDD signal line 111 that faces away from the substrate. If the protrusion 180 is over-etched, the two second test lines 170 and the connecting line 192 will be disconnected, thereby indicating that the sidewall of the fourth metal layer where the protrusion 180 is located has been over-etched, and the fabrication process of the power line 110 and the protrusion 180 can be improved in time, which is beneficial to the fabrication of the display panel 100.

[0104] For example, as shown in FIG8, the protrusion 180 includes a plurality of first protrusions 181 and a plurality of second protrusions 182. The first protrusions 181 may be located at the edge of the ELVSS signal line 112, and the second protrusions 182 may be located at the edge of the ELVDD signal line 111. One of the two connected second test lines 170 covers the side of the first protrusion 181 facing away from the substrate, and the other of the two connected second test lines 170 covers the side of the second protrusion 182 facing away from the substrate. When at least one of the first protrusions 181 and the second protrusion 182 is over-etched, the two second test lines 170 and the connecting line 192 will be disconnected, thereby determining that the sidewall of the fourth metal layer where the protrusion 180 is located has been over-etched, and the fabrication process of the power line 110 and the protrusion 180 can be improved in time, which is beneficial to the fabrication of the display panel 100. An insulating layer is provided between the second test line 170 covering the first protrusion 181 and the first protrusion 181, and between the second test line 170 covering the second protrusion 182 and the second protrusion 182, so as to prevent short circuit between the ELVSS signal line 112 and the ELVDD signal line 111.

[0105] It should be noted that only the display panel 100 of the non-display area 100b can be fabricated, without fabricating the display panel 100 of the display area 100a, thereby saving module materials. Correspondingly, the mask used to fabricate the display panel 100 of the non-display area 100b can only include the pattern of the non-display area 100b, thus simplifying the mask structure. If metal residues or over-etching of signal lines are found in the display panel 100 of the non-display area 100b, the display panel 100 of the non-display area 100b is improved until the display panel 100 of the non-display area 100b does not have the fabrication defects described in the above embodiments. Then, a complete display panel 100, including display area 100a and non-display area 100b, is prepared according to the improved process. Since the process has been improved, the various manufacturing defects mentioned above no longer exist in non-display area 100b. Therefore, test lines do not need to be set in non-display area 100b, thereby saving wiring space on the complete display panel 100 and simplifying the manufacturing process of the complete display panel 100.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, The display panel includes a non-display area and includes test lines and at least two signal lines. The display panel located in the non-display area includes a base layer. At least a portion of two adjacent signal lines are spaced apart on the base layer. The test lines are located between the two adjacent signal lines. The test lines include a first test line. When there is metal residue on the base layer, and two adjacent signal lines are short-circuited through the metal residue, either the first test line or the two adjacent signal lines forms a partial test loop. The test lines include at least two second test lines. The second test lines are located on the side of the signal lines away from the base layer. The connecting ends of the two second test lines are connected to each other to form a partial test loop. The edges of the signal lines are provided with protrusions. The orthographic projection of either of the two second test lines on the plane where the protrusion is located coincides with a portion of the protrusion.

2. The display panel according to claim 1, characterized in that, It also includes a display area, which is adjacent to the non-display area. The base layer includes a first side that is close to the display area and a second side that is far away from the display area, which are disposed opposite to each other. The orthographic projection of the test end of the first test line on the plane of the base layer is located on the side of the second side that is far away from the display area. The orthographic projection of the first test line on the plane of the base layer coincides with the base layer.

3. The display panel according to claim 2, characterized in that, At least a portion of the connection end of the first test line has its orthographic projection on the plane of the base layer located between the first side and the second side.

4. The display panel according to claim 3, characterized in that, At least a portion of the connection end of the first test line is projected onto the plane of the base layer, with its orthographic projection located on the side of the first side closest to the display area.

5. The display panel according to claim 4, characterized in that, Multiple fan-out lines are spaced apart in the non-display area. The fan-out lines are located on the side of the base layer away from the signal lines. The orthographic projection of the connection end on the plane of the base layer coincides with the orthographic projection of the fan-out lines on the plane of the base layer.

6. The display panel according to claim 5, characterized in that, At least a portion of the fan-out lines are projected onto the plane of the substrate, with their orthogonal projections located between the orthogonal projections of two adjacent signal lines onto the plane of the substrate.

7. The display panel according to any one of claims 2-6, characterized in that, The non-display area includes a bending area, the base layer includes a buffer layer located at least in the bending area, the first test line includes a power test line, the signal line includes a high-level signal line and a low-level signal line, both of which are located on the buffer layer, and the power test line is located between the high-level signal line and the low-level signal line.

8. The display panel according to any one of claims 2-4, characterized in that, The non-display area includes a bending area, the base layer includes a dam, the first test line includes a touch test line, the dam is located between the bending area and the display area, the signal line includes multiple touch lines, and the touch test line is located between two adjacent touch lines.

9. The display panel according to any one of claims 1-6, characterized in that, The protrusion includes a first protrusion and a second protrusion. The first protrusion is located on one of the at least two signal lines, and the second protrusion is located on the other of the at least two signal lines. The orthographic projection of one of the two second test lines on the plane where the first protrusion is located coincides with a portion of the first protrusion, and the orthographic projection of the other of the two second test lines on the plane where the second protrusion is located coincides with a portion of the second protrusion.

10. A display device, characterized in that, Includes the display panel described in any one of claims 1-9 above.

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