Memory Built-In Self-Test with Automated Multi-Step Reference Fine Tuning

Abstract

A storage device may use reference trimming to sense stored data during a memory read operation, and a memory built-in self-test system may perform a multi-step process to set reference trimming for the storage device. The memory built-in self-test system may set a reference trimming range corresponding to a range of available reference trimming values, and then select one of the reference trimming values in the reference trimming range as the reference trimming for the storage device. The memory built-in self-test system may set the reference trimming range by prompting memory read operations to be performed at different positions of the reference trimming range relative to the read characteristics of the storage device, and set the position of the reference trimming range relative to the read characteristics of the storage device based on a failure event that the storage device cannot correctly sense the stored data during the memory read operation.

Description

[0001] Related Applications

[0002] This patent application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 945,457, filed on December 9, 2019, which is incorporated herein by reference. Technical Field

[0003] This application generally relates to electronic design automation, and more particularly to built-in self-test for memory with an automated multi-step process for setting reference trimming for a storage device. Background Art

[0004] Magnetoresistive Random Access Memory (MRAM) has become an attractive non-volatile memory solution due to its small size, fast operating speed, and good durability. MRAM devices can store data in magnetic domains, e.g., as the spin polarities of magnets in their free layers. MRAM devices can write data in magnetic domains by setting the spin polarities of the magnets in their free layers (e.g., providing a spin-polarized current through a Magnetic Tunnel Junction (MTJ), which exerts a torque on the local magnetization in the free layer, commonly referred to as Spin Torque Transfer (STT)).

[0005] To read the stored data, an MRAM device can determine the spin polarity of the magnet in its free layer relative to a pinned reference layer below the corresponding free layer. When the spin polarity is parallel to the pinned reference layer, the resistivity on the reference Bit-Line (BL) of the MRAM device can be considered low, and thus corresponds to a data "0" value. When the spin polarity is anti-parallel to the pinned reference layer, the resistivity on the reference bit-line of the MRAM device can be considered high, and thus corresponds to a data "1" value. The MRAM device can include a sensing circuit that detects the resistivity on the reference bit-line of the MRAM device and compares the detected resistivity with a reference resistance to determine whether the detected resistivity is considered low corresponding to a data "0" value or high corresponding to a data "1" value.

[0006] Many MRAM devices have a relatively small resistivity separation between a high resistance state associated with a data “1” value and a low resistance state associated with a data “0” value, which can pose challenges for reliable data read operations. To counteract this lack of resistivity separation, some MRAM sensing circuits have included additional trimming circuitry that finely adjusts a reference resistance, a reference voltage, or a reference current to more reliably distinguish between the high and low resistance states of its memory cells. Most trimming circuitry receives an external input via a knob, for example, during a post-processing compensation method, to shift a reference value to correspond to a trim value. For example, an engineer can adjust the reference resistance, reference voltage, or reference current when approaching the low state to increase the margin or separation for reading in the high resistance state. The engineer can also adjust the reference resistance, reference voltage, or reference current when approaching the high state to increase the margin or separation for reading in the low resistance state. In some examples, a sense amplifier can compare a voltage or current on an active bit line (BL) connected to a memory resistance to a resistance value of a reference BL and amplify the difference between the reference resistance, reference voltage, or reference current and the memory resistance, memory voltage, or memory current, respectively. The separation between two inputs of the sense amplifier can allow for reliable sensing of the stored data. Test engineers typically determine the value of reference trimming in an MRAM device through extensive scan testing over different environmental conditions (such as temperature variations) to identify the full distribution of bit characteristics of the MRAM device before performing engineering analysis to identify the reference trimming settings. Such MRAM device testing has proven to be expensive or impractical in larger MRAM array implementations. Summary of the Invention

[0007] This application discloses a storage device that uses reference trimming to sense stored data during a memory read operation and a memory built-in self-test system that performs a multi-step process to set reference trimming for the storage device. The memory built-in self-test system can set a reference trimming range corresponding to a range of available reference trimming values and then select one of the reference trimming values in the reference trimming range to set the reference trimming for the storage device. The memory built-in self-test system can set the reference trimming range by prompting the storage device to perform memory read operations at different positions of the reference trimming range relative to the read characteristics of the storage device, determining when the storage device cannot correctly sense the stored data during these read operations, and setting the position of the reference trimming range relative to the read characteristics of the storage device based on a failure event where the storage device cannot correctly sense the stored data. Embodiments will be described in more detail below. Brief Description of the Drawings

[0008] Figure 1Illustrates an example storage system 100 including memory built - in self - test with an automated multi - step reference fine - tuning process according to various embodiments.

[0009] Figure 2 Illustrates a graph of example read characteristics of a magnetoresistive storage device according to various embodiments.

[0010] Figure 3 Illustrates a flowchart of an example implementation of an automated reference fine - tuning range shift process according to various embodiments.

[0011] Figure 4A and Figure 4B Illustrates a graph of an example reference fine - tuning range shift relative to reference selection results according to various embodiments.

[0012] Figures 5A to 5D Illustrates a graph of an example automated fine - tuning range according to various embodiments.

[0013] Figures 6A to 6D Illustrates a graph of an example automated bit - line resistance search process according to various embodiments.

[0014] Figure 7 Illustrates a flowchart of an example implementation of an automated fine - tuning feedback process according to various embodiments.

[0015] Figures 8A to 8C Illustrates a graph of example fine - tuning reference selection results using different failure thresholds according to various embodiments. Detailed Description

[0016] Memory Built - in Self - Test with Automated Multi - Step Reference Fine - Tuning

[0017] Figure 1 Illustrates an example storage system 100 including memory built - in self - test with an automated multi - step reference fine - tuning process according to various embodiments. Reference Figure 1, the storage system 100 includes a storage device 130 that stores data 101 during a data write operation and senses the stored data 107 during a data read operation. In some embodiments, the storage device 130 may include a magnetoresistive random access memory (MRAM) that stores data 101 in magnetic domains, e.g., as the spin polarities of magnets in a free layer. The magnetoresistive random access memory may use a spin transfer torque (STT) mechanism that can write data 101 by providing a spin-polarized current through a magnetic tunnel junction (MTJ) that applies a torque to the local magnetization in the free layer. In other embodiments, the storage device 130 may include other types of random access memory (RAM), such as resistive random access memory (ReRAM), conductive bridge random access memory (CBRAM), phase change memory (PCM), ferromagnetic random access memory (FeRAM), etc., or may include other types of non-volatile memory.

[0018] The storage system 100 may include a memory built-in self-test controller 110 that controls the memory access operations of the storage device 130. The memory built-in self-test controller 110 may generate a control signal 102 and an address signal 104 that, when provided to the storage device 130, may prompt the storage device 130 to perform a memory access operation, e.g., a data write operation or a data read operation, at the address indicated by the address signal 104. When the control signal 102 corresponds to a data write operation, the storage device 130 may store data 101 from the memory built-in self-test controller 110 at the address indicated by the address signal 104 in response to the control signal 102. When the control signal 102 corresponds to a data read operation, the storage device 130 may locate and output the stored data 107 at the address indicated by the address signal 104 in response to the control signal 102. The storage device 130 may read the stored data 107 by sensing an electrical value (e.g., voltage, current, resistance, etc.) associated with a bit line of the storage device 130 and comparing the sensed electrical value with a reference value to determine whether the stored data 107 corresponds to a high data value associated with data "1" or a low data value associated with data "0". In some embodiments, one or more intermediate data values may exist between the high data value and the low data value.

[0019] Since, in some cases, the reference value used by the storage device 130 to sense the data value of the stored data 107 may be misaligned with the electrical characteristics of one or more memory cells in the storage device 130, the storage device 130 may adjust the reference value based on a trim signal 105 and a trim range signal 106. The storage device 130 may use the adjusted reference value to determine whether the stored data 107 corresponds to a high data value or a low data value. Refer to the following Figure 2An example of describing the read characteristics of a magnetoresistive memory device using a reference trimming value.

[0020] Figure 2 Graph 200 illustrating example read characteristics of a magnetoresistive memory device according to various embodiments. Refer to Figure 2 , graph 200 has an x-axis corresponding to memory data (such as bit line resistance 202 or bit line current) during the read operation of the magnetoresistive memory device, and a y-axis corresponding to the probability 201 or likelihood of each bit line resistance 202 occurring. In this example, the read characteristics can include two groups: one group for data associated with reading the stored "low" value or reading zero 203, and another group for data associated with reading the stored "high" value or reading one 204.

[0021] The magnetoresistive memory device can set the value of a reference resistance 205, which can be used to determine whether the sensed bit line resistance value corresponds to the stored data "0" value or the stored data "1" value in the magnetoresistive memory device. In this example, the value of the reference resistance 205 falls within the range corresponding to the bit line resistance associated with reading the stored data "0" value or reading zero 203, which means that the magnetoresistive memory device may incorrectly sense the resistance of the stored data "0" value as the stored data "1" value. In some instances, the magnetoresistive memory device can use a reference trim 206 and a reference trim range 208 to adjust the reference resistance 205 to produce a reference resistance setting. The reference trim range 208 can correspond to the range within which the reference resistance 205 can be adjusted with the value of the reference trim 206. The adjusted reference resistance can be located in the middle between the edge of reading zero 203 and the edge of reading one 204 to avoid any read sensing errors of the magnetoresistive memory device.

[0022] There may be a situation where no value of the reference trim 206 in the reference resistance 205 and the reference trim range 208 results in the adjusted reference resistance 207 falling between the read zero 203 characteristic and the read one 204 characteristic of the magnetoresistive memory device. As will be described in more detail below, the magnetoresistive memory device can set the position of the reference trim range 208 relative to the bit line resistance 202 of the read zero 203 and read one 204 characteristics of the magnetoresistive memory device such that the value of the reference trim 206 in the reference trim range 208 will result in the adjusted reference resistance falling in the middle between the upper boundary of the read zero 203 characteristic and the lower boundary of the read one 204 characteristic of the magnetoresistive memory device. For example, when the adjusted reference resistance 207 is closer to the upper edge of the read zero range 203 or the lower edge of the read one range 204, the adjusted reference resistance 207 may not have a balanced read margin for reading 1 and 0. The trim range can overlap with the distribution tails of both read zero 203 and read one 204, which can avoid an unbalanced read margin.

[0023] Return reference Figure 1 , the storage system 100 may include a built-in self-test interface 120 to generate a trim signal 105 and a trim range signal 106 for the storage device 130. The trim range signal 106 may correspond to the position of the reference trim range relative to the read characteristics of the storage device 130. When the storage device 130 does not have a control input on the active bit line connected to the read storage cell, in some embodiments, the trim range signal 106 may prompt the storage device 130 to set the position of the reference trim range or shift the reference trim range from one setting to another, for example, by adding an adder circuit component in the reference bit line of the storage device 130 to modify the reference value while keeping the active bit line characteristics of the storage device 130 the same. When the storage device 130 includes a control input for modifying the active bit line of the storage cell, in some embodiments, the trim range signal 106 may prompt the storage device 130 to modify the active bit line characteristics while keeping the position of the reference trim range the same. These two embodiments will be described in more detail below.

[0024] The storage device 130 may use the trim signal 105 to select a reference trim value within the reference trim range and set the reference value of the storage device 130 with the reference trim value. The storage device 130 may utilize the reference value during a memory read operation, for example, to sense whether the stored data corresponds to a high data value or a low data value. In some embodiments, the reference trim value may correspond to a resistance value, a voltage value, a current value, etc., which may be used to adjust a reference resistance, a reference voltage, a reference current, respectively.

[0025] The built-in self-test interface 120 may provide the trim signal 105 and the trim range signal 106 to the storage device 130. The storage device 130 may utilize the trim range signal 106 to perform a relative shift of the reference trim range, for example, so that a wider trim setting may be available for the reference value. The adjustment of the reference trim range may change the read characteristics of the storage device 130 to accommodate any memory characteristic shift caused by process updates and other variations. The storage device 130 may adjust the reference value for reading the stored data 107 based on the reference trim value.

[0026] The memory built-in self-test controller 110 may include a trim setting unit 112 for initiating a two-step search process to automatically identify the value of the trim range signal 106 and the value of the trim signal 105 within the trim range defined by the trim range signal 106, for example, by identifying the position of a reference trim range relative to the read characteristics of the storage device 130 and then identifying the value within the reference trim range to be set as the reference trim. The trim setting unit 112 may write test data (e.g., data 101) to the storage device 130, for example, by generating a control signal 102 and an address signal 104, which prompt the storage device 130 to perform a data write operation with the data 101. In some embodiments, the trim setting unit 112 may write the same data value (e.g., data "1" or data "0") to the memory cells in the storage device 130.

[0027] The trim setting unit 112 may also generate a trim setting signal 103, which prompts the built-in self-test interface 120 to select the values of the trim signal 105 and the trim range signal 106 and provide the selected value in the trim signal 105 to the storage device 130. The trim setting unit 112 may prompt the storage device 130 to perform a data read operation using the reference trim value in the trim signal 105 and output test data, e.g., stored data 107. The built-in self-test interface 120 may determine when the storage device 130 fails to output stored data 107 having the same value as the data 101. In some embodiments, the built-in self-test interface 120 may compare the stored data 107 read from the storage device 130 with the type of the test data (e.g., data "1" value or data "0" value) and detect a failure event in which the storage device 130 fails to output stored data 107 having the correct value based on this comparison.

[0028] The built-in self-test interface 120 may include a trim range search circuit 122 to determine the value of the trim range signal 106, which may allow the storage device 130 to set a reference trim range relative to the read characteristics of the storage device 130. The trim setting unit 112 and the trim range search circuit 122 may iteratively write test data to the storage device 130 and read test data from the storage device 130 using different values of the trim signal 105 and the trim range signal 106, which may allow the trim range search circuit 122 to determine the position of the reference trim range relative to the read characteristics of the storage device 130 and set the value of the trim range signal 106. The reference Figure 3 Embodiments of the automated reference trim range setting process are described in more detail.

[0029] Figure 3 A flowchart illustrating an example implementation of an automated reference trim range shifting process according to various embodiments is provided. Reference Figure 3, in block 301, the memory built-in self-test system can store test data having a common data type into a storage device. The memory built-in self-test system can write the test data into the storage device by generating control signals and address signals (the control signals and address signals prompt the storage device to perform a data write operation using the test data). In some embodiments, the memory built-in self-test system can write the same data value (e.g., all data "1" values or all data "0" values) into the storage cells in the storage device.

[0030] In block 302, the memory built-in self-test system can provide a test reference trim value and a test trim range value to the storage device for use during a memory read operation. The storage device can use the test trim range value to set the position of the reference trim range relative to the read characteristics of the storage device. The storage device can use the test reference trim value to set a reference trim within the reference trim range of the storage device. When the storage device has no control input on the active bit line connected to the read storage cell, in some embodiments, the test trim range value can prompt the storage device to set the position of the reference trim range or shift the position of the reference trim range from one setting to another setting. For example, by adding an adder circuit component in the reference bit line to modify the reference value while keeping the active bit line characteristics of the storage device the same. When the storage device includes a control input for modifying the active bit line of the storage cell, in some embodiments, the test trim range signal can prompt the storage device to modify the active bit line characteristics of the storage device while keeping the position of the reference trim range the same. These embodiments will be described in more detail below with reference to Figure 4A and Figure 4B These embodiments will be described in more detail.

[0031] Figure 4A and Figure 4B illustrate graphs of the shift of an example reference trim range relative to a reference selection result according to various embodiments. Referring to Figure 4A , graph 400 has an x-axis corresponding to the bit line resistance 402 during a read operation of a magnetoresistive storage device, and a y-axis corresponding to the probability 401 or likelihood of each bit line resistance 402 occurring. In this example, the read characteristics can include two groups: one group for the bit line resistance associated with reading a stored data "0" value or reading zero 403 and another group for the bit line resistance associated with reading a stored data "1" value or reading one 404.

[0032] The magnetoresistive memory device may also include a reference resistor 405, which can be used to determine whether the sensed bit line resistance value corresponds to a stored data "0" value or a stored data "1" value. The magnetoresistive memory device may adjust the reference resistor 405 within a reference trim range 406 to produce an adjusted reference resistor. The reference trim range 406 may correspond to a range of values available for the reference resistor 405. The reference trim range 406 may be adjusted with an input value of reference trim.

[0033] The magnetoresistive memory device may use a trim range value to shift the position of the reference trim range 406 relative to the bit line resistance 402 of the magnetoresistive memory device, as shown by the shifted reference trim range 416. In some embodiments, the magnetoresistive memory device may use a trim range value to adjust the compensation bias current of the bit lines in the magnetoresistive memory device, which may shift the reference trim range 406 to correspond to a new set of bit line resistances 402 at the shifted reference trim range 416.

[0034] Reference Figure 4B , the graph 410 has an x-axis corresponding to the bit line resistance 402 during the read operation of the magnetoresistive memory device, and a y-axis corresponding to the probability 401 or likelihood of each bit line resistance 402 occurring. In this example, the read characteristics may be changed in two aspects: one aspect is the effective bit line resistance associated with reading a bit and the other aspect is the reference bit line resistance associated with the reference for determining whether the read data is "1" or "0".

[0035] The magnetoresistive memory device may also include a reference resistor 405, which can be used to determine whether the sensed bit line resistance value corresponds to a stored data "0" value or a stored data "1" value stored in the magnetoresistive memory device. The magnetoresistive memory device may adjust the reference resistor 405 within a reference trim range 406 to produce an adjusted reference resistor. The reference trim range 406 may correspond to a range within which the reference resistor 405 can be adjusted within the values of the reference trim range 406.

[0036] The magnetoresistive memory device may use a trim range value to shift the bit line resistance 402. Before shifting the reference trim range 406, the effective bit lines in the magnetoresistive memory device may have a resistance value in the zero state or read zero 403, or a resistance value in the one state or read one 404, which may be shifted in the magnetoresistive memory device to an adjusted read zero 413 and an adjusted read one 414, respectively. In some embodiments, the magnetoresistive memory device may use an adder circuit component to control both the effective bit line and the reference bit line to have independent trim adjustment values. For example, the adder circuit component may adjust the current for the effective bit line to shift the memory read characteristics (read zero 403 and read one 404) to read zero 413 and read one 414.

[0037] Return referenceFigure 3 In block 303, the memory built-in self-test system may prompt the storage device to read stored test data from the memory using test reference trim values and trim range values. The memory built-in self-test system may generate a control signal that prompts the storage device to perform a data read operation at the memory location identified by the address signal. In response to the control signal, the storage device may sense the stored test data and compare the sensed data with a reference value to determine whether the stored test data corresponds to a one or a zero. The storage device may use the test reference trim values and test trim range values to set the reference value. In some embodiments, the test reference trim may correspond to the highest and lowest edges of the test reference trim range to perform a trim range coverage assessment. For example, when the common data type corresponds to a low data value or a data "0" value, the test reference trim may have the lowest value in the test trim range. Conversely, when the common data type corresponds to a high data value or a data "1" value, the test reference trim may have the highest value in the test trim range.

[0038] In block 304, the memory built-in self-test system may identify a failure event where the storage device cannot correctly set the reference trim range using the test trim range values. The memory built-in self-test system may compare the data read from the storage device with the common data type of the stored data to determine whether the storage device correctly reads the stored data under each test reference trim setting. The memory built-in self-test system may accumulate the number of failure bits where the storage device cannot correctly read the stored data using the test reference trim and store it as the failure bit count for the common data type set in block 301. In some embodiments, the stored failure bit counts may be compared and used to determine how to set the most significant bit of the reference trim range digital setting. For example, when the trim range tends to a data "1" distribution, the failure bit count may be higher at the highest reference trim setting in the current trim range setting. Thus, the memory built-in self-test system may determine to shift the trim range in the data "0" direction and set the trim range bits accordingly.

[0039] In block 305, the memory built-in self-test system may determine whether to store the test results and move on to test different data types for the storage device. When the memory built-in self-test system has accumulated failures for one data type, the execution may return to block 301, and the memory built-in self-test system may perform the test and store the failure information for the different data types to the storage device.

[0040] When there is no additional data type to collect, the execution can proceed to block 306, where the memory built-in self-test system can determine whether there is another fine-tuning range value to select. In some embodiments, when the memory built-in self-test system has accumulated the identified failures for all data types, the memory built-in self-test system can compare the results of the identified failures to determine the bits for the fine-tuning range value. For example, the memory built-in self-test system can determine a "1" value or a "0" value for each bit in the fine-tuning range value. In some embodiments, the memory built-in self-test system can determine the bits of the fine-tuning range value bit by bit (e.g., in order from the most significant bit (MSB) to the least significant bit (LSB)) based on the identified failures of each data type. The higher the number of identified failures on a data type can indicate that the fine-tuning range tends to that data type, so the memory built-in self-test system can set the bits in the fine-tuning range value that shift the reference fine-tuning range towards other data types.

[0041] In some embodiments, the memory built-in self-test system can compare the accumulated failures determined in block 304 to identify the direction in which the reference fine-tuning range may be shifted based on the comparison result. In some embodiments, the memory built-in self-test system can identify the direction in which the reference fine-tuning range may be shifted as towards a reference value with a lower accumulated failure count.

[0042] When the memory built-in self-test system determines to shift the reference fine-tuning range in the identified direction, for example, when the adjacent reference fine-tuning range positions in that direction have not been tested previously, the execution can proceed to block 307, where the memory built-in self-test system can select another test fine-tuning range value. In some embodiments, the memory built-in self-test system can select a test fine-tuning range value to shift the position of the reference fine-tuning range relative to the read characteristics of the storage device in the direction identified in block 306. When incrementally setting the bits of the fine-tuning range value using the comparison of the identified failures, in some embodiments, when the additional bits of the fine-tuning range value remain unset, the execution can proceed to block 307.

[0043] When the memory built-in self-test system determines that the reference trim range is not shifted in the identified direction, e.g., when the adjacent reference trim range positions in that direction have been previously tested, the execution can proceed to block 308, and the memory built-in self-test system can set the final trim range value in these two adjacent trim range bit settings, e.g., based on the evaluation results obtained for the storage device. In some embodiments, the memory built-in self-test system can set the trim range value of the storage device to one of the test reference trim value ranges or the reference trim value range shift corresponding to the effective bit line value shift in the identified direction. When incrementally setting the bits of the trim range value using the identified failed comparison, in some embodiments, when no bits of the trim range value remain unset, the execution can proceed to block 308. Embodiments of setting the reference trim range signal will be described in more detail below.

[0044] Figures 5A to 5D A graph illustrating an example automated trim range setting according to various embodiments is provided. Referring Figure 5A to, graph 500 has an x-axis corresponding to the reference resistance 502 used by the magnetoresistive storage device during a read operation, and a y-axis corresponding to the cumulative failures 501 of the read operations using various reference resistances 502. The reference resistance 502 can include a reference trim range 505, which corresponds to a set of reference resistances 502 that can be used by the magnetoresistive storage device during a read operation. The magnetoresistive storage device can utilize a reference trim value to select one of the reference resistances 502 within the reference trim range 505 for use during a read operation.

[0045] In this example, graph 500 shows a read zero failure 504 and a read one failure 503. The read zero failure 504 can correspond to a plurality of cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistances. The read one failure 503 can correspond to a plurality of cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistances.

[0046] During an automated trim range setting process, a magnetoresistive memory device may write and read a data value of "0" using a reference trim value at the lower edge of a reference trim range 505, and may write and read a data value of "1" using a reference trim value at the upper edge of the reference trim range 505. Cumulative failures of these read operations may correspond to failure edge points 506, which may be the intercept points between the cumulative failures and the read-zero failure 504 and the read-one failure 503, respectively. The automated trim range setting process may utilize the magnitudes of the two failure edge points 506 to determine the direction to shift the reference trim range 505 for subsequent read operations of the magnetoresistive memory device. In this example, the failure count at the lower trim range edge exceeds the failure count at the higher trim range edge, so the automated trim range setting process should shift the reference trim range 505 to a higher set of reference resistance values. In some embodiments, bits in the trim value may be set based on the magnitudes of the two failure edge points 506. For example, the magnitudes of the two failure edge points 506 may be used to determine a differential failure bit count (dFBC) between the cumulative read-zero failure 504 and the cumulative read-one failure 503 at the failure edge point 506. When the differential failure bit count has a value corresponding to a higher number of read-zero failures at the failure edge point 506, in some embodiments, the bit in the reference trim range value may be set to "1". When the differential failure bit count has a value corresponding to a lower number of read-zero failures at the failure edge point 506, in some embodiments, the bit in the reference trim range value may be set to "0". In some embodiments, unset bits in the reference trim value may be set to zero, which may shift the reference trim range 505 in the determined direction.

[0047] Reference Figure 5B , graph 510 has an x-axis corresponding to the reference resistance 502 used by the magnetoresistive memory device during a read operation, and a y-axis corresponding to the cumulative failures 501 of read operations using various reference resistances 502. The reference resistance 502 may include a reference trim range 515, which corresponds to a set of reference resistances 502 available to the magnetoresistive memory device during a read operation. The automated trim range setting process has shifted Figure 5A the reference trim range 505 in to a set of high reference resistance values, as shown by the reference trim range 515. The magnetoresistive memory device may utilize a reference trim value to select one of the reference resistances 502 within the reference trim range 515 for use during a read operation.

[0048] In this example, the graph 510 shows read zero failures 504 and read one failures 503. The read zero failures 504 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistors. The read one failures 503 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistors.

[0049] During the automated trim range setting process, the magnetoresistive storage device may read the data value "0" using a reference trim value at the lower edge of the reference trim range 515, and may read the data value "1" using a reference trim value at the upper edge of the reference trim range 515. The cumulative failures of these read operations may correspond to the failure edge point 516. The automated trim range setting process may utilize the magnitude of the failure edge point 516 to determine the direction to shift the reference trim range 515 for subsequent read operations of the magnetoresistive storage device. In this example, the automated trim range setting process should shift the reference trim range 515 to a set of higher reference resistance values. In some embodiments, bits in the trim range value may be set based on the magnitudes of two failure edge points 516. For example, the magnitudes of the two failure edge points 516 may be used to determine the differential failure bit count (dFBC) between the cumulative read zero failures 504 at the failure edge point 516 and the cumulative read one failures 503 at the failure edge point 516. When the differential failure bit count has a value corresponding to a higher number of read zero failures at the failure edge point 516, in some embodiments, the most significant unset bit in the reference trim range value may be set to "1". When the differential failure bit count has a value corresponding to a lower number of read zero failures at the failure edge point 516, in some embodiments, the most significant unset bit in the reference trim range value may be set to "0". In some embodiments, the remaining unset bits in the reference trim value may be set to zero, which may shift the reference trim range 505 in the determined direction.

[0050] Reference Figure 5C , the graph 520 has an x-axis corresponding to the reference resistors 502 used by the magnetoresistive storage device during read operations, and a y-axis corresponding to the cumulative failures 501 of the read operations using various reference resistors 502. The reference resistors 502 may include a reference trim range 525, which corresponds to a set of reference resistors 502 available for the magnetoresistive storage device during read operations. The automated trim range setting process has shifted Figure 5B the reference trim range 515 in to a set of high reference resistance values, as shown by the reference trim range 525. The magnetoresistive storage device may utilize the reference trim value to select one of the reference resistors 502 within the reference trim range 525 for use during read operations.

[0051] In this example, graph 520 shows read zero failures 504 and read one failures 503. The read zero failures 504 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistors. The read one failures 503 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistors.

[0052] During an automated trim range setting process, the magnetoresistive storage device may read the data value "0" using a reference trim value at the lower edge of reference trim range 525, and may read the data value "1" using a reference trim value at the upper edge of reference trim range 525. The cumulative failures of these read operations may correspond to failure edge points 526. The automated trim range setting process may utilize the magnitude of the failure edge points 526 to determine the direction to shift the reference trim range 525 for subsequent read operations of the magnetoresistive storage device. In this example, the automated trim range setting process should shift the reference trim range 525 to a set of lower reference resistance values. In some embodiments, bits in the trim range value may be set based on the magnitudes of two failure edge points 526. For example, the magnitudes of the two failure edge points 526 may be used to determine a differential failure bit count between the cumulative read zero failures 504 and the cumulative read one failures 503 at the failure edge point 526. When the differential failure bit count has a value corresponding to a higher number of read zero failures at the failure edge point 526, in some embodiments, the most significant unset bit in the reference trim range value may be set to "1". When the differential failure bit count has a value corresponding to a lower number of read zero failures at the failure edge point 526, in some embodiments, the most significant unset bit in the reference trim range value may be set to "0". In some embodiments, the remaining unset bits in the reference trim value may be set to zero, which may shift the reference trim range 505 in the determined direction.

[0053] Reference Figure 5D , graph 530 has an x-axis corresponding to the reference resistors 502 used by the magnetoresistive storage device during read operations, and has a y-axis corresponding to the cumulative failures 501 of read operations using various reference resistors 502. The reference resistors 502 may include a reference trim range 535, which corresponds to a set of reference resistors 502 available for the magnetoresistive storage device during read operations. The automated trim range setting process has shifted Figure 5C the reference trim range 525 in [reference] to a set of lower reference resistance values, as shown by reference trim range 535. The magnetoresistive storage device may utilize the reference trim values to select one of the reference resistors 502 within the reference trim range 535 for use during read operations.

[0054] In this example, graph 530 shows read zero failures 504 and read one failures 503. The read zero failures 504 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value “0” using various reference resistors. The read one failures 503 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value “1” using various reference resistors.

[0055] During an automated fine-tuning range setting process, a magnetoresistive storage device may read the data value “0” using a reference fine-tuning value at the lower edge of a reference fine-tuning range 535, and may read the data value “1” using a reference fine-tuning value at the upper edge of the reference fine-tuning range 535. Cumulative failures of these read operations may correspond to failure edge points 536. The automated fine-tuning range setting process may utilize the magnitude of the failure edge points 536 to determine the direction to shift the reference fine-tuning range 535 for subsequent read operations of the magnetoresistive storage device. In this example, the automated fine-tuning range setting process determines that a previous reference Figure 5C performed a shift of the reference fine-tuning range 535 to a set of lower reference resistance values, so the automated fine-tuning range setting process selects either the reference fine-tuning range 525 or the reference fine-tuning range 535 as the setting for the reference fine-tuning range of the magnetoresistive storage device. In some embodiments, bits in the fine-tuning range value may be set based on the magnitudes of two failure edge points 536. For example, the magnitudes of the two failure edge points 536 may be used to determine a differential failure bit count between the cumulative read zero failures 504 at the failure edge point 536 and the cumulative read one failures 503 at the failure edge point 536. When the differential failure bit count has a value corresponding to a higher number of read zero failures at the failure edge point 536, in some embodiments, the most significant unset bit in the reference fine-tuning range value may be set to “1”. When the differential failure bit count has a value corresponding to a lower number of read zero failures at the failure edge point 536, in some embodiments, the most significant unset bit in the reference fine-tuning range value may be set to “0”. In some embodiments, the remaining unset bits in the reference fine-tuning value may be set to zero, which may shift the reference fine-tuning range 505 in the determined direction. Reference Figures 5A to 5D The described process may continue until all bits in the reference fine-tuning range value have been set. Although Figures 5A to 5D memory read operations performed using reference resistors 502 have been described, in some embodiments, memory read operations may be performed using a reference voltage or a reference current.

[0056] Figures 6A to 6D Graphs illustrate example automated fine-tuning range control during a valid bit line resistance search process according to various embodiments. Reference Figure 6A, the curve graph 600 has an x-axis corresponding to the reference resistance 602 used by the magnetoresistive memory device during a read operation, and a y-axis corresponding to the cumulative failure 601 of the read operations using various reference resistances 602. The reference resistance 602 may include a reference trim range 605, which corresponds to a set of reference resistances 602 available for the magnetoresistive memory device during a read operation. The magnetoresistive memory device may utilize a reference trim value to select one of the reference resistances 602 within the reference trim range 605 for use during a read operation.

[0057] In this example, the curve graph 600 shows a read zero failure 604 and a read one failure 603. The read zero failure 604 may correspond to multiple cumulative failures where the memory device cannot correctly read the data value "0" using various reference resistances. The read one failure 603 may correspond to multiple cumulative failures where the memory device cannot correctly read the data value "1" using various reference resistances.

[0058] During an automated bit line resistance search process, the magnetoresistive memory device may write and read the data value "0" using a reference trim value at the lower edge of the reference trim range 605, and may write and read the data value "1" using a reference trim value at the upper edge of the reference trim range 605. The cumulative failures of these two data type read operations may correspond to a failure edge point 606. The automated bit line resistance search process may utilize the magnitude of the failure edge point 606 to determine the shift direction of the read characteristics of the magnetoresistive memory device for subsequent read operations. In this example, instead of shifting the reference resistance value, the automated bit line resistance search process shifts the read characteristics of the magnetoresistive memory device by reducing the total resistance accumulation of the effective bit line through circuit control (e.g., by adding an additional current source, bypass resistor, or bias control based on the relative magnitudes of the cumulative failure differences at the two edges of the trim range). In some embodiments, bits in the trim range value may be set based on the magnitudes of the two failure edge points 606. For example, the magnitudes of the two failure edge points 606 may be used to determine the differential failure bit count between the cumulative read zero failures 604 and the cumulative read one failures 603 at the failure edge point 606. When the differential failure bit count has a value corresponding to a higher number of read zero failures at the failure edge point 606, in some embodiments, the highest significant unset bit in the reference trim range value may be set to "1". When the differential failure bit count has a value corresponding to a lower number of read zero failures at the failure edge point 606, in some embodiments, the highest significant unset bit in the reference trim range value may be set to "0". In some embodiments, the remaining unset bits in the reference trim value may be set to zero, which may shift the reference trim range 605 in the determined direction.

[0059] Reference Figure 6B, the graph 610 has an x-axis corresponding to the reference resistance 602 used by the magnetoresistive memory device during a read operation, and a y-axis corresponding to the cumulative failures 601 of the read operations using various reference resistances 602. The reference resistance 602 can be selected within a fixed reference trim range 605. The magnetoresistive memory device can utilize a reference trim value to select one of the reference resistances 602 within the reference trim range 605 for use during a read operation.

[0060] In this example, the graph 610 shows a read zero failure 614 and a read one failure 613, which have been shifted from Figure 6A the read zero failure 604 and the read one failure 603 therein, respectively. The read zero failure 614 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistances. The read one failure 613 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistances.

[0061] During an automated bit line resistance search process, the magnetoresistive memory device can read the data value "0" using a reference trim value at the lower edge of the reference trim range 605, and can read the data value "1" using a reference trim value at the upper edge of the reference trim range 605. The cumulative failures of these read operations can correspond to the failure edge points 616. The automated bit line resistance search process can utilize the magnitude of the failure edge points 616 to determine the shift direction of the read characteristics of the magnetoresistive memory device for subsequent read operations. In this example, due to the relative magnitude of the cumulative failures or the differential failure bit count at the respective edges of the trim range, the automated bit line resistance search process should shift the read characteristics of the magnetoresistive memory device to a lower effective bit line resistance value. In some embodiments, bits in the trim range value can be set based on the magnitudes of the two failure edge points 616. For example, the magnitudes of the two failure edge points 616 can be used to determine the differential failure bit count between the cumulative read zero failures 614 and the cumulative read one failures 613 at the failure edge points 616. When the differential failure bit count has a value corresponding to a higher number of read zero failures at the failure edge points 616, in some embodiments, the most significant unset bit in the reference trim range value can be set to "1". When the differential failure bit count has a value corresponding to a lower number of read zero failures at the failure edge points 616, in some embodiments, the most significant unset bit in the reference trim range value can be set to "0". In some embodiments, the remaining unset bits in the reference trim value can be set to zero, which can shift the reference trim range 605 in the determined direction.

[0062] Reference Figure 6C, the graph 620 has an x-axis corresponding to the reference resistance 602 used by the magnetoresistive memory device during a read operation, and a y-axis corresponding to the cumulative failure 601 of the read operations using various reference resistances 602. The reference resistance 602 may include a reference trim range 605, which corresponds to a set of reference resistances 602 available for the magnetoresistive memory device during a read operation. The magnetoresistive memory device may utilize a reference trim value to select one of the reference resistances 602 within the reference trim range 605 for use during a read operation.

[0063] In this example, the graph 620 shows a read zero failure 624 and a read one failure 623, which have been shifted from the Figure 6B read zero failure 614 and read one failure 613 therein, respectively. The read zero failure 624 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistances. The read one failure 623 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistances.

[0064] During an automated bit line resistance search process, the magnetoresistive memory device may read the data value "0" using a reference trim value at the lower edge of the reference trim range 605, and may read the data value "1" using a reference trim value at the upper edge of the reference trim range 605. The cumulative failures of these read operations may correspond to the failure edge points 626. The automated bit line resistance search process may utilize the magnitude of the failure edge points 626 to determine the shift direction of the read characteristics of the magnetoresistive memory device for subsequent read operations. In this example, due to the relative magnitudes of the cumulative failures, the automated bit line resistance search process should shift the read characteristics of the magnetoresistive memory device to a higher reference resistance value. In some embodiments, bits in the trim range value may be set based on the magnitudes of the two failure edge points 626. For example, the magnitudes of the two failure edge points 626 may be used to determine the differential failure bit count between the cumulative read zero failures 624 and the cumulative read one failures 623 at the failure edge point 626. When the differential failure bit count has a value corresponding to a higher number of read zero failures at the failure edge point 626, in some embodiments, the most significant unset bit in the reference trim range value may be set to "1". When the differential failure bit count has a value corresponding to a lower number of read zero failures at the failure edge point 626, in some embodiments, the most significant unset bit in the reference trim range value may be set to "0". In some embodiments, the remaining unset bits in the reference trim value may be set to zero, which may shift the reference trim range 605 in the determined direction.

[0065] Reference Figure 6D, the graph 630 has an x-axis corresponding to the reference resistance 602 used by the magnetoresistive memory device during a read operation, and a y-axis corresponding to the cumulative failures 601 of the read operations using various reference resistances 602. The reference resistance 602 may include a reference trim range 605, which corresponds to a set of reference resistances 602 available for the magnetoresistive memory device during a read operation. The magnetoresistive memory device may utilize a reference trim value to select one of the reference resistances 602 within the reference trim range 605 for use during a read operation.

[0066] In this example, the graph 630 shows a read zero failure 634 and a read one failure 633, which have been shifted from Figure 6C the read zero failure 624 and the read one failure 623 therein, respectively. The read zero failure 634 may correspond to multiple cumulative failures where the memory device cannot correctly read the data value "0" using various reference resistances. The read one failure 633 may correspond to multiple cumulative failures where the memory device cannot correctly read the data value "1" using various reference resistances.

[0067] During an automated bit line resistance search process, the magnetoresistive memory device may read the data value "0" using a reference trim value at the lower edge of the reference trim range 605, and may read the data value "1" using a reference trim value at the upper edge of the reference trim range 605. The cumulative failures of these read operations may correspond to the failure edge points 636. The automated bit line resistance search process may utilize the magnitude of the failure edge points 636 to determine the shift direction of the read characteristics of the magnetoresistive memory device for subsequent read operations. In this example, the automated bit line resistance search process determines that the read characteristics of the magnetoresistive memory device are shifted higher than the effective bit line resistance value previously performed with respect to Figure 6C so the automated bit line resistance search process may set the read characteristics of the magnetoresistive memory device to Figure 6C or Figure 6D the read characteristics used in. In some embodiments, bits in the trim range value may be set based on the magnitudes of the two failure edge points 636. For example, the magnitudes of the two failure edge points 636 may be used to determine the differential failure bit count between the cumulative read zero failures 634 and the cumulative read one failures 633 at the failure edge point 636. When the differential failure bit count has a value corresponding to a higher number of read zero failures at the failure edge point 636, in some embodiments, the most significant unset bit in the reference trim range value may be set to "1". When the differential failure bit count has a value corresponding to a lower number of read zero failures at the failure edge point 636, in some embodiments, the most significant unset bit in the reference trim range value may be set to "0". In some embodiments, the remaining unset bits in the reference trim value may be set to zero, which may shift the reference trim range 605 in the determined direction. Refer toFigures 6A to 6D The described process may continue until all bits in the reference trim range value have been set. Although Figures 6A to 6D a memory read operation performed using a reference resistor is described, in some embodiments, a reference voltage or a reference current may be used to perform the memory read operation.

[0068] Returning to Figure 1 , after the built-in self-test interface 120 has determined the value of the trim range signal 106, the built-in self-test interface 120 may initiate an automated feedback process to identify the setting of the reference trim value within the trim range. The built-in self-test interface 120 may include a trim feedback circuit 124 that performs the automated feedback process by iteratively setting the reference trim signal 105 with different values and using the failure events detected by the built-in self-test interface 120 to identify the setting of the reference trim value within the trim range.

[0069] The trim setting unit 112 and the trim feedback circuit 124 may iterate the process of selecting a reference trim value and reading test data from the memory until the trim feedback circuit 124 identifies a reference trim setting for the test data type. In some embodiments, the trim feedback circuit 124 may identify multiple reference trim settings, e.g., one for each data type, such as a low data value and a high data value. The trim feedback circuit 124 may use the identified reference trim setting for the test data type (e.g., an aggregated reference trim setting) to set the value of the reference trim. Embodiments of the automated feedback process will be described in more detail below.

[0070] Figure 7 FIG. illustrates an example implementation of an automated trim feedback process according to various embodiments. Referring to Figure 7 , at block 701, the memory built-in self-test system may provide test data having a common data type to the storage device and prompt the storage device to store the test data. The memory built-in self-test system may write the test data to the storage device by generating a control signal that prompts the storage device to perform a data write operation using the test data. In some embodiments, the memory built-in self-test system may write the same data value (e.g., all data “1” values or all data “0” values) to the storage cells in the storage device.

[0071] At block 702, a memory built-in self-test system may provide test reference fine-tuning to a storage device for use during a memory read operation. The memory built-in self-test system may be in a test start mode or a test boundary mode. In the test start mode, the memory built-in self-test system may set the test reference fine-tuning value to the highest setting or the lowest setting based on the common data type stored in the storage device at block 701. For example, when the common data type corresponds to data level "0", the memory built-in self-test system may set the test reference fine-tuning value to the highest setting. Conversely, when the common data type corresponds to data level "1", the memory built-in self-test system may set the test reference fine-tuning value to the lowest setting.

[0072] In the test boundary mode, the memory built-in self-test system may select the value of the test reference fine-tuning based on a binary search process. In some embodiments, the memory built-in self-test system may use different techniques or search methods to select the test reference fine-tuning value.

[0073] At block 703, the memory built-in self-test system may prompt the storage device to read stored test data from the memory using the test reference fine-tuning. The memory built-in self-test system may generate a control signal that is used to prompt the storage device to perform a data read operation. In response to the control signal, the storage device may sense the stored test data and compare the sensed data with a reference value to determine the value of the stored test data. In some embodiments, the reference value may correspond to an initial reference value of the storage device that has been adjusted based on the test reference fine-tuning.

[0074] At block 704, the memory built-in self-test system may identify a failure event where the storage device cannot correctly read the stored data using the test reference fine-tuning. The memory built-in self-test system may compare the data read from the storage device with the common data type of the stored data to determine whether the storage device correctly reads the stored data using the test reference fine-tuning.

[0075] In the test start mode, the memory built-in self-test system may accumulate the failure events where the storage device cannot correctly read the stored data using the test reference fine-tuning and store it as a hard failure count for the common data type set at block 701. The execution may return to block 702, where the memory built-in self-test system may switch to the test boundary mode and select the test reference fine-tuning to be provided to the storage device.

[0076] In a test boundary mode, a memory built-in self-test system can accumulate failure events in which a memory device cannot correctly read stored data using a test reference trim, and then compare the accumulated failures with a baseline failure count (e.g., a read zero failure count at a maximum reference trim setting or a read one failure count at a minimum reference trim setting). By comparing the accumulated failures with the baseline failure count, the memory built-in self-test system can avoid the influence of hard failures on setting the reference trim value. In some embodiments, the memory built-in self-test system can also accumulate failures and then compare the accumulated failures with a failure screening threshold to determine a failure result. In some examples, the failure result can be used to set at least a portion of a reference trim for a common data type. By comparing the accumulated failures with the failure screening threshold, the memory built-in self-test system can avoid the influence of low statistical weak bit storage effects and can determine a setting of a reference trim with a wider read margin. In some embodiments, in the test boundary mode, the memory built-in self-test system can use the result of the comparison to set a bit of a boundary reference trim value for a common data type.

[0077] In block 705, the memory built-in self-test system can determine whether to perform an automated trim feedback process using at least one additional test reference trim. In some embodiments, the search process can include a specific number of iterative searches, where each search uses a new test reference trim that is partially based on the failure result of a previous search. When the memory built-in self-test system has partially set a bit of a boundary reference trim value for a common data type in block 704, the memory built-in self-test system can determine in block 705 whether to perform another search when the boundary reference trim value has not been fully set. When another search is to be performed using at least one additional test reference trim, the execution can return to block 702; otherwise, the execution can proceed to block 706.

[0078] In block 706, the memory built-in self-test system can determine whether to perform an automated trim feedback process using an additional test data type. In some embodiments, the memory built-in self-test system can perform an automated trim feedback process using multiple different data types (e.g., values "0" and "1") and possibly one or more other data types. When another search is to be performed using at least one additional data type, the execution can return to block 701; otherwise, the execution can proceed to block 707. When the execution returns to block 701, the memory built-in self-test system can switch from the test boundary mode to the test start mode to store a new test data type into the memory device.

[0079] At block 707, the memory built-in self-test system may set the reference trim of the storage device using test reference trim based on the identified failures. The memory built-in self-test system may set the reference trim by leveraging the failure results identified at block 704 (e.g., to use the failure margin reference trim values for each data type) and then aggregating or averaging the failure margin reference trim for each data type into a final reference trim value. In some embodiments, the memory built-in self-test system may provide the final reference trim value to the storage device for subsequent memory read operations.

[0080] Figure 8A A graph illustrating example storage device failures at different sense reference values in accordance with various embodiments is provided. Refer Figure 8A , graph 800 has an x-axis corresponding to a reference resistance 802 used by a magnetoresistive storage device during a read operation and a y-axis corresponding to an accumulated failure 801 of the read operations using various reference resistances 802. The range of the reference resistance 802 may be between a minimum trim value 806 and a maximum trim value 807, which correspond to the lowest value and the highest value of the reference trim, respectively.

[0081] In this example, the magnetoresistive storage device may have an array of memory cells, one or more of which may fail regardless of the value of the reference trim. For example, when one or more failures in the magnetoresistive storage device correspond to a read zero failure, the accumulated failure 801 may not reach zero at the maximum trim value 807. In some embodiments, the accumulated failure 801 at the maximum trim value 807 may correspond to a baseline read zero failure count that exists regardless of the reference trim value. Since the read zero failure at the maximum trim value 807 may correspond to the lowest level of read zero failure regardless of the reference trim value, the accumulated failure 801 at the maximum trim value 807 may not be considered when setting the reference trim value based on the read zero failure.

[0082] When one or more failures in the magnetoresistive storage device correspond to a read one failure, the accumulated failure 801 may not reach zero at the minimum trim value 806. In some embodiments, the accumulated failure 801 at the minimum trim value 806 may correspond to a baseline read one failure count that exists regardless of the reference trim value. Since the read one failure at the minimum trim value 806 may correspond to the lowest level of read zero failure regardless of the reference trim value, the accumulated failure 801 at the minimum trim value 806 may not be considered when setting the reference trim value based on the read one failure.

[0083] In this example, the graph 800 shows read zero failures 804 and read one failures 803. The read zero failures 804 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistors. The read zero failures 804 show a high number of failures when the reference trim is closer to the minimum trim value 806 and a low number of failures when the reference trim is closer to the maximum trim value 807. The read one failures 803 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistors. The read one failures 803 show a lower number of failures when the reference trim is closer to the minimum trim value 806 and a higher number of failures when the reference trim is closer to the maximum trim value 807.

[0084] The following references Figure 8B describe an example of automated trim value search using a failure tail. In some embodiments, the trim feedback circuit 300 may use a failure cliff as a failure threshold 302 to perform an automated trim value search. The following references Figure 8C describe an example of automated trim value search using a failure cliff.

[0085] Figure 8B and Figure 8C illustrate graphs of example trim reference selection results using different failure thresholds according to various embodiments. Referring to Figure 8B , the graph 810 has an x-axis corresponding to the reference resistors 812 used by the magnetoresistive storage device during a read operation and a y-axis corresponding to the cumulative failures 811 of the read operations using the various reference resistors 812. The reference resistors 812 may correspond to an initial reference resistor combined with various reference trim values.

[0086] In this example, the graph 810 shows read zero failures 814 and read one failures 813. The read zero failures 814 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistors. The read zero failures 814 show a high number of failures when closer to a smaller reference trim value and a low number of failures when closer to a larger reference trim value. The read one failures 813 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistors. The read one failures 813 show a low number of failures when closer to a smaller reference trim value and a high number of failures when closer to a larger reference trim value.

[0087] Using Figure 8B the failure tail shown, the trim feedback circuit performing an automated trim value search may set the failure threshold 816 to the failure tail corresponding to the low-level failures of the read zero failures 814 and the read one failures 813. In some embodiments, the read zero failures 814 may be Figure 8AThe difference between the cumulative read zero failures 804 at the different reference resistors 802 shown and Figure 8A the cumulative read zero failures 804 at the maximum trim value 807 shown. A read one failure 813 can be Figure 8A the difference between the cumulative read one failures 803 at the different reference resistors 802 shown and Figure 8A the cumulative read one failures 803 at the minimum trim value 806 shown. In some embodiments, the trim feedback circuit can determine a failure bit count (e.g., providing a small number of bit failures) when reading the data value "0" from the storage device using the maximum reference trim, and set the failure threshold 816 for the data value "0" to the failure bit count. The trim feedback circuit can also determine a failure bit count (e.g., providing a small number of bit failures) when reading the data value "1" from the storage device using the minimum reference trim, and set the failure threshold 816 for the data value "1" to the failure bit count. The trim feedback circuit can perform an automated search for the final trim value 815 using the failure threshold 816.

[0088] Refer to Figure 8C , the graph 820 has an x-axis corresponding to the reference resistors 822 used by the magnetoresistive storage device during a read operation, and a y-axis corresponding to the cumulative failures 821 of the read operations using the various reference resistors 822. The reference resistors 822 can correspond to the initial reference resistor combined with various reference trim values.

[0089] In this example, the graph 820 shows the read zero failures 824 and the read one failures 823. The read zero failures 824 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using the various reference resistors. The read zero failures 824 show a high number of failures when closer to the smaller reference trim values and a low number of failures when closer to the larger reference trim values. The read one failures 823 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using the various reference resistors. The read one failures 823 show a low number of failures when closer to the smaller reference trim values and a high number of failures when closer to the larger reference trim values.

[0090] The trim feedback circuit can use Figure 8CImplement automated fine-tuning value search using the failure cliff shown. For example, in the case where a failure count is read and zero failure counts are read exceeding the failure threshold 826, the fine-tuning feedback circuit can perform an automated search to identify the boundary fine-tuning value. The failure threshold 826 can correspond to a level of failure that can be repaired, for example, using redundant row-based repair and / or redundant column-based repair, or a level of failure that can be corrected, for example, using read data correction utilizing an error correction control (ECC) process. In some embodiments, the failure threshold 826 can be set by the fine-tuning feedback circuit, for example, in response to user input. The fine-tuning feedback circuit can utilize the boundary fine-tuning value to select the final fine-tuning value 825 of the magnetoresistive storage device. The final fine-tuning value 825 can be different from Figure 8B the final fine-tuning value 815 shown. Figure 8B The final fine-tuning value 815 in can correspond to the common low point of zero read failures 814 and one read failure 813, while the final fine-tuning value 825 can have a greater margin 827 from the intersection of the failure threshold 826 with zero read failures 824 and one read failure 823. Although Figures 8A to 8C memory read operations performed using a reference resistor are described, in some embodiments, memory read operations can be performed using a reference voltage or a reference current.

[0091] The systems and devices described above can use a dedicated processor system, a microcontroller, a programmable logic device, a microprocessor, or any combination thereof to perform some or all of the operations described herein. Some of the operations described above can be implemented in software, while other operations can be implemented in hardware. Any of the operations, processes, and / or methods described herein can be performed by a device, apparatus, and / or system that is substantially similar to the devices, apparatuses, and / or systems described herein and with reference to the illustrated figures.

[0092] The processing device can execute instructions or "code" stored in the memory. The memory can also store data. The processing device can include, but is not limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc. The processing device can be part of an integrated control system or a system manager, or can be provided as a portable electronic device configured to dock locally or remotely with a networked system via wireless transmission.

[0093] Processor memory can be integrated with the processing device, for example, RAM or flash memory arranged in an integrated circuit microprocessor, etc. In other examples, the memory can include independent devices, such as external disk drives, storage arrays, portable flash key cards, etc. The memory and the processing device can be operably coupled together or communicate with each other, such as through I / O ports, network connections, etc., and the processing device can read files stored on the memory. Depending on the permission settings, the associated memory can be "read-only" (ROM) or not by design. Other examples of memory can include, but are not limited to, WORM, EPROM, EEPROM, flash memory, etc., which can be implemented in solid-state semiconductor devices. Other memories can include moving parts, such as known rotating disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0094] The operating instructions or commands may be implemented or embodied in a tangible form of stored computer software (also referred to as a "computer program" or "code"). The program or code may be stored in a digital memory and may be read by a processing device. "Computer-readable storage media" (or alternatively, "machine-readable storage media") may include all of the aforementioned types of memory as well as new technologies of the future, as long as the memory may be able to store digital information having the properties of a computer program or other data at least temporarily, and as long as the stored information can be "read" by an appropriate processing device. The term "computer-readable" may not be limited to the historical use of "computer" to imply a complete mainframe, minicomputer, desktop or even laptop computer. On the contrary, "computer-readable" may include storage media that can be read by a processor, a processing device, or any computing system. Such a medium may be any available medium that can be accessed locally and / or remotely by a computer or processor, and may include volatile and non-volatile media, removable and non-removable media, or any combination thereof.

[0095] Programs stored in computer-readable storage media may include computer program products. For example, storage media may be used as a convenient means for storing or transmitting computer programs. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams can be equivalently aggregated into a single logical device, program or operation without clear boundaries.

[0096] in conclusion

[0097] Although this application describes specific examples of implementing embodiments of the present invention, those skilled in the art should understand that there are many variations and permutations of the above systems and techniques that fall within the spirit and scope of the present invention as set forth in the appended claims. For example, although specific terms have been used above to refer to electronic design automation processes, it should be understood that any desired combination of electronic design automation processes can be used to implement various examples of the present invention.

[0098] Those skilled in the art will also recognize that the concepts taught herein can be adapted to suit a particular application in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are only one of many alternative embodiments that will become apparent upon reading this disclosure.

[0099] Although the specification may refer to "one," "a," "another," or "some" examples in several places, this does not necessarily mean that each such reference is to the same one or more examples or that a feature should apply only to a single example.

Claims

1. A system, comprising: A storage device configured to sense a value of stored data using reference trimming during a memory read operation; And A memory built-in self-test system configured to prompt the storage device to perform a plurality of the memory read operations using different positions of an available value range of the reference trimming relative to a read characteristic of the storage device and using a plurality of values of the reference trimming within the range, and wherein the memory built-in self-test system is configured to set a position of the available value range of the reference trimming relative to the read characteristic of the storage device at least in part based on a failure event that the storage device fails to correctly sense the stored data during the memory read operation using the different positions of the available value range for the reference trimming, and wherein the memory built-in self-test system is further configured to set the reference trimming of the storage device within the available value range of the reference trimming having the position set by the memory built-in self-test system.

2. The system according to claim 1, wherein The memory built-in self-test system is configured to perform the plurality of memory read operations by iteratively shifting the available value range of the reference trimming relative to the read characteristic of the storage device.

3. The system according to claim 2, wherein, The memory built-in self-test system is configured to iteratively shift the available value range of the reference trimming at least in part based on a relative magnitude of memory read failures of the storage device using values of the reference trimming at boundaries of the available value range of the reference trimming.

4. The system according to claim 1, wherein, The memory built-in self-test system is configured to perform the plurality of memory read and write operations by iteratively shifting the read characteristic of the storage device relative to the available value range of the reference trimming.

5. The system according to claim 4, wherein, The memory built-in self-test system is configured to iteratively shift the read characteristic of the storage device at least in part based on a relative magnitude of memory read failures of the storage device using values of the reference trimming at boundaries of the available value range of the reference trimming.

6. The system according to claim 1, wherein, The storage device is a magnetoresistive random access memory (MRAM) device.

7. A method, comprising: Prompting, by a memory built-in self-test system, a storage device to perform a plurality of memory read operations using different positions of a reference trimming range relative to a read characteristic of the storage device and using a plurality of values of a reference trimming within the reference trimming range, wherein the reference trimming range corresponds to an available value range of the reference trimming; Determining, by the memory built-in self-test system, when the storage device fails to correctly sense a value of stored data using a test value of the reference trimming within the different positions of the reference trimming range; Setting, by the memory built-in self-test system, a position of the reference trimming range relative to the read characteristic of the storage device at least in part based on a failure event that the storage device fails to correctly sense the stored data during the memory read operation using the different positions of the reference trimming range; and The reference trim of the storage device is set within the reference trim range having a position set by the memory built-in self-test system through the memory built-in self-test system.

8. The method according to claim 7, wherein Prompting the storage device to perform the plurality of memory read operations includes: iteratively shifting the reference trim range relative to the read characteristics of the storage device.

9. The method according to claim 8, wherein, The iteratively shifting the reference trim range relative to the read characteristics of the storage device is at least partially based on the relative magnitudes of memory read failures of the storage device using the values of the reference trim at the boundaries of the available value range of the reference trim.

10. The method according to claim 7, wherein Prompting the storage device to perform the plurality of memory read and write operations includes: iteratively shifting the read characteristics of the storage device relative to the reference trim range.

11. The method according to claim 10, wherein The iteratively shifting the read characteristics of the storage device relative to the reference trim range is at least partially based on the relative magnitudes of memory read failures of the storage device using the values of the reference trim at the boundaries of the available value range of the reference trim.

12. The method according to claim 7, wherein The storage device is a magnetoresistive random access memory (MRAM) device.

13. An apparatus, comprising: A memory built-in self-test controller configured to prompt a storage device to perform memory read operations using a plurality of values of a reference trim within a reference trim range at different positions relative to the read characteristics of the storage device, wherein the reference trim range corresponds to an available value range of the reference trim, and wherein the storage device is configured to sense a value of stored data using the reference trim during the memory read operations; and A trim range circuit configured to determine when the storage device cannot correctly sense the value of the stored data using a test value of the reference trim, and to set a position of the reference trim range relative to the read characteristics of the storage device at least partially based on a failure event that the storage device fails to correctly sense the stored data during the memory read operations using the different positions for the reference trim range, and wherein the apparatus further includes a trim feedback circuit configured to set the reference trim of the storage device within the reference trim range having the position set by the trim range circuit.

14. The apparatus according to claim 13, wherein, The memory built-in self-test controller is configured to iteratively shift the reference trim range relative to the read characteristics of the storage device for the memory read operations.

15. The apparatus according to claim 14, wherein, The memory built-in self-test controller is configured to iteratively shift the reference trim range at least partially based on the relative magnitudes of memory read failures of the storage device using the values of the reference trim at the boundaries of the available value range of the reference trim.

16. The apparatus according to claim 13, wherein, The memory built-in self-test controller is configured to iteratively shift the read characteristics of the storage device relative to the reference trim range.

17. The apparatus according to claim 16, wherein, The memory built-in self-test controller is configured to iteratively shift the read characteristics of the memory device based at least in part on a relative magnitude of a memory read failure of the memory device using a value of the reference fine-tuning at a boundary of the available value range of the reference fine-tuning.

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