Charge sensitive amplifier circuit for a sensor front end

Abstract

A charge sensitive amplifier circuit (1) for a sensor front end comprises an input node (I) connected to a sensor (2) to receive input charge and an output node (O) connected to a charge conversion circuit (3). The charge sensitive amplifier circuit (1) comprises a first transfer switch (10) between the input node (I) and the output node (O) to transfer the input charge to the output node (O). The charge sensitive amplifier circuit (1) further comprises a second transfer switch (20) in parallel with the first transfer switch (10) between the input node (I) and the output node (O) to transfer the input charge to the output node (O).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a charge sensitive amplifier circuit for a sensor front-end, e.g. of an optical sensor, to transfer charges generated by a photosensitive cell of the optical sensor to a charge-to-voltage conversion stage. BACKGROUND

[0002] In line sensors with a large number of pixels and serial readout, photosensitive cells, e.g. photodiodes, are connected in series to a line to read out charges generated in the respective photosensitive cell by the incidence of light. The charges generated from the photodiodes during the exposure time are applied through the line to a charge sensitive amplifier to transfer the charges to a conversion stage, e.g. a charge-to-voltage conversion stage. The transfer of the charges has to be completed within a defined transfer time (readout time) before the next pixel / photosensitive cell is connected through the line to the input node of the charge sensitive amplifier to transfer the charges generated in the photosensitive cell to the charge conversion stage.

[0003] The line sensor input stage including the charge sensitive amplifier requires a high stability accuracy within the short transfer time, which requires a wide average bandwidth of the input stage and the charge sensitive amplifier. On the other hand, the noise of the input stage is optimized at low bandwidth at the end of the integration phase where the charges are integrated. Furthermore, the charge sensitive amplifier for the sensor front-end requires a high dynamic range. This requirement is also in contrast to the requirement to optimize the input stage noise with as low charge sensitive amplifier bandwidth as possible.

[0004] The charge sensitive amplifier can include a single transistor switch to transfer the input charges generated by the photodiode / photosensitive cell to the charge conversion stage. The single transistor switch can be controlled such that the bandwidth is large at the beginning of the integration and is reduced at the end of the charge transfer. This can be achieved by using a high ohmic and a low ohmic phase for the switch during the charge transfer. It can also be done dynamically. Depending on the charge at the input, the transfer time will be longer or shorter at the low ohmic phase and the transistor switch will become more and more high ohmic during the charge removal.

[0005] In line sensors, each input stage is connected to a row of pixels, some of which can be defective and others not. If the charge sensitive amplifier of the input stage does not remove a large amount of charge, these charges will appear as image artifacts on the subsequent pixels. The input charge can vary over decades, because not only the charge of the signal has to be removed by the charge sensitive amplifier of the input stage, but also the excess charge from the defective pixels has to be removed.

[0006] Due to the high dynamic range of the input charge applied at the input node of the charge sensitive amplifier at the input stage, the single transistor switch included in the charge sensitive amplifier for transferring the charge generated by the photodiode to the charge conversion stage is not the optimal solution because too much bandwidth is needed to remove all the charge during the transfer phase and the low noise requirement is still met at the end of the charge transfer.

[0007] It is desirable to provide a charge sensitive amplifier circuit for a sensor front-end that allows optimizing the noise of the sensor front-end without limiting the charge input range. SUMMARY

[0008] A charge sensitive amplifier circuit for a sensor front-end is specified in claim 1 that has a high dynamic input charge range within a defined transfer time without compromising the noise of the input stage.

[0009] According to an embodiment of a charge sensitive amplifier circuit for a sensor front-end, the charge sensitive amplifier circuit comprises an input node connected to a sensor to receive an input charge and an output node connected to a charge conversion circuit. The charge sensitive amplifier circuit further comprises a first transfer switch between the input node and the output node for transferring the input charge to the output node and a second transfer switch in parallel to the first transfer switch between the input node and the output node for transferring the input charge to the output node.

[0010] Instead of using a single transfer switch / transfer gate, a first transfer switch / transfer gate and at least a second transfer switch / transfer gate are implemented in the charge sensitive amplifier circuit. Both transistor switches have a dynamic control to reduce the bandwidth at the end of the charge integration.

[0011] The first transfer switch is controlled such that the bandwidth is large at the beginning of the integration and is reduced by switching the first transfer switch almost off, i.e. by operating the first transfer switch with a low conductance, at the end of the charge transfer. At the end of the charge transfer, the first transfer switch is advantageously not completely switched off, i.e. is not operated in a fully non-conducting state.

[0012] According to a possible embodiment of the charge sensitive amplifier circuit, only the first transfer switch is switched on, i.e. is operated in a high conducting state, during a small charge transfer, whereas during a large charge transfer, both the first transfer switch and the second transfer switch are switched on at the beginning of the integration / charge transfer time, but only the first transfer switch completes the charge output to the output node. The second transfer switch is only switched on if a large input charge has to be removed at the beginning of the integration / charge transfer time.

[0013] According to another possible embodiment, at the end of the charge transfer / end of the charge transfer time, the second transfer switch is turned off before the first transfer switch is almost turned off. Due to the last closing of the first transfer switch, the bandwidth limitation at the end of integration is still driven by the first transfer switch which does not need a high bandwidth.

[0014] Thus, the proposed configuration of the charge sensitive amplifier circuit makes it possible to reduce the noise without reducing the input charge range. The proposed charge sensitive amplifier circuit has a variable bandwidth and is able to overcome the contradiction between, on the one hand, the need for a wide average bandwidth to require a high stability precision of the input stage and, on the other hand, the requirement of a low bandwidth to reduce the noise of the input stage. The proposed circuit configuration is suitable for integrated circuits.

[0015] Additional features and advantages are set forth in the detailed description. It should be understood that the general description and the following detailed description are merely exemplary and are intended to provide a general overview or framework for understanding the nature and character of the claims. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding and are incorporated in and constitute a part of the specification. Thus, the disclosure will be further understood with reference to the following detailed description and drawings, in which:

[0017] Figure 1 Embodiments of an image sensor circuit comprising a charge sensitive amplifier circuit for a sensor front-end are shown, which has a high dynamic input charge range while reducing the noise of the circuit; and

[0018] Figure 2 Respective control signals for controlling the first transfer switch and the second transfer switch of the charge sensitive amplifier circuit are shown. DETAILED DESCRIPTION

[0019] Figure 1 Embodiments of an image sensor circuit 100 are shown, which comprises a charge sensitive amplifier circuit 1 for a sensor front-end, a sensor 2 and a charge conversion circuit 3. The charge conversion circuit 3 can be implemented as a charge-to-voltage conversion circuit, a charge-to-current conversion circuit, a charge-to-digital conversion circuit, etc.

[0020] The charge sensitive amplifier circuit 1 comprises an input node I connected to the sensor 2 to receive input charges from the sensor 2, and an output node O connected to the charge conversion circuit 3. The charge sensitive amplifier circuit 1 further comprises a first transfer switch 10 between the input node I and the output node O for transferring input charges received from the sensor 2 to the output node O. In addition, the charge sensitive amplifier circuit 1 comprises at least one second transfer switch 2 in parallel to the first transfer switch 10 between the input node I and the output node O for transferring input charges to the output node O. The input node I of the charge sensitive amplifier circuit 1 is connected to the sensor 2, and the output node O of the charge sensitive amplifier circuit 1 is connected to the charge conversion circuit 2.

[0021] The sensor 2 can be configured as an optical sensor comprising a plurality of light sensitive cells D1 which can be configured as photodiodes. Each light sensitive cell D1 can be connected via a respective controllable switch to a line for reading out the charges generated by the respective photodiode during an exposure time. The lines to which the light sensitive cells are connected for reading out their charges are denoted by line capacitances CLINE in Figure 1 The optical sensor 2 can be controlled such that the light sensitive cells D1 are read out sequentially and the respective charges of the light sensitive cells D1 are applied to the input node I of the charge sensitive amplifier circuit 1 to be transferred by the charge sensitive amplifier circuit 1 to the charge conversion circuit 3.

[0022] According to another possible embodiment, the sensor 3 can be configured as a capacitive sensor comprising a plurality of capacitive sensor cells. The capacitive sensor is controlled such that the capacitive cells are read out sequentially and the respective charges of the capacitive cells are applied to the input node I of the charge sensitive amplifier circuit 10 to be transferred to the charge conversion circuit 3.

[0023] According to an embodiment of the charge sensitive amplifier circuit 1, the input charges received by the charge sensitive amplifier circuit 1 at the input node I are transferred by the transfer switches 10 and 20 to the output node O and thus to the charge conversion circuit 3. The first transfer switch 10 and the second transfer switch 20 are controlled such that the charge transfer of the charges generated from one of the photodiodes D1 and applied to the input node I is completed within a defined transfer time / line time before the next pixel / light sensitive cell is connected via a line to the input node I of the charge sensitive amplifier circuit 1.

[0024] The charge sensitive amplifier circuit 1 comprises a control circuit 30 for generating respective control signals CS1, CS2 for controlling the respective conductivities of the first transfer switch 10 and the second transfer switch 20. The control circuit 30 is configured to generate the control signal CS1 for controlling the first transfer switch 10 during the transfer time of the first transfer switch and the control signal CS2 for controlling the second transfer switch 20 during the transfer time of the second transfer switch for transferring the input charge from the input node I to the output node O by the transfer switches 10 and 20.

[0025] The control circuit 30 is configured to generate the control signal CS1 for controlling the first transfer switch 10 and the control signal CS2 for controlling the second transfer switch 20 such that the respective first transfer switch 10 and the second transfer switch 20 are operated in a time-dependent operating state during the respective transfer time of the first transfer switch 10 and the second transfer switch 20.

[0026] According to a possible embodiment of the charge sensitive amplifier circuit, the control circuit 30 is configured to generate the respective control signals CS1, CS2 for controlling the first transfer switch 10 and the second transfer switch 20 such that the respective conductivities of the first transfer switch 10 and the second transfer switch 20 are higher at the beginning of the respective transfer time of the first transfer switch 10 and the second transfer switch 20 than at the end phase of the respective transfer time of the first transfer switch 10 and the second transfer switch 20.

[0027] According to a possible embodiment of the charge sensitive amplifier circuit, the control circuit 30 is configured to generate the respective control signals CS1, CS2 for controlling the first transfer switch 10 and the second transfer switch 20 such that the respective conductivities of the first transfer switch 10 and the second transfer switch 20 continuously decrease from the beginning of the respective transfer time of the first transfer switch 10 and the second transfer switch 20 until the end phase of the respective transfer time of the first transfer switch 10 and the second transfer switch 20.

[0028] According to an embodiment of the charge sensitive amplifier circuit 1, at the beginning of the respective transfer time of the first transfer switch 10 and the second transfer switch 20, the conductivity of the second transistor 20 is higher than the conductivity of the first transistor 10, although both transfer switches are operated in the on state. This is achieved by configuring the first transfer switch 10 as a high-ohmic switch and the second transfer switch 20 as a low-ohmic switch. The first transfer switch shows a lower conductivity at the beginning of the transfer time than the second transfer switch.

[0029] According to a possible embodiment of the charge sensitive amplifier circuit 1, at the end of the respective transfer times of the first and second transfer switches 10, 20, the conductivity of the second transfer switch 20 is lower than the conductivity of the first transfer switch 10. In particular, at the end phase of the transfer time of the second transfer switch, the second transfer switch 20 is completely off, i.e. operates in a non-conductive state, and at the end phase of the transfer time of the first transfer switch, the first transfer switch 10 is almost off, i.e. still operates in a low conductive state. This configuration ensures that the first transfer switch 10 is never completely off, especially at the end phase of the transfer time of the first transfer switch, to prevent the input node I from becoming negative and to block the charge conversion of the next pixel.

[0030] According to an embodiment of the charge sensitive amplifier circuit 1, the first and second transfer switches 10, 20 are configured such that the respective conductivities of the first and second transfer switches 10, 20 depend on whether the level of the respective control signal CS1, CS2 is higher or lower than a respective threshold voltage of the first and second transfer switches 10, 20.

[0031] The first and second transfer switches 10, 20 can have the same threshold voltage. In this case, the control circuit 30 can be configured to generate the control signal CS1 for controlling the first transfer switch 10 with another level than the control signal CS2 for controlling the second transfer switch 20. In particular, the control circuit 30 generates the respective levels of the first and second control signals CS1, CS2 such that at the end phase of the respective transfer times of the first and second transfer switches 10, 20, the conductivity of the first transfer switch 10 is higher than the conductivity of the second transfer switch 20 to ensure that the first transfer switch 10 does not completely turn off at the end of the transfer time.

[0032] Figure 2 The possibility is shown that the control signal CS1 is generated by the control circuit 30 for controlling the conductivity of the first transfer switch 10 during the transfer time and that the control signal CS2 is generated by the control circuit 30 for controlling the conductivity of the second transfer switch 20, assuming that the first and second transfer switches 10, 20 have the same threshold voltage.

[0033] As Figure 2 shown, the control circuit 30 generates the respective control signals CS1 and CS2 for controlling the first and second transfer switches 10, 20 such that the minimum and maximum levels of the control signal CS1 for controlling the first transfer switch 10 generated during the transfer time of the first transfer switch are higher than the minimum and maximum levels of the control signal CS2 for controlling the second transfer switch 20.

[0034] Figure 2It is shown that during the respective transfer time of the first and second transfer switch, the process of generating the control signal CS1 is at a higher level than the process of the control signal CS2. The threshold levels of the first and second transfer switch are indicated in Figure 2 by horizontal dashed lines. With regard to the embodiment shown, the first and second transfer switch have the same threshold voltage. Figure 2

[0035] When the respective control signals CS1 and CS2 have their maximum levels, the first transfer switch 10 and the second transfer switch 20 are on, i.e. operate in the on state. On the other hand, when the respective control signals CS1 and CS2 have their respective minimum levels, the first transfer switch 10 operates in the low on state and the second transfer switch 20 operates in the on state with a conductivity lower than the conductivity of the first transfer switch or in the off state / non-conducting state.

[0036] As shown in Figure 2 the minimum level of the control signal CS2 is lower than the minimum level of the control signal CS1. The minimum level of the control signal CS1 is equal to the threshold voltage of the first transfer switch 10, which enables the first transfer switch 10 to operate in the low on state at the end phase of the transfer time of the first transfer switch. However, since the control signal CS1 is generated by the control circuit 30 at a level not lower than the threshold voltage of the first transfer switch 10, it is ensured that the first transfer switch 10 does not completely turn off at the end of the transfer time. This allows to prevent the input node I of the charge sensitive amplifier circuit to become negative and to block the charge transfer of the next pixel.

[0037] As mentioned above, the first and second transfer switch 10, 20 are configured such that the conductivity of the second transfer switch 20 is higher than the conductivity of the first transfer switch 10, even at the beginning of the transfer time of the second transfer switch 20, where the maximum value of the control signal CS2 for controlling the second transfer switch 20 is lower than the maximum level of the control signal CS1 for controlling the first transfer switch 10 at the beginning of the transfer time of the first transfer switch 10.

[0038] In order to provide the first transfer switch 10 with a lower conductivity than the second transfer switch 20 at the beginning of the transfer time, i.e. as a high ohmic transfer switch, and the second transfer switch 20 with a higher conductivity than the first transfer switch 10 at the beginning of the transfer time, i.e. as a low ohmic transfer switch, the geometry, in particular the relation of the length and width of the respective conduction channels of the transfer switches 10 and 20, has to be chosen in an appropriate way.

[0039] ​According to another possible embodiment of the charge-sensitive amplifier circuit 1, the control circuit 30 is configured to generate a control signal CS1 for controlling the conductivity of the first transfer switch 10, which has the same level as the control signal CS2 for controlling the conductivity of the second transfer switch 20. In this case, it must be ensured that the threshold voltage of the first transfer switch 10 is different from the threshold voltage of the second transfer switch 20 in order to provide the second transfer switch 20 with a higher conductivity than the first transfer switch 10; that is, the transfer switch 10 is set as a high-ohm switch and the transfer switch 20 is set as a low-ohm switch.

[0040] According to another possible embodiment, the first transfer switch 10 and the second transfer switch 20 can be implemented such that the first bulk bias voltage applied to the first transfer switch 10 is different from the second bulk bias voltage applied to the second transfer switch 20. In this case, the control circuit 30 can also be configured to generate a control signal CS1 for controlling the first transfer switch 10, which has the same level as the control signal CS2 for controlling the second transfer switch 20, but still ensures that at the beginning of the corresponding transfer time of the first transfer switch 10 and the second transfer switch 20, the conductivity of the second transfer switch 20 is greater than the conductivity of the first transfer switch 10.

[0041] like Figure 2 As shown, the control circuit 30 is configured to generate corresponding control signals CS1 and CS2 for controlling the first transfer switch 10 and the second transfer switch 20, such that the end phase of the transfer time of the second transfer switch 20 ends before the end phase of the transfer time of the first transfer switch 10.

[0042] According to a possible embodiment of the charge-sensitive amplifier circuit 1, the control circuit 30 may include at least one amplifier 31, which has an input side coupled to the input node I of the charge-sensitive amplifier circuit, and an output side that generates a control signal CS1 for controlling the first transfer switch 10 and / or a control signal CS2 for controlling the second transfer switch 20 in response to the level of the input charge. The at least one amplifier 31 may be configured as an operational transconductance amplifier.

[0043] like Figure 1 As shown in the embodiment of the charge-sensitive amplifier circuit 1, the control signal CS1 generated by amplifier 31 can be directly applied to the control node of the first transfer switch 10. This means that the control signal CS1 is the output signal of amplifier 31. Figure 1 In the embodiment of the charge-sensitive amplifier circuit 1 shown, the control signal CS2 is derived from the output signal of amplifier 31. Figure 1As shown, the level shifter 32 is connected between the output of the amplifier 31 and the control node of the second transfer switch 20.

[0044] The level shifter 32 enables the second transfer switch 20 to be controlled by a control signal CS2, which is a level-shifted copy of the control signal CSI applied to the first transfer switch 10. In order to provide the control signal CS2 with a process lower than that of the control signal CSI, the level shifter 32 shifts the process of the control signal CSI generated at the output of the amplifier 31 down, so that the process of the control signal CS2 is lower than that of the control signal CSI, as Figure 2 shown.

[0045] According to a possible embodiment of the charge-sensitive amplifier circuit 1, the control circuit 30 can be configured to adjust the gain of the amplifier 31 so that the gain of the amplifier 31 is higher in a first phase of the respective transfer time of the first transfer switch 10 and the second transfer switch 20 than in a second phase of the respective transfer time of the first transfer switch 10 and the second transfer switch 20. In this case, it is possible to ensure that the gain of the amplifier 31 is higher at the beginning of the integration and then dynamically reduced.

[0046] In order to reduce the gain of the amplifier 31, according to a possible embodiment of the charge-sensitive amplifier circuit 1, the control circuit 30 comprises a resistor 33 with a variable resistance. As Figure 1 shown, the resistor 33 is connected to the output side of the amplifier 31 and to the reference / ground potential GND. Reference symbol 34 denotes a load capacitor connected between the output side of the amplifier 31 and the reference / ground potential.

[0047] The function of the charge-sensitive amplifier circuit 1 is described as follows.

[0048] At the beginning of the charge integration, the control circuit 30 generates the control signal CSI for controlling the first transfer switch 10 and the control signal CS2 for controlling the second transfer switch 20 so that the first transfer switch 10 starts to transfer the input charge from the input node I to the output node O.

[0049] If the input charge is high, the control circuit 30 raises the control signal CSI for controlling the first transfer switch 10 to its maximum level by means of the amplifier 31 and generates the control signal CS2 for controlling the second transfer switch 20 so that the second transfer switch 20 starts to transfer the charge from the input node I in parallel to the output node O.

[0050] If most of the charge is transferred from the input node I to the output node O, the level of the output signal of the amplifier 31 drops, which results in a drop of the level (e.g. control voltage) of the control signal CS1 applied at the control node of the first transfer switch 10. The control signal CS2 derived from the output signal of the amplifier 31 and thus from the control signal CS1 is generated by the level shifter 32 such that the second transfer switch 20 is completely switched off, i.e. the second transfer switch 20 is operated in a non-conductive state. At the end of the transfer time, the remaining small fraction of the charge is transferred only through the first transfer switch 10.

[0051] In case the first transfer switch 10 has to be high-ohmic at the end of the integration due to noise and in case a negative charge at the input node I is never generated by completely switching off the second transfer switch 20, it is difficult to optimize the first transfer switch 10 for a high dynamic range of input charges, especially if the excess charge caused by a defective pixel has to be removed from the input node I of the charge sensitive amplifier circuit within a short transfer time. Adding the second transfer switch 20 in parallel to the first transfer switch 10 allows to shorten the time required for removing large charges without compromising the noise performance.

[0052] The proposed concept of the charge sensitive amplifier circuit 10 can be extended to a higher number of transfer switches / gates and level shifters, e.g. using four transfer switches / gates and three level shifters to increase the dynamic range or speed of the charge transfer. According to a possible embodiment, the control circuit 30 can comprise more than two transfer switches with different threshold or bulk voltages or different geometries.

[0053] Furthermore, according to another possible embodiment of the charge sensitive amplifier circuit 10, a second amplifier can be provided in the control circuit 30 in addition to the amplifier 31, which controls the second transfer switch 20 to obtain the same benefits as described above.

[0054] List of reference signs

[0055] 1 charge sensitive amplifier circuit

[0056] 2 sensor

[0057] 3 conversion circuit

[0058] 10 first transfer switch

[0059] 20 second transfer switch

[0060] 30 control circuit

[0061] 31 amplifier

[0062] 32 level shifter

[0063] 33 resistor

[0064] 34 load capacitor

[0065] 100 image sensor circuit

[0066] D1 light sensitive cell / photodiode

[0067] I input node

[0068] O output node

[0069] CS1, CS2 control signal

Claims

1. A charge-sensitive amplifier circuit for a sensor front end, comprising: - Input node (I), which is connected to sensor (2) to receive input charge, - Output node (O), which is connected to the charge conversion circuit (3), - A first transfer switch (10), located between the input node (I) and the output node (O), to transfer the input charge to the output node (O). A second transfer switch (20), which is connected in parallel with the first transfer switch (10) between the input node (I) and the output node (O), transfers the input charge to the output node (O). - A control circuit (30) is used to generate corresponding control signals (CS1, CS2) to control the corresponding conductivity of the first transfer switch and the second transfer switch (10, 20). -The control circuit (30) is configured to generate corresponding control signals (CS1, CS2) for controlling the first transfer switch and the second transfer switch (10, 20) during the corresponding transfer times of the first transfer switch and the second transfer switch (10, 20) to transfer input charge from input node (I) to output node (O). -The control circuit (30) is configured to generate corresponding control signals (CS1, CS2) for the first transfer switch and the second transfer switch (10, 20), such that during the corresponding transfer times of the first transfer switch and the second transfer switch (10, 20), the corresponding first transfer switch and the second transfer switch (10, 20) operate in a time-related operation state. Specifically, at the beginning of the corresponding transfer time of the first transfer switch and the second transfer switch (10, 20), the conductivity of the second transfer switch (20) is higher than that of the first transfer switch (10). Wherein, at the end of the corresponding transfer time of the first transfer switch and the second transfer switch (10, 20), the conductivity of the second transfer switch (20) is lower than that of the first transfer switch (10).

2. The charge-sensitive amplifier circuit according to claim 1, -in, The control circuit (30) is configured to generate corresponding control signals (CS1, CS2) for controlling the first transfer switch and the second transfer switch (10, 20), such that the corresponding conductivity of the first transfer switch and the second transfer switch (10, 20) is higher at the beginning of the corresponding transfer time of the first transfer switch and the second transfer switch (10, 20) than at the end of the corresponding transfer time of the first transfer switch and the second transfer switch (10, 20). -The control circuit (30) is configured to generate corresponding control signals (CS1, CS2) for controlling the first transfer switch and the second transfer switch (10, 20), such that the corresponding conductivity of the first transfer switch and the second transfer switch (10, 20) continuously decreases from the beginning of the corresponding transfer time of the first transfer switch and the second transfer switch (10, 20) until the end of the corresponding transfer time of the first transfer switch and the second transfer switch (10, 20).

3. The charge-sensitive amplifier circuit according to claim 1, in, At the end of the corresponding transfer time of the first transfer switch and the second transfer switch (10, 20), the second transfer switch (20) operates in a non-conducting state, while the first transfer switch (10) operates in a low-conducting state.

4. The charge-sensitive amplifier circuit according to claim 1, in, The first transfer switch and the second transfer switch (10, 20) are configured such that the respective conductivity of the first transfer switch and the second transfer switch (10, 20) depends on whether the level of the respective control signal (CS1, CS2) is higher or lower than the respective threshold voltage of the first transfer switch and the second transfer switch (10, 20).

5. The charge-sensitive amplifier circuit according to claim 4, -The control circuit (30) is configured to generate a control signal (CS1) for controlling the first transfer switch (10), which has a different level than the control signal (CS2) for controlling the second transfer switch (20). -in, The first transfer switch and the second transfer switch (10, 20) have the same threshold voltage.

6. The charge-sensitive amplifier circuit according to claim 4, -The control circuit (30) is configured to generate a control signal (CS1) for controlling the first transfer switch (10), which has the same level as the control signal (CS2) for controlling the second transfer switch (20). -in, The threshold voltage of the first transfer switch (10) is different from the threshold voltage of the second transfer switch (20), or -The first body bias voltage applied to the first transfer switch (10) is different from the second body bias voltage applied to the second transfer switch (20).

7. The charge-sensitive amplifier circuit according to claim 2, in, The control circuit (30) is configured to generate corresponding control signals (CS1, CS2) for controlling the first transfer switch and the second transfer switch (10, 20), such that the end phase of the transfer time of the second transfer switch (20) ends before the end phase of the transfer time of the first transfer switch (10).

8. The charge-sensitive amplifier circuit according to claim 1, in, The control circuit (30) includes at least one amplifier (31), which has an input side coupled to the input node (I) and an output side that generates a control signal (CS1) for controlling the first transfer switch (10) and / or a control signal (CS2) for controlling the second transfer switch (20) in response to the level of the input charge.

9. The charge-sensitive amplifier circuit according to claim 1, in, The control circuit (30) includes more than two transfer switches with different thresholds or body voltages or different geometries.

10. The charge-sensitive amplifier circuit according to claim 8, in, The control circuit (30) is configured to adjust the gain of the at least one amplifier (31) such that the gain of the at least one amplifier (31) is higher at the beginning of the transition time than at the end of the transition time.

11. A sensor circuit, comprising: -Sensor(2), - Charge conversion circuit (3), and -The charge-sensitive amplifier circuit (1) as described in claim 1, -The input node (I) of the charge-sensitive amplifier circuit (1) is connected to the sensor (2), and the output node (O) of the charge-sensitive amplifier circuit (1) is connected to the charge conversion circuit (3).

12. The sensor circuit according to claim 11, -The sensor (2) is configured as an optical sensor comprising a plurality of photosensitive units (D1). -in, The optical sensor (2) is controlled such that the photosensitive unit (D1) is read out sequentially, and the corresponding charge of the photosensitive unit (D1) is applied to the input node (I) of the charge sensitive amplifier circuit (1) to be transferred to the charge conversion circuit (3).

13. The sensor circuit according to claim 11, - Wherein, the sensor (2) is configured as a capacitive sensor comprising multiple capacitive sensor units, -in, The capacitance sensor is controlled such that the capacitance cells are read out sequentially, and the corresponding charge of the capacitance cells is applied to the input node (I) of the charge-sensitive amplifier circuit (1) to be transferred to the charge conversion circuit (3).

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