Solid-state imaging device and imaging device using the same

Abstract

A solid-state imaging device includes a pixel circuit (3) and a negative feedback circuit (21). The pixel circuit (3) includes a photodiode (PD), a charge accumulation section (FD0) that holds signal charges generated by the photodiode (PD), an amplification transistor (SF) that outputs a pixel signal corresponding to the signal charges of the charge accumulation section (FD0), a first reset transistor (RS) that resets the charge accumulation section (FD0), a first accumulation capacitor element (C1) that holds the signal charges, and a first transistor (GC1) that controls connection of the charge accumulation section (FD0) and the first accumulation capacitor element (C1). The negative feedback circuit (21) negatively feeds back a feedback signal corresponding to a reset output of the amplification transistor (SF) to the charge accumulation section (FD0) via the first reset transistor (RS).

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device and an imaging device using the solid-state imaging device. Background Art

[0002] Patent Document 1 discloses a negative feedback circuit for reducing reset noise.

[0003] (Prior art literature)

[0004] (Patent Document)

[0005] Patent Document 1: U.S. Patent No. 6777660 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] However, conventional technologies have a problem in that it is difficult to expand the dynamic range and improve the SN.

[0008] Therefore, the present disclosure provides a solid-state imaging device and an imaging device capable of expanding the dynamic range and improving SN.

[0009] Means used to solve the problem

[0010] In order to solve the above-mentioned problems, the solid-state imaging device in the present disclosure includes a pixel circuit and a negative feedback circuit, wherein the pixel circuit includes: a photodiode; a charge storage unit; a transfer transistor, which transfers the signal charge generated in the photodiode to the charge storage unit; an amplifying transistor, which outputs a pixel signal corresponding to the signal charge of the charge storage unit; a first reset transistor, which resets the charge storage unit; a first storage capacitor element; and a first transistor, which controls the connection between the charge storage unit and the first storage capacitor element, and the negative feedback circuit negatively feeds back a feedback signal corresponding to the reset output of the amplifying transistor to the charge storage unit (FD0) via the first reset transistor. A switching element is provided between the transmission Tr and the photodiode (PD) and the storage capacitor element C. In low illumination, the first storage capacitor element is turned to the OFF state (cut-off state), thereby improving the image quality under low illumination through CDS (correlated double sampling). In high illumination, the first storage capacitor element is turned to the ON state (conductive state), thereby improving the image quality under high illumination and reducing reset noise through a negative feedback circuit.

[0011] Effects of the Invention

[0012] The solid-state imaging device and imaging device of the present disclosure can achieve both expansion of the dynamic range and improvement of the SN. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A A first configuration example of a main portion of a solid-state imaging device in one embodiment of the present disclosure is shown.

[0014] Figure 1B A second configuration example of the main portion of the solid-state imaging device in one embodiment of the present disclosure is shown.

[0015] Figure 1C A third configuration example of the main portion of the solid-state imaging device in one embodiment of the present disclosure is shown.

[0016] Figure 2 This is a block diagram showing a configuration example of a solid-state imaging device according to Embodiment 1A.

[0017] Figure 3 Multiple areas within the pixel array section are shown.

[0018] Figure 4 Multiple areas within the pixel array section are shown.

[0019] Figure 5 A circuit example including important parts of the pixel circuit and negative feedback circuit according to Embodiment 1A is shown.

[0020] Figure 6A An example is shown in which the solid-state imaging device in Embodiment 1A is configured as a stacked back-illuminated image sensor.

[0021] Figure 6B An example is shown in which the solid-state imaging device in Embodiment 1A is configured as a stacked back-illuminated image sensor.

[0022] Figure 6C An example is shown in which the solid-state imaging device in Embodiment 1A is configured as a stacked back-illuminated image sensor.

[0023] Figure 6D An example is shown in which the solid-state imaging device in Embodiment 1A is configured as a stacked back-illuminated image sensor.

[0024] Figure 7 This is a timing chart showing the n-times exposure operation of the solid-state imaging device performed by the HCG readout operation in Embodiment 1A.

[0025] Figure 8 The timing of the LCG read operation in Embodiment 1A is shown as an example.

[0026] Figure 9 The CDS readout order in the LCG readout operation is shown.

[0027] Figure 10AThe waveform of the slope signal is shown.

[0028] Figure 10B The relationship between the ramp period and the reset noise level is shown.

[0029] Figure 11 The timing related to charge accumulation in the photodiode and the storage capacitor element is shown.

[0030] Figure 12A Horizontal scanning lines serving as calculation units for the deviation of reset noise are shown.

[0031] Figure 12B The deviation (standard deviation) of the reset noise in units of horizontal scanning lines is shown.

[0032] Figure 13 : is a flowchart showing an example of a process for generating a ramp signal.

[0033] Figure 14 This is a flowchart showing another example of processing for generating a ramp signal.

[0034] Figure 15 This is a flowchart showing still another processing example of generating a ramp signal.

[0035] Figure 16 An overview of how WDR is implemented within a pixel is shown.

[0036] Figure 17 The FD potential in the HCG readout operation for a low-illuminance frame and the LCG readout operation for a high-illuminance frame are shown.

[0037] Figure 18A As a comparative example, the relationship between the subject illumination and the gain (SN) during LCG readout is shown in a case where no negative feedback circuit is provided.

[0038] Figure 18B The relationship between the subject illumination and the gain (SN) during HCG reading according to Embodiment 1A is shown.

[0039] Figure 18C As a comparative example, the relationship between the subject illumination and the gain (SN) during HCG reading is shown in a case where no negative feedback circuit is provided.

[0040] Figure 18D The relationship between the subject illumination and the gain (SN) during HCG reading according to Embodiment 1A is shown.

[0041] Figure 19 The timing related to charge accumulation in the photodiode and the storage capacitor element is shown.

[0042] Figure 20A The read timing in a state where the storage capacitor element is connected (ie, LCG read operation) is shown as an example.

[0043] Figure 20B Shown Figure 20A The readout order of the reset component and signal component in the LCG readout work.

[0044] Figure 21 A circuit example including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 2A is shown.

[0045] Figure 22 The timing of the LCG read operation in a state where the storage capacitor element according to Embodiment 2A is connected is shown as an example.

[0046] Figure 23 The following exemplifies the read timing in a state where the storage capacitor element according to Embodiment 2B is connected.

[0047] Figure 24 A circuit example including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 3A is shown.

[0048] Figure 25 The timing of the LCG read operation in a state where the storage capacitor element according to Embodiment 3A is connected is shown as an example.

[0049] Figure 26 The timing of the LCG read operation in a state where the storage capacitor element according to Embodiment 3B is connected is shown as an example.

[0050] Figure 27 An example of a circuit including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 4 is shown.

[0051] Figure 28A This is a timing chart showing the readout procedure of one frame in the fourth embodiment.

[0052] Figure 28B Shown Figure 28A The readout order of the reset component and signal component in the HCG readout and the LCG readout.

[0053] Figure 29 A configuration example of a signal processing unit that performs WDR synthesis using two frames is shown.

[0054] Figure 30A As a comparative example, the relationship between the subject illumination and the gain (SN) during LCG readout is shown in a case where no negative feedback circuit is provided.

[0055] Figure 30BAs a comparative example, the relationship between the subject illumination and the gain (SN) during LCG readout is shown in a case where no negative feedback circuit is provided.

[0056] Figure 30C The relationship between the subject illumination and the gain (SN) during LCG readout according to the fourth embodiment is shown.

[0057] Figure 30D The relationship between the subject illumination and the gain (SN) during LCG readout according to the fourth embodiment is shown.

[0058] Figure 31A As a comparative example, the relationship between the subject illumination and the signal output level (LSB) during LCG readout is shown in a case where no negative feedback circuit is provided.

[0059] Figure 31B As a comparative example, the relationship between the subject illumination and the signal output level (LSB) during LCG readout is shown in a case where no negative feedback circuit is provided.

[0060] Figure 31C The relationship between the subject illumination and the signal output level (LSB) during LCG readout according to the fourth embodiment is shown.

[0061] Figure 31D The relationship between the subject illumination and the signal output level (LSB) during LCG readout according to the fourth embodiment is shown.

[0062] Figure 32 An example of a circuit including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 5 is shown.

[0063] Figure 33A This is a timing chart showing the readout procedure of one frame in the fifth embodiment.

[0064] Figure 33B Shown Figure 33A The readout order of the reset component and signal component in the HCG readout and the LCG readout.

[0065] Figure 34A An example of a circuit including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 6 is shown.

[0066] Figure 34B A configuration example of a signal processing unit that performs WDR synthesis using three frames is shown.

[0067] Figure 35A This is a timing chart showing the readout procedure of one frame in the sixth embodiment.

[0068] Figure 35B Shown Figure 35A The reading order of the reset component and signal component in HCG reading, MCG reading and LCG reading.

[0069] Figure 36 An example of timing related to charge accumulation in the photodiode and two storage capacitor elements is shown.

[0070] Figure 37 This is an explanatory diagram showing an overview of a WDR synthesis method within a pixel.

[0071] Figure 38 Shown Figure 37 FD potential in HCG readout, MCG readout, and LCG readout.

[0072] Figure 39A As a comparative example, the relationship between the subject illumination and the gain (SN) in LCG readout in a case where no negative feedback circuit is provided is shown.

[0073] Figure 39B As a comparative example, the relationship between the subject illumination and the gain (SN) in LCG readout in a case where no negative feedback circuit is provided is shown.

[0074] Figure 39C The relationship between the subject illumination and the gain (SN) in the LCG readout according to the sixth embodiment is shown.

[0075] Figure 39D The relationship between the subject illumination and the gain (SN) in the LCG readout according to the sixth embodiment is shown.

[0076] Figure 40 An example of a circuit including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 7 is shown.

[0077] Figure 41A This is a timing chart showing the readout procedure of one frame in the seventh embodiment.

[0078] Figure 41B Shown Figure 41A The reading order of the reset component and signal component in HCG reading, MCG reading and LCG reading.

[0079] Figure 42 A circuit example including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 8 is shown.

[0080] Figure 43A This is a timing chart showing the readout procedure of one frame in the eighth embodiment.

[0081] Figure 43B Shown Figure 43AThe reading order of the reset component and signal component in HCG reading, MCG reading and LCG reading.

[0082] Figure 44 An example of timing related to charge accumulation in the photodiode and two storage capacitor elements is shown.

[0083] Figure 45 An example of a circuit including important parts of a pixel circuit and a negative feedback circuit according to Embodiment 9 is shown.

[0084] Figure 46A This is a timing chart showing the readout procedure of one frame in the ninth embodiment.

[0085] Figure 46B Shown Figure 46A The reading order of the reset component and signal component in HCG reading, MCG reading and LCG reading.

[0086] Figure 47 This is a block diagram showing a configuration example of an imaging device according to a tenth embodiment.

[0087] Figure 48 This is a block diagram showing another configuration example of the imaging device according to the tenth embodiment.

[0088] Figure 49 An example is shown in which the imaging device according to Embodiment 10 is mounted on a vehicle.

[0089] Figure 50 The embodiment 10 is shown Figure 49 An example of the shooting range in the example shown.

[0090] Figure 51A Patent Document 1 shows the relationship between the subject illumination and SN when the FD capacitance directly connected to the photodiode is small.

[0091] Figure 51B shows the FD capacitance ratio Figure 51A The relationship between the subject illumination and SN in the case of large. DETAILED DESCRIPTION

[0092] (Insights that form the basis of this disclosure)

[0093] The present inventors have discovered the following problems with the solid-state imaging device described in the background art.

[0094] The solid-state imaging device disclosed in Patent Document 1 accumulates the signal charge generated by the photodiode as is in the floating diffusion layer (hereinafter also referred to as the FD capacitor), and uses a feedback circuit to input the reset level output from the source follower circuit to the reset transistor RS via a feedback amplifier and a feedback line to reduce reset noise.

[0095] Figure 51A This chart shows the relationship between subject illumination and SN (Signal to Noise Ratio) when the FD capacitance directly connected to the photodiode is small, as described in Patent Document 1. The horizontal axis represents subject illumination, and the vertical axis represents SN. min represents the minimum subject illumination that can be captured, and max represents the maximum subject illumination. It can be seen that reducing the FD capacitance improves (decreases) the minimum subject illumination, but deteriorates (decreases) the maximum subject illumination (Problem 1).

[0096] Figure 51B The opposite situation is shown, that is, the relationship between the subject illumination and SN when the FD capacitance is large. When the FD capacitance is increased, the minimum subject illumination deteriorates (increases), but the maximum subject illumination improves (increases) (Question 2).

[0097] Whether increasing or decreasing the FD capacitance, the dynamic range cannot be expanded.

[0098] Furthermore, in order to substantially increase or keep the FD capacitance unchanged, it is conceivable to add another capacitance element to the FD capacitance. However, adding a capacitance element will easily cause another problem of reset noise (Problem 3).

[0099] Therefore, the present disclosure provides a solid-state imaging device and an imaging device capable of achieving both an expansion of the dynamic range and an improvement in SN.

[0100] (Overview of a Solid-State Imaging Device in One Aspect of the Present Disclosure)

[0101] In one embodiment of the present disclosure, a solid-state imaging device includes a storage circuit group for storing signal charge overflowing from a photodiode. This storage circuit group comprises a plurality of series-connected storage circuits (m ≥ 1), each comprising a set of switching elements and storage capacitors, serving as an overflow gate. The device comprises a horizontally arranged series-connected storage circuit group and a vertically arranged series-connected storage circuit group for the photodiode PD.

[0102] During the exposure period, when m=1, the charge overflowing from the photodiode PD is received by the storage capacitor element of the storage circuit. When m>2, the charge overflowing from the storage capacitor element is further received by the storage capacitor element in the subsequent storage circuit.

[0103] Furthermore, since the storage capacitor element within the storage circuit cannot fully transfer the signal charge, reset noise is generated during the shutter and reset of the signal. Here, reset noise refers to kTC noise. The noise level is represented by √(kTC)(C) or √(kTC) / e(ele) in terms of charge, and by √(kT / C)(V) in terms of voltage. In order to suppress such reset noise, the solid-state imaging device in one embodiment of the present disclosure further has a negative feedback circuit that performs negative feedback on the reset signal.

[0104] Next, an overview of a solid-state imaging device according to one embodiment of the present disclosure will be given. Figures 1A to 1C The following describes the three configuration examples shown.

[0105] [0.1 First Configuration Example of Solid-State Imaging Device]

[0106] First, a first configuration example will be described. The first configuration example shows a configuration in which the above-mentioned storage circuits are connected in two stages (m=2) in the vertical direction.

[0107] Figure 1A A first configuration example of the main portion of the solid-state imaging device 100 in one embodiment of the present disclosure is shown.

[0108] Figure 1A The solid-state imaging device 100 includes a pixel circuit 3 and a negative feedback circuit 21 .

[0109] This figure shows one of a plurality of pixel circuits 3 arranged in a matrix. Pixel circuit 3 includes a photodiode PD, a transfer transistor TG, a charge storage unit FD0, a transfer transistor TG, an amplifier transistor SF, a reset transistor RS, a first storage capacitor element C1, a first transistor GC1, a second storage capacitor element C2, a second transistor GC2, and a select transistor SEL.

[0110] The photodiode PD is a photoelectric conversion element that converts incident light into signal charges. During exposure, the signal charges overflowing the photodiode PD are transferred to and held in the first storage capacitor element C1, as indicated by the dashed arrows in the figure. Furthermore, the signal charges overflowing the first storage capacitor element C1 are transferred to and held in the second storage capacitor element C2.

[0111] The charge storage unit FD0 is formed as, for example, a floating diffusion layer, and holds signal charges generated by the photodiode PD. In the figure, the capacity of the charge storage unit FD0 or the charge storage unit FD0 as a capacitive element is referred to as C0.

[0112] The amplifier transistor SF outputs a pixel signal corresponding to the signal charge of the charge storage unit FD0 to the vertical signal line 19 via the selection transistor SEL.

[0113] The reset transistor RS resets the charge storage unit FD0. Specifically, the reset transistor RS can perform three reset operations by controlling the first transistor GC1 and the second transistor GC2. Specifically, the reset transistor RS can perform (i) resetting the floating diffusion layer FD0, the first storage capacitor element C1, and the second storage capacitor element C2; (ii) resetting the first storage capacitor element C1 and the second storage capacitor element C2; and (iii) resetting the second storage capacitor element C2.

[0114] The first storage capacitor element C1 holds signal charges overflowed from the photodiode PD. For example, during exposure, the first storage capacitor element C1 stores signal charges overflowed from the photodiode PD via the transfer transistor TG and the first transistor GC1.

[0115] The first transistor GC1 controls the connection between the charge storage unit FD0 and the first storage capacitor element C1. The first transistor GC1 functions as a switching element, having an on state and an off state. Furthermore, the gate voltage of the transfer transistor TG and the gate voltage of the first transistor GC1 are set so that, during exposure, the transfer transistor TG and the first transistor GC1 do not need to be completely off, allowing the signal charge overflowing from the photodiode PD to be transferred from the transfer transistor TG to the first storage capacitor element C1 via the charge storage unit FD0 and the first transistor GC1.

[0116] The second storage capacitor element C2 holds the signal charge overflowed from the first storage capacitor element C1. For example, the second storage capacitor element C2 accumulates the signal charge overflowed from the first storage capacitor element C1 via the second transistor GC2.

[0117] The second transistor GC2 is a gain control transistor that controls the connection between the first storage capacitor element C1 and the second storage capacitor element C2. The second transistor GC2 functions as a switching element, having an on state and an off state. Furthermore, the gate voltage of the second transistor GC2 is set so that, during exposure, the gate voltage does not need to be completely off, allowing signal charge overflowing from the first storage capacitor element C1 to be transferred to the second storage capacitor element C2 via the second transistor GC2.

[0118] The selection transistor SEL is a switching element for selecting whether or not to output a pixel signal from the amplifier transistor SF to the vertical signal line 19. The pixel signal has at least two levels: a reset level and a signal level.

[0119] One negative feedback circuit 21 is provided for each column of pixel circuits 3. Alternatively, one negative feedback circuit 21 is provided for each pixel circuit 3. The negative feedback circuit 21 transmits a feedback signal corresponding to the reset output of the amplifier transistor SF from the vertical signal line 19 via the feedback line 20 through the first reset transistor RS, and negatively feeds it back to the charge storage unit FD0. Specifically, the negative feedback circuit 21 includes a feedback amplifier FA. The reset output of the amplifier transistor SF is input to the negative input terminal of the feedback amplifier FA via the vertical signal line 19. A reference voltage VREF, which serves as a reference for the reset level, is input to the positive input terminal of the feedback amplifier FA. The output terminal of the feedback amplifier FA transmits the difference between the reference voltage VREF and the reset output via the feedback line 20 and the first reset transistor RS to the charge storage unit FD0.

[0120] exist Figure 1A In the first configuration example of the solid-state imaging device 100 shown, an overflow storage circuit group is provided to hold the signal charge overflowing from the photodiode PD. The storage circuit group is composed of a switch element and a storage capacitor element as a set, connected in series in multiple stages (m ≥ 1). Figure 1A This is an example where m = 2. The first-stage storage circuit is a combination of the first transistor GC1 and the first storage capacitor C1. The second-stage storage circuit is a combination of the second transistor GC2 and the second storage capacitor C2. Furthermore, the combination of the transfer transistor TG and the charge storage unit FD0 can also be considered the zero-stage storage circuit. Although the storage circuit group is a source of reset noise, it is reset by the negative feedback circuit 21. This suppresses reset noise.

[0121] According to this configuration, it is possible to achieve both an expansion of the dynamic range and an improvement of the SN.

[0122] [0.2 Second Configuration Example of Solid-State Imaging Device]

[0123] Next, a second configuration example will be described. The second configuration example shows a configuration in which the above-mentioned storage circuits are connected in two stages (m=2) in the horizontal direction.

[0124] Figure 1B A second configuration example of the main portion of the solid-state imaging device 100 in one embodiment of the present disclosure is shown. Figure 1B The second construction example and Figure 1A Compared with the first configuration example of FIG, the circuit configuration inside the pixel circuit 3 is different. The following description will focus on the differences.

[0125] The structure of pixel circuit 3 Figure 1A The difference is that a first storage capacitor element C3, a first transistor GC, a second storage capacitor element C4, and a second transistor TGC are added instead of the first storage capacitor element C1, the first transistor GC1, the second storage capacitor element C2, and the second transistor GC2.

[0126] During exposure, the signal charge overflowing the photodiode PD is transferred to and held in the second storage capacitor element C4, as indicated by the dashed arrow in the figure. Although there is no overflow element OF between the photodiode PD and the second storage capacitor element C4, the potential structure allows the charge to be transferred along this path.

[0127] The reset transistor RS is capable of performing three types of reset operations under the control of the first transistor GC and the second transistor TGC. Specifically, the reset transistor RS is capable of (i) resetting the floating diffusion layer FD0, the first storage capacitor element C3, and the second storage capacitor element C4; (ii) resetting the first storage capacitor element C3 and the second storage capacitor element C4; and (iii) resetting the first storage capacitor element C3.

[0128] When the transfer transistor TG is in the on state, the charge overflowing from the charge storage unit FD0 is transferred to the first storage capacitor element C3 and held therein as indicated by the dotted arrow in the figure.

[0129] The first transistor GC is a transistor that controls the connection between the charge storage unit FD0 and the first storage capacitor element C3. The first transistor GC functions as a switching element and has an on state and an off state.

[0130] During exposure, the signal charge overflowing the photodiode PD is transferred to the second storage capacitor element C4 and held there, as indicated by the dotted arrow in the figure.

[0131] The second transistor TGC is a gain control transistor that controls the connection between the first storage capacitor element C3 and the second storage capacitor element C4. The second transistor TGC functions as a switching element and has an on state and an off state.

[0132] exist Figure 1B In the second configuration example of the solid-state imaging device 100 shown in FIG, an overflow storage circuit group is provided to hold the signal charge overflowing from the photodiode PD. The storage circuit group is composed of a switching element and a storage capacitor element as a set, which are connected in series in multiple stages (m ≥ 1). Figure 1BThis is an example where m = 2. The first-stage storage circuit is the combination of the first transistor GC and the first storage capacitor C3. The second-stage storage circuit is the combination of the second transistor TGC and the second storage capacitor C4. Furthermore, the combination of the transfer transistor TG and the charge storage unit FD0 can be considered the 0th-stage storage circuit.

[0133] According to the second configuration example, it is possible to achieve both an expansion of the dynamic range and an improvement of the SN.

[0134] [0.3 Third Configuration Example of Solid-State Imaging Device]

[0135] Next, a third configuration example will be described. The third configuration example shows a configuration in which an overflow element is added to the second configuration example in which the storage circuits are connected in two stages (m=2) in the horizontal direction.

[0136] Figure 1C A third configuration example of the main portion of the solid-state imaging device 100 in one embodiment of the present disclosure is shown. Figure 1C The third example of the structure and Figure 1B Compared with the second configuration example, the difference is that an overflow element OF is added to the pixel circuit 3. The following description will focus on the difference.

[0137] The overflow element OF transfers the signal charge overflowed from the photodiode PD to the first storage capacitor element C4 via the overflow element OF, not to the second storage capacitor element C3 via the transfer transistor TG.

[0138] Furthermore, the signal charge overflowing from the first storage capacitor element C4 is transferred to the second storage capacitor element C3 via the first transistor TGC.

[0139] Figure 1C The third configuration is shown by the dotted arrow. Figure 1B Compared to the second configuration example, the direction of signal charge overflowing from the photodiode PD is the same. In the third configuration example, since the signal charge overflowing from the photodiode PD does not flow through the charge storage unit FD0 but is instead stored in the storage capacitor C4, the dark current component can be reduced compared to the first configuration example. Furthermore, compared to the second configuration example, the presence of the overflow element OF can suppress the overflow level.

[0140] In the above-mentioned first to third configuration examples, shooting operations of low illumination frames, shooting operations of high illumination frames, shooting operations of synthesizing low illumination frames and high illumination frames, shooting operations of synthesizing low illumination frames, medium illumination frames and high illumination frames, etc. are performed.

[0141] Here, a low-illumination frame refers to, for example, a frame captured with all m-level storage circuits in the off state, and is suitable for low-illumination environments. A high-illumination frame refers to, for example, a frame captured with all m-level storage circuits in the on state, and is suitable for high-illumination environments. A medium-illumination frame refers to, for example, a frame captured with some of the m-level storage circuits in the on state, and is suitable for medium-illumination environments. The terms high, medium, and low illumination do not represent absolute illumination levels, but rather may be relative.

[0142] For example, in shooting a low-light frame, shooting is performed with the storage circuit OFF state (cut-off state) of m levels, so that the signal charge transferred from the photodiode PD to the charge storage unit FD0 is completely read out by the CDS (=signal component-reset component).

[0143] Furthermore, during high-illumination frame capture, a gentle ramp signal is applied to the control voltage of the switching elements within each storage circuit. This allows for negative feedback via the feedback amplifier FA as the switching element transitions from the ON state (conducting state) to the OFF state, thereby reducing reset noise in the storage capacitor element. Furthermore, the signal from the photodiode PD and the signal from the storage capacitor element can be read separately and combined.

[0144] With this, the dynamic range can be expanded by associating and synthesizing the signal components read out in the low illumination area and the signal components read out in the high illumination area, or by selectively reading out the appropriate frame according to the illumination.

[0145] This method uses only the signal charge transferred from the photodiode PD to the charge storage unit FD0 during low-light frame capture. This increases the intra-pixel gain, specifically the gain of the signal charge converted to voltage by the amplifier transistor SF. This increases the voltage (pixel signal) corresponding to the amount of received light, thereby counteracting noise generated by the amplifier transistor SF and the analog circuitry. This allows for high-quality image output with a high signal-to-noise ratio (SN) for dark subjects.

[0146] Furthermore, when capturing high-illuminance frames, an m-stage accumulation circuit is used to reduce intra-pixel gain, thereby expanding the dynamic range and enabling the capture of high-illuminance light. Furthermore, the negative feedback circuit 21 can be used to improve the SN. Specifically, for bright subjects, grayscale levels corresponding to the subject can be accurately reproduced, enabling output of images without blown-out highlights.

[0147] Therefore, the present inventors have developed a technique for expanding the dynamic range and improving the SN. In addition to the storage capacitor elements (C1, C2, C3, and C4) in the photodiode PD, they also include switching elements (transistors (GC1, GC2, and GC)) and a charge storage transfer element (TGC). This configuration achieves both an expansion of the dynamic range and an improvement in the SN. While increasing the signal level generally degrades the SN, the above configuration suppresses SN degradation even at higher signal levels.

[0148] Furthermore, since the three frames for WDR (Wide Dynamic Range), namely, the low illumination frame, the medium illumination frame, and the high illumination frame, can be generated at exactly the same timing and using exactly the same pixels, false color, coloring, and blurring will not occur.

[0149] Furthermore, the device can be expanded to include a global shutter method in addition to a rolling shutter method, thereby enabling development as a distance measuring device using a TOF (Time of Flight) method.

[0150] Furthermore, the number of frames for WDR conversion depends on the number m of stages of the storage circuit and can be expanded from 2 or 3 to 5, thereby increasing the dynamic range.

[0151] While it is generally difficult to use high-saturation pixels, this embodiment allows for an increase in the saturation level with the limited capacitance of the photodiode PD. Increasing the storage capacity within the storage circuit can increase the voltage amplitude between the capacitor terminals and the capacitance area within the limited pixel unit, allowing for the semiconductor chip that constitutes the solid-state imaging device to be three-dimensional or multilayered.

[0152] For example, the storage capacitor element within the storage circuit can be configured on a semiconductor chip having pixels or a semiconductor chip having logic circuits. Furthermore, even when configured on a semiconductor chip having pixels, the storage capacitor element can be formed on the top or bottom metal layer.

[0153] Furthermore, the contacts or plugs connecting the storage capacitor wiring to the silicon substrate can contribute to dark-time characteristics (dark current, noise, and stuttering). Furthermore, the TSV connections or hybrid connections between the pixel chip and logic chip can also contribute to dark-time characteristics (dark current, noise, and stuttering).

[0154] When these noises are superimposed on the reset noise, they can be reduced by the negative feedback circuit 21 , and thus lower noise can be achieved compared to a case where the negative feedback circuit 21 is not provided.

[0155] As described above, a solid-state imaging device according to one embodiment of the present disclosure includes a pixel circuit 3 and a negative feedback circuit 21. The pixel circuit 3 includes: a photodiode PD, a charge storage unit FD0, a transfer transistor TG for transferring the signal charge generated by the photodiode PD to the charge storage unit FD0, an amplifier transistor SF for outputting a pixel signal corresponding to the signal charge of the charge storage unit FD0, a first reset transistor RS for resetting the charge storage unit FD0, a first storage capacitor element C1 / C4, and a first transistor GC1 / TGC for controlling the connection between the charge storage unit FD0 and the first storage capacitor element C1 / C4. The negative feedback circuit 21 negatively feeds back a feedback signal corresponding to the reset output of the amplifier transistor SF to the charge storage unit FD0 via the first reset transistor RS.

[0156] This increases the saturation signal charge through the first storage capacitor element C1 or C4 and the first transistor GC1 / TGC, and thus expands the dynamic range through switching. Furthermore, since the charge storage unit FD0 and the first storage capacitor element C1 or C4 can be reset to their reset levels through the negative feedback circuit 21, kTC noise during reset can be suppressed, thereby improving image quality.

[0157] Here, the gate voltage of the transfer transistor TG and the gate voltage of the first transistors GC1 / TGC may be set so that the signal charge overflowing from the photodiode PD can be transferred to the first storage capacitor elements C1 / C4 during exposure.

[0158] With this, it is possible to generate pixel signals for low illumination and pixel signals for high illumination using the overflowed signal charge, thereby easily expanding the dynamic range.

[0159] Here, the first transistor GC1 may be connected in series with the first reset transistor RS between the first reset transistor RS and the charge storage unit FD0 , and the first storage capacitor element C1 may be connected to a connection point between the first reset transistor RS and the first transistor GC1 .

[0160] According to this, it is possible to construct a system having at least one level in the vertical direction. Figure 1A For example, the storage circuit shown in the first configuration example can selectively or simultaneously generate pixel signals for low illumination frames and pixel signals for high illumination frames.

[0161] Here, the first transistor TGC may connect the first storage capacitor element C4 to a connection point between the first reset transistor RS and the charge storage unit FD0 .

[0162] According to this, it is possible to construct a system having at least one level in the horizontal direction. Figure 1CFor example, the storage circuit shown in the second configuration example can selectively or simultaneously generate pixel signals for low illumination frames and pixel signals for high illumination frames.

[0163] Here, the solid-state imaging device may further include an overflow element OF to transfer the signal charge overflowed from the photodiode PD to the first storage capacitor element C4.

[0164] According to this, it is possible to construct a system having at least one level in the horizontal direction. Figure 1C The storage circuit shown in the third configuration example is configured to include an overflow element OF. For example, since overflowed signal charge does not flow through the charge storage unit FD0 but can be transferred to the first storage capacitor element, noise caused by dark current or the like can be suppressed.

[0165] Here, the solid-state imaging device may further include: a second transistor GC2, which is inserted in series between the first reset transistor RS and the first transistor GC1; and a second storage capacitor element C2, which is connected to the connection point between the first reset transistor RS and the second transistor GC2, and is connected to the charge storage unit FD0 via the first transistor GC1 and the second transistor GC2.

[0166] According to this, it is possible to construct a system having at least two levels in the vertical direction. Figure 1A The storage circuit shown in the first configuration example of FIG. For example, it is possible to selectively or simultaneously generate pixel signals for low-illuminance frames, pixel signals for medium-illuminance frames, and pixel signals for high-illuminance frames. Furthermore, it is possible to synthesize the low-illuminance frames and the medium-illuminance frames to expand the dynamic range.

[0167] Here, the solid-state imaging device may further include: a second transistor GC, which is inserted between the charge storage unit FD0 and the following connection point, which is the connection point between the first reset transistor RS and the first transistor TGC; and a second storage capacitor element C3, which is connected to the connection point between the first reset transistor RS and the first transistor TGC.

[0168] According to this, it is possible to construct a system having at least two levels in the horizontal direction. Figure 1B and Figure 1C The storage circuits shown in the second and third configuration examples are described. For example, pixel signals for low-illuminance frames, pixel signals for medium-illuminance frames, and pixel signals for high-illuminance frames can be selectively or simultaneously generated. Furthermore, the low-illuminance frames and medium-illuminance frames can be synthesized to expand the dynamic range.

[0169] Here, the solid-state imaging device may further include: a plurality of pixel circuits 3; a driving unit that drives the plurality of pixel circuits 3 to expose them simultaneously; and a control circuit that scans the plurality of pixel circuits 3 to read pixel signals.

[0170] This allows for a global shutter that exposes all pixels simultaneously, thereby expanding the dynamic range and suppressing kTC noise during resetting, thereby improving image quality.

[0171] Here, the solid-state imaging device may include a control circuit that reads out a first pixel signal for constituting a first frame and a second pixel signal for constituting a second frame from the pixel circuit 3, wherein the second frame is a frame for higher illumination than the first frame, the first pixel signal corresponds to a signal charge transmitted from the photodiode PD to the charge storage unit FD0, the second pixel signal corresponds to a signal charge transmitted from the photodiode PD to the charge storage unit FD0 and the first storage capacitor element C1 and mixed, and the first pixel signal and the second pixel signal are based on the signal charge generated by the photodiode PD of one pixel circuit 3 during the same exposure period.

[0172] With this, the first frame for low illumination and the second frame for high illumination can be generated simultaneously within one frame period, thereby expanding the dynamic range and suppressing kTC noise during resetting.

[0173] Here, the solid-state imaging device may also include a control circuit, which reads out a first pixel signal for constituting a first frame, a second pixel signal for constituting a second frame, and a third pixel signal for constituting a third frame from the pixel circuit 3, wherein the second frame is a frame for higher illumination than the first frame, and the third frame is a frame for higher illumination than the second frame, the first pixel signal corresponds to the signal charge transferred from the photodiode PD to the charge storage unit FD0, the second pixel signal corresponds to the signal charge transferred from the photodiode PD to the charge storage unit FD0 and the first storage capacitor element C1 and mixed, the third pixel signal corresponds to the signal charge transferred from the photodiode PD to the charge storage unit FD0, the first storage capacitor element C1 and the second storage capacitor element C2 and mixed, and the first pixel signal, the second pixel signal and the third pixel signal are based on the signal charge generated by the photodiode PD of one pixel circuit 3 during the same exposure period.

[0174] This allows the first frame for low illumination, the second frame for medium illumination, and the third frame for high illumination to be simultaneously exposed and generated within one frame period, thereby expanding the dynamic range and suppressing noise during reset.

[0175] Here, the solid-state imaging device may also include a control circuit, which reads out a first pixel signal for constituting a first frame, a second pixel signal for constituting a second frame, and a third pixel signal for constituting a third frame from the pixel circuit 3, wherein the second frame is a frame for higher illumination than the first frame, and the third frame is a frame for higher illumination than the second frame, the first pixel signal corresponds to the signal charge transferred from the photodiode PD to the charge storage unit FD0, the second pixel signal corresponds to the signal charge transferred from the photodiode PD to the charge storage unit FD0 and the first storage capacitor element C1 and mixed, the third pixel signal corresponds to the signal charge transferred from the photodiode PD to the charge storage unit FD0, the first storage capacitor element C1 and the second storage capacitor element C2 and mixed, and the first pixel signal, the second pixel signal and the third pixel signal are based on the signal charge generated by the photodiode PD of one pixel circuit 3 during different exposure periods.

[0176] Thus, within one frame period, the first frame for low illumination, the second frame for medium illumination, and the third frame for high illumination can be exposed and generated at different timings, thereby expanding the dynamic range and suppressing kTC noise during reset.

[0177] Here, the first reset transistor RS and at least a control signal input to the first reset transistor RS may have a ramp-shaped voltage waveform so that the state of the transistor gradually shifts from the on state to the off state.

[0178] According to this, the reset is performed by the negative feedback circuit 21 , and thus the occurrence of reset noise can be further suppressed.

[0179] Here, the solid-state imaging device may further include: a measuring unit that measures the reset noise level of pixel circuits 3 belonging to a predetermined area among the plurality of pixel circuits 3; and a determining unit that determines the slope of the ramp-shaped voltage waveform based on the measurement result so as to reduce the deviation of the reset noise level.

[0180] This makes it possible to suppress the reset noise level in accordance with the characteristics of the solid-state imaging device.

[0181] Here, the measuring unit may measure the reset level while changing the slope of the voltage waveform for each row of pixel circuits belonging to the specified area, and the determining unit may determine the optimal slope of the voltage waveform based on the deviation of each row of pixel circuits belonging to the specified area.

[0182] With this, even if the characteristics of the solid-state imaging device vary, the reset noise level can be appropriately suppressed.

[0183] Here, the solid-state imaging device may include a negative feedback circuit 21 for each column of a plurality of pixel circuits 3 arranged in a matrix or for each pixel circuit 3, and the negative feedback circuit 21 may include a first feedback amplifier, which outputs a feedback signal to the first reset transistor RS of the pixel circuit 3 belonging to the corresponding column or to the first reset transistor RS of the corresponding pixel circuit 3.

[0184] With this configuration, the negative feedback circuit 21 can be provided for each column of the pixel circuits 3 or for each pixel circuit 3 .

[0185] Here, the negative feedback circuit 21 may be configured for each column, the pixel circuit (3) may further include a second reset transistor RS2 for resetting the charge storage unit FD0, and the negative feedback circuit 21 may further include a second feedback amplifier for outputting a feedback signal to the second reset transistor RS2 of the pixel circuit 3 belonging to the corresponding column.

[0186] This allows two different pixel rows to be reset by the negative feedback circuit 21. For example, one row can be reset at the start of exposure, while the other row can be reset at the time of reading.

[0187] Here, the solid-state imaging device may include a first semiconductor chip and a second semiconductor chip bonded together, the first semiconductor chip having a photodiode PD and a first storage capacitor element C1 / C4 for each pixel circuit, and the second semiconductor chip having a first feedback amplifier corresponding to each column of the pixel circuit or corresponding to each pixel circuit.

[0188] Based on this, the flexibility of the configuration design of the negative feedback circuit 21 and the first storage capacitor element C1 can be improved, and negative feedback can be applied on a column-by-column or pixel-by-pixel basis, thereby reducing parasitic resistance and parasitic capacitance. By increasing the speed, high-frequency noise can be reduced, and reset noise can be reduced.

[0189] Here, the negative feedback circuit 21 may be configured for each pixel circuit, and the solid-state imaging device may include a first semiconductor chip and a second semiconductor chip bonded together, the first semiconductor chip may include a photodiode PD for each pixel circuit, and the second semiconductor chip may include a first feedback amplifier and a first storage capacitor element C1 / C4 corresponding to each pixel circuit.

[0190] This allows negative feedback to be applied to each pixel, thereby increasing the speed of the operation. This also reduces high-frequency noise and significantly reduces reset noise.

[0191] Here, the solid-state imaging device may include a first semiconductor chip and a second semiconductor chip bonded together, wherein the first semiconductor chip includes a photodiode PD and a charge storage unit FD0 for each pixel circuit, and the second semiconductor chip includes a first storage capacitor element C1 / C4 for each pixel circuit.

[0192] With this, the photodiode PD and the storage capacitor element C can be mounted on the first semiconductor chip for each pixel, and the storage capacitor element can be mounted on the second semiconductor chip for each pixel, thereby significantly expanding the dynamic range.

[0193] Furthermore, a camera device involved in one form of the present disclosure includes the above-mentioned solid-state camera device, and the camera device corresponds to at least one of a monitoring system for a transport machine, a sensor system for an ADAS advanced driver assistance system, and a sensor system for autonomous driving, and the camera device is mounted on at least one of the front end, surroundings, sides, rear end, and interior rearview mirror of the transport machine.

[0194] Hereinafter, a solid-state imaging device according to an embodiment of the present disclosure will be described with reference to the drawings.

[0195] (Implementation 1A)

[0196] First, a configuration example of a solid-state imaging device according to this embodiment will be described. Figure 1A A configuration example in which one stage of storage circuits is provided in the vertical direction in the first configuration example will be described in detail.

[0197] [1A.1 Configuration Example of Solid-State Imaging Device 100]

[0198] Figure 2 This is a block diagram showing a configuration example of the solid-state imaging device 100 according to Embodiment 1A.

[0199] The solid-state imaging device 100 shown in the figure includes a pixel array section 10, a horizontal scanning circuit 12, a vertical scanning circuit 14, a plurality of vertical signal lines 19, a timing control section 200, a column processing section 26, a reference signal generating section 27, an output circuit 28, and signal processing sections 70 and 80. Furthermore, the solid-state imaging device 100 includes an MCLK terminal for receiving an external master clock signal, a DATA terminal for transmitting and receiving commands and data to and from the outside, and a D1 terminal for transmitting image data to the outside. In addition, the solid-state imaging device 100 includes terminals for receiving power supply voltage and ground voltage.

[0200] The pixel array unit 10 includes a plurality of pixel circuits 3 arranged in a matrix. Figure 2The pixels are arranged in n rows and m columns. Each pixel circuit 3 includes a high-sensitivity pixel, storage capacitors (C1, C2, C3, C4), an overflow element (OF), gain control elements (GC1, GC2, GC), a charge storage transfer element (TGC), and a charge transfer element (TG). The overflow element is also called an overflow gate.

[0201] The horizontal scanning circuit 12 sequentially scans the memories 256 in the plurality of column AD circuits 25 to output the AD-converted pixel signals to the signal processing units 70 and 80 via horizontal signal lines. This scanning may be performed in the same order as the arrangement of the column AD circuits 25 .

[0202] The vertical scanning circuit 14 scans the horizontal scanning line group (also referred to as the row control line group) 15 provided for each row of pixel circuits 3 within the pixel array section 10 on a row-by-row basis. Accordingly, the vertical scanning circuit 14 selects pixel circuits 3 on a row-by-row basis and simultaneously outputs pixel signals from the pixel circuits 3 belonging to the selected row to m vertical signal lines 19. The number of horizontal scanning line groups 15 provided is equal to the number of rows of pixel circuits 3.

[0203] exist Figure 2 n horizontal scanning line groups 15 are set in Figure 2 The horizontal scanning line group 15 includes: reset control line Transfer control line for charge storage Gain control line Select control line and overflow control line

[0204] The vertical signal line 19 is provided for each column of the pixel circuit 3 in the pixel array section 10, and transmits the pixel signal from the pixel circuit 3 belonging to the selected row to the column AD circuit 25. The plurality of vertical signal lines 19 are as follows: Figure 2 As shown in FIG, it is composed of m+1 vertical signal lines (H0, ..., Hm). Multiple ADC input lines are as follows Figure 2 As shown, it is composed of m+1 ADC input lines (ADIN0, ..., ADINm).

[0205] The ramp signal generating unit 30 determines the slope of the control signal of the following control line as the control signal switching element of the pixel transistor, generates the optimal ramp signal, and reduces the reset noise. The above-mentioned control line includes at least the reset control line It also includes a transfer control line for storing charge Gain control line and overflow control line

[0206] The vertical scanning circuit 14 provides the output signal supplied from the ramp signal generating section 30 as a pixel control signal ( V1 , V2 , . . . , Vn) based on the control signal group CN1 .

[0207] The timing control unit 200 controls the entire solid-state imaging device 100 by generating various control signal groups. These control signal groups include control signal groups CN1, CN2, CN4, CN5, and CN8, as well as counter clock signals CK0 and CK1. For example, the timing control unit 200 receives the master clock MCLK via a terminal, generates various internal clocks, and controls the horizontal scanning circuit 12, the vertical scanning circuit 14, and the like.

[0208] The column processing unit 26 includes a column AD circuit 25 provided for each column. Each column AD circuit 25 performs AD conversion on a pixel signal from a vertical signal line 19 .

[0209] Each column AD circuit 25 includes a feedback amplifier FA, a voltage comparator 252 , a counter unit 254 , and a memory 256 .

[0210] The feedback amplifier FA compares the analog pixel signal from the vertical signal line 19 with the reference signal VREF generated by the reference signal generating unit 29. For example, when the reference signal VREF becomes larger than the pixel signal, the output signal is fed back to the pixel to increase the pixel signal, thereby forming a negative feedback circuit 21. The multiple output signal lines of the feedback amplifier FA, namely the feedback lines 20, are arranged in a Figure 2 The number of columns in the image is (m+1), which is the same as the number of columns in (H0, ..., Hm), or 2x(m+1), which is twice the number of columns. Alternatively, the number of columns may be (m+1) when the shutter and reset are performed simultaneously, or 2x(m+1) when the shutter and reset are performed separately.

[0211] The voltage comparator 252 compares the analog pixel signal from the vertical signal line 19 with the reference signal RAMP including a ramp waveform (i.e., a triangular wave) generated by the reference signal generating unit 27, and inverts the output signal showing the comparison result when the former becomes larger than the latter.

[0212] The counter section 254 counts the time from when the triangular wave in the reference signal RAMP starts to change until the output signal of the voltage comparator 252 inverts. Since the time until inversion is determined by the value of the analog pixel signal, the count value becomes the value of the digitized pixel signal.

[0213] The memory 256 holds the count value of the counter section 254 , that is, holds a digital pixel signal.

[0214] The reference signal generating section 27 generates a reference signal RAMP including a triangular wave, and outputs the reference signal RAMP to the positive input terminal of the voltage comparator 252 in each column AD circuit 25 .

[0215] The output circuit 28 outputs a digital pixel signal to the image data terminal D1 .

[0216] The signal processing unit 70 includes a WDR synthesis circuit 76 and is composed of a memory 77 , a low illuminance signal generation circuit 71 , a medium illuminance signal generation circuit 72 , a high illuminance signal generation circuit 73 , and the WDR synthesis circuit 76 .

[0217] The signal processing unit 80 detects the reset noise of the reset noise detection area through the noise calculation circuit 86, and holds the optimal value of the noise in the optimal value holding circuit 87. In addition, the reset noise detection area may be, for example, Figure 3 OB area A14 or Figure 4 The front OB area A15. Figure 3 as well as Figure 4 The figure shows a plurality of regions within the pixel array section 10. The OB region A14 is a region including optical black pixels. The pre-OB region A15 is a region within the OB region used for a specific purpose such as reset noise detection. The effective region A16 is a region including the pixel circuit 3 used to form an image by photographing. Then, when the signal processing section 80 completes the search in the reset noise detection region, it sends the optimal value to the timing control circuit, and the ramp signal generating section 30 generates the optimal ramp voltage at the time of the reset noise detection region. Figure 3 Read the signal of the effective area A16 in Figure 4 The signals of the OB area A14 and the effective area A16 are read out.

[0218] As a result, the signal processing units 70 and 80 can be expected to achieve an expansion of the dynamic range and an improvement in SN.

[0219] In some cases, the vertical scanning circuit 14, reference signal generating unit 27, reference signal generating unit 29, ramp signal generating unit 30, and feedback line 20 are collectively referred to as a driving unit. The column processing unit 26 and horizontal scanning circuit 12 are collectively referred to as a control unit. The noise calculation circuit 86 is sometimes referred to as a measuring unit. The optimal value holding circuit 87 is sometimes referred to as a determining unit.

[0220] [1A.2 Example of Pixel Circuit Configuration]

[0221] Next, a configuration example of the pixel circuit 3 will be described.

[0222] Figure 5FIG1 shows an example circuit including the important parts of the pixel circuit 3 and the negative feedback circuit 21 according to Embodiment 1A. The pixel circuit 3 in the figure includes a photodiode PD, a transfer transistor TG, a storage capacitor element C1 and a floating diffusion layer FD1, a parasitic capacitor C0 and a floating diffusion layer FD0, a reset transistor RS, a gain control transistor GC1, an amplifier transistor SF, and a select transistor SEL.

[0223] Furthermore, the horizontal scanning line group 15 includes a reset control line Read control line Gain control line and select control lines

[0224] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates electric charge according to the amount of received light.

[0225] Furthermore, capacitor C0 connected to floating diffusion layer FD0 holds signal charge (e.g., electrons) transferred from photodiode PD, converts the held signal charge into a voltage, and supplies the converted voltage to the gate of amplifier transistor SF. The actual capacitance of floating diffusion layer FD0 includes not only the capacitance of floating diffusion layer FD0 itself but also the gate capacitance of amplifier transistor SF, the capacitance between the gate and drain of amplifier transistor SF, and the parasitic capacitance of the source wiring of gain control transistor GC1 when gain control transistor GC1 is off.

[0226] The transfer transistor (TG) is switched according to the read control signal The switching transistor that turns on and off. The transfer transistor TG reads the control signal When the level is high, the signal charge photoelectrically converted by the photodiode PD is transferred to the floating diffusion layer FD.

[0227] When the signal charge photoelectrically converted by the photodiode PD overflows the storage capacitor C1, the signal charge is transferred by adjusting the control voltage of the gain control element GC1, or when the signal charge exceeds a preset potential.

[0228] The reset transistor RS is in accordance with the reset control signal The switching transistor is turned on and off. The reset transistor RS is reset when the control signal When the reset control signal is high, the power supply voltage applied to the drain is used as the reset level and is set to the floating diffusion layer FD0 via the gain control transistor GC1. When it is at a high level, the floating diffusion layer FD0 is reset to a reset level.

[0229] The gain control transistor GC1 is set according to the gain control signal The floating diffusion layer FD0 and the floating diffusion layer FD1 are electrically disconnected or connected. This changes the conversion gain for converting the signal charge in the floating diffusion layer FD0 into a voltage. Specifically, when the gain control transistor GC1 is turned off during the transfer of signal charge from the photodiode PD to the floating diffusion layer FD0, the conversion gain of the floating diffusion layer FD0 can be increased to C0. Conversely, when the gain control transistor GC1 is turned on, the floating diffusion layers FD0 and FD1 are connected, reducing the conversion gain to C0 + C1.

[0230] The amplifier transistor SF and the load current source 30 connected to the vertical signal line 19 form a source follower, and outputs the gate voltage, ie, the voltage of the floating diffusion layer FD0 , to the vertical signal line 19 as an analog pixel signal.

[0231] The selection transistor SEL is selected according to the selection control signal The switching transistor is turned on and off. The selection transistor SEL selects the control signal When it is at a high level, the source of the amplifier transistor SF is electrically connected to the vertical signal line 19 .

[0232] [1A.3 Example of a BSI Configuration Using a Stacked Pixel Circuit and a Negative Feedback Circuit]

[0233] As pixel cells become increasingly smaller or the dynamic range is expanded, this can be achieved by increasing the aperture area of ​​the photodiode by providing a MIM capacitor or MOS capacitor on the wiring layer side opposite to the light-receiving side of the photodiode PD. Trench capacitors can be provided within the cell.

[0234] Furthermore, the solid-state imaging device 100 may be configured as a stacked back-illuminated image sensor.

[0235] Figure 6A This figure shows an example of a solid-state imaging device in Embodiment 1A configured as a stacked backside-illuminated image sensor. The solid-state imaging device in this figure includes a first semiconductor chip and a second semiconductor chip bonded together. The first and second semiconductor chips are bonded together on their respective wiring layer-side surfaces. In the figure, PD represents a photodiode PD, C represents a first storage capacitor element C1, and amp represents a feedback amplifier FA.

[0236] The first semiconductor chip is shown as a top chip in the figure and includes the main portion of the solid-state imaging device 100, which is a back-illuminated CMOS image sensor. The first semiconductor chip includes a photodiode PD of each pixel circuit 3 and a first storage capacitor element C1.

[0237] The second semiconductor chip is shown as a bottom chip in the figure, and includes main logic circuits such as signal processing units 70 and 80. The second semiconductor chip includes a feedback amplifier FA corresponding to each column of the pixel circuit 3.

[0238] In such a solid-state imaging device 100, each pixel is mounted on the top chip as a stacked BSI type CIS, and a feedback amplifier FA corresponding to each pixel column is mounted on the bottom chip. That is, the PD and storage capacitor element C can be mounted on the top chip for each pixel, and the feedback amplifier can be configured on the bottom chip for each column. Since negative feedback can be applied on a column basis, parasitic resistance and / or parasitic capacitance can be reduced to a certain extent, and high-frequency noise can be reduced by increasing the speed, and reset noise can also be reduced. Specifically, the top chip and the bottom chip can be provided with Figure 5 The connection points A, B, B′.

[0239] Figure 6B This example shows a solid-state imaging device in Embodiment 1A constructed as a stacked backside-illuminated image sensor. As a stacked BSI-type CIS, each pixel is mounted on a pixel chip (top chip), and a feedback amplifier is mounted on a logic chip (bottom chip) corresponding to each pixel. The top chip includes a photodiode PD and a storage capacitor element C for each pixel, while the bottom chip forms a feedback amplifier for each pixel. Because negative feedback can be applied to each pixel, parasitic resistance and / or parasitic capacitance can be reduced, high-frequency noise can be reduced by increasing the speed, and reset noise can be significantly reduced.

[0240] Figure 6C This example shows a solid-state imaging device in Embodiment 1A configured as a stacked backside-illuminated image sensor. As a stacked BSI CIS, each pixel is mounted on a pixel chip (top chip), and a feedback amplifier is mounted on a logic chip (bottom chip) corresponding to each pixel. A photodiode PD is mounted on the top chip for each pixel, while a storage capacitor element C and a feedback amplifier are configured for each pixel on the bottom chip. Since negative feedback can be applied to each pixel for faster processing, high-frequency noise can be reduced, and reset noise can be significantly reduced.

[0241] Figure 6D This example shows a solid-state imaging device in Embodiment 1A configured as a stacked backside-illuminated image sensor. As a stacked BSI CIS, each pixel is mounted on a pixel chip (top chip), and a feedback amplifier is mounted on the logic chip (bottom chip) corresponding to each pixel. The top chip can be equipped with a photodiode PD and a storage capacitor element C for each pixel, while the bottom chip can be configured to form a storage capacitor element C for each pixel, significantly expanding the dynamic range.

[0242] [1A.4 Characteristics Improvement by Polysilicon Plugs]

[0243] The following will describe the solid-state imaging device 100 as Figures 6A to 6D The following is an example of a pixel configuration in which back-illuminated image sensors are stacked.

[0244] Generally speaking, when the wiring at one end of a MIM (Metal Insulator Metal) capacitor or a MOS (Metal Oxide Semiconductor) capacitor is normally brought into contact with a substrate, damage occurs during the formation of the contact portion, and dark-time characteristics (dark current, noise, and fixed pad) become a problem.

[0245] In addition, if the wiring connected to the substrate at one end of the MIM capacitor or MOS capacitor is not metal wiring but a polysilicon plug of polysilicon wiring, damage to the connection part can be reduced and dark time characteristics (dark current, noise, fixed disk) can be suppressed.

[0246] Moreover, if the wiring connected to the substrate at one end of the gate wiring of the amplifier transistor SF is not a metal wiring but a polysilicon plug (polysilicon contactor (n)) of a polysilicon wiring, damage to the connection portion can be reduced and dark time characteristics (dark current, noise, fixed disk) can be suppressed.

[0247] Furthermore, if the potentials (A, B, and C) of the plugs that store signal charge (negative charge) in the capacitor element are higher than the GND potential, dark-time characteristics (dark current, noise, and fixed pad) will increase. Therefore, by setting the potential (VC1) on the opposite side of the capacitor element C1 to a potential midway between GND and the pixel potential during exposure, dark-time characteristics can be improved.

[0248] [1A.5 HCG reading operation example]

[0249] Then, Figure 5 The following describes the HCG (High Control Gain) readout operation in the solid-state imaging device 100. The HCG readout operation is an imaging operation in which the first transistor GC1 is turned off, eliminating the use of the first storage capacitor C1. Instead, only the floating diffusion layer FD0 is used to accumulate signal charge, increasing the conversion gain of the amplifier transistor SF. Therefore, the HCG operation provides high sensitivity and is suitable for imaging in low-light environments. In the CDS (Correlated Double Sampling) method of the HCG readout operation, the signal level is read after the reset level of the analog pixel signal. The CDS method takes the difference between the reset level and the signal level.

[0250] Figure 7 1A is a timing chart showing the n-time exposure operation of the solid-state imaging device 100 by the HCG readout operation in the embodiment 1A.

[0251] The down-count period is used to perform A / D conversion on the reset component level in the analog pixel signal output from amplifier transistor SF. Counter section 254 counts down the time from the start of the down-count period (when the triangular wave begins to change) until the output of voltage comparator 252 inverts. This count value is the A / D conversion result of the reset component Vrst of the analog pixel signal itself.

[0252] The up-count period is used to perform A / D conversion on the level of the data component in the analog pixel signal output from amplifier transistor SF. The counter unit counts up the time from the start of the up-count period (when the triangular wave begins to change) until the output of voltage comparator 252 inverts. This up-count converts the data component in the analog pixel signal into a digital value.

[0253] Because this up-counting process uses the down-count value representing the reset component as the initial value, the count value at the end of the up-counting period represents the result of CDS (Correlated Double Sampling), which subtracts the reset component from the data component. In other words, the count value at the end of the up-counting period is the digital value representing the signal component itself. In this way, the column AD circuit 25 eliminates errors caused by variations such as clock skew and counter delay between columns and extracts only the true signal component, i.e., performs digital CDS.

[0254] [1A.6LCG readout example]

[0255] Then, Figure 5 The LCG (Low Control Gain) readout operation in FIG100 is described below. LCG readout operation turns on the first transistor GC1 and utilizes the first storage capacitor C1 to capture signal charge. The floating diffusion layer FD0 and the first storage capacitor C1 are used to accumulate signal charge, thereby reducing the conversion gain of the amplifier transistor SF. Therefore, LCG operation is a low-sensitivity capture operation suitable for capturing images in high-illumination environments. In CDS (Correlated Double Sampling) during LCG readout, after the signal level is read, the feedback amplifier FA reads the reset level. In other words, in LCG readout, the order of reading the signal level and reset level is reversed compared to HCG readout.

[0256] Figure 8 The readout order of one frame in the LCG readout operation of embodiment 1A is shown.

[0257] The gain of converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between high gain and low gain according to the on and off state of the gain control transistor GC1.

[0258] In the case of HCG readout working as Figure 7 As shown, the normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component). This transition is the readout of signal charge from the photodiode PD to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high. Since this transition is normal CDS, reset noise can be eliminated and reduced to zero.

[0259] Figure 9 The image shows the readout order of pixel signals for CDS during LCG readout. In the case of LCG, the sequence is LCG (S: signal component) → LCG (R: reset component). This transition reads signal charge from storage capacitor element C0 and storage capacitor element C1 to floating diffusion layer FD0, when the conversion gain of floating diffusion layer FD1 is low.

[0260] This transition can eliminate DC offset (reset coupling), but cannot eliminate pixel reset noise, which remains as kTC noise.

[0261] The terms "long exposure," "middle exposure," and "short exposure" may also be defined here. Originally, long exposure refers to exposure for low illumination with a longer exposure time, middle exposure refers to exposure for medium illumination with a medium exposure time, and short exposure refers to exposure for high illumination with a shorter exposure time. In this specification, when all frames have the same exposure time, the terms "long," "middle," and "short" do not imply different exposure times. Instead, they define long exposure as exposure for low illumination, middle exposure as exposure for medium illumination, and short exposure as exposure for high illumination.

[0262] The kTC noise in the short exposure (high illumination) appears on the low illumination side. Figure 18B As shown. Here, kTC noise, when expressed in terms of charge, can be expressed as √(kTC). This noise must be set sufficiently smaller than the signal level. Thus, at the boundary between short exposure (high illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0263] [1A.7 Configuration and Operation Example of Negative Feedback Circuit]

[0264] At high illumination levels, turning on the storage capacitor element C can reduce reset noise and increase the maximum subject illumination through the negative feedback circuit 21. Generally, when the control voltage of the reset transistor and the control voltage of the gain control element GC1 are suddenly turned off (OFF), reset noise (kTC noise) is generated in the storage capacitor element (C1) and capacitor C0.

[0265] As a countermeasure, a switching element is provided between the photodiode PD and the storage capacitor element (C1). One end of the switching element is connected to the negative input terminal of the feedback amplifier via the SF element and a vertical signal line. The other end of the switching element is connected to the feedback line 20, which serves as the feedback output signal, to form negative feedback. The switching element may also be a reset transistor or a gain control element GC1. A DC reference voltage VREF is connected to the positive input terminal of the feedback amplifier.

[0266] Furthermore, the control signal input to at least the first reset transistor RS among the first transistor GC1, the transfer transistor TG, and the first reset transistor RS has a ramp-shaped voltage waveform that gradually shifts from an on state to an off state. Hereinafter, a signal having a ramp-shaped voltage waveform is referred to as a ramp signal.

[0267] Figure 10A The waveform of the ramp signal is shown in FIG. Figure 10A As shown, the control voltage of the reset transistor and the control voltage of the gain control element GC1 are used as ramp signals and change smoothly. Figure 10B The relationship between the tilt period and the reset noise level is shown in FIG. Figure 10B The reset noise shown in the figure, while applying negative feedback, causes the input voltage at one end of the feedback amplifier to approach the reference voltage VREF. As these two potentials approach each other, the rate of change of the voltage at the FD portion decreases. When these two potentials are equal, the potential at the FD portion becomes constant.

[0268] Then, the operation can be terminated by finally isolating the feedback amplifier from the negative feedback circuit 21 .

[0269] Finally, by subtracting the reset component from the signal component, reset noise can be reduced, and the signal can be extracted in a good SN state.

[0270] Here, the bandwidth of the feedback amplifier may preferably be larger than the bandwidth of the pixel portion. In this case, the high-frequency component of the reset noise can be efficiently eliminated.

[0271] As described above, in this embodiment, it is possible to achieve both an expansion of the dynamic range and an improvement of the SN.

[0272] Figure 11The timing related to charge accumulation in the photodiode PD and storage capacitor element C1 is shown. Photodiode PD is continuously exposed during a 1V period (one vertical synchronization period), resulting in a charge amount of Q0. Storage capacitor element C1 receives the charge overflowing from the photodiode PD as the Q1 signal. Q0 and Q1 are exposed at exactly the same timing.

[0273] In the rolling shutter method, reset is performed row by row through row scanning. Exposure begins after this, with exposure time represented by T_Q0 = T_Q1. Next, the charge from the photodiodes is read out to the storage capacitor C1 row by row. After this, the signal charge from the storage capacitor C1 is read out using the rolling shutter method.

[0274] The timing example of the HCG reading operation in the state where the storage capacitor element C1 is not connected is the same as that of the Figure 7 same.

[0275] The timing example of the LCD readout operation in the state where the storage capacitor element C1 is connected is shown by Figure 8 Shown.

[0276] First, between times t1 and t2, the photodiode PD and FD0 and FD1 are reset, waiting for the start of exposure. Then, between times t3 and t4, the shutter is activated, and exposure begins. At time t5, the exposure period ends. Between times t5 and t6, the signal charge accumulated in the photodiode is transferred to FD0 and FD1 via the transfer signal (TG). Between times t6 and t7, the signal component is read. Next, between times t7 and t8, a reset operation is performed. Between times t8 and t9, the reset component is read.

[0277] Here, reset noise may also occur during the shutter period between times t3 and t4, and during the reset period between times t7 and t8. Therefore, during these periods, the negative feedback circuit 21 operates to gradually turn off the reset transistor RS, reducing the reset noise. Here, a ramp-shaped signal is applied to the reset transistor (RS) at this time.

[0278] Conventionally, since there are photodiodes PD and storage capacitor elements C but no transmission elements Tr and switching elements, it is not possible to selectively switch between low illuminance and high illuminance.

[0279] In this embodiment, during low illumination, the signal charge accumulated in the photodiode is transferred via the transmission Tr and read out after the CDS, completely eliminating reset noise. Furthermore, during high illumination, the signal charge accumulated in the photodiode and the storage capacitor are read out via the switching element. During shutter and reset operations, the negative feedback circuit 21 reduces reset noise, significantly improving SN. This allows for selective switching between low and high illumination.

[0280] [1A.8 Circuit Example of a Ramp Signal as a Control Signal for a Switching Element]

[0281] In this embodiment, the circuit comprises a photodiode PD, a transfer transistor (TG), and a negative feedback circuit 21. The negative feedback circuit 21 comprises a reset transistor, a switch element, storage capacitors (C1 and C2), an amplifier transistor SF, and a feedback amplifier. The switch element comprises gain control elements (GC1, GC2, GC) and a charge storage transfer element (TGC). An overflow element (OF) may also be added.

[0282] As described above, the control signals of these reset transistors and switch elements are turned OFF (cut off) by applying gentle ramp-shaped signals during shuttering and reading, so that the negative feedback circuit 21 operates smoothly and reset noise is reduced. Figure 10A The ramp signal is shown to be gradually turned OFF during the ramp period. Figure 10B The relationship between the ramp period and the reset noise level is shown in FIG. As can be seen from the figure, although the noise level drops sharply at the beginning of the ramp period, it gradually decreases after a certain period of time.

[0283] The problem here is that variations in switching element performance can occur due to the manufacturing process, power supply voltage, and temperature. Process-related variations can be fixed to optimal values ​​during shipping inspection. However, variations in power supply voltage and temperature, which occur during actual operation, require correction during operation.

[0284] Figure 2 The circuit as a countermeasure is shown. The ramp signal generating unit 30 has a built-in DAC circuit. First, the ramp signal is generated using the clock CK1 and the control signal CN5 sent from the timing control unit 200. The ramp signal is configured to be Figure 3 OB area A14 or Figure 4 When the noise component of the leading OB area A15 is detected, the signal is read out every 1H by the control signal CN5, and the slope of the ramp is determined by the clock CK1.

[0285] Figure 12A Horizontal scanning lines serving as calculation units for the deviation of reset noise are shown. Figure 12B The reset noise detection area is read out by the noise calculation circuit 86 in the signal processing unit 80 according to the reset noise detection area. Figure 12A As shown in 1H (i.e. 1 horizontal scan), it becomes Figure 12B The normal distribution of the noise signal is calculated, and the σ (standard deviation) of the noise signal is calculated, and the optimal slope setting is maintained by the optimal value holding circuit 87.

[0286] The optimum value here is a value when the signal readout in the reset noise detection region is the minimum value, or when the difference before and after the slope of the ramp-shaped voltage changes is equal to or smaller than a desired value.

[0287] Furthermore, the slopes of the reset transistor, overflow element OF or gain control element GC1, GC2, and charge storage transmission element TGC that constitute the switching element can be determined by operating each optimal value every 1H and selecting them in sequence, or by operating all optimal values ​​every 1H and selecting them in sequence.

[0288] The signal processing unit 80 changes the slope of the voltage waveform for each row of pixel circuits belonging to a predetermined area, i.e., a reset noise detection area, while measuring the reset level, calculates the deviation σ (standard deviation), and determines the optimal slope of the voltage waveform based on the deviation of each row of pixel circuits belonging to the predetermined area.

[0289] [1A.9 Operation Example of a Ramp Signal as a Control Signal for a Switching Element]

[0290] In this embodiment, the Figure 3 OB area A14 or Figure 4 The leading OB area generates a ramp signal.

[0291] Figure 13 This is a flowchart showing an example of a process for generating a ramp signal. First, in <S1>, scanning of the first row of a frame is started, and in <S2>, the signal of the OB area A14 or the preceding OB area A15 is read. Here, in <S3>, the ramp signal is initialized and the reset control signal of the mHth is generated. In <S4>, the Figure 12B The standard deviation σ of the reset noise of the sHth is shown. In <S5>, the row scan is performed according to the algorithm for searching the optimal noise level σ. By repeating the operations of <S4> <S5>, the ramp signal with the optimal noise level σ is selected. In <S6>, the selection signal is used to control Figure 3 Valid area A16 or Figure 4Here, the mHth and sHth are values ​​set by an algorithm.

[0292] and, Figure 14 This is a flowchart showing another example of processing for generating a ramp signal. First, in <S1>, scanning of the first row of a frame is started, and in <S2>, the signal of the OB area A14 or the pre-OB area A15 is read. Here, in <S3>, the ramp signal is initialized and the reset control signal for the 1H is generated. In <S4>, the Figure 12B The standard deviation σ of the reset noise of the 1H is shown. In <S5>, the ramp signal is adjusted to generate the reset control signal of the 2H. In <S6>, the ramp signal is initialized to generate the reset control signal of the 1H. In this way, the standard deviation σ of the reset noise is calculated every 1H. In <S7>, the ramp signal is adjusted to generate the reset control signal of the nH. In <S8>, the ramp signal is initialized to generate the reset control signal of the nH. Then, in <S9>, the slope at which the standard deviation σ of the reset noise becomes the optimal value is determined. In <S10>, the reset control signal is initialized with the above-mentioned selection signal. Figure 3 The effective area A16 or Figure 4 It is controlled by the signal of the front OB area A15.

[0293] and, Figure 15 This is a flowchart showing another example of processing for generating a ramp signal. First, in <S1>, scanning of the first row of a frame is started, and in <S2>, the signal of the OB area A14 or the pre-OB area A15 is read. Here, in <S3>, the ramp signal is initialized and the reset control signal for the first H is generated. In <S4>, the 1H reset signal is calculated. Figure 12B The standard deviation σ of the reset noise in the first hour is shown in FIG. In < S5 >, the ramp signal is adjusted to generate the reset control signal in the second hour.

[0294] In <S6>, the noise level σ of the 2H is calculated, the difference from the previous row is calculated, and compared with the desired value. If the difference is less than the desired value, the value is considered to be the optimal value, and in <S10> the selection signal is used to select the optimal value. Figure 3 The valid area shown or Figure 4 The OB area is controlled by the signal shown.

[0295] On the contrary, when the difference is equal to or greater than the desired value, the operation is repeated until nH is reached.

[0296] In < S7 >, the ramp signal is adjusted to generate an nH-th reset control signal.

[0297] In <S8>, the noise level σ of the nHth row is calculated, the difference from the previous row is calculated, and compared with the desired value. If the difference is less than the desired value, the value is considered to be the optimal value, and in <S10> the selection signal is used to select the optimal value. Figure 3 The valid area shown or Figure 4 The OB area is controlled by the signal shown.

[0298] On the contrary, when the difference is greater than the desired value, the ramp signal with the noise level σ closest to the desired value is selected in <S9>. Then, in <S10>, the selected signal is used to control Figure 3 The effective area A16 or Figure 4 The signal of the front OB area A15 is shown.

[0299] exist Figure 3 OB area A14 is set as the reset noise detection area. This setting has the advantage of minimizing chip area expansion. However, since the gain of OB area A14 is set to the same value as the gain of active area A16, detection accuracy deteriorates when the gain is low. Furthermore, significant reset noise may overlap in the OB area.

[0300] exist Figure 4 The advantage of this setting is that reset noise can be detected while maintaining a constant gain. Therefore, increasing the gain for detection improves accuracy, enabling stable detection.

[0301] [1A.10 Expansion of dynamic range]

[0302] The characteristic of this embodiment is that WDR synthesis is not performed, but a low illumination area or a high illumination area is selected according to the illumination conditions to expand the dynamic range.

[0303] For example, it is possible to use a low illumination frame at night and a high illumination frame during the day, etc. Alternatively, a low illumination frame or a high illumination frame may be selected according to the instantaneous illumination during driving.

[0304] At this time, the two frames, Long and Short, are exposed at exactly the same timing, and since exactly the same pixels are used, no false color, shading, or blurring occurs.

[0305] Figure 16 An overview of how WDR is implemented within a pixel is shown. Figure 29The figure shows an example configuration of a signal processing unit 70 that performs WDR synthesis using two frames. However, in this embodiment, since synthesis is not performed, there is no need to include a WDR synthesis circuit 76. WDR is implemented by using a signal charge of Q0 for long exposure (low illumination) and a signal charge of (Q0 + Q1) for short exposure (high illumination).

[0306] Figure 16 The horizontal axes [1][2][3][4] show the product of illuminance and exposure time, illuminance for a certain time, or exposure time at a certain illuminance. Regarding the vertical axes, [1] shows the charge accumulation level. [2] shows the FD potential. [3] shows the value after AD conversion. [4] shows the SN.

[0307] Figure 17 The FD potential in the HCG readout operation for a low illumination frame and the LCG readout operation for a high illumination frame are shown. Hereinafter, the HCG readout is referred to as Read1 and the LCG readout is referred to as Read2.

[0308] Figures 18A to 18D The relationship between the subject illuminance and the gain (SN) according to Embodiment 1A is shown. Figure 18A As a comparative example, the relationship between the subject illuminance and the gain (SN) in LCG readout in a case where the negative feedback circuit 21 is not provided is shown. Figure 18B The relationship between the subject illumination and the gain (SN) in the LCG readout according to Embodiment 1A is shown.

[0309] Figure 18C As a comparative example, the relationship between the subject illuminance and the gain (SN) in HCG reading is shown in the case where the negative feedback circuit 21 is not provided. Figure 18D The relationship between the subject illumination and the gain (SN) in HCG reading according to Embodiment 1A is shown.

[0310] Figure 18B and Figure 18D It is the Long frame of Read1 (ie, HCG readout for low illumination frame), and is equal because no reset noise occurs.

[0311] Figure 18A and Figure 18C The Short frame of Read2 (i.e., LCG readout for high illumination frame) is shown. Figure 18A That generates reset noise, but by Figure 18CThe reduction in reset noise shown in the figure shows that the SN has improved at low illumination levels. Furthermore, the dynamic range has been expanded from very dim illumination (0.1 Lux) to very bright illumination (100,000 Lux: equivalent to sunlight), exceeding 120 dB, due to the effect of storage capacity. The SN at the connecting portion of the frame has also been reduced to over 20 dB.

[0312] Without the need for WDR synthesis, low-illuminance areas or high-illuminance areas can be selected according to the illumination conditions to expand the dynamic range, thereby improving noise under low illumination and expanding the dynamic range under high illumination.

[0313] As described above, according to this embodiment, it is possible to achieve both improvements in dynamic range and SN while reducing the reset noise of the storage capacitor element.

[0314] (Implementation 1B)

[0315] Embodiment 1A has described the readout using the rolling shutter method, but Embodiment 1B can also support the readout using the global shutter method.

[0316] Compared to a rolling shutter, a global shutter method can suppress distortion when photographing fast-moving objects.

[0317] The solid-state imaging device 100 in Embodiment 1B differs from that in Embodiment 1A mainly in that the vertical scanning circuit 14 can also be driven in accordance with a global shutter.

[0318] [1B.1 Configuration and Operation Example of Negative Feedback Circuit]

[0319] Figure 19 The timing of charge accumulation in the photodiode PD and storage capacitor element C1 is shown. Photodiode PD is continuously exposed during a 1V period (one vertical synchronization period), resulting in a charge amount of Q0. Storage capacitor element C1 receives the charge overflowing from the photodiode PD as the Q1 signal. Q0 and Q1 are exposed at exactly the same timing.

[0320] In the global shutter method, a global reset is performed on all pixels simultaneously. After this, exposure begins, with the exposure time represented by T_Q0 + Q1. Next, the charge from the photodiode to the storage capacitor C1 is read out simultaneously. After this, the signal charge from the storage capacitor C1 is read out using the rolling shutter method.

[0321] The read timing in the state where the storage capacitor element C1 is connected (ie, LCG read operation) is shown by Figure 20A Shown.

[0322] use Figure 20AThe timing will be explained.

[0323] First, between times t1 and t2, the photodiode PD and FD0 and FD1 are reset, waiting for the start of exposure. Then, between times t2 and t3, the global shutter is activated, and exposure begins. At time t4, the exposure period ends. Between times t4 and t5, the signal charge accumulated in the photodiode is transferred to FD0 and FD1 via the transfer signal (TG). At time t5, the gain control transistor GC1 is turned on, setting a low conversion gain to accommodate more signal charge. From times t5 to t6, the wait is for the corresponding row to be read using a rolling shutter method. When the corresponding row is reached, the signal component is read between times t6 and t7. Next, a reset operation is performed between times t7 and t8. Between times t8 and t9, the reset component is read.

[0324] Here, reset noise occurs during the global shutter period between times t2 and t3, and reset noise also occurs during the reset period between times t7 and t8. Therefore, during these periods, negative feedback circuit 21 is activated to gradually turn off reset control signal RS, thereby reducing reset noise. This figure shows how a ramp-shaped signal is applied to the reset transistor (RS).

[0325] Figure 20B Shown Figure 20A As shown in the figure, in the LCG read operation, the signal component and the reset component are read in this order.

[0326] (Implementation 2A)

[0327] In embodiment 2A, Figure 1B The second configuration example of the embodiment having one storage circuit stage in the horizontal direction will be described in detail. The following description will focus on the differences from the embodiment 1A.

[0328] [2A.1 Example of Pixel Circuit Configuration]

[0329] Next, a configuration example of the pixel circuit 3 will be described.

[0330] Figure 21 FIG. 1 shows an example circuit including the essential parts of the pixel circuit 3 and the negative feedback circuit 21 according to Embodiment 2A. The pixel circuit 3 in the figure includes a photodiode PD, a transfer transistor TG, a storage capacitor element C2, a storage transfer transistor TGC, a floating diffusion layer FD0, a parasitic capacitor C0, a floating diffusion layer FD2, a reset transistor RS, an amplifier transistor SF, and a select transistor SEL.

[0331] Furthermore, the horizontal scanning line group 15 includes a reset control line Read control line Storage transfer transistor control line and select control lines

[0332] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates electric charge according to the amount of received light.

[0333] Furthermore, capacitor C0 connected to floating diffusion layer FD0 holds signal charge (e.g., electrons) transferred from photodiode PD, converts the held signal charge into a voltage, and supplies the converted voltage to the gate of amplifier transistor SF. The actual capacitance of floating diffusion layer FD0 is not only the capacitance of floating diffusion layer FD0 itself, but also includes the gate capacitance of amplifier transistor SF and the floating capacitance between the gate and drain of amplifier transistor SF.

[0334] The transfer transistor TG is connected to the readout control signal The transfer transistor TG reads the control signal When the voltage is high, the photodiode PD transfers the signal charge after photoelectric conversion to the floating diffusion layer FD.

[0335] The storage transfer transistor TGC is switched according to the read control signal The storage transfer transistor TGC reads the control signal. When at a high level, the signal charge accumulated in the storage capacitor element C4 is transferred to the floating diffusion layer FD0 .

[0336] When the signal charge photoelectrically converted by the photodiode PD overflows the storage capacitor element C4, the control voltage of the storage transfer transistor TGC is applied. Adjust to transmit. Or transmit when a preset potential is exceeded.

[0337] Furthermore, the storage capacitor element C0 changes the conversion gain for converting the signal charge in the floating diffusion layer FD0 into a voltage. Specifically, when transferring signal charge from the photodiode PD to the floating diffusion layer FD0, turning off the storage transfer transistor TGC increases the conversion gain of the floating diffusion layer FD0 to C0. Conversely, turning on the storage transfer transistor TGC connects the floating diffusion layers FD0 and FD1, allowing for greater signal charge storage. This reduces the conversion gain to C0 + C4.

[0338] The reset transistor RS is in accordance with the reset control signal The reset transistor RS is used to turn on and off the switch transistor. When the reset control signal is high, the power supply voltage applied to the drain is used as the reset level and is set to the floating diffusion layer FD0. When it is at a high level, the floating diffusion layer FD0 is reset to a reset level.

[0339] The amplifier transistor SF forms a source follower together with a load current source 30 connected to the vertical signal line 19 , and transmits the gate voltage, ie, the voltage of the floating diffusion layer FD0 , to the vertical signal line 19 as an analog pixel signal.

[0340] The selection transistor SEL is selected according to the selection control signal The switching transistor is turned on and off. The selection transistor SEL selects the control signal When it is at a high level, the source of the amplifier transistor SF is electrically connected to the vertical signal line 19 .

[0341] [2A.2 Configuration and Operation Example of Negative Feedback Circuit]

[0342] Figure 11 The timing of charge accumulation in the photodiode PD and the storage capacitor element C2 is the same as that in the embodiment 1A.

[0343] The timing example of the HCG reading operation in the state where the storage capacitor element C4 according to the embodiment 2A is not connected is similar to the timing example of the HCG reading operation in the embodiment 2A. Figure 7 same.

[0344] The timing example of the LCG read operation in the state where the storage capacitor element C4 is connected is shown by Figure 22 Shown.

[0345] First, between times t1 and t2, the photodiode PD and FD0 and FD1 are reset, waiting for the start of exposure. Then, between times t3 and t4, the shutter is activated, and exposure begins. At time t5, the exposure period ends. At time t5, the accumulation transfer transistor TGC is turned on, allowing a low conversion gain to be set to receive more signal charge. Between times t5 and t6, the signal charge accumulated in the photodiode is transferred to FD0 and FD1 via transfer signal TG. Between times t6 and t7, the signal component is read out. Next, a reset operation is performed between times t7 and t8. Between times t8 and t9, the reset component is read out.

[0346] Here, reset noise is generated during the shutter period between time t3 and t4, and reset noise is generated during the reset period between time t7 and t8. Therefore, by making the negative feedback circuit 21 play a role during this period, the reset control signal RS and the accumulated charge transmission element TGC are smoothly cut off, thereby reducing the reset noise. The reset transistor (RS) and the accumulated charge transmission element (TGC) at this time are applied with a ramp-shaped signal as shown by the solid line. Alternatively, as another method, the negative feedback circuit 21 is played a role during the shutter period between time t3 and t4, the reset control signal RS is smoothly cut off, and the accumulated charge transmission element TGC is sharply cut off as shown by the dotted line. At this time, through the law of charge accumulation, although the reset noise of the storage capacitor element C4 does not decrease, it generates reset noise in the positive and negative directions at FD0. Until the signal is read out (LCG), since the FD part is not reset, the reset noise of the storage capacitor element C4 and the FD part at this time is eliminated and can become zero.

[0347] (Implementation 2B)

[0348] Embodiment 2A has described the readout using the rolling shutter method, but Embodiment 2B can also support the readout using the global shutter method.

[0349] Compared to a rolling shutter, a global shutter method can suppress distortion when shooting fast-moving objects.

[0350] The solid-state imaging device 100 in Embodiment 2B differs from that in Embodiment 2A primarily in that the vertical scanning circuit 14 can also be driven in accordance with a global shutter.

[0351] [2B.1 Configuration and Operation Example of Negative Feedback Circuit]

[0352] Figure 19 The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 is the same as that in the embodiment 1B.

[0353] The read timing example in the state where the storage capacitor element C4 according to the embodiment 2B is connected is as follows: Figure 23 Shown.

[0354] use Figure 23 The timing will be explained.

[0355] First, from time t1 to t2, the photodiode PD and FD0 and FD1 are reset, waiting for the start of exposure. Then, from time t2 to t3, the global shutter is activated, and exposure begins. At time t4, the exposure period ends. From time t4 to t5, the signal charge accumulated in the photodiode is transferred to FD0 and FD2 via the transfer signal TG. At time t4, the accumulation transfer transistor TGC is turned on, allowing a low conversion gain to be set to receive more signal charge. From time t5 to t6, the corresponding row is read out using a rolling shutter method. Once the corresponding row is reached, the signal component is read out between time t6 and t7. Next, a reset operation is performed between time t7 and t8. The reset component is read out between time t8 and t9.

[0356] Here, reset noise is generated during the global shutter period of time t2 and t3, and reset noise is generated during the reset period of time t7 and t8. Therefore, during this period, the negative feedback circuit 21 is brought into play, and the reset control signal RS and the accumulated charge transmission element TGC are smoothly cut off, so that the reset noise is reduced. The reset transistor (RS) and the accumulated charge transmission element (TGC) at this time are represented by a solid line as being applied with a ramp-shaped signal. Alternatively, as another method, the negative feedback circuit 21 is brought into play during the shutter period of time t2 and t3, and the reset control signal RS is smoothly cut off, and the accumulated charge transmission element TGC is sharply cut off as being represented by a dotted line. At this time, according to the law of charge accumulation, although the reset noise of the storage capacitor element C4 does not decrease, reset noise in the positive and negative directions is generated in FD0. Until the signal is read out (LCG), since the FD part is not reset, the reset noise of the storage capacitor element C4 and the FD part at this time is eliminated and becomes zero.

[0357] (Implementation 3A)

[0358] In embodiment 3A, Figure 1C The following describes in detail a configuration example in which a single-stage storage circuit is provided in the horizontal direction in the third configuration example. The following description will focus on the differences between the embodiment 1A.

[0359] The solid-state imaging device 100 in Embodiment 3A will be described from a different perspective from that in Embodiment 1. The configuration example of the solid-state imaging device 100 is the same except that the number of controlled horizontal scanning line groups 15 is different.

[0360] In the present embodiment, the charge overflowing from the photodiode PD is directly accumulated in the storage capacitor element C4 without passing through the FD portion or the vicinity of the surface, and therefore the dark current component can be reduced.

[0361] [3A.1 Example of Pixel Circuit Configuration]

[0362] Next, a configuration example of the pixel circuit 3 will be described.

[0363] Figure 24 FIG3 shows an example circuit including the essential parts of the pixel circuit 3 and the negative feedback circuit 21 according to Embodiment 3A. The pixel circuit 3 in the figure includes a photodiode (PD), a transfer transistor TG, an overflow gate OF1, a storage capacitor element C4, a storage transfer transistor TGC, a floating diffusion layer FD0, a parasitic capacitor C0, a floating diffusion layer FD2, a reset transistor RS, an amplifier transistor SF, and a select transistor SEL.

[0364] Furthermore, the horizontal scanning line group 15 includes a reset control line Read control line Overflow control line and select control lines

[0365] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates electric charge according to the amount of received light.

[0366] Furthermore, capacitor C0 connected to floating diffusion layer FD0 holds signal charge (e.g., electrons) transferred from photodiode PD, converts the held signal charge into a voltage, and supplies the converted voltage to the gate of amplifier transistor SF. The substantial capacitance of floating diffusion layer FD0 includes not only the capacitance of floating diffusion layer FD0 itself but also the gate capacitance of amplifier transistor SF, the capacitance between the gate and drain of amplifier transistor SF, and the floating capacitance of the source wiring of gain control transistor GC1 when gain control transistor GC1 is off.

[0367] The transfer transistor TG is connected to the readout control signal The transfer transistor TG reads the control signal When the voltage is high, the photodiode PD transfers the signal charge after photoelectric conversion to the floating diffusion layer FD.

[0368] The storage transfer transistor TGC is switched according to the read control signal The transfer transistor TGC reads the control signal When at a high level, the signal charge accumulated in the storage capacitor element C4 is transferred to the floating diffusion layer FD.

[0369] The overflow gate OF is read according to the control signal The overflow gate OF1 is used to turn on and off the overflow gate and switch transistor. When the level is high, the signal charge photoelectrically converted by the photodiode PD is transferred to the storage capacitor element C4 via the overflow gate OF.

[0370] When the signal charge photoelectrically converted by the photodiode PD overflows from the storage capacitor C4, the control voltage of the storage transfer transistor TGC is applied. Adjust to transmit. Or transmit when the preset potential is exceeded.

[0371] Furthermore, storage capacitor element C4 changes the conversion gain for converting the signal charge in floating diffusion layer FD0 into a voltage. Specifically, when transferring signal charge from photodiode PD to floating diffusion layer FD0, turning off storage transfer transistor TGC increases the conversion gain of floating diffusion layer FD0 to C0. Conversely, turning on storage transfer transistor TGC connects floating diffusion layer FD0 to FD1, allowing for greater signal charge storage. This reduces the conversion gain to C0 + C4.

[0372] The reset transistor RS is in accordance with the reset control signal The reset transistor RS is used to turn on and off the switch transistor. When the reset control signal is high, the power supply voltage applied to the drain is used as the reset level and is set to the floating diffusion layer FD0. When it is at a high level, the floating diffusion layer FD0 is reset to a reset level.

[0373] The amplifier transistor SF forms a source follower together with a load current source 30 connected to the vertical signal line 19 , and outputs the gate voltage, ie, the voltage of the floating diffusion layer FD0 , to the vertical signal line 19 as an analog pixel signal.

[0374] The selection transistor SEL is selected according to the selection control signal The selection transistor SEL selects the control signal When it is at a high level, the source of the amplifier transistor SF is electrically connected to the vertical signal line 19 .

[0375] [3A.2 Configuration and Operation Example of Negative Feedback Circuit]

[0376] Figure 11 The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 is the same as that in the embodiment 1A.

[0377] The timing example of the HCG reading operation in the state where the storage capacitor element C4 is not connected is similar to the timing example of the HCG reading operation in the state where the storage capacitor element C4 is not connected. Figure 7 same.

[0378] The timing example of the LCG read operation in the state where the storage capacitor element C4 is connected is shown by Figure 25 Shown.

[0379] First, between times t1 and t2, the photodiode PD and FD0 and FD2 are reset, waiting for the start of exposure. Then, between times t3 and t4, the shutter is activated, and exposure begins. At time t5, the exposure period ends. At time t5, the accumulation transfer transistor TGC is turned on, setting a low conversion gain to accommodate more signal charge. Between times t5 and t6, the signal charge accumulated in the photodiode is transferred to FD0 and FD1 via transfer signal TG. The signal component is read out between times t6 and t7. Next, a reset operation is performed between times t7 and t8. The reset component is read out between times t8 and t9.

[0380] Here, reset noise is generated during the shutter period between time t3 and t4, and reset noise is generated during the reset period between time t7 and t8. Therefore, during this period, the negative feedback circuit 21 is brought into play, and the reset control signal RS and the accumulated charge transmission element TGC are smoothly cut off, so that the reset noise is reduced. The reset transistor (RS) and the accumulated charge transmission element (TGC) at this time are shown by the solid line in the form of a ramp-shaped signal applied. Alternatively, as another method, the negative feedback circuit 21 is brought into play during the shutter period between time t3 and t4, and the reset control signal RS is smoothly cut off, and the accumulated charge transmission element TGC is sharply cut off. At this time, according to the law of charge accumulation, although the reset noise of the storage capacitor element C4 does not decrease, reset noise in the positive and negative directions is generated in FD0. Until the signal is read out (LCG), since the FD part is not reset, the reset noise of the storage capacitor element C4 and the FD part at this time is eliminated and becomes zero.

[0381] (Implementation 3B)

[0382] The solid-state imaging device 100 in Embodiment 1B differs from that in Embodiment 1A primarily in that the vertical scanning circuit 14 can also be driven in accordance with a global shutter.

[0383] [3B.1 Configuration and Operation Example of Negative Feedback Circuit]

[0384] Figure 19The timing for charge accumulation in the photodiode PD and storage capacitor element C1 is the same as in Embodiment 1B. However, the photodiode PD is continuously exposed during the 1V period (one vertical synchronization period), and the charge amount is Q0. The charge overflowing from the photodiode PD is received by the storage capacitor element C via the overflow gate OF1 as the Q1 signal. Q0 and Q1 are exposed at exactly the same timing.

[0385] In global shutter mode, a global reset is performed on all pixels simultaneously. Exposure begins after this, with exposure time represented by T_Q0 + Q1. Next, the charge from the photodiode is transferred to storage capacitor C4 by adjusting the control voltage of overflow gate OF1. Subsequently, in rolling shutter mode, the signal charge from storage capacitor C2 is read out by turning on storage transfer transistor TGC.

[0386] The timing example of the LCG read operation in a state where the storage capacitor element C4 according to the embodiment 3B is connected is shown in FIG. Figure 26 Shown.

[0387] use Figure 26 The timing will be explained.

[0388] First, from time t1 to t2, the photodiode PD and FD0 and FD1 are reset, waiting for the start of exposure. Then, from time t2 to t3, the global shutter is activated, and exposure begins. Then, from time t3 to t4, the overflow gate is turned on, allowing all the photoelectrically converted charge to be stored in the storage capacitor C4. At time t4, the exposure time has ended, so the overflow gate is turned off. At time t6, the storage transfer transistor TGC is turned on, setting a low conversion gain to accommodate more signal charge. From time t5 to t6, the corresponding row is read out in the rolling shutter mode. Once the corresponding row is reached, the signal component is read out between time t6 and t7. Next, a reset operation is performed between time t7 and t8. The reset component is read out between time t8 and t9.

[0389] Here, reset noise is generated during the global shutter period between time t2 and t3, and reset noise is generated during the reset period between time t7 and t8. Therefore, by making the negative feedback circuit 21 play a role during this period, the reset control signal RS and the accumulated charge transfer element TGC are smoothly cut off, thereby reducing the reset noise. The reset transistor (RS) and the accumulated charge transfer element (TGC) at this time are shown by a solid line as being applied with a ramp-shaped signal. Alternatively, as another method, during the shutter period between time t2 and t3, the negative feedback circuit 21 is played a role, the reset control signal RS is smoothly cut off, and the accumulated charge transfer element TGC is sharply cut off as shown by a dotted line. At this time, according to the law of charge accumulation, although the reset noise of the storage capacitor element C4 does not decrease, reset noise in the positive and negative directions is generated in FD0. Until the signal is read out (LCG), since the FD part is not reset, the reset noise of the storage capacitor element C4 and the FD part at this time is eliminated and becomes zero.

[0390] (Implementation 4)

[0391] The solid-state imaging device 100 in the fourth embodiment will be described from a different perspective from that in the first embodiment. The configuration example of the solid-state imaging device 100 is the same as that of the first embodiment except that the number of horizontal scanning line groups 15 to be controlled is different.

[0392] While Embodiment 1A includes a unit for selecting signals for a high-illuminance region and a low-illuminance region, Embodiment 4 reads two pixel signals, one for forming a high-illuminance frame and one for forming a low-illuminance frame, during a single frame period and synthesizes these two pixel signals. This allows for an expanded dynamic range.

[0393] [4.1 Example of Pixel Circuit Configuration]

[0394] Next, a configuration example of the pixel circuit 3 will be described.

[0395] Figure 27 An example of a circuit including the important parts of the pixel circuit 3 and the negative feedback circuit 21 according to Embodiment 4 is shown. Figure 24 Equivalent to, and in Figure 1C The following description will focus on the differences.

[0396] [4.2 Readout Operation Example of This Embodiment]

[0397] Figure 28A This is a timing chart showing the readout procedure of one frame in the fourth embodiment.

[0398] The gain of converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain and a low gain according to the on and off state of the gain control transistor GC1 .

[0399] In the case of HCG, the normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component). This transition is the reading of signal charges from the photodiode PD in a state where the conversion gain of the floating diffusion layer FD0 is high to the floating diffusion layer FD0.

[0400] Since this transition is a normal CDS, the reset noise can be canceled and reduced to zero.

[0401] Figure 28B Shown Figure 28A The order of reading the reset component and signal component in HCG and LCG readout. The figure shows the CDS sequence for 1H. In the case of LCG, it becomes LCG (S: signal component) → LCG (R: reset component). This transition reads the signal charge from storage capacitor element C0 and storage capacitor element C1 to floating diffusion layer FD0, when the conversion gain of floating diffusion layer FD1 is low.

[0402] This transition can eliminate the DC offset (reset coupling) in LCG, but it cannot cancel the pixel reset noise, and thus remains as kTC noise.

[0403] The kTC noise under the short exposure (high illumination) appears on the low illumination side. Figure 30C Here, kTC noise, expressed as charge, is √(kTC). This noise must be set significantly smaller than the signal level. Thus, at the boundary between short exposure (high illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0404] [4.3 Configuration and Operation Example of Negative Feedback Circuit]

[0405] Figure 11 The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 shown is the same as that in the embodiment 1A.

[0406] use Figure 28A The timing will be explained.

[0407] First, at time t1 to t2, the photodiodes PD and FD0 and FD1 are reset, waiting for the start of exposure. Then, at time t3 to t4, the shutter is actuated, and exposure begins. At time t5, the exposure time ends.

[0408] During HCG, a reset operation is performed between times t5 and t6. The reset component is read between times t8 and t9. Next, between times t7 and t8, the signal charge accumulated in the photodiode is transferred to FD0 via transfer signal TG. The signal component is read between times t8 and t9.

[0409] During LCG, between times t9 and t10, the signal charge accumulated in the photodiode is transferred to FD0 via transfer signal TG. The signal component is read out between times t10 and t11. A reset operation is then performed between times t11 and t12. The reset component is read out between times t12 and t13.

[0410] Here, reset noise occurs during the shutter period between times t3 and t4, and reset noise occurs during the reset period between times t11 and t12. Therefore, by operating the negative feedback circuit 21 during these periods, the reset control signal RS is gradually turned off, reducing reset noise. This figure shows how a ramp-shaped signal is applied to the reset transistor (RS).

[0411] [4.4 Expansion of dynamic range]

[0412] The characteristic of this embodiment is that the two frames of Long and Short for synthesizing WDR are exposed at exactly the same timing and use exactly the same pixels, so that false color, coloring, or blurring does not occur.

[0413] Figure 16 An overview of the WDR synthesis method within a pixel is shown. Figure 29 The following shows an example of a signal processing unit that performs WDR synthesis using two frames. WDR synthesis is performed using a signal charge of Q0 during long exposure (low illumination) and a signal charge of (Q0 + Q1) during short exposure (high illumination).

[0414] Figure 16 The horizontal axes [1], [2], [3], and [4] respectively represent the product of illuminance and exposure time, illuminance for a certain time, or exposure time at a certain illuminance. Regarding the vertical axes, [1] represents the charge accumulation level. [2] represents the FD potential. [3] represents the value after AD conversion. [4] represents the SN.

[0415] Figure 17 The signal charge amounts and the FD potentials of the first Read1 for reading a low-illuminance frame and the second Read2 for reading a high-illuminance frame are shown.

[0416] Figures 30A to 30D The relationship between the subject illumination and the gain (SN) according to the fourth embodiment is shown.

[0417] Figure 30A 、 Figure 30B As a comparative example, the relationship between the subject illumination and the gain (SN) in LCG reading is shown in the case where the negative feedback circuit 21 is not provided. Figure 30A In the analog gain is 0dB, Figure 30B In the analog gain mode, the analog gain is 12dB.

[0418] Figure 30C 、 Figure 30D FIG. 4 shows the relationship between the subject illumination and the gain (SN) in the LCG readout according to the fourth embodiment. Figure 30C In the analog gain is 0dB, Figure 30D In the analog gain mode, the analog gain is 18dB.

[0419] Figure 30A The image shows a synthesis where the actual first Read 1 is a WDR long frame (low-illuminance frame) and the second Read 2 is a WDR short frame (high-illuminance frame). The SN at the connected portion of the frames is 20dB or higher, and the dynamic range is 120dB or higher. The dynamic range is expanded from very dim illumination (0.1 lux) to very bright illumination (100,000 lux: equivalent to sunlight) depending on the storage capacity.

[0420] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are as follows: Figure 29 The pixel signal of the first low-light frame (long exposure) and the pixel signal of the second high-light frame (short exposure) are synthesized. This synthesis enables a wide dynamic range function (WDR function), that is, it is possible to expand the dynamic range.

[0421] The pixel signals of frames in low illumination areas (Long exposure) are set to high intra-pixel gains, while the pixel signals of frames in high illumination areas (Short exposure) are set to low intra-pixel gains. This can improve noise under low illumination and expand the dynamic range under high illumination.

[0422] According to this embodiment, it is possible to achieve both improvements in dynamic range and SN while reducing the reset noise of the storage capacitor element.

[0423] The corresponding relationship between SN and signal output level is given by Figure 30A and Figure 31A 、 Figure 30B and Figure 31B 、 Figure 30C and Figure 31C 、 Figure 30D and Figure 31D Shown.

[0424] Figure 31A 、 Figure 31BAs a comparative example, the relationship between the subject illumination and the signal output level (LSB) in LCG reading is shown in the case where the negative feedback circuit 21 is not provided. Figure 31A In the analog gain is 0dB, Figure 31B In the analog gain mode, the analog gain is 12dB.

[0425] Figure 31C 、 Figure 31D FIG4 shows the relationship between the subject illumination and the signal output level (LSB) in the LCG readout according to the fourth embodiment. Figure 31C In the analog gain is 0dB, Figure 31D The analog gain is 18dB.

[0426] This example shows the case where the column ADC is 12 bits, and the signal output level is limited to 4095 LSBs (MSBs). First, the signal in the low-illuminance area uses a low-illuminance frame, increases proportionally with the illuminance, and is limited to 4095 LSBs (MSBs). Next, the signal in the high-illuminance area uses a high-illuminance frame, increases proportionally with the illuminance, and is limited to 4095 LSBs (MSBs). This value determines the maximum subject illumination.

[0427] In addition, the dynamic range here is often expressed as maximum subject illumination - minimum subject illumination, and the minimum subject illumination is basically defined as SN = 1 dB.

[0428] That is, the range in which the low illumination frame is used is when the analog gain is increased and the signal level is less than the MSB, and the range in which the high illumination frame is used is when the analog gain is increased and the signal level is less than the MSB.

[0429] As mentioned above, when the gain is increased, the signal level rises, and the maximum subject illumination corresponding to the MSB decreases on the low illumination side. The problem in this case is that the SN deteriorates at the boundary between the low illumination frame and the high illumination frame. This is because the reset noise is accompanied by the high illumination frame.

[0430] In this embodiment, since the reset noise is reduced in the negative feedback circuit 21, it can be used in a state where the gain is increased compared to the conventional technology. Figure 30B As shown in the figure, the analog gain can only be increased to 12dB. However, if there are measures to reduce reset noise, such as Figure 30D As shown, analog gain up to 18dB can be used. In addition, the allowable value used is SN20dB or above.

[0431] (Implementation 5)

[0432] The solid-state imaging device 100 in Embodiment 5 will be described from a different perspective from that in Embodiment 1C. The configuration example of the solid-state imaging device 100 differs in the number of controlled horizontal scanning line groups 15, but the other configurations are the same.

[0433] In embodiments 2A and 3A, a unit for selecting a signal in a high illumination area and a signal in a low illumination area is provided. In embodiment 5, a unit for synthesizing two frames of a signal in a high illumination area and a signal in a low illumination area is provided, thereby expanding the dynamic range.

[0434] [5.1 Example of Pixel Circuit Configuration]

[0435] Next, a configuration example of the pixel circuit 3 will be described.

[0436] Figure 32 An example of a circuit including the important parts of the pixel circuit 3 and the negative feedback circuit 21 according to Embodiment 5 is shown. Figure 5 Equivalent to, and in Figure 1A The following description will focus on the differences.

[0437] [5.2 Readout Operation Example of This Embodiment]

[0438] Figure 33A This is a timing chart showing the readout procedure of one frame in the fifth embodiment.

[0439] The gain of converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain and a low gain according to the on and off state of the gain control transistor GC1 .

[0440] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the reading of signal charges from the photodiode (PD) to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high.

[0441] Since this transition is a normal CDS, the reset noise can be canceled and reduced to zero.

[0442] Figure 33B Shown Figure 33AThe order of reading the reset component and signal component in HCG and LCG readout. This figure shows the CDS sequence for 1H. In the case of LCG, it becomes LCG (S: signal component) → LCG (R: reset component). This transition reads the signal charge from storage capacitor elements C0 and C4 to floating diffusion layer FD0, when the conversion gain of floating diffusion layer FD1 is low.

[0443] This transition can eliminate the DC offset (reset coupling) in LCG, but the pixel reset noise cannot be eliminated and remains as kTC noise.

[0444] The kTC noise under the short exposure (high illumination) appears on the low illumination side. Figure 30C As shown. Here, kTC noise, expressed as charge, is √(kTC). This noise must be set significantly smaller than the signal level. Thus, at the boundary between short exposure (high illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0445] [5.3 Configuration and Operation Example of Negative Feedback Circuit]

[0446] Figure 11 The timing of charge accumulation in the photodiode PD and the storage capacitor element C1 is the same as that in the fourth embodiment.

[0447] use Figure 33A The timing will be explained.

[0448] First, at time t1 to t2, the photodiodes PD and FD0 and FD1 are reset, waiting for the start of exposure. Then, at time t3 to t4, the shutter is actuated, and exposure begins. At time t5, the exposure time ends.

[0449] In the HCG, a reset operation is performed between times t5 and t6. The reset component is read between times t8 and t9. Subsequently, between times t7 and t8, the signal charge accumulated in the photodiode is transferred to FD0 via transfer signal TG. The signal component is read between times t8 and t9.

[0450] In the LCG, between times t9 and t10, the signal charge accumulated in the photodiode is transferred to FD0 via transfer signal TG. The signal component is read out between times t10 and t11. A reset operation then occurs between times t11 and t12. The reset component is read out between times t12 and t13.

[0451] Here, reset noise occurs during the shutter period between times t3 and t4, and reset noise also occurs during the reset period between times t11 and t12. Therefore, by activating the negative feedback circuit 21 during this period, the reset control signal RS and the charge storage transfer element TGC are gradually turned off, reducing reset noise. The application of ramp-shaped signals to the reset transistor (RS) and the charge storage transfer element (TGC) at this time is shown by the solid line.

[0452] [5.4 Expansion of dynamic range]

[0453] The characteristic of this embodiment is that the two frames of Long and Short synthesized by WDR are exposed at exactly the same timing and use exactly the same pixels, so false color, coloring, or blurring will not occur.

[0454] Figure 16 An overview of the intra-pixel synthesis method of WDR is shown. Figure 29 The following shows an example of a signal processing unit that synthesizes two frames of WDR. The WDR is synthesized using a signal charge of Q0 during long exposure (low illumination) and a signal charge of (Q0 + Q1) during short exposure (high illumination).

[0455] Figure 16 The horizontal axes [1][2][3][4] show the product of illuminance and exposure time, illuminance for a certain time, or exposure time at a certain illuminance. Regarding the vertical axes, [1] shows the charge accumulation level. [2] shows the FD potential. [3] shows the value after AD conversion. [4] shows the SN.

[0456] Figure 16 The signal charge amounts and the FD potentials of the first Read1 for reading a low-illuminance frame and the second Read2 for reading a high-illuminance frame are shown.

[0457] 30A to 30D The relationship between the subject illumination and the gain (SN) according to the fifth embodiment is shown.

[0458] Figure 30A The image shows a synthesis where the actual first Read 1 is a WDR long frame (low-illuminance frame) and the second Read 2 is a WDR short frame (high-illuminance frame). The SN at the connected portion of the frame is 20 dB or higher, and the dynamic range is 120 dB or higher. The dynamic range is expanded from very dim illumination (0.1 Lux) to very bright illumination (100,000 Lux: equivalent to sunlight) depending on the storage capacity.

[0459] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are as follows: Figure 29The pixel signal of the first low-light frame (long exposure) and the pixel signal of the second high-light frame (short exposure) are synthesized. This synthesis enables a wide dynamic range function (WDR function), that is, it is possible to expand the dynamic range.

[0460] The pixel signals of frames in low illumination areas (Long exposure) are set to high intra-pixel gains, while the pixel signals of frames in high illumination areas (Short exposure) are set to low intra-pixel gains. This improves noise under low illumination and expands the dynamic range under high illumination.

[0461] As described above, according to this embodiment, it is possible to achieve both improvements in dynamic range and SN while reducing the reset noise of the storage capacitor element.

[0462] In this embodiment, since the reset noise is reduced in the negative feedback circuit 21, it can be used in a state with increased gain compared to the conventional technology. Figure 30B As shown in the figure, the analog gain can only be increased to 12dB. However, if there are measures to reduce reset noise, such as Figure 30D As shown, analog gain up to 18dB can be used. In addition, the allowable value used is SN20dB or above.

[0463] (Implementation 6)

[0464] The solid-state imaging device 100 in Embodiment 6 will be described from a different perspective from Embodiment 1A. The configuration example of the solid-state imaging device 100 differs in the addition of a gain control transistor MCG in each pixel and the number of horizontal scanning line groups 15 controlled, but the other configurations are the same.

[0465] While Embodiment 1A includes a means for selecting a signal for a high-illuminance region and a signal for a low-illuminance region, Embodiment 6 includes a means for synthesizing three frames: a signal for a high-illuminance region, a signal for an intermediate-illuminance region, and a signal for a low-illuminance region. This allows for optimization of the SN at the boundaries between frames, and the effect of resetting noise reduction allows for increased analog gain for later use, thereby optimizing low-illuminance characteristics.

[0466] [6.1 Example of Pixel Circuit Configuration]

[0467] Next, a configuration example of the pixel circuit 3 will be described.

[0468] Figure 34A FIG. 1 shows an example of a circuit including the pixel circuit 3 and the important part of the negative feedback circuit 21 according to the sixth embodiment. Figure 1AThe first configuration example is equivalent to that of the embodiment in which two storage circuits are provided in the vertical direction. The following description will focus on the differences.

[0469] [6.2 Readout Operation Example of This Embodiment]

[0470] Figure 35A The readout order of one frame in the sixth embodiment is shown.

[0471] The gain of converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched between a high gain, a medium gain (MCG), and a low gain according to the on and off states of the gain control transistors GC1 and GC2.

[0472] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the reading of signal charges from the photodiode (PD) to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high.

[0473] Since this transition is a normal CDS, the reset noise can be canceled and reduced to zero.

[0474] Figure 35B Shown Figure 35A The order of reading the reset component and signal component in HCG reading, MCG reading, and LCG reading. This figure shows the CDS order of 1H. In the case where HCG reading is followed by MCG (S: signal component) → LCG, it becomes LCG (S: signal component) → LCG (R: reset component) → MCG (R: reset component).

[0475] In the intermediate gain (MCG), this transition becomes the reading of signal charges from the storage capacitance element C0 and the storage capacitance element C1 to the floating diffusion layer FD0 in a state where the conversion gain of the floating diffusion layer FD1 is low.

[0476] In low gain (LCG), this transfer becomes a readout of signal charges from the storage capacitance element C0 , the storage capacitance element C1 , and the storage capacitance element C2 to the floating diffusion layer FD0 in a state where the conversion gain of the floating diffusion layer FD2 is low.

[0477] This transfer can eliminate DC offset (reset coupling) in MCG and LCG, but cannot eliminate pixel reset noise, and remains as kTC noise.

[0478] During the middle exposure (medium illumination), kTC noise appears on the medium illumination side. Figure 39AAs shown. Here, kTC noise, expressed as charge, is √(kTC). This noise must be set significantly smaller than the signal level. Thus, at the boundary between medium exposure (medium illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0479] The kTC noise under the short exposure (high illumination) appears on the low illumination side. Figure 39A As shown. Here, kTC noise, expressed as charge, is √(kTC). This noise must be set significantly smaller than the signal level. Thus, at the boundary between medium exposure (medium illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0480] [6.3 Configuration and Operation Example of Negative Feedback Circuit]

[0481] Figure 36 This figure shows an example of the timing for charge accumulation in the photodiode PD and the storage capacitor element C1. The photodiode PD is continuously exposed during a 1V period (one vertical synchronization period), with a charge amount of Q0. The storage capacitor element C1 receives the charge overflowing from the photodiode PD as the Q1 signal. Furthermore, the storage capacitor element C2 receives the charge overflowing from the storage capacitor element C1 as the Q2 signal. Q0, Q1, and Q2 are exposed at exactly the same timing.

[0482] In the rolling shutter mode, the reset is performed row by row through row scanning. After that, exposure begins, and the exposure time is represented by T_Q0 = T_Q1 = T_Q2.

[0483] use Figure 35A An example of timing is given below.

[0484] First, at time t1 to t2, the photodiode PD and FD0, FD1, and FD2 are reset, waiting for the start of exposure. Then, at time t3 to t4, the shutter is actuated, and exposure begins. At time t5, the exposure time ends.

[0485] A reset operation is performed between times t5 and t6. Between times t6 and t7, the reset component of HCG is read. Then, between times t7 and t8, the signal charge accumulated in the photodiode is transferred to FD0 via transfer signal TG. Between times t8 and t9, the signal component of HCG is read.

[0486] At t9, the signal charge accumulated in the photodiode is transferred to FD1 by turning on the transfer signal GC1. Between time t9 and t10, the signal charge accumulated in the photodiode is transferred to FD1 by the transfer signal TG. Between time t10 and t11, the signal component of LCG is read.

[0487] At t11, the signal charge accumulated in the photodiode is transferred to FD2 by turning on the transfer signal GC2. Between time t11 and t12, the signal charge accumulated in the photodiode is transferred to FD1 by the transfer signal TG. Between time t12 and t13, the signal component of LCG is read.

[0488] Between time t13 and t14, the LCG reset operation is performed, and between time t14 and t15, the reset component of the LCG is read.

[0489] At time t15, GC2 is turned off. Between time t15 and t16, the MCG reset operation is performed. Between time t16 and t17, the reset component of the MCG is read.

[0490] Here, reset noise occurs during the shutter period between times t3 and t4, and during the reset period between times t13 and t14, and between times t15 and t16. Therefore, by operating the negative feedback circuit 21 during these periods, the reset control signal RS and the gain control signal GC2 are gradually turned off, reducing the reset noise. This figure shows how ramp-shaped signals are applied to the reset transistor (RS) and the gain control transistor (GC2).

[0491] [6.4 Expansion of dynamic range]

[0492] A feature of this embodiment is that the three frames of Long, Middle, and Short synthesized by WDR are exposed at exactly the same timing and use exactly the same pixels, so false color, coloring, or blurring does not occur.

[0493] Figure 37 An overview of the WDR synthesis method within a pixel is shown. Figure 34B This figure shows an example of a signal processing unit that synthesizes three frames of WDR. The WDR is synthesized using a signal charge of Q0 for long exposure (low illumination), a signal charge of (Q0+Q1) for middle exposure (medium illumination), and a signal charge of (Q0+Q1+Q2) for short exposure (high illumination).

[0494] Figure 37 The horizontal axes [1][2][3][4] show the product of illuminance and exposure time, illuminance for a certain time, or exposure time at a certain illuminance. Regarding the vertical axes, [1] shows the charge accumulation level. [2] shows the FD potential. [3] shows the value after AD conversion. [4] shows the SN.

[0495] Figure 38 Shown Figure 37FD potentials in HCG readout, MCG readout, and LCG readout. Specifically, the signal charge amounts and FD potentials are shown for the first readout of a low illumination frame (Read1), the second readout of a medium illumination frame (Read2), and the third readout of a high illumination frame (Read3).

[0496] Figures 39A to 39D The relationship between the subject illumination and the gain (SN) according to the sixth embodiment is shown.

[0497] Figure 39A 、 Figure 39B As a comparative example, the relationship between the subject illumination and the gain (SN) in LCG reading is shown in the case where the negative feedback circuit 21 is not provided. Figure 39A In the analog gain is 0dB, Figure 39B In the analog gain mode, the analog gain is 24dB.

[0498] Figure 39C 、 Figure 39D FIG. 4 shows the relationship between the subject illumination and the gain (SN) in the LCG readout according to the sixth embodiment. Figure 39C In the analog gain is 0dB, Figure 39D In the analog gain mode, the analog gain is 30dB.

[0499] Figure 39A The image shows a synthesis where the actual first Read 1 is a WDR Long frame (low illumination frame), the second Read 2 is a WDR Middle frame (medium illumination frame), and the third Read 3 is a WDR Short frame (high illumination frame). The SN at the connected portion of the frame is 20dB or higher, and the dynamic range is 120dB or higher. The dynamic range is expanded from very dim illumination (0.1 lux) to very bright illumination (100,000 lux: equivalent to sunlight) depending on the storage capacity.

[0500] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are as follows: Figure 34B The pixel signals of the first low-light frame (Long exposure), the second medium-light frame (Middle exposure), and the third high-light frame (Short exposure) are synthesized. This synthesis enables a wide dynamic range function (WDR function) and expands the dynamic range.

[0501] The pixel signals of frames in low illumination areas (Long exposure) are set to high intra-pixel gain, the pixel signals of frames in medium illumination areas (Middle exposure) are set to medium intra-pixel gain, and the pixel signals of frames in high illumination areas (Short exposure) are set to low intra-pixel gain. This improves noise under low illumination and expands the dynamic range under high illumination.

[0502] As described above, according to this embodiment, it is possible to achieve both improvements in dynamic range and SN while reducing the reset noise of the storage capacitor element.

[0503] In this embodiment, since the reset noise is reduced in the negative feedback circuit 21, it can be used in a state with increased gain compared to the conventional technology. Figure 39B As shown in the figure, the analog gain can only be increased to 24dB. However, if there are measures to reduce reset noise, such as Figure 39D As shown, analog gain up to 30dB can be used. In addition, the allowable value used is SN20dB or above.

[0504] (Implementation 7)

[0505] The solid-state imaging device 100 in Embodiment 7 will be described from a different perspective from Embodiment 3. The configuration example of the solid-state imaging device 100 differs in the addition of a gain control transistor MCG in a pixel and the number of controlled horizontal scanning line groups 15 , but the other configurations are the same.

[0506] While Embodiment 3A includes a means for selecting a signal for a high-illuminance region and a signal for a low-illuminance region, Embodiment 7 includes a means for synthesizing three frames: a signal for a high-illuminance region, a signal for an intermediate-illuminance region, and a signal for a low-illuminance region. This allows for optimization of the SN at the boundaries between frames, and the effect of resetting noise reduction allows for increased analog gain, thereby optimizing low-illuminance characteristics.

[0507] [7.1 Example of Pixel Circuit Configuration]

[0508] Next, a configuration example of the pixel circuit 3 will be described.

[0509] Figure 40 FIG. 1 shows an example of a circuit including important parts of the pixel circuit 3 and the negative feedback circuit 21 according to Embodiment 7. Figure 1C The third configuration example is equivalent to the configuration example having two storage circuits in the horizontal direction. The following description will focus on the differences.

[0510] [7.2 Readout Operation Example of This Embodiment]

[0511] Figure 41A This is a timing chart showing the readout procedure of one frame in the seventh embodiment.

[0512] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched to a high gain, a medium gain (MCG), and a low gain according to the on and off states of the gain control transistor GC and the storage transfer transistor TGC1.

[0513] The normal CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) in the case of HCG. This transition is the reading of signal charges from the photodiode (PD) to the floating diffusion layer FD0 when the conversion gain of the floating diffusion layer FD0 is high.

[0514] Since this transition is a normal CDS, the reset noise can be canceled and reduced to zero.

[0515] Figure 41B Shown Figure 41A The readout order of the reset component and signal component in HCG readout, MCG readout, and LCG readout. The figure shows the CDS sequence of 1H, and the readout order is MCG (R: reset component) → HCG (R: reset component) → HCG (S: signal component) → MCG (S: signal component) → LCG (S: signal component) → LCG (R: reset component).

[0516] In the intermediate gain (MCG), this transition is the reading of signal charges from the storage capacitance element C0 and the storage capacitance element C3 to the floating diffusion layer FD0 in a state where the conversion gain of the floating diffusion layer FD1 is low.

[0517] In low gain (LCG), this transition is the reading of signal charges from the storage capacitance element C0 , the storage capacitance element C3 , and the storage capacitance element C4 to the floating diffusion layer FD0 in a state where the conversion gain of the floating diffusion layer FD2 is low.

[0518] This transition can eliminate DC offset (reset coupling) in LCG, but cannot eliminate pixel reset noise, which remains as kTC noise.

[0519] Furthermore, the kTC noise under the short exposure (high illumination) appears on the low illumination side. Figure 18B As shown. Here, kTC noise, expressed as charge, is √(kTC). This noise must be set significantly smaller than the signal level. Thus, at the boundary between medium exposure (medium illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0520] [7.3 Configuration and Operation Example of Negative Feedback Circuit]

[0521] Figure 36This figure shows an example of the timing for charge accumulation in the photodiode PD and two storage capacitors C1 and C2. The photodiode PD is exposed during the 1V period (one vertical synchronization period), with a charge of Q0. Storage capacitor C1 receives the charge overflowing from the photodiode PD as the Q1 signal. Furthermore, storage capacitor C4 receives the charge overflowing from storage capacitor C1 as the Q2 signal. Q0, Q1, and Q2 are exposed at exactly the same timing.

[0522] In the rolling shutter method, reset is performed row by row through row scanning. After that, exposure begins, and the exposure time is represented by T_Q0 = T_Q1 = T_Q2.

[0523] use Figure 41A , an example of timing is described.

[0524] First, at time t1 to t2, the photodiode PD and FD0, FD1, and FD2 are reset, waiting for the start of exposure. Then, at time t3 to t4, the shutter is actuated, and exposure begins. At time t5, the exposure time ends.

[0525] First, at time t5, the gain control signal GC1 is turned on and transmitted to FD1. Between time t5 and t6, a reset operation is performed. Between time t6 and t7, the reset component of HCG is read.

[0526] Next, a reset operation is performed between time t7 and time t8, and a reset component of HCG is read between time t8 and time t9.

[0527] Next, between time t9 and t10, the signal charge accumulated in the photodiode is transferred to FD0 by the transfer signal TG. Between time t10 and t11, the signal component of HCG is read out.

[0528] At time t11, the transfer signal GC1 is turned on, transferring the signal charge accumulated in the photodiode to FD1. Between time t11 and t12, the transfer signal TG transfers the signal charge accumulated in the photodiode to FD1. Between time t12 and t13, the signal component of HCG is read.

[0529] At time t13, the signal charge accumulated in the photodiode is transferred to FD2 by turning on the storage transfer transistor TGC. From time t13 to t14, the signal charge accumulated in the storage capacitor element C2 is transferred to FD2 by the transfer signal TGC. Between time t14 and t15, the signal component of LCG is read.

[0530] A reset operation is performed between time t15 and time t16. A reset component of the MCG is read between time t16 and time t17.

[0531] At time t16, each transistor is turned off.

[0532] Here, reset noise occurs during the shutter period between times t3 and t4, and reset noise also occurs during the reset period between times t15 and t16. Therefore, by operating the negative feedback circuit 21 during this period, the reset control signal RS and the charge storage transfer element TGC are gradually turned off, reducing reset noise. The solid line shows how the ramp-shaped signal is applied to the reset transistor (RS) and the charge storage transfer element (TGC).

[0533] [7.4 Expansion of dynamic range]

[0534] A feature of this embodiment is that the three frames of Long, Middle, and Short synthesized by WDR are exposed at exactly the same timing and use exactly the same pixels, so false color, coloring, or blurring does not occur.

[0535] Figure 37 This is an explanatory diagram showing an overview of a WDR synthesis method within a pixel. Figure 34B This figure shows an example of a signal processing unit that synthesizes three frames of WDR. WDR is synthesized as follows: a signal charge of Q0 during long exposure (low illumination), a signal charge of (Q0+Q1) during middle exposure (medium illumination), and a signal charge of (Q0+Q1+Q2) during short exposure (high illumination).

[0536] Figure 37 The horizontal axes [1][2][3][4] show the product of illuminance and exposure time, illuminance for a certain time, or exposure time at a certain illuminance. Regarding the vertical axes, [1] shows the charge accumulation level. [2] shows the FD potential. [3] shows the value after AD conversion. [4] shows the SN.

[0537] Figure 37 The signal charge amounts and FD potentials are shown for the first time Read1 for reading a low-illuminance frame, the second time Read2 for reading a medium-illuminance frame, and the third time Read3 for reading a high-illuminance frame.

[0538] Figures 39A to 39D The relationship between the subject illumination and the gain (SN) according to the seventh embodiment is shown.

[0539] Figure 39A and Figure 39BAs a comparative example, the relationship between the subject illumination and the gain (SN) in LCG reading is shown when the negative feedback circuit 21 is not provided. Figure 39A In the analog gain is 0dB, Figure 39B In the analog gain mode, the analog gain is 24dB.

[0540] Figure 39C and Figure 39D FIG. 4 shows the relationship between the subject illumination and the gain (SN) in the LCG readout according to the sixth embodiment. Figure 39C In the analog gain is 0dB, Figure 39D In the analog gain mode, the analog gain is 30dB.

[0541] Figure 39A The image shows a synthesis where the actual first Read 1 is a WDR Long frame (low illumination frame), the second Read 2 is a WDR Middle frame (medium illumination frame), and the third Read 3 is a WDR Short frame (high illumination frame). The SN at the connected portion of the frame is 20dB or higher, and the dynamic range is 120dB or higher. The dynamic range is expanded from very dim illumination (0.1 lux) to very bright illumination (100,000 lux: equivalent to sunlight) depending on the storage capacity.

[0542] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are as follows: Figure 34B The pixel signals of the first low-light frame (Long exposure), the second medium-light frame (Middle exposure), and the third high-light frame (Short exposure) are synthesized. This synthesis enables a wide dynamic range function (WDR function), that is, it is possible to expand the dynamic range.

[0543] The pixel signals of frames in low illumination areas (Long exposure) are set to high intra-pixel gain, the pixel signals of frames in medium illumination areas (Middle exposure) are set to medium intra-pixel gain, and the pixel signals of frames in high illumination areas (Short exposure) are set to low intra-pixel gain. This improves noise under low illumination and expands the dynamic range under high illumination.

[0544] As described above, according to this embodiment, it is possible to achieve both expansion of the dynamic range and improvement of SN while reducing the reset noise of the storage capacitor element.

[0545] (Implementation 8)

[0546] In the sixth embodiment, since 1V exposure is used, the readout line and the shutter line are read out in the same manner, and thus a single feedback amplifier is used. In the eighth embodiment, since the readout line and the shutter line are read out in different manners, two feedback amplifiers are used. Since negative feedback can be configured independently, the exposure time within a single frame period can be freely set multiple times.

[0547] [8.1 Example of Pixel Circuit Configuration]

[0548] Next, a configuration example of the pixel circuit 3 will be described.

[0549] Figure 42 FIG. 1 shows an example of a circuit including important parts of the pixel circuit 3 and the negative feedback circuit 21 according to the eighth embodiment. Figure 1A The first configuration example, or the fifth embodiment Figure 32 The configuration example is different in that a second reset transistor RS2, a selection transistor SEL2, a current source, and a negative feedback circuit 21a are added.

[0550] This allows two different pixel rows to be reset by performing negative feedback using the negative feedback circuits 21 and 21 a . For example, one row can be reset at the start of exposure, while the other row can be reset at the time of reading.

[0551] The following description will focus on the differences.

[0552] [8.2 Readout Operation Example of This Embodiment]

[0553] Figure 43A This is a timing chart showing the readout order of one frame in Embodiment 8A.

[0554] The gain of converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched to a high gain, a medium gain (MCG), and a low gain (LCG) according to the on and off states of the gain control transistors GC1 and GC2.

[0555] The normal CDS sequence for 1H in the case of HCG is HCG (R: reset component) → HCG (S: signal component). This transition reads the signal charge from the photodiode PD to the floating diffusion layer FD0, when the conversion gain of the floating diffusion layer FD0 is high. Because this transition is normal CDS, reset noise is canceled and reduced to zero.

[0556] In the case of MCG, MCG (R: reset component) → MCG (S: signal component) This transition is the reading of signal charges from the photodiode PD to the floating diffusion layer FD0 when the conversion gains of the floating diffusion layers FD0 and FD1 are intermediate.

[0557] In the case of LCG, the transition is LCG (R: reset component) → LCG (S: signal component). This transition reads the signal charge from the photodiode PD to the floating diffusion layer FD0, when the conversion gain of the floating diffusion layers FD0, FD1, and FD2 is intermediate. Since this transition is not a conventional CDS, reset noise cannot be canceled. Therefore, a negative feedback circuit 21 is used to reduce reset noise.

[0558] Figure 43B Shown Figure 43A The order of reading the reset component and signal component in HCG reading, MCG reading, and LCG reading is shown in the figure. The CDS sequence for 1H is HCG (R: reset component) → HCG (S: signal component) → MCG (S: signal component) → MCG (R: reset component) → LCG (S: signal component) → LCG (R: reset component).

[0559] Although the transition between MCG and LCG can eliminate DC offset (reset coupling), it cannot eliminate pixel reset noise, which remains as kTC noise.

[0560] This kTC noise under medium exposure (medium illumination) appears at medium illumination. Here, kTC noise, expressed as charge, is √(kTC). This noise must be set significantly smaller than the signal level. Thus, at the boundary between medium and long exposures (low illumination), the SN of the latter must be significantly superior to that of the former.

[0561] This kTC noise under short exposure (high illumination) appears on the low illumination side. Here, kTC noise is expressed as √(kTC) in terms of charge. This noise must be set significantly smaller than the signal level. Thus, at the boundary between medium exposure (medium illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0562] [8.3 Configuration and Operation Example of Negative Feedback Circuit]

[0563] Figure 44 An example of the timing for charge accumulation in the photodiode PD and the storage capacitor elements C1 and C2 is shown. With the charge accumulation times for the PD, C1, and C2 being the same, exposure is performed continuously for a 1V period (one vertical synchronization period) with the relationship T_Q0 > T_Q1 > T_Q2, with the first exposure time being T_Q0, the second exposure time being T_Q1, and the third exposure time being T_Q2.

[0564] When the charge of the photodiode PD is Q0, the charge of the storage capacitor C1 is Q1, and the charge of the storage capacitor C2 is Q2, the signal charge of Q0 is stored at T_Q0, the signal charge of Q0+Q1 is stored at T_Q1, and the signal charge of Q0+Q1+Q2 is stored at T_Q2.

[0565] In the rolling shutter method, resetting is performed row by row scanning. Charge reading from the photodiodes to the storage capacitors C1 and C2 is performed row by row. After this, the signal charge of the storage capacitors C1 and C2 is read out in the rolling shutter method.

[0566] use Figure 43A An example of timing will be described.

[0567] First, between time t1 and t2, the photodiode PD and FD0, FD1, and FD2 are reset, waiting for the start of exposure. Then, between time t3 and t4, the shutter is actuated, and exposure begins. At time t5, the exposure time ends.

[0568] Between time t5 and t6, a reset operation is performed. Between time t6 and t7, the reset component of HCG is read. Then, between time t7 and t8, the signal charge accumulated in the photodiode is transferred to FD0 via the transfer signal (TG). Between time t8 and t9, the signal component of HCG is read.

[0569] At time t9, the transfer signal GC1 is turned on, transferring the signal charge accumulated in the photodiode to FD1. Between time t9 and t10, the transfer signal (TG) transfers the signal charge accumulated in the photodiode to FD1. Between time t10 and t11, the signal component of the LCG is read.

[0570] Next, at time t9 to t10, the photodiode PD and FD0, FD1, and FD2 are reset, and the exposure is awaited. Then, at time t11 to t12, the shutter is actuated, and exposure begins. At time t13, the exposure period ends.

[0571] At time t13, the signal charge accumulated in storage capacitor C1 is transferred to FD1 by turning on transfer signal GC1. From time t13 to t14, the signal charge accumulated in the photodiode and the charge accumulated in storage capacitor C1 are transferred to FD1 by transfer signal (TG). Between time t14 and t15, the signal component of LCG is read.

[0572] The reset operation is performed between time t15 and time t16. The reset component of HCG is read between time t16 and time t17.

[0573] Next, at time t17 to t18, the photodiode PD and FD0, FD1, and FD2 are reset, and the exposure is awaited. Then, at time t19 to t20, the shutter is actuated, and exposure begins. At time t21, the exposure period ends.

[0574] At time t21, the signal charge accumulated in storage capacitor element C2 is transferred to FD1 by turning on transfer signal GC2. From time t23 to t24, the signal charge accumulated in the photodiode, the charge accumulated in storage capacitor element C1, and the charge accumulated in storage capacitor element C2 are transferred to FD1 via transfer signal (TG). Between time t22 and t23, the signal component of LCG is read.

[0575] The reset operation is performed between time t23 and time t24. The reset component of HCG is read between time t24 and time t25.

[0576] Here, reset noise occurs during the shutter period between times t11 and t12, the reset period between times t15 and t16, the shutter period between times t19 and t20, and the reset period between times t23 and t24. Therefore, by activating the negative feedback circuit 21 during these periods, the reset control signal RS and the gain control signal GC2 are gradually turned off, reducing the reset noise. This figure shows how ramp-shaped signals are applied to the reset transistor (RS) and the gain control signal (GC2).

[0577] [8.4 Expansion of dynamic range]

[0578] In Embodiments 1 to 7, the three frames of Long, Middle, and Short for synthesizing WDR are exposed at exactly the same timing and use exactly the same pixels, so that false color, coloring, or blurring does not occur.

[0579] A characteristic of the eighth embodiment is that the three frames of Long, Middle, and Short synthesized by the WDR are equipped with two negative feedback circuits 21 and 21a during shutter and readout, so that the timing can be changed independently. Therefore, for example, the dynamic range can be expanded by shortening the exposure time.

[0580] The relationship between the subject illumination and the gain (SN ratio) in the eighth embodiment is different from that in the sixth and seventh embodiments. Figures 39A to 39D For example, the dynamic range can be expanded by making the exposure time variable.

[0581] With the accumulation time of PD, C1, and C2 being the same, for example, when the first exposure time is set to T_Q0, the second exposure time is set to T_Q1, and the third exposure time is set to T_Q2, the 1V period (1 vertical synchronization period) is continuously exposed with the relationship of T_Q0>T_Q1>T_Q2.

[0582] At this time, when the charge of the photodiode PD is Q0, the charge of the storage capacitor element C1 is Q1, and the charge of the storage capacitor element C2 is Q2, the signal charge of Q0 is accumulated at T_Q0, the signal charge of Q0+Q1 is accumulated at T_Q1, and the signal charge of Q0+Q1+Q2 is accumulated at T_Q2.

[0583] For the pixel signal of the frame in the low illumination area (Long exposure), the intra-pixel gain x exposure time is set high; for the pixel signal of the frame in the medium illumination area (Middle exposure), the intra-pixel gain x exposure time is set to the middle; for the pixel signal of the frame in the high illumination area (Short exposure), the intra-pixel gain x exposure time is set low. This can improve the noise under low illumination and expand the dynamic range under high illumination.

[0584] According to this embodiment, it is possible to achieve both improvement in dynamic range and improvement in SN while reducing the reset noise of the storage capacitor element.

[0585] Although Line-by-Line control of three exposures is shown here as an example, it can also be realized as exposure of more than three images.

[0586] (Implementation 9)

[0587] In Embodiment 7, since 1V exposure is used, the readout line and the shutter line are read out simultaneously, thus using a single feedback amplifier. In Embodiment 9, since the readout line and the shutter line are different, readout is performed using two feedback amplifiers. Since negative feedback can be independently configured for each, multiple exposure times can be freely set within a single frame period.

[0588] [9.1 Example of Pixel Circuit Configuration]

[0589] Next, a configuration example of the pixel circuit 3 will be described.

[0590] Figure 45 FIG. 1 shows an example of a circuit including important parts of the pixel circuit 3 and the negative feedback circuit 21 according to Embodiment 9. Figure 1C The third configuration example or the seventh embodiment Figure 40 The difference between the configuration example and the embodiment is that a second reset transistor RS2, a selection transistor SEL2, a current source, and a negative feedback circuit 21a are added.

[0591] This allows the negative feedback circuits 21 and 21a to reset two different pixel rows. For example, one row can be reset at the start of exposure, while the other row can be reset at the time of reading.

[0592] [9.2 Readout Operation Example of This Embodiment]

[0593] Figure 46A This is a timing chart showing the readout procedure of one frame in the ninth embodiment.

[0594] The gain for converting the signal charge in the floating diffusion layer FD1 into a voltage can be selectively switched to a high gain, a medium gain (MCG), and a low gain according to the on and off of the gain control transistor GC1 and the storage transfer transistor (TG)C.

[0595] The normal CDS sequence for 1H in the case of HCG is HCG (R: reset component) → HCG (S: signal component). This transition reads the signal charge from the photodiode PD, where the conversion gain of the floating diffusion layer FD0 is high, to the floating diffusion layer FD0. Because this transition is normal CDS, reset noise is eliminated and reduced to zero.

[0596] In the case of MCG, it is MCG (R: reset component)→MCG (S: signal component). This transition is the reading of signal charges from the photodiode PD to the floating diffusion layer FD0 when the conversion gains of the floating diffusion layers FD0 and FD1 are intermediate.

[0597] In the case of LCG, the transition is LCG (R: reset component) → LCG (S: signal component). This transfer reads the signal charge from the photodiode PD to the floating diffusion layer FD0, when the conversion gain of the floating diffusion layers FD0, FD1, and FD2 is intermediate. Since this transfer is not a conventional CDS, reset noise cannot be canceled. Instead, a negative feedback circuit is used to reduce reset noise.

[0598] Figure 46B Shown Figure 46A The order of reading the reset component and signal component in HCG readout, MCG readout, and LCG readout. The figure shows the CDS order for 1H, which is HCG (R: reset component) → HCG (S: signal component) → MCG (S: signal component) → MCG (R: reset component) → LCG (S: signal component) → LCG (R: reset component).

[0599] Although the transition between MCG and LCG can eliminate DC offset (reset coupling), it cannot eliminate pixel reset noise, so it remains as kTC noise.

[0600] This kTC noise under medium exposure (medium illumination) appears at medium illumination. Here, kTC noise, expressed as charge, is √(kTC). This noise must be set significantly smaller than the signal level. Thus, at the boundary between medium exposure (medium illumination) and long exposure (low illumination), the SN of the latter must be significantly superior to that of the former.

[0601] This kTC noise under short exposure (high illumination) appears on the low illumination side. Here, kTC noise, expressed as charge, is √(kTC). This noise needs to be set significantly smaller than the signal level. Thus, at the boundary between medium exposure (medium illumination) and long exposure (low illumination), the SN of the latter needs to be significantly superior to that of the former.

[0602] [9.3 Configuration and Operation Example of Negative Feedback Circuit]

[0603] Figure 44 An example of the timing for charge accumulation in the photodiode PD and the storage capacitor elements C1 and C2 is shown. With the charge accumulation times for the PD, C1, and C2 being the same, exposure is performed continuously within a 1V period (one vertical synchronization period) with the relationship T_Q0 > T_Q1 > T_Q2, with the first exposure time being T_Q0, the second exposure time being T_Q1, and the third exposure time being T_Q2.

[0604] When the charge of the photodiode PD is Q0, the charge of the storage capacitor C3 is Q1, and the charge of the storage capacitor C4 is Q2, the signal charge of Q0 is stored at T_Q0, the signal charge of Q0+Q1 is stored at T_Q1, and the signal charge of Q0+Q1+Q2 is stored at T_Q2.

[0605] use Figure 46A An example of timing will be described.

[0606] First, at time t1 to t2, the photodiode PD and FD0, FD1, and FD2 are reset, waiting for the start of exposure. Then, at time t3 to t4, the shutter is actuated, and exposure begins. At time t5, the exposure time ends.

[0607] Between times t5 and t6, a reset operation is performed. Between times t6 and t7, the reset component of the HCG is read. Next, between times t7 and t8, the signal charge accumulated in the photodiode is transferred to FD0 via the transfer signal (TG). Between times t8 and t9, the signal component of the HCG is read.

[0608] At time t9, the transfer signal GC1 is turned on, transferring the signal charge accumulated in the photodiode to FD1. Between time t9 and t10, the signal charge accumulated in the photodiode is transferred to FD1 via the transfer signal (TG). Between time t10 and t11, the signal component of the LCG is read.

[0609] Next, at time t9 to t10, the photodiode PD and FD0, FD1, and FD2 are reset, and the exposure is awaited. Then, at time t11 to t12, the shutter is actuated, and exposure begins. At time t13, the exposure period ends.

[0610] At time t13, the signal charge accumulated in storage capacitor C1 is transferred to FD1 by turning on transfer signal GC1. From time t13 to t14, the signal charge accumulated in the photodiode and the charge accumulated in storage capacitor C1 are output to FD1 via transfer signal (TG). Between time t14 and t15, the signal component of LCG is read.

[0611] Between time t15 and t16, a reset operation is performed, and between time t16 and t17, the reset component of HCG is read.

[0612] Next, at time t17 to t18, the photodiode PD and FD0, FD1, and FD2 are reset, and the exposure is awaited. Then, at time t19 to t20, the shutter is actuated, and exposure begins. At time t21, the exposure period ends.

[0613] At time t21, the signal charge accumulated in storage capacitor element C4 is transferred to FD1 by turning on the storage transfer transistor (TG) C. From time t23 to t24, the signal charge accumulated in the photodiode, the charge accumulated in storage capacitor element C1, and the charge accumulated in storage capacitor element C2 are transferred to FD1 via the transmission signal (TG) and the storage transfer transistor (TG) C. Between time t22 and t23, the signal component of the LCG is read.

[0614] Between time t23 and t24, a reset operation is performed, and between time t24 and t25, the reset component of HCG is read.

[0615] Here, reset noise is generated during the shutter period between time t11 and t12, and reset noise is generated during the reset period between time t15 and t16. Furthermore, reset noise is generated during the shutter period between time t19 and t20, and reset noise is generated during the reset period between time t23 and t24. Therefore, by making the negative feedback circuit 21 work during this period, the reset control signal RS and the accumulated charge transfer element TGC are smoothly cut off, thereby reducing reset noise. The reset transistor (RS) and the accumulated charge transfer element (TGC) at this time are shown by a solid line to indicate the appearance of a ramp-shaped signal being applied. Alternatively, as another method, during the shutter period between time t11 and t12, and during the shutter period between time t19 and t20, the negative feedback circuit 21 is made work, the reset control signal RS is smoothly cut off, and the accumulated charge transfer element TGC is sharply cut off to indicate the appearance of a dotted line ... Since the FD portion is not reset until the signal is read (LCG), the reset noise of the storage capacitor element C4 and the FD portion at this time is canceled and becomes zero.

[0616] [9.4 Expansion of Dynamic Range]

[0617] In Embodiments 1 to 7, the three frames of Long, Middle, and Short for synthesizing WDR are exposed at exactly the same timing and use exactly the same pixels, so that false color, coloring, or blurring does not occur.

[0618] The characteristic of the ninth embodiment is that the three frames of Long, Middle, and Short synthesized by WDR are equipped with two negative feedback circuits 21 for shutter and readout, so that the timing can be changed independently. Therefore, for example, by shortening the exposure time, the D range can be expanded.

[0619] The relationship between the subject illumination and the gain (SN) in the ninth embodiment is different from that in the sixth and seventh embodiments. Figures 39A to 39D , which can expand the dynamic range by making the exposure time variable.

[0620] To make the accumulation time of PD, C1, and C2 the same, for example, when the first exposure time is set to T_Q0, the second exposure time is set to T_Q1, and the third exposure time is set to T_Q2, exposure is continuously performed during the 1V period (1 vertical synchronization period) with the relationship T_Q0>T_Q1>T_Q2.

[0621] At this time, when the charge of the photodiode PD is Q0, the charge of the storage capacitor element C3 is Q1, and the charge of the storage capacitor element C4 is Q2, the signal charge of Q0 is accumulated at T_Q0, the signal charge of Q0+Q1 is accumulated at T_Q1, and the signal charge of Q0+Q1+Q2 is accumulated at T_Q2.

[0622] For the pixel signals of frames in low illumination areas (Long exposure), the intra-pixel gain x exposure time is set higher; for the pixel signals of frames in medium illumination areas (Middle exposure), the intra-pixel gain x exposure time is set to the middle; for the pixel signals of frames in high illumination areas (Short exposure), the intra-pixel gain x exposure time is set lower. Accordingly, the noise under low illumination can be improved and the dynamic range under high illumination can be expanded.

[0623] As described above, according to this embodiment, it is possible to achieve both improvements in dynamic range and SN while reducing the reset noise of the storage capacitor element.

[0624] Although line-by-line control of three exposures is used as an example here, it can also be realized as exposure of more than three images.

[0625] (Implementation 10)

[0626] Hereinafter, an imaging device according to Embodiment 10 will be described with reference to the drawings. The imaging device according to this embodiment includes one or more solid-state imaging devices 100 according to Embodiments 1 to 9. These will be described in detail below.

[0627] Figure 47 The monitoring system is a block diagram illustrating an example configuration of an imaging device according to Embodiment 10. The imaging device in this figure includes a CIS (CMOS Image Sensor) 91, an ISP (Image Signal Processor) 92, and a monitor 9, and is, for example, a camera in a digital camera or smartphone. The CIS 91 is the solid-state imaging device 100 shown in each embodiment. The ISP 92 receives image signals from the CIS 91 and performs image processing such as image enlargement, reduction, compression encoding, and decoding. The monitor 93 is used to confirm the user during filming.

[0628] Furthermore, CIS 91 and ISP 92 may be a single-chip SoC (System on Chip) 90, or they may be other chips. If CIS 91 and ISP 92 are other chips, signal processing unit 70 may include either CIS 91 or CIS 92. Furthermore, a portion of signal processing unit 70 may be implemented as software rather than as a circuit.

[0629] and, Figure 48 The block diagram of the sensing system in the ADAS (Advanced Driver Assistance System) or autonomous driving is a block diagram showing another configuration example of the camera device involved in the tenth embodiment. The camera device in this figure includes: CIS (CMOS Image Sensor) 91, ISP (Image Signal Processor) 92, sensor 94, sensor ECU (Electronic Control Unit: Electronic Control Unit) 95, warning unit 96, and control unit 97, and is, for example, a camera system installed in a vehicle. CIS 91 and ISP 92 are the same as signal processing unit 70. Sensor 94 is, for example, a radar sensor for ranging or an optical radar (Lidar: Light Detection and Ranging) sensor for ranging.

[0630] The sensor ECU 95 controls a warning unit 96 and a control unit 97, which receive signals from the ISP 92 and the sensor 94. The warning unit 96 may be, for example, various status indicators or warning lights within the vehicle's instrument panel. The control unit 97 controls actuators such as the vehicle's steering wheel and brakes that control vehicle movement.

[0631] Alternatively, Figure 2 The camera device is connected to a monitor in a monitoring system and corresponds to a sensing system such as ADAS (Advanced Driver Assistance System) or autonomous driving, in which warnings or controls (steering wheel, brakes, etc.) are executed via a sensor ECU.

[0632] Figure 49 An example is shown in which the imaging device according to the tenth embodiment is mounted on the vehicle M1. Figure 50 The embodiment 10 is shown Figure 49 An example of the shooting range in the example shown.

[0633] like Figure 49 As shown, for example Figure 2The camera device is installed at each of a plurality of mounting locations C1 to C9. Mounting location C1 is the front end of vehicle M1. Mounting location C2 is the left side of vehicle M1. Mounting location C3 is the right side of vehicle M1. Mounting location C4 is the left rearview mirror. Mounting location C5 is the right rearview mirror. Mounting location C6 is the interior rearview mirror. Mounting location C7 is the center of the rear end of vehicle M1. Mounting location C8 is the left side of the rear end of vehicle M1. Mounting location C9 is the right side of the rear end of vehicle M1.

[0634] and, Figure 50 The illustrated imaging ranges S1 to S9 correspond to the cameras installed at positions C1 to C9.

[0635] like Figure 49 and Figure 50 As shown, the camera device, which is a monitoring camera or a sensing camera, can be installed at the front, periphery, side, rear end, or smart rearview mirror of a transport machine (vehicle, car) according to the range of the captured object.

[0636] As described above, the imaging device in the tenth embodiment includes the above-mentioned Figure 47 or Figure 48 The camera device constitutes any one of the monitoring system, the ADAS (Advanced Driver Assistance System) sensing system, and the autonomous driving sensing system.

[0637] Here, the camera device may be mounted on one or more of the front end, left side, right side, and rearview mirror of the transport machine.

[0638] Furthermore, the camera device is a camera device having the above-mentioned solid-state camera device 100, corresponding to at least one of a monitoring system for a transport machine, a sensor system for an ADAS (advanced driver assistance system), and a sensor system for autonomous driving, and the camera device is mounted on at least one of the front end, surroundings, sides, rear end, and interior rearview mirror of the transport machine.

[0639] (Other Embodiments)

[0640] The solid-state imaging device of the present disclosure and the imaging device using the same have been described above based on the embodiments. However, the solid-state imaging device of the present disclosure and the imaging device using the same are not limited to the above-described embodiments. Other embodiments implemented by combining any of the components in the above-described embodiments, modifications of the above-described embodiments that can be conceived by those skilled in the art without departing from the scope of the present disclosure, and various devices incorporating the solid-state imaging device of the present disclosure and the imaging device using the same are all included in the present invention.

[0641] Industrial Applicability

[0642] The present disclosure can be utilized in a solid-state imaging device and an imaging device.

[0643] Explanation of symbols

[0644] 3 Pixel Circuit

[0645] 21 Negative Feedback Circuit

[0646] C1, C4: First storage capacitor element

[0647] C2, C3 Second storage capacitor elements

[0648] GC1, TGC 1st transistor

[0649] GC, GC2 Second transistor

[0650] FA 1st feedback amplifier

[0651] FA2 2nd feedback amplifier

[0652] FD0 Charge storage unit

[0653] OF overflow element

[0654] PD Photodiode

[0655] RS 1st reset transistor

[0656] RS2 2nd reset transistor

[0657] SF amplifier transistor

[0658] TG pass transistor

Claims

1. A solid-state imaging device, The solid-state imaging device includes a pixel circuit and a negative feedback circuit. The pixel circuit comprises: Photodiode; a charge storage unit; a transfer transistor for transferring the signal charge generated in the photodiode to the charge storage unit; an amplifying transistor configured to output a pixel signal corresponding to the signal charge of the charge storage unit; a first reset transistor for resetting the charge storage unit; a first storage capacitor element; as well as a first transistor for controlling the connection between the charge storage unit and the first storage capacitor element; The negative feedback circuit negatively feeds back a feedback signal corresponding to the reset output of the amplifier transistor to the charge storage unit via the first reset transistor. The solid-state imaging device includes a control circuit configured to read out, from the pixel circuit, a first pixel signal for constituting a first frame and a second pixel signal for constituting a second frame, the second frame being a frame for higher illumination than the first frame. The first pixel signal corresponds to the signal charge transferred from the photodiode to the charge storage unit. The second pixel signal corresponds to signal charges transferred from the photodiode to the charge storage unit and the first storage capacitor element and mixed therewith. The first pixel signal and the second pixel signal are based on signal charges generated by the photodiode of one pixel circuit during the same exposure period.

2. The solid-state imaging device according to claim 1, The first transistor is connected in series with the first reset transistor between the first reset transistor and the charge storage unit. The first storage capacitor is connected to a connection point between the first reset transistor and the first transistor. The solid-state imaging device further comprises: a second transistor connected in series between the first transistor and the charge storage unit; and A second storage capacitor is connected to a connection point between the first transistor and the second transistor, and is connected to the charge storage unit via the second transistor.

3. The solid-state imaging device according to claim 2, The gate voltage of the transfer transistor and the gate voltage of the first transistor are set so that the signal charge overflowing from the photodiode can be transferred to the first storage capacitor element during exposure.

4. The solid-state imaging device according to claim 2, The solid-state imaging device further includes an overflow element that transfers signal charges overflowing from the photodiode to the first storage capacitor element.

5. The solid-state imaging device according to claim 1, The first transistor is connected in series with the first reset transistor between the first reset transistor and the charge storage unit. The first storage capacitor is connected to a connection point between the first reset transistor and the first transistor. The solid-state imaging device further includes a second transistor and a second storage capacitor element. The second transistor is connected to a connection point between the first reset transistor and the first transistor. The first storage capacitor element and the second storage capacitor element are connected via the second transistor.

6. The solid-state imaging device according to any one of claims 2 to 5, The solid-state imaging device includes: a plurality of said pixel circuits; a driving unit configured to drive the plurality of pixel circuits so as to expose the plurality of pixel circuits simultaneously; and The control circuit reads out the pixel signal by scanning the plurality of pixel circuits.

7. The solid-state imaging device according to any one of claims 2 to 5, The control circuit further reads out a third pixel signal for constituting a third frame from the pixel circuit, the third frame being a frame for higher illumination than the second frame. The third pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit, the first storage capacitor element, and the second storage capacitor element and mixed therewith. The first pixel signal, the second pixel signal, and the third pixel signal are based on signal charges generated by the photodiode of one pixel circuit during the same exposure period.

8. The solid-state imaging device according to any one of claims 2 to 5, The control circuit further reads out a third pixel signal constituting a third frame from the pixel circuit, the third frame being a frame for higher illumination than the second frame, The third pixel signal corresponds to a signal charge transferred from the photodiode to the charge storage unit, the first storage capacitor element, and the second storage capacitor element and mixed therewith. The first pixel signal, the second pixel signal, and the third pixel signal are based on signal charges generated by the photodiode of one pixel circuit during different exposure periods.

9. The solid-state imaging device according to claim 1, The first reset transistor and at least a control signal input to the first reset transistor have a ramp-shaped voltage waveform so as to gradually shift the state of the transistor from an on state to an off state.

10. The solid-state imaging device according to claim 1, The first reset transistor and at least a control signal input to the first reset transistor have a ramp-shaped voltage waveform so as to gradually shift the state of the transistor from an on state to an off state. The solid-state imaging device further comprises: a measuring unit that measures a reset noise level of pixel circuits belonging to a predetermined area among the plurality of pixel circuits; and The determination unit determines the slope of the ramp-shaped voltage waveform based on the measurement result so as to reduce the variation in the reset noise level.

11. The solid-state imaging device according to claim 10, The measuring section measures the reset noise level while changing the slope of the voltage waveform for each row of pixel circuits belonging to the predetermined area. The determination unit determines an optimal slope of the voltage waveform based on the variation in each row of pixel circuits belonging to the predetermined area.

12. The solid-state imaging device according to claim 1, The solid-state imaging device includes the negative feedback circuit for each column of the plurality of pixel circuits arranged in a matrix or for each pixel circuit. The negative feedback circuit includes a first feedback amplifier configured to output the feedback signal to the first reset transistor of the pixel circuit belonging to a corresponding column or to the first reset transistor of the corresponding pixel circuit.

13. The solid-state imaging device according to claim 12, The solid-state imaging device includes a first semiconductor chip and a second semiconductor chip bonded together. The first semiconductor chip includes the photodiode of each pixel circuit and the first storage capacitor element. The second semiconductor chip includes the first feedback amplifier corresponding to each column of the pixel circuits or corresponding to each pixel circuit.

14. The solid-state imaging device according to claim 12, The negative feedback circuit is configured for each pixel circuit. The solid-state imaging device includes a first semiconductor chip and a second semiconductor chip bonded together. The first semiconductor chip includes the photodiode of each pixel circuit. The second semiconductor chip includes the first feedback amplifier and the first storage capacitor element corresponding to each pixel circuit.

15. The solid-state imaging device according to claim 12, The solid-state imaging device includes a first semiconductor chip and a second semiconductor chip bonded together. The first semiconductor chip includes the photodiode and the charge storage unit of each pixel circuit. The second semiconductor chip includes the first storage capacitor element for each pixel circuit.

16. The solid-state imaging device according to claim 1, The negative feedback circuit is arranged for each column of the plurality of pixel circuits arranged in a matrix. The negative feedback circuit includes a first feedback amplifier, the first feedback amplifier outputting the feedback signal to the first reset transistor of the pixel circuit belonging to the corresponding column, or to the first reset transistor of the corresponding pixel circuit. The pixel circuit further includes a second reset transistor for resetting the charge storage unit. The negative feedback circuit further includes a second feedback amplifier configured to output the feedback signal to the second reset transistor of the pixel circuit belonging to the corresponding column.

17. An imaging device comprising the solid-state imaging device according to any one of claims 1 to 16, The camera device corresponds to at least one of a monitoring system for a transport machine, a sensor system for an advanced driver assistance system, and a sensor system for an autonomous driving system. The camera device is mounted on at least one of the front end, the periphery, the side, the rear end, and the interior rearview mirror of the transport machine.

Images