Linear voltage regulator with fast load regulation and method thereof

Abstract

A linear regulator and a voltage regulation method, the linear regulator comprising: an error amplifier configured to receive an output voltage at an output node and a reference voltage at a reference node, and output a first control voltage; a first PMOS transistor configured to receive an input voltage from a power supply node, and output a first output current to the output node according to the first control voltage; an AC coupling capacitor configured to couple the output voltage to an AC coupling voltage; a high-speed amplifier configured to receive the AC coupling voltage and output a second control voltage; a second PMOS transistor configured to receive an input voltage and output a second output current to the output node according to the second control voltage; and a load configured to draw a load current from the output node.

Description

[0001] Related Applications

[0002] The present invention claims the international priority of U.S. patent application No. 17 / 249,691 (filing date: March 10, 2021), the entire contents of which are incorporated as part of the patent specification of the present invention for reference. Technical Field

[0003] The present invention generally relates to a linear voltage regulator, and more particularly, to a voltage regulator with fast load regulation and related methods. Background Art

[0004] As we all know, a linear regulator receives an input voltage from a power supply and outputs an output voltage to a load based on a reference voltage, so that the output voltage can be maintained at a level that is nearly equal to the reference voltage regardless of the load size. Figure 1 As shown, Figure 1 FIG. 1 is a schematic diagram of a conventional linear regulator 100 . The linear regulator 100 includes an error amplifier 111 configured to receive an output voltage V out and the reference voltage V (at reference node 102) ref , and output control voltage V ctl ; A p-channel metal oxide semiconductor (PMOS) transistor configured to receive an input voltage V from a power supply node 103 sup , and according to the control voltage V ctl The first output current I out output to the output node 101; and a load 120 configured to draw a load current I from the output node 101 load .

[0005] In one embodiment, the linear regulator 100 further includes a short-circuit capacitor 113 configured to short-circuit the output node 101 to the ground. Figure 1 The purpose of the linear regulator 100 is to use the negative feedback control loop formed by the error amplifier 111 and the PMOS transistor 112 to control the output current I in a closed loop manner. out With load current I load Matching, regardless of load current I load Whatever the value is, the output voltage V out Keep stable and keep the reference voltage V refHere, the error amplifier 111 acts as a controller, and the PMOS transistor 112 acts as an output device controlled by the controller. In fact, the output voltage V out As the load current I load The deviation from the reference voltage V ref . Load current I load A large increase (drop) in the output voltage V out This is because the negative feedback control loop is prone to instability and cannot be designed with a wide enough bandwidth to increase (decrease) the output current I in a timely manner. out , to match the load current I load The increase (decrease) of , causes the charge stored in the parallel capacitor 113 to change instantly, and thus causes the output voltage V out Change happens in an instant.

[0006] Therefore, there is an urgent need for a linear regulator with fast load regulation, so that a large sudden change in load current will not cause a large sudden change in output voltage. Summary of the invention

[0007] In one embodiment, a linear regulator includes: an error amplifier configured to receive an output voltage at an output node and a reference voltage at a reference node, and output a first control voltage; a first P-channel metal oxide semiconductor (PMOS) transistor configured to receive an input voltage from a power supply node, and output a first output current to the output node according to the first control voltage; an alternating current (AC) coupling capacitor configured to couple the output voltage to an AC coupling voltage; a non-inverting amplifier configured to receive the AC coupling voltage and output a second control voltage; a second PMOS transistor configured to receive an input voltage and output a second output current to the output node according to the second control voltage; and a load configured to draw a load current from the output node.

[0008] In one embodiment, a voltage regulation method includes: receiving an input voltage and a reference voltage; combining a load configured to draw a load current from an output node; using an error amplifier to generate a first control voltage based on the difference between the reference voltage and an output voltage at the output node; using a first P-channel metal oxide semiconductor (PMOS) transistor to convert the input voltage into a first output current provided to the output node based on the first control voltage; using an alternate current (AC) coupling capacitor to couple the output voltage to an AC coupling voltage; using a non-inverting amplifier to amplify the AC coupling voltage into a second control voltage; and using a second PMOS transistor to convert the input voltage into a second output current provided to the output node based on the second control voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 1 is a schematic diagram showing a conventional linear regulator.

[0010] Figure 2A FIG. 4 is a schematic diagram of a linear regulator according to an embodiment of the present invention.

[0011] Figure 2B FIG. 4 is a schematic diagram of an error amplifier according to an embodiment of the present invention.

[0012] Figure 2C A schematic diagram of a non-inverting amplifier according to an embodiment of the present invention is shown.

[0013] Figure 3 Shows Figure 2A Simulation results of a linear regulator.

[0014] Figure 4 A flow chart of a voltage regulation method according to an embodiment of the present invention is shown.

[0015] Explanation of symbols

[0016] 100, 200: Linear regulator

[0017] 101, 201: Output nodes

[0018] 102, 202: Reference nodes

[0019] 103, 203: Power node

[0020] 111, 211: Error amplifier

[0021] 112, 212: PMOS transistor

[0022] 113, 213: Short-circuit capacitor

[0023] 120, 230: Load

[0024] 221: Non-inverting amplifier

[0025] 222: Second PMOS transistor

[0026] 223: AC coupling capacitor

[0027] 400: Flowchart

[0028] 410, 420, 430, 440, 450, 460, 470: Steps

[0029] 211a, 211b, 211c, 221a, 221d: NMOS transistors

[0030] 211d, 211e, 221b, 221e: PMOS transistors

[0031] 211f: Resistors

[0032] 211g: Capacitor

[0033] 221_1: Input stage

[0034] 221_2: Output stage

[0035] 221c: Self-biased feedback resistor

[0036] I b : Bias current

[0037] I l ,I load : Load current

[0038] I o1 : First output current

[0039] I o2 : Second output current

[0040] I out : Output current

[0041] V ac : AC coupling voltage

[0042] V amp : Amplified voltage

[0043] V b : Bias voltage

[0044] V c1 : First control voltage

[0045] V c2: Second control voltage

[0046] V ctl : Control voltage

[0047] V DD : Power Node

[0048] V o 、V out : Output voltage

[0049] V r 、V ref : Reference voltage

[0050] V s 、V sup : Input voltage DETAILED DESCRIPTION

[0051] The present invention relates to a voltage regulator circuit and related methods. Although the specification describes several example embodiments of the present invention, these embodiments are considered to be advantageous ways to implement the present invention, it should be understood that the present invention can be implemented in many ways and is not limited to the specific examples described below, or to the specific ways of implementing any features of these examples. In other cases, well-known details are not shown or described to avoid obscuring the various embodiments of the present invention.

[0052] Those skilled in the art understand the terms and basic concepts related to microelectronics used in the present invention, such as "circuit node", "power supply node", "ground node", "differential pair", "voltage", "current", "metal oxide semiconductor (MOS)", "p-channel metal oxide semiconductor (PMOS)", "n-channel metal oxide semiconductor (n-channel metal oxide semiconductor)", "amplifier", "non-inverting amplifier", "common source amplifier", "class AB amplifier", "operational amplifier", "single-stage amplifier", "voltage gain", "negative feedback control loop", "stability", "frequency compensation", "two-stage amplifier", "non-inverting amplifier", "AC", "AC coupling", "DC", "DC coupling", "current source" and "load". When used in the paragraphs related to microelectronics, such terms and basic concepts are obvious to those skilled in the art and will not be described in detail herein.

[0053] A person skilled in the art can read a schematic diagram of a circuit including components such as capacitors, resistors, NMOS transistors, PMOS transistors, etc., and does not need a lengthy description of how one component is connected to another component in the schematic diagram. A person skilled in the art can also recognize the ground symbol and the symbols of PMOS transistors and NMOS transistors, and recognize their "source terminal", "gate terminal" and "drain terminal". In short, in relation to MOS transistors, the "source terminal" is referred to as the "source", the "gate terminal" is referred to as the "gate", and the "drain terminal" is referred to as the "drain". A person skilled in the art can also understand units such as volts (V), amperes (A), microvolts (mV), decibels (dB), microseconds (ms), nanoseconds (ns), millimeters (mm), nanometers (nm), ohms (Ohm), kiloohms (KOhm), picofarads (pF), nanofarads (nF) and microfarads (μF).

[0054] MOS transistors, PMOS or NMOS, have a width and a channel length. Sometimes, when it is clear from the context that the "length" refers to the "channel length" of the transistor without causing confusion, the "channel length" is simply referred to as "length". The width and length of a MOS transistor are expressed as "W / L". For example, when it is mentioned that "the W / L of an NMOS transistor is 1 mm / 30 nm", it means "the width and length of the NMOS transistor are 1 mm and 30 nm respectively".

[0055] The present invention is presented in an engineering sense rather than a strict mathematical sense. For example, "A equals B" means "the difference between A and B is less than the engineering tolerance. "X is zero" means "the absolute value of X is less than the engineering tolerance."

[0056] In the present invention, when the meaning of a “circuit node” is clear from the context, a “circuit node” is often referred to as a “node” for short.

[0057] Throughout the present description, a ground node is a node with substantially zero voltage (0V). A power node is a node with substantially fixed voltage and is denoted by “V DD " indicates that this is a convention widely used in the literature. In the present invention, sometimes "V DD ” refers to the power node “V DD ”. For example, “V DD is 1.5V” obviously means that the power node V DD The voltage level on is 1.5V.

[0058] A DC node is a node with a substantially fixed voltage level. Both a power node and a ground node are DC nodes.

[0059] A circuit is a collection of transistors, capacitors, resistors, and / or other electronic devices interconnected in a specific way to perform a specific function. A network is a single circuit or a collection of multiple circuits.

[0060] An error amplifier is a circuit configured to receive a first input voltage and a second input voltage and output an output voltage such that the value of the output voltage is equal to a fixed value plus a variable value, and the variable value is approximately proportional to the difference between the first input voltage and the second input voltage, wherein the difference represents an error.

[0061] like Figure 2A As shown, Figure 2A 2 is a schematic diagram of a linear regulator 200 according to an embodiment of the present invention. The linear regulator 200 comprises an error amplifier 211 configured to receive an output voltage V (at an output node 201) o and the reference voltage Vr (at the reference node 202), and outputs the first control voltage V c1 ; A first PMOS transistor 212, configured to receive an input voltage V (at the power supply node 203) s And according to the first control voltage V c1 The control output first output current I o1 to the output node 201; an alternating current (AC) coupling capacitor 233, configured to convert the output voltage V o Coupled to AC coupling voltage V ac ; Non-inverting amplifier 221, configured to receive AC coupling voltage V ac , and outputs the second control voltage V c2 ; A second PMOS transistor 222, configured to receive an input voltage V (at the power supply node 203) s And according to the second control voltage V c2 The control output second output current I o2 to the output node 201; and a load 230 configured to draw a load current I from the output node 201 l In one embodiment, the linear regulator 200 further includes a short-circuit capacitor 213 configured to short-circuit the output node 201 to the ground.

[0062] The error amplifier 211 and the first PMOS transistor 212 form a first negative feedback control loop, and the AC coupling capacitor 223, the non-inverting amplifier 221 and the second PMOS transistor 222 form a second negative feedback control loop. The first negative feedback control loop is a direct current (DC) coupled low-speed loop configured to gradually adjust the first output current I o1 To track the load current I tThe second negative feedback control loop is an AC coupled high-speed loop, which is configured to adjust the second output current I in real time. o2 To track the load current I l The first negative feedback loop ensures that in a stable state, the output voltage V o Approximately equal to the reference voltage V r , and the second negative feedback loop ensures that when the load current It changes sharply, the output voltage V o There will be no large fluctuations and it can quickly recover from disturbances caused by sudden changes. The first negative feedback control loop does not need to have a wide bandwidth, so the restrictions set for stability are relatively loose. The second negative feedback loop needs to have a wide bandwidth and is therefore prone to instability. However, the AC coupling effectively introduces a zero point in the transfer function of the feedback loop, which helps to improve stability. Here, "transfer function", "feedback loop" and "zero point" are defined in textbooks on control theory, and the related concepts are well known to those skilled in the art, so they will not be described in detail here.

[0063] like Figure 2B As shown, Figure 2B 2 is a schematic diagram of an exemplary embodiment of the error amplifier 211. The error amplifier 211 is implemented by a single-stage operational amplifier, which includes: an NMOS transistor 211a implementing a current source, which is configured to b Establishing bias current I b Two NMOS transistors 211b and 211c implement a differential pair, configured to use a bias current I based on b The output voltage V o And reference voltage V r The difference between them is amplified into the first control voltage V c1 ; and two PMOS transistors 211d and 211e implement active loads for the differential pair to achieve differential to single-ended conversion. Here, “V DD " represents a power supply node. The error amplifier 211 is a well-known circuit in the prior art, and thus will not be described in detail here. In a further embodiment, the error amplifier 211 further includes a frequency compensation network, and the frequency compensation network includes a resistor 211f connected in series and a capacitor 211g for improving the stability of the first negative feedback control loop. The concept of frequency compensation is well-known in the prior art, and thus will not be described in detail here.

[0064] like Figure 2C As shown, Figure 2C FIG. 2 is a schematic diagram of an exemplary embodiment of the non-inverting amplifier 211. The non-inverting amplifier 221 is a two-stage amplifier including receiving an AC coupling voltage V acThe input stage 221_1 outputs the amplified voltage Vamp, and receives the amplified voltage V amp And output the second control voltage V c2 The purpose of the input stage 221_1 is to provide high gain so that the AC coupling voltage V ac The small change in can be amplified to the amplified voltage V amp The purpose of the output stage 221_2 is to provide a high driving capability so that even when the second PMOS transistor 222 is heavily loaded, the amplified voltage V amp A large change in the control voltage V c2 . As an example and not limitation, the input stage 221_1 is a common source amplifier implemented by a self-biased inverter, which includes an NMOS transistor 221a, a PMOS transistor 221b and a self-biased feedback resistor 221c; the output stage 221_2 is a class AB amplifier implemented by an inverter, which includes an NMOS transistor 221d and a PMOS transistor 221e. The concepts of "common source amplifier", "inverter", "self-bias" and "class AB amplifier" are well known to those skilled in the art and are not repeated here. The class AB amplifier can effectively provide high driving capability and is therefore used to implement the output stage 221_2. In one embodiment, the voltage gain of the input stage 221_1 is greater than the voltage gain of the output stage 221_2. By way of example and not limitation, the voltage gain of the input stage 221_1 is approximately 16dB, and the voltage gain of the output stage 221_2 is approximately 12dB.

[0065] In one embodiment, the linear regulator 200 is integrated and manufactured on a silicon substrate using CMOS process technology. For example, but not limited to: using 22nm CMOS process, the minimum channel length is 30nm; V s is 1.1V; V DD is 1.5V; V r is 0.9V; W / L (width / length) of NMOS transistor 211a is 2.5mm / 500nm; Vb is 650mV; I b10mA; W / L of NMOS transistors 211b and 211c is 1.25mm / 500nm; W / L of PMOS transistors 211d and 211e is 1.25mm / 500nm; resistor 211f is 20 ohms; capacitor 211g is 100pF; W / L of PMOS transistor 212 is 16mm / 30nm; AC coupling capacitor 223 is 5pF; W / L of NMOS transistor 221a is 0.6mm / 3 0nm; W / L of PMOS transistor 221b is 0.6mm / 30nm; resistor 221c is 25KOhm; W / L of NMOS transistor 221d is 1.2mm / 30nm; W / L of PMOS transistor 221e is 2.4mm / 30nm; W / L of PMOS transistor 222 is 16mm / 30nm; and short-circuit capacitor 213 is realized by a 11nF on-chip capacitor and a 11μF off-chip capacitor in parallel. The simulation results are shown in Figure 3 Here, the load current (I l ) and output voltage (V o ). Initially, the load current is 100mA (M1) and the output voltage is 904mV (M2). The load current rises rapidly from 100mA at time 1.0μs (M3) to 3.0A at time 1.01μs (M4). Incidentally, the output voltage drops to 872mV at time 1.02μs (M5), but rebounds quickly and stabilizes at 898mV at time 1.99μs (M6). The load current drops rapidly from 3.0A at time 3.0μs (M7) to 100mA at time 3.01μs (M8). Incidentally, the output voltage rises to 956mV at time 3.01μs (M9), but drops quickly and stabilizes at 904mV at time 4.18μs (M10). This indicates that the linear regulator 200 has a very fast load regulation capability.

[0066] like Figure 3As depicted in the flowchart 400, the voltage regulation method according to an embodiment of the present invention includes: (step 410) receiving an input voltage and a reference voltage; (step 420) combining a load circuit configured to draw a load current from an output node; (step 430) using an error amplifier to generate a first control voltage based on the difference between the reference voltage and the output voltage at the output node; (step 440) using a first PMOS transistor to convert the input voltage into a first output current provided to the output node based on the first control voltage; (step 450) using an AC coupling capacitor to couple the output voltage to the AC coupling voltage; (step 460) using a non-inverting amplifier to amplify the AC coupling voltage into a second control voltage; and (step 470) using a second PMOS transistor to convert the input voltage into a second output current provided to the output node based on the second control voltage.

[0067] Those skilled in the art will readily observe that many modifications and variations can be made to the apparatus and method while maintaining the teachings of the present invention.Therefore, the above disclosure should be interpreted as being limited only by the appended claims.

Claims

1. A linear regulator, comprising: an error amplifier configured to receive an output voltage at an output node and a reference voltage at a reference node, and output a first control voltage; a first P-channel metal oxide semiconductor transistor configured to receive an input voltage from a power node and output a first output current to the output node according to the first control voltage; an AC coupling capacitor configured to couple the output voltage to an AC coupling voltage; a non-inverting amplifier configured to receive the AC coupling voltage and output a second control voltage; a second P-channel metal oxide semiconductor transistor configured to receive an input voltage and output a second output current to an output node according to a second control voltage; as well as A load is configured to draw a load current from the output node.

2. The linear regulator according to claim 1, wherein: The error amplifier is a single-stage operational amplifier.

3. The linear regulator as claimed in claim 2, wherein the single-stage operational amplifier comprises: a current source configured to generate a bias current; a differential pair configured to use the bias current to amplify the difference between the output voltage and the reference voltage into the first control voltage; as well as An active load is used for the differential pair to achieve differential to single-ended conversion. 4 . The linear regulator as claimed in claim 3 , wherein the single-stage operational amplifier further comprises a frequency compensation network. 5 . The linear regulator as claimed in claim 4 , wherein the frequency compensation network comprises a resistor and a capacitor connected in series, and the capacitor is coupled to the first control voltage.

6. The linear regulator as claimed in claim 1, wherein the non-inverting amplifier is a two-stage amplifier comprising: an input stage configured to receive the AC-coupled voltage and output an amplified voltage; as well as An output stage is configured to receive the amplified voltage and output the second control voltage. 7 . The linear regulator as claimed in claim 6 , wherein the input stage has a higher voltage gain than the output stage.

8. The linear regulator of claim 6, wherein the input stage is a self-biased inverter.

9. The linear regulator as claimed in claim 6, wherein the output stage is an inverter.

10. A voltage stabilization method, comprising: receiving an input voltage and a reference voltage; In combination with a load, it is configured to draw a load current from an output node; Using an error amplifier to generate a first control voltage according to the difference between the reference voltage and an output voltage at the output node; Using a first P-channel metal oxide semiconductor transistor to convert the input voltage into a first output current provided to the output node according to the first control voltage; Using an AC coupling capacitor to couple the output voltage to an AC coupling voltage; Amplifying the AC coupling voltage into a second control voltage using a non-inverting amplifier; and A second P-type channel metal oxide semiconductor transistor is used to convert the input voltage into a second output current provided to the output node according to the second control voltage.

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