A statistical device for E / E / PE failure rate

Abstract

This application discloses a statistical device for calculating E / E / PE failure rates, belonging to the field of functional safety analysis. The device includes: a state transition module for generating a dynamic state transition diagram for an integrated circuit and determining a percentage variable of the number of times the circuit enters each state relative to a set total; a time stamp module for sending a trigger signal to a logic calculation module based on preset conditions and an output signal from the state transition module; and a logic calculation module for determining the average failure rate and instantaneous failure rate of the integrated circuit based on the trigger signal and the percentage variable. Because the device does not require the creation of a complex state transition matrix for the state transition relationships between the various operating states of the integrated circuit, nor does it require the use of complex fault tree formulas for calculation, the average failure rate and instantaneous failure rate of the integrated circuit can be determined through simple logical calculations. This makes the calculation process of the average failure rate and instantaneous failure rate of the integrated circuit simpler and more accurate.

Description

Technical Field

[0001] The present invention relates to the field of functional safety analysis, and in particular to a statistical device for E / E / PE failure rates. Background Art

[0002] In the IEC61508 standard, E / E / PE refers to electrical / electronic / programmable electronic systems. With increasing demands for safety and reliability, research on failure rates has become a hot topic. Existing techniques primarily use fault tree formulas and Markov transition matrices to determine the average and instantaneous failure rates of integrated circuits.

[0003] While the fault tree formula method can easily calculate the average failure rate of an integrated circuit, it cannot accurately represent the instantaneous failure rate of an integrated circuit. Consequently, the calculated instantaneous failure rate cannot provide accurate theoretical guidance for the actual operating state of the integrated circuit. Another method uses the Markov transition matrix to calculate the average and instantaneous failure rates of an integrated circuit. However, this method requires creating a state transition matrix based on the state transition relationships between the various operating states of the integrated circuit. If the integrated circuit is under complex voting conditions, the state transition relationships of the integrated circuit become extremely complex, making the compilation of the state transition matrix and the cyclic calculation process of the multidimensional matrix even more difficult and complex. Clearly, neither method can dynamically display the curve of the instantaneous failure rate of the integrated circuit over time; only the final curve results can be seen.

[0004] Therefore, it can be seen that how to easily and accurately calculate the average failure rate and instantaneous failure rate of integrated circuits is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0005] In view of this, the present invention aims to provide a statistical device for E / E / PE failure rates, which can easily and accurately calculate the average failure rate and instantaneous failure rate of integrated circuits. The specific scheme is as follows:

[0006] A statistical device for E / E / PE failure rate, comprising:

[0007] A state transition module, configured to generate a state transition dynamic graph of the target integrated circuit and determine a variable proportion of the number of times the target integrated circuit enters each state in the total number of each state;

[0008] A time marking module, configured to send a trigger signal to a logic calculation module according to a preset condition and an output signal of the state transfer module;

[0009] The logic calculation module is used to determine the average failure rate and the instantaneous failure rate of the target integrated circuit according to the trigger signal and the proportion variable.

[0010] Preferably, the state transfer module includes:

[0011] a region setting unit, configured to set a corresponding target graphical region for an operating state in which the target integrated circuit can enter a target operating state through a transition probability, and to convert the transition probability into a boundary line of the target graphical region after multiplying the transition probability by a preset total; wherein the target graphical region represents an integer between zero and the preset total;

[0012] A number sequence generating unit, configured to generate a target number sequence corresponding to the target graphic area;

[0013] a state setting unit, configured to set a corresponding counting variable for the number of times the target integrated circuit enters each operating state;

[0014] a zero-state transition unit, configured to count the number of times the target integrated circuit enters the initial operating state to obtain a basic counting variable, and simultaneously read a variable K0 from a sequence corresponding to the initial operating state based on the basic counting variable, and determine the transition state of the target integrated circuit based on the value of the variable K0 and a boundary line of a graphical region corresponding to the target integrated circuit entering the initial operating state; wherein the variable K0 is greater than or equal to 1 and less than or equal to the preset total number;

[0015] The target state transfer unit is used to count the number of times the target integrated circuit enters the i-th operating state to obtain a counting variable F i , and according to the counting variable F i Read the variable K from the sequence corresponding to the i-th operating state i , and according to the variable K i The value of and the boundary line of the graphic area corresponding to the target integrated circuit entering the i-th operating state determine the transfer state of the target integrated circuit; wherein, the variable K i is greater than or equal to 1 and less than or equal to the preset total number;

[0016] The periodic clearing unit is used to clear the number of times the target integrated circuit enters each operating state and directly transfer the operating state of the target integrated circuit to the initial operating state.

[0017] Preferably, when the target integrated circuit is a 1oo1 structure, the operating status of the target integrated circuit includes a normal operating status, a safe failure status, a first dangerous failure status that can be detected, a second dangerous failure status that can be recovered and not detected during periodic maintenance, and a third dangerous failure status that cannot be recovered and not detected during periodic maintenance.

[0018] Preferably, the state transfer module includes: a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, which can characterize the proportion of the number of times the target integrated circuit enters the normal operating state, the safe failure state, the first dangerous failure state, the second dangerous failure state and the third dangerous failure state in the respective set totals, and a sixth output terminal that can characterize the target time conversion coefficient.

[0019] Preferably, the logic calculation module includes: a first logic calculation unit for counting the number of times the target integrated circuit enters the safe failure state, and a second logic calculation unit for counting the number of times the target integrated circuit enters the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state;

[0020] The first output end of the state transfer module is connected to the input end of the time stamp module, the second output end and the sixth output end of the state transfer module are respectively connected to the first input end and the second output end of the first logic calculation unit, the third output end, the fourth output end, the fifth output end and the sixth output end of the state transfer module are respectively connected to the second input end, the third input end, the fifth input end and the fourth input end of the second logic calculation unit, and the first input end of the second logic calculation unit is connected to the output end of the time stamp module.

[0021] Preferably, the second logic calculation unit includes: a first adder, a second adder, a third adder, a first accumulator, a second accumulator, a delayer, a signal selector and a divider;

[0022] wherein the input end of the second adder is connected to the third input end of the first adder, the output end of the first adder is connected to the first input end of the third adder, the output end of the second adder is connected to the input end of the first accumulator, the output end of the first accumulator is connected to the input end of the second adder, and the output end of the first accumulator is also connected to the first input end of the signal selector, the output end of the third adder is connected to the second input end of the signal selector, the control end of the signal selector is connected to the output end of the delayer, the output end of the signal selector is connected to the input end of the second accumulator, and the output end of the second accumulator is respectively connected to the second input end of the third adder and the first input end of the divider;

[0023] Correspondingly, the input end of the delay device is the first input end of the second logic calculation unit, the first input end, the second input end and the third input end of the first adder are respectively the second input end, the third input end and the fifth input end of the second logic calculation unit, and the second input end of the divider is the fourth input end of the second logic calculation unit.

[0024] Preferably, the time stamp module includes:

[0025] a first signal triggering unit, configured to, when the basic count variable is less than or equal to a preset threshold, send a first trigger signal to the logic calculation module, so that the logic calculation module accumulates a variable representing a proportion of the number of times the target integrated circuit enters the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state relative to a set total number of the respective numbers;

[0026] a second signal triggering unit, configured to send a second triggering signal to the logic calculation module when the basic counting variable is greater than the preset threshold value, so that the logic calculation module clears the variables of the proportion of the number of times the target integrated circuit enters the first dangerous failure state and the second dangerous failure state in the respective set totals.

[0027] Preferably, it also includes:

[0028] An oscilloscope is used to display the operating time of the target integrated circuit, the average failure rate and the instantaneous failure rate of the target integrated circuit.

[0029] It can be seen that in the E / E / PE failure rate statistics device provided by the present invention, because there is no need to create a complex state transition matrix for the state transition relationship between the various operating states of the target integrated circuit, and there is no need to use a complex fault tree formula method for calculation, only a simple logical calculation module is used to count the proportion of the number of times the target integrated circuit enters the failure state in the respective set totals, and the average failure rate and instantaneous failure rate of the target integrated circuit can be accurately determined. In this way, the calculation process of the average failure rate and instantaneous failure rate of the integrated circuit can be simpler and more accurate. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0031] Figure 1 A structural diagram of a statistical device for E / E / PE failure rates provided by an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a boundary line of a graphic region 1 corresponding to an operating state 1 in a target integrated circuit;

[0033] Figure 3 A schematic diagram of a boundary line of a graphic region 2 corresponding to an operating state 2 in a target integrated circuit;

[0034] Figure 4 A schematic diagram of the structure of a state transfer module provided by an embodiment of the present invention when it is 1oo1;

[0035] Figure 5 A specific structural diagram of a statistical device for E / E / PE failure rates provided by an embodiment of the present invention;

[0036] Figure 6 A structural diagram of a second logic calculation unit provided by an embodiment of the present invention;

[0037] Figure 7 It is a 1oo1 state transition static diagram;

[0038] Figure 8 This is a diagram showing the statistical results of 1oo1 instantaneous failure rate statistics using an E / E / PE failure rate statistics device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0040] See Figure 1 , Figure 1 This is a structural diagram of a statistical device for E / E / PE failure rates provided by an embodiment of the present invention, the statistical device comprising:

[0041] The state transition module 11 is used to generate a state transition dynamic diagram of the target integrated circuit and determine the proportion variable of the number of times the target integrated circuit enters each state in the total number of each set state;

[0042] A time marking module 12 is used to send a trigger signal to the logic calculation module according to a preset condition and an output signal of the state transfer module;

[0043] The logic calculation module 13 is used to determine the average failure rate and the instantaneous failure rate of the target integrated circuit according to the trigger signal and the proportion variable.

[0044] In this embodiment, a statistical device for E / E / PE failure rates is provided. When the statistical device is used to collect statistics on the average failure rate and instantaneous failure rate of a target integrated circuit, the calculation process of the average failure rate and instantaneous failure rate of the target integrated circuit can be made simpler and more accurate.

[0045] The statistical device is provided with a state transition module, a time stamp module, and a logic calculation module. The state transition module is used to generate a state transition dynamic graph of the target integrated circuit and, based on the state transition dynamic graph of the target integrated circuit, determine the percentage of the number of times the target integrated circuit enters each state relative to the total number of times the target integrated circuit enters each state. It is understood that the target integrated circuit has various operating states, and these operating states can be converted or transferred to each other under certain trigger conditions. Therefore, based on the state transition dynamic graph of the target integrated circuit, the percentage of the number of times the target integrated circuit enters each state relative to the total number of times the target integrated circuit enters each state can be determined.

[0046] The time-stamping module is used to send a trigger signal to the logic calculation module based on preset conditions and the output signal of the state transition module, triggering the logic calculation module to calculate the average failure rate and instantaneous failure rate of the target integrated circuit. In other words, the time-stamping module can control when the logic calculation module begins the process of calculating the average failure rate and instantaneous failure rate of the target integrated circuit based on the output signal of the state transition module and preset conditions.

[0047] When the logic calculation module receives a trigger signal from the time-stamping module, it determines the average failure rate and instantaneous failure rate of the target integrated circuit based on the trigger signal and the percentage variable output by the state transition module. It is understood that because the state transition module can calculate the percentage variable of the number of times the target integrated circuit enters each state relative to a preset total, the average failure rate and instantaneous failure rate of the target integrated circuit can be determined by the logic calculation module accumulating and calculating the state transition module's output signals.

[0048] Compared to the prior art, this statistical device eliminates the need to create a complex state transition matrix for the state transition relationships between the various operating states of the target integrated circuit, nor does it require the use of complex fault tree formulas for calculations. Instead, the device simply accumulates and calculates the output signals of the state transition module using a logic calculation module under a trigger signal from a time stamp module to accurately determine the average failure rate and instantaneous failure rate of the target integrated circuit. Compared to the prior art, which requires the creation of a complex state transition matrix, this statistical device simplifies and facilitates the calculation of the average failure rate and instantaneous failure rate of the target integrated circuit.

[0049] It can be seen that in the E / E / PE failure rate statistics device provided in this embodiment, because there is no need to create a complex state transition matrix for the state transition relationship between the various operating states of the target integrated circuit, nor is there any need to use a complex fault tree formula method for calculation. Instead, the average failure rate and instantaneous failure rate of the target integrated circuit can be accurately determined by simply counting the proportion of the number of times the target integrated circuit enters the failure state in the respective set totals through a simple logical calculation module. This makes the calculation process of the average failure rate and instantaneous failure rate of the integrated circuit simpler and more accurate.

[0050] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the state transfer module includes:

[0051] a region setting unit, configured to set a corresponding target graphical region for an operating state that the target integrated circuit can enter into a target operating state through a transition probability, and to convert the transition probability into a boundary line of the target graphical region after multiplying it by a preset total; wherein the target graphical region represents an integer between zero and the preset total;

[0052] A number sequence generating unit, used for generating a target number sequence corresponding to a target graphic area;

[0053] a state setting unit, configured to set corresponding counting variables for the number of times the target integrated circuit enters each operating state;

[0054] a zero-state transition unit, configured to count the number of times the target integrated circuit enters the initial operating state to obtain a basic counting variable, and simultaneously read a variable K0 from a sequence corresponding to the initial operating state based on the basic counting variable, and determine the transition state of the target integrated circuit based on the value of the variable K0 and a boundary line of a graphical region corresponding to the target integrated circuit entering the initial operating state; wherein the variable K0 is greater than or equal to 1 and less than or equal to a preset total number;

[0055] The target state transfer unit is used to count the number of times the target integrated circuit enters the i-th operating state to obtain a counting variable F i , and according to the counting variable F i Read the variable K from the sequence corresponding to the i-th running state i , and according to the variable K i The value of and the boundary line of the graphic area corresponding to the target integrated circuit entering the i-th operating state determine the transfer state of the target integrated circuit; wherein, the variable K i Greater than or equal to 1 and less than or equal to the preset total number;

[0056] The periodic clearing unit is used to clear the number of times the target integrated circuit enters each operating state and directly transfer the operating state of the target integrated circuit to the initial operating state.

[0057] In this embodiment, the internal execution logic of the state transfer module is described in detail, wherein the state transfer module includes a region setting unit, a sequence generating unit, a state setting unit, a zero state transfer unit, a target state transfer unit, and a periodic zero clearing unit.

[0058] It should be noted that the trigger conditions in the state transition dynamic diagram are the core content of this application, and the state transition module described in this embodiment is to explain this trigger condition. It is understandable that, under normal circumstances, the trigger conditions in the state transition static diagram corresponding to the 1oo1 structure refer to: the failure probability corresponding to each operating state in the 1oo1 structure. However, in more complex integrated circuits, the failure data of each operating state of the integrated circuit is difficult to directly represent using data. For example, if the target integrated circuit has a 20% probability of transitioning from operating state 1 to operating state 2, then after the target integrated circuit has been running for a period of time, what state is the target integrated circuit in? The technical solution provided in this embodiment can better display the operating state position of the target integrated circuit at each moment.

[0059] Specifically, the state transition module pre-defines a preset total number mm and an empirical total number mm1. The region setting unit sets corresponding target graphical regions for the operating states in which the target integrated circuit can enter the target operating state through transition probabilities. The transition probabilities are multiplied by the preset total number mm to convert the target graphical regions into demarcation lines. The target graphical regions represent integers between zero and the preset total number mm. In other words, the region setting unit designs separate graphical regions for states that can enter other states through transition probabilities, with each graphical region representing an integer between 0 and mm.

[0060] Assuming that the transition probability of the target integrated circuit from one operating state to another is: λ1, λ2... or u1, u2..., etc., then each transition probability can be converted into a dividing line in the graphic area corresponding to the operating state. It can be understood that because the number of dividing lines is finite, a finite number of sub-areas will be formed in the graphic area corresponding to each operating state, and the number of dividing lines in each graphic area will also be equal to the number of transition paths when the target integrated circuit transitions from one operating state to another. See Figure 2 and Figure 3 , Figure 2 is a schematic diagram of the boundary line of the graphic area 1 corresponding to the operating state 1 in the target integrated circuit, Figure 3 Schematic diagram of the boundary line of the graphic area 2 corresponding to the operating state 2 in the target integrated circuit.

[0061] The number sequence generation unit is used to generate a target number sequence corresponding to the target graphic area. That is, the number sequence generation unit generates number sequences corresponding to all graphic areas in the target integrated circuit. For example, for graphic area 0 of the target integrated circuit, number sequence P0 is generated corresponding to graphic area 1, number sequence P1 is generated corresponding to graphic area 2, and so on. The numbers in each number sequence are randomly arranged, and number sequence P0 is a random number sequence consisting of numbers from 1 to mm, and number sequences P1, P2, etc. are random number sequences consisting of numbers from 1 to mm1.

[0062] The state setting unit is used to set the corresponding counting variable for the number of times the target integrated circuit enters each operating state. For example, the state setting unit sets the counting variable m to correspond to the initial operating state of the target integrated circuit, and sets the counting variable F 01 、F 02 ...F 0N They correspond to the 1st operating state, the 2nd operating state... and the Nth operating state of the target integrated circuit respectively; wherein the number of counting variables is equal to the number of operating states of the target integrated circuit, and the initial value of each counting variable is 0.

[0063] The zero-state transfer unit is used to count the number of times the target integrated circuit enters the initial operating state to obtain a basic counting variable, and at the same time read the variable K0 from the sequence corresponding to the initial operating state based on the basic counting variable, and determine the transfer state of the target integrated circuit based on the value of the variable K0 and the boundary line of the graphic area corresponding to the target integrated circuit entering the initial operating state.

[0064] In this embodiment, the target integrated circuit has N+2 states: operating state 0, operating state 1, operating state 2, operating state N, and cycle reset. The internal logic of operating state 0 includes the execution action and the corresponding transition conditions. Operating state 0 is the target integrated circuit's base operating state, and it is always possible to transition to other operating states based on the transition probability.

[0065] The execution action of the operation state 0 is: every time the target integrated circuit enters or returns to the initial operation state 0, the basic counting variable m=m+1, the number access variable K0 is set, the mth number in the sequence P0 is read, and the variable F1=F is set. 01 / mm, F2=F 02 / mm……F N =F 0N / mm, and the time conversion coefficient is mout. It should be noted that because the integers in sequence P0 are not equal to each other and are randomly arranged, when reading numbers from sequence P0, the reading starts from the first number in sequence P0. However, when the count of the counting variable m corresponding to the initial operating state begins to increase, the current operating state of the target integrated circuit may not necessarily be in the initial operating state. In this case, the data in sequence P0 will not be read until the operating state of the target integrated circuit returns to the initial operating state. At this time, the data in sequence P0 will be read based on the value of the counting variable m. In other words, the number in sequence P0 will be read according to the value of the counting variable m.

[0066] The transition conditions for operating state 0 are:

[0067] When m>the maintenance cycle time value of the target integrated circuit, the target integrated circuit will enter the cycle reset state;

[0068] When m ≤ the target integrated circuit's maintenance cycle time, the target integrated circuit will be transferred as follows:

[0069] When K0 ≤ the first dividing line value in the graphic region 0, the target integrated circuit will transition from the initial operating state 0 to the operating state 1; wherein each dividing line value is equal to each transition probability in the graphic region corresponding to the target integrated circuit operating state 0 multiplied by mm;

[0070] When the first dividing line value in the graphic region 0 is less than K0 and less than the second dividing line value in the graphic region 0, the target integrated circuit will transfer from the initial operating state 0 to the operating state 2;

[0071] Similarly, when K0>the last dividing line value in the graphic area 0, the target integrated circuit will jump to the initial operation state 0 again.

[0072] The jumps of the target integrated circuit to other operating states can be attributed to the target state transfer unit, wherein the target state transfer unit is used to count the number of times the target integrated circuit enters the i-th operating state to obtain the counting variable F i , and according to the counting variable F i Read the variable K from the sequence corresponding to the i-th running state i , and according to the variable K i The value of and the boundary line of the graphic area corresponding to the target integrated circuit entering the i-th operating state determine the transfer state of the target integrated circuit.

[0073] The internal logic of running state 1 includes the execution actions of running state 1 and the corresponding transition conditions. The execution actions of running state 1 include:

[0074] Each time the target integrated circuit enters or returns to the operating state 1, the counting variable F 01 =F 01 +1;

[0075] The transition conditions for operating state 1 are:

[0076] When K1 ≤ the first dividing line value in the graph area 1, the target integrated circuit will enter the operation state 1;

[0077] When the first dividing line value in the graphic area 1 is less than K1 and less than the second dividing line value in the graphic area 1, the target integrated circuit will be transferred to the operating state 2;

[0078] Similarly, when K1> the last dividing line value in the graph area 1, the target integrated circuit will jump to the operation state 1 again;

[0079] The internal logic of the running state N includes the execution action of the running state N and the corresponding transition conditions. The execution action of the running state N includes:

[0080] Each time the target integrated circuit enters or returns to the operating state N, the counting variable F 0N =F 0N +1;

[0081] The transition condition of operating state N is:

[0082] When KN ≤ the first dividing line value in the graphic area N, the target integrated circuit will enter the operation state 1;

[0083] When the first dividing line value in the graphics area 1 is less than K N ≤ the second dividing line value of the graphic area 1, the target integrated circuit will transfer to the operating state 2;

[0084] Similarly, when K N > the last dividing line value in the graphic area 1, the target integrated circuit will jump to the operating state N again.

[0085] In practical applications, several events E1, E2, E3, etc. can be connected to the input of the state transition module. When the target integrated circuit is in a certain operating state and cannot transition to another operating state through the transition probability, the target integrated circuit can be returned to the initial operating state 0 by combining the various events connected to the input of the state transition module. At the same time, the output of the state transition module can also be set with the following variables: the initial operating state count variable mm, the time conversion coefficient mout, and the proportion of the count variables of each operating state in the preset total number mm, to facilitate calculations in subsequent processes.

[0086] The periodic zeroing unit is used to clear the number of times the target integrated circuit enters each operating state and directly transfer the operating state of the target integrated circuit to the initial operating state. That is, the periodic zeroing unit will reset the counting variables m and F of the state transfer module. 01 、F 02 ...F 0N Clear all zeros and regenerate several new sequences. The number of sequences is the same as the number of graphic areas. Sequence P0 is an integer sequence from 1 to mm, and sequences P1, P2, etc. are all integer sequences from 1 to mm1. The numbers in each sequence are randomly arranged. The new sequences P0, P1, P2, etc. will overwrite the original sequences P0, P1, P2, etc.

[0087] As a preferred embodiment, when the target integrated circuit is a 1oo1 structure, the operating state of the target integrated circuit includes a normal operating state, a safe failure state, a first dangerous failure state that can be detected, a second dangerous failure state that can be recovered and not detected during periodic maintenance, and a third dangerous failure state that cannot be recovered and not detected during periodic maintenance.

[0088] This embodiment specifically illustrates the calculation process of the average failure rate and instantaneous failure rate of an integrated circuit using a 1oo1 integrated circuit. When the target integrated circuit has a 1oo1 structure, the operating states of the target integrated circuit include a normal operating state, a safe failure state, a detectable first dangerous failure state, a second dangerous failure state that can be recovered during periodic maintenance and remains undetected, and a third dangerous failure state that cannot be recovered during periodic maintenance and remains undetected. The normal operating state, safe failure state, first dangerous failure state, second dangerous failure state, and third dangerous failure state of the 1oo1 integrated circuit can be labeled OK, FS, FDD, FDU1, and FDU2, respectively.

[0089] See Figure 4 , Figure 4 A schematic diagram of the structure of a state transition module in a 1oo1 configuration according to an embodiment of the present invention is provided. As a preferred embodiment, the state transition module includes: a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, each capable of representing a variable representing the percentage of the number of times a target integrated circuit enters a normal operating state, a safe failure state, a first dangerous failure state, a second dangerous failure state, and a third dangerous failure state relative to a set total; and a sixth output terminal capable of representing a target time conversion coefficient.

[0090] If the target integrated circuit has a 1oo1 structure, then in order to facilitate the logical calculation of the subsequent process, the state transition module is provided with the first output terminal, the second output terminal, the third output terminal, the fourth output terminal, the fifth output terminal, which can represent the percentage of the number of times the target integrated circuit enters the normal operating state, the safe failure state, the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state in the total number of each set variable, and the sixth output terminal which can represent the target time conversion coefficient. For details, please refer to Figure 4 ,The 6 output terminals of the state transfer module are marked with m, FS, FDD, FDU1, FDU2 and mout respectively.

[0091] See Figure 5 , Figure 5 A detailed structural diagram of a device for counting E / E / PE failure rates provided by an embodiment of the present invention. As a preferred embodiment, the logic calculation module includes: a first logic calculation unit L1 for counting the number of times a target integrated circuit enters a safe failure state; and a second logic calculation unit L2 for counting the number of times the target integrated circuit enters a first dangerous failure state, a second dangerous failure state, and a third dangerous failure state;

[0092] Among them, the first output end of the state transfer module is connected to the input end of the time stamp module Y, the second output end and the sixth output end of the state transfer module are respectively connected to the first input end and the second output end of the first logic calculation unit L1, the third output end, the fourth output end, the fifth output end and the sixth output end of the state transfer module are respectively connected to the second input end, the third input end, the fifth input end and the fourth input end of the second logic calculation unit L2, and the first input end of the second logic calculation unit L2 is connected to the output end of the time stamp module Y.

[0093] It is understood that when the target integrated circuit has a 1oo1 structure, the various operating states of the 1oo1 can be roughly divided into two categories: one category has no impact on the safety of the 1oo1 operating state, such as the normal operating state and the safe failure state; the other category has an impact on the safety of the 1oo1 operating state, such as the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state. Therefore, a first logic calculation unit and a second logic calculation unit can be provided in the logic calculation module. The first logic calculation unit is used to count the number of times the 1oo1 enters the safe failure state, while the second logic calculation unit is used to count the number of times the 1oo1 enters the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state.

[0094] See Figure 6 , Figure 6 This is a structural diagram of a second logic calculation unit provided by an embodiment of the present invention. As a preferred embodiment, the second logic calculation unit L2 includes: a first adder A1, a second adder A2, a third adder A3, a first accumulator B1, a second accumulator B2, a delayer, a signal selector S, and a divider D;

[0095] Wherein, the input end of the second adder A2 is connected to the third input end of the first adder A1, the output end of the first adder A1 is connected to the first input end of the third adder A3, the output end of the second adder A2 is connected to the input end of the first accumulator B1, the output end of the first accumulator B1 is connected to the input end of the second adder A2, and the output end of the first accumulator B1 is also connected to the first input end of the signal selector S, the output end of the third adder A3 is connected to the second input end of the signal selector S, the control end of the signal selector S is connected to the output end of the delay device, the output end of the signal selector S is connected to the input end of the second accumulator B2, and the output end of the second accumulator B2 is respectively connected to the second input end of the third adder A3 and the first input end of the divider D;

[0096] Correspondingly, the input end of the delay device is the first input end of the second logic calculation unit L2, the first input end, the second input end and the third input end of the first adder A1 are respectively the second input end, the third input end and the fifth input end of the second logic calculation unit L2, and the second input end of the divider D is the fourth input end of the second logic calculation unit L2.

[0097] As a preferred embodiment, the time stamp module includes:

[0098] a first signal triggering unit, configured to send a first trigger signal to the logic calculation module when the basic count variable is less than or equal to a preset threshold, so as to cause the logic calculation module to accumulate a variable representing a proportion of the number of times the target integrated circuit enters the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state relative to a set total number of the respective numbers;

[0099] The second signal trigger unit is used to send a second trigger signal to the logic calculation module when the basic counting variable is greater than a preset threshold value, so that the logic calculation module clears the ratio variable of the number of times the target integrated circuit enters the first dangerous failure state and the second dangerous failure state to the respective set totals.

[0100] In this embodiment, the preset threshold can be set to the maintenance cycle TI of the target integrated circuit. That is, when the target integrated circuit reaches the maintenance cycle TI, the target integrated circuit is repaired and maintained. Specifically, when the basic counting variable m of the target integrated circuit entering the initial operating state is less than or equal to the preset threshold TI, a first trigger signal 0 is sent to the logic calculation module, so that the logic calculation module can accumulate the percentage variables of the number of times the target integrated circuit enters the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state relative to the respective set totals. When the basic counting variable m of the target integrated circuit entering the initial operating state is greater than the preset threshold TI, the second signal trigger unit in the time stamp module can send a second trigger signal 1 to the logic calculation module, so that the logic calculation module can clear the percentage variables of the number of times the target integrated circuit enters the first dangerous failure state and the second dangerous failure state relative to the respective set totals.

[0101] Based on the above embodiment, this embodiment further illustrates and optimizes the technical solution. As a preferred implementation, the above statistical device further includes:

[0102] The oscilloscope is used to display the operating time of the target integrated circuit, the average failure rate of the target integrated circuit, and the instantaneous failure rate.

[0103] In practical applications, an oscilloscope can also be provided in the statistical device to display the operating time, average failure rate, and instantaneous failure rate of the target integrated circuit. It is conceivable that by adding an oscilloscope to the statistical device, the user can clearly and intuitively view the various operating states and various operating data of the target integrated circuit, thereby further improving the user experience when using the statistical device. Of course, in practical applications, the number of oscilloscopes provided in the statistical device can also be adjusted according to the number of interfaces the user desires to display, which will not be discussed in detail here.

[0104] Based on the technical content disclosed in the above embodiments, this embodiment takes 1oo1 as an example to explain in detail the statistical process of the statistical device provided by the present invention. Figure 7 , Figure 7 This is a static diagram of the 1oo1 state transition. Assume that the probability of 1oo1 transitioning from OK to FS, FDD, FDU1, and FDU2 is s = 172 × 10 -9 dd=120×10 -9 and E×du, (1-E)×du, where du=601×10 -9 , detection coverage E = 85%; the probability of FDD transferring to OK is u0 = 0.125, the probability of FS transferring to OK is usd = 0.0417, the maintenance cycle time is 1 year TI = 8760 hours, and the total life cycle is expected to be 10 years.

[0105] Then, the calculation process of 1oo1 failure rate PFD is as follows:

[0106] Step 1: If the life cycle of 1oo1 is 10 years and calculated as 8760 hours per year, the preset total number mm can be set as 3600×8760×10≈32×10 7 , the total number of samples can be set as mm1 = 3 × 10 4 ;

[0107] Step 2: From Figure 7 It can be seen that the states that 1oo1 can enter through transition probability are: OK, FS, and FDD. Therefore, corresponding graphic regions can be designed for these three states, and named them OK region, FS region, and FDD region respectively. Then, the boundary values ​​of the OK region are: mm×s, mm×(s+dd), mm×(s+dd+E×du), and mm×(s+dd+du); the boundary value of the FS region is mm1×usd; the boundary value of the FDD region is mm1×u0;

[0108] Step 3: Since the number of graphic regions is 3, three number sequences P0, P1, and P2 need to be generated. Among them, P0 is an integer sequence from 1 to mm, P1 is an integer sequence from 1 to mm1, P2 is an integer sequence from 1 to mm1, and the numbers in P0, P1, and P2 are randomly arranged and non-repetitive;

[0109] Step 4: Since 1oo1 has 5 states, 5 counting variables need to be set up. Among them, the counting variable for the OK state is m, the counting variable for the FS state is FS0, the counting variable for the FDD state is FDD0; the counting variable for the FDU1 state is FDU10, and the counting variable for the FDU2 state is FDU20. The initial values of these counting variables are all 0;

[0110] Step 5: Use the stateflow state flow function in Matlab software to write the logic inside the state transition module, which has 6 states: OK, FS, FDD, FDU1, FDU2, and cycle clear. Among them, the internal logic of the OK state includes execution actions and corresponding transition conditions;

[0111] 1. The execution action of the OK state is: each time 1oo1 enters or returns to the OK state, the counting variable m = m + 1; set the number fetching variable Kok, and read the m-th number in the sequence P0. Assume variables FDD = FDD0 / mm, FDU1 = FDU10 / mm, FDD2 = FDD20 / mm, FS = FS0 / mm, and the time conversion coefficient mout = 8760;

[0112] The transition conditions of the OK state are:

[0113] When m > 3600 × TI = 31536000, the state transfers to the cycle clear state; <000​​​​​​​​​​​​​​​​​​

[0120] 2. Internal logic of FS state

[0121] Execution action: Each time entering or returning to the FS state, the counting variable FS0 = FS0 + 1, the number variable Ks is set, and the FS0th number in the sequence P1 is read;

[0122] Transfer conditions:

[0123] When K s >mm1×usd, return to FS state, and m=m+1;

[0124] When K s When ≤mm1×usd, transfer to OK state

[0125] 3. Internal logic of FDD state

[0126] Execution action: Each time entering or returning to the FDD state, the counting variable FDD0 = FDD0 + 1, the access variable Kdd is set, and the FDD0th number in the sequence P2 is read;

[0127] Transfer conditions:

[0128] When Kdd>mm1×u0, it returns to the FDD state and m=m+1;

[0129] When Kdd≤mm1×u0, transfer to OK state;

[0130] 4. Internal logic of FDU1 status

[0131] Execution action: Each time entering the FDU1 state, the counting variable FDD10 = FDD10 + 1;

[0132] No transfer condition logic;

[0133] 5. Internal logic of FDU2 status

[0134] Execution action: Each time entering FDU2 state, the counting variable FDD20 = FDD20 + 1;

[0135] No transfer condition logic.

[0136] 6. Internal logic of cycle clear state

[0137] Execution action: m = 0, FDD0 = 0, FS0 = 0, FFDU10 = 0, FFDU20 = 0

[0138] Regenerate 3 number sequences. The number sequence P0 is a random integer sequence from 1 to mm. The number sequences P1 and P2 are random integer sequences from 1 to mm1. The number sequences P0, P1, and P2 at this time will overwrite the original number sequences P0, P1, P2, and so on.

[0139] 7. Connect event E1 to the input of the state transition module. Event E1 can be simply designed as a continuous pulse, triggered by edge triggering. When the 1oo1 is in FDU1 or FDU2, if event E1 is triggered, the 1oo1 will return to the OK state.

[0140] Step 6: Figure 5 The state transfer module 1oo1 can be designed by the stateflow function in Matlab software and imported into the simulation design logic diagram in Simulink. Figure 5 In the structure shown, the oscilloscope connected to the backend of the time-stamping module Y displays the 1oo1 runtime data. When m at the 1oo1 output is greater than 31536000, the time-stamping module Y sends a trigger signal 1 to the second logic unit L1. The oscilloscope connected to the backend of the first logic calculation unit L1 accumulates the 1oo1 output variable FS over time. The oscilloscope connected to the backend of the second logic calculation unit L2 accumulates the 1oo1 output variables FDD, FDU1, and FDU2 over time.

[0141] Step 7: The second logic calculation unit L2 calculates the 1oo1 failure probability PFD(t), which is equal to the sum of the variables FDD, FDU1, and FDU2, and the cumulative time. If the failure rate is calculated as an average per hour, PFD(t) needs to be divided by the time conversion factor mout = 8760 hours.

[0142] Step 8: Set the maintenance period to TI = 8760 hours. When m > 31536000, the time stamp module outputs a trigger signal of 1 and sends this trigger signal to the second logic calculation unit L2. When the second logic control unit L2 receives the trigger signal 1 sent by the time stamp module, PFD(t) equals FDU2(TI). (Because the state FDU2 cannot be repaired during periodic maintenance, it is a residual failure.)

[0143] When m≤31536000, the time stamp module outputs a trigger signal 0 and enters the next maintenance cycle after a period of time delay in the second logic calculation unit L2. In the next maintenance cycle, the initial value of PFD(t) is FDU2(TI), and the value of PFD(t) is equal to the sum of the variables FDD, FDU1 and FDU2, the accumulated time, and FDU2(TI).

[0144] Step 9: Matlab will automatically repeat the calculations from step 5 to step 8 until the total time or number of runs reaches 3 years. The simulation ends and the 1oo1 PFD(t) curve for 3 years is obtained. Figure 8 , Figure 8 This is a diagram showing the statistical results of 1oo1 instantaneous failure rate statistics using an E / E / PE failure rate statistics device provided by an embodiment of the present invention.

[0145] When the method provided by the present invention is used to calculate the average failure rate and instantaneous failure rate of 1oo1, the failure rate of 1oo1 in the first year is PFD=4.93×10 -3 The failure rate in the second year is PFD = 6.32 × 10 -3 The failure rate in the third year is PFD = 6.86 × 10 -3 The average failure rate over three years is PFD avg =6.04×10 -3

[0146] Use the fault tree formula method to calculate the average failure rate of 1oo1: PFD avg ≈6.02×10 -3 ;

[0147] The average failure rate of 1oo1 is calculated using the Markov transfer matrix method: PFD avg ≈5.98×10 -3 .

[0148] Clearly, the average failure rate calculated by the method provided by the present invention has a relatively small error. Furthermore, as can be seen from the PFD(t) curve, the annual increase is not constant, meaning that the cumulative new failure rates are not equal each year. This makes the method more realistic than the fault tree formula method. Furthermore, the method provided by the present invention does not create a complex state transition matrix to represent the state transition relationships between the various operating states of the target integrated circuit. Instead, a simple logical calculation module simply calculates the percentage of the number of times the target integrated circuit enters a failure state relative to the total number of failures, accurately determining the average and instantaneous failure rates of the target integrated circuit. This makes the calculation of the average and instantaneous failure rates of the integrated circuit much simpler and more accurate.

[0149] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements limited by the sentence "comprise a..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0150] The above is a detailed introduction to the statistical device for E / E / PE failure rate provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A statistical device for E / E / PE failure rate, characterized in that: include: A state transition module, configured to generate a state transition dynamic graph of the target integrated circuit and determine a variable proportion of the number of times the target integrated circuit enters each state in the total number of each state; A time marking module, configured to send a trigger signal to a logic calculation module according to a preset condition and an output signal of the state transfer module; The logic calculation module is configured to determine the average failure rate and the instantaneous failure rate of the target integrated circuit according to the trigger signal and the proportion variable; Among them, the state transfer module includes: an area setting unit, which is used to set a corresponding target graphic area for the operating state in which the target integrated circuit can enter the target operating state through the transition probability, and multiply the transition probability by a preset total number to convert it into a dividing line of the target graphic area; wherein the target graphic area represents an integer from zero to the preset total number; a number series generation unit, which is used to generate a target number series corresponding to the target graphic area; a state setting unit, which is used to set a corresponding counting variable for the number of times the target integrated circuit enters each operating state; a zero state transfer unit, which is used to count the number of times the target integrated circuit enters the initial operating state to obtain a basic counting variable, and at the same time read a variable from the number series corresponding to the initial operating state according to the basic counting variable. , and according to the variables The value of and the boundary line of the graphic area corresponding to the target integrated circuit entering the initial operating state determine the transfer state of the target integrated circuit; wherein, the variable is greater than or equal to 1 and less than or equal to the preset total number; a target state transfer unit for the target integrated circuit to enter the first Count the number of running states to get the count variable , while according to the counting variable From the said Read the variables in the sequence corresponding to the running status , and according to the variables The value of the target integrated circuit and the The boundary line of the graphic area corresponding to the running state determines the transfer state of the target integrated circuit; wherein the variable Greater than or equal to 1 and less than or equal to the preset total number; a periodic clearing unit, used to clear the number of times the target integrated circuit enters each operating state, and directly transfer the operating state of the target integrated circuit to the initial operating state.

2. The statistical device according to claim 1, characterized in that When the target integrated circuit is a 1oo1 structure, the operating status of the target integrated circuit includes a normal operating status, a safe failure status, a first dangerous failure status that can be detected, a second dangerous failure status that can be recovered and not detected during periodic maintenance, and a third dangerous failure status that cannot be recovered and not detected during periodic maintenance.

3. The statistical device according to claim 2, characterized in that The state transfer module includes: a first output terminal, a second output terminal, a third output terminal, a fourth output terminal, a fifth output terminal, which can represent the proportion of the number of times the target integrated circuit enters the normal operating state, the safe failure state, the first dangerous failure state, the second dangerous failure state and the third dangerous failure state in the respective set totals; and a sixth output terminal that can represent the target time conversion coefficient.

4. The statistical device according to claim 3, characterized in that The logic calculation module includes: a first logic calculation unit for counting the number of times the target integrated circuit enters the safe failure state, and a second logic calculation unit for counting the number of times the target integrated circuit enters the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state; The first output end of the state transfer module is connected to the input end of the time stamp module, the second output end and the sixth output end of the state transfer module are respectively connected to the first input end and the second output end of the first logic calculation unit, the third output end, the fourth output end, the fifth output end and the sixth output end of the state transfer module are respectively connected to the second input end, the third input end, the fifth input end and the fourth input end of the second logic calculation unit, and the first input end of the second logic calculation unit is connected to the output end of the time stamp module.

5. The statistical device according to claim 4, characterized in that The second logic calculation unit includes: a first adder, a second adder, a third adder, a first accumulator, a second accumulator, a delayer, a signal selector and a divider; wherein the input end of the second adder is connected to the third input end of the first adder, the output end of the first adder is connected to the first input end of the third adder, the output end of the second adder is connected to the input end of the first accumulator, the output end of the first accumulator is connected to the input end of the second adder, and the output end of the first accumulator is also connected to the first input end of the signal selector, the output end of the third adder is connected to the second input end of the signal selector, the control end of the signal selector is connected to the output end of the delayer, the output end of the signal selector is connected to the input end of the second accumulator, and the output end of the second accumulator is respectively connected to the second input end of the third adder and the first input end of the divider; Correspondingly, the input end of the delay device is the first input end of the second logic calculation unit, the first input end, the second input end and the third input end of the first adder are respectively the second input end, the third input end and the fifth input end of the second logic calculation unit, and the second input end of the divider is the fourth input end of the second logic calculation unit.

6. The statistical device according to claim 3, characterized in that The time stamp module includes: a first signal triggering unit, configured to, when the basic count variable is less than or equal to a preset threshold, send a first trigger signal to the logic calculation module, so that the logic calculation module accumulates a variable representing a proportion of the number of times the target integrated circuit enters the first dangerous failure state, the second dangerous failure state, and the third dangerous failure state relative to a set total number of the respective numbers; a second signal triggering unit, configured to send a second triggering signal to the logic calculation module when the basic counting variable is greater than the preset threshold value, so that the logic calculation module clears the variables of the proportion of the number of times the target integrated circuit enters the first dangerous failure state and the second dangerous failure state in the respective set totals.

7. The statistical device according to claim 1, characterized in that Also includes: An oscilloscope is used to display the operating time of the target integrated circuit, the average failure rate and the instantaneous failure rate of the target integrated circuit.

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