Processing method of via stack structure, library establishing method, device and storage medium

Abstract

A via stack structure processing method, library establishment method, device and storage medium. The method for generating a via stack structure includes determining a first part of a via stack structure connecting a first metal layer and a second metal layer based on an alignment reference of the first metal layer, the second metal layer being a lower metal layer of the first metal layer, the alignment reference being a second part of the via stack structure, the second part connecting the second metal layer and a lower metal layer of the second metal layer, determining whether to adjust the position of the first part based on a metal layer mode of the first metal layer; wherein when the metal layer mode is a double pitch mode, the position of the first part is adjusted. The method can overcome the defects of the existing EDA tool provided by the inserted via stack structure method, and realize the definition of high-quality via stack structure, make the insertion of via stack structure independent of PDK and standard cell library and facilitate user use.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a processing method for generating a via ladder structure of a multi-layer metal, a library establishing method for the via ladder structure, a processing method for inserting the via ladder structure to a circuit unit, a processing device, and a storage medium. BACKGROUND

[0002] A via ladder structure, which can also be referred to as a via pillar, is a multi-layer via array that is introduced into a chip design to improve the performance of the design. When the via ladder structure is inserted at the pins of a circuit unit, the impedance of the connection line can be effectively reduced. Despite the many benefits, the insertion function of the via ladder structure provided by the current commercial electronic design automation (EDA) tool has many defects.

[0003] The method of defining and inserting the via ladder structure provided by the EDA tool is usually based on a winding track, for example, a wire winder inserts a target via ladder structure into the winding track. This method has the following defects:

[0004] (1) The insertion ratio of the via ladder structure is highly dependent on the process design kit (PDK) and the standard cell library, that is, it is highly dependent on the process of the semiconductor. For the PDK and the standard cell library that are not friendly to the via ladder structure, the insertion ratio of the via ladder structure can be as low as zero.

[0005] (2) Since the insertion of the via ladder structure is based on the definition of the track, the alignment of the via and the metal trace can never be better optimized, so the advantage brought by the via ladder structure itself is greatly discounted.

[0006] (3) Due to the spacing or pitch of the track, the area of the inserted via ladder structure is usually larger than the actual requirement, and the more layers of the via ladder structure, the larger the projected area of the via ladder structure, which will waste the winding resources and increase the electrical parameters of the winding, such as resistance and capacitance. SUMMARY

[0007] The processing method for generating a via stack structure of a multi-layer metal provided by at least one embodiment of the present disclosure includes: determining a first part of the via stack structure connecting a first metal layer and a second metal layer based on an alignment reference of the first metal layer, the second metal layer being a lower metal layer of the first metal layer, the alignment reference being a second part of the via stack structure, the second part connecting the second metal layer and a lower metal layer of the second metal layer, and determining whether to adjust the position of the first part based on a metal layer mode of the first metal layer; and wherein the position of the first part is adjusted when the metal layer mode is a double pitch mode.

[0008] For example, in the processing method provided by an embodiment of the present disclosure, the first part includes at least one via between the first metal layer and the second metal layer and at least one metal line segment in the first metal layer.

[0009] For example, in the processing method provided by an embodiment of the present disclosure, determining the first part of the via stack structure connecting the first metal layer and the second metal layer based on the alignment reference of the first metal layer includes: determining at least one track closest to a horizontal coordinate or a vertical coordinate of the alignment reference from a plurality of tracks pre-set in the first metal layer based on the horizontal coordinate or the vertical coordinate.

[0010] For example, in the processing method provided by an embodiment of the present disclosure, when the metal layer mode is a double pitch mode, the at least one metal line segment is moved so that every two metal line segments in the at least one metal line segment are spaced apart by two tracks.

[0011] For example, the processing method provided by an embodiment of the present disclosure further includes: adjusting the length of the at least one metal line segment based on a pre-set size of the via stack structure.

[0012] For example, the processing method provided by an embodiment of the present disclosure further includes: determining the center position of the at least one via based on the orthographic projection of the at least one metal line segment and the alignment reference.

[0013] For example, the processing method provided by an embodiment of the present disclosure further includes: the spacing between every two metal line segments in the at least one metal line segment is greater than or equal to a pre-set threshold value.

[0014] For example, the processing method provided by an embodiment of the present disclosure further includes: determining whether each metal line segment in the at least one metal line segment meets a minimum spacing rule or a cross-metal layer spacing rule; and moving the metal line segment meeting the minimum spacing rule or the cross-metal layer spacing rule away from a pre-set track when the determination result is yes.

[0015] For example, in the processing method provided by an embodiment of the present disclosure, the at least one track closest to the abscissa or the ordinate is determined from the plurality of tracks pre-set in the first metal layer based on the abscissa or the ordinate of the alignment reference, comprising: establishing a mapping table comprising a mapping relationship between track identification and track position, wherein each track in the plurality of tracks has a different track identification, and the track position is represented by a plurality of pre-stored abscissas or a plurality of ordinates; determining the position of the alignment reference, the position of the alignment reference comprising an abscissa and an ordinate; searching for the plurality of abscissas or the plurality of ordinates pre-recorded in the mapping table according to the abscissa or the ordinate of the position of the alignment reference, to determine at least one abscissa closest to the abscissa of the position of the alignment reference or at least one ordinate closest to the ordinate of the position of the alignment reference; determining at least one track corresponding to the at least one abscissa as the at least one track closest to the abscissa, or determining at least one track corresponding to the at least one ordinate as the at least one track closest to the ordinate.

[0016] An embodiment of the present disclosure provides a method for establishing a library of via stack structures, comprising: obtaining parameter information of a plurality of via stack structures; classifying the plurality of via stack structures according to electrical parameters and winding resources; marking the plurality of via stack structures based on the geometric structure of the input port of each of the plurality of via stack structures; and performing pattern extraction on the classified and marked plurality of via stack structures to obtain a plurality of via stack structure templates; wherein the pattern extraction comprises extracting a plurality of preset parameters.

[0017] For example, in the establishing method provided by an embodiment of the present disclosure, the parameter information of the plurality of via stack structures is obtained by: obtaining the parameter information from the historically generated via stack structures; and / or performing the processing method of any one of the above first method embodiments on the circuit unit to establish the via stack structure of the circuit unit and obtain the parameter information.

[0018] An embodiment of the present disclosure provides a processing method for inserting a via stack structure into a circuit unit, comprising: based on the geometric structure of the input port of the circuit unit, performing the processing method of any one of the above first method embodiments on at least one metal layer of the circuit unit; or based on the geometric structure of the input port of the circuit unit, obtaining a target via stack structure template corresponding to the circuit unit from the library obtained by performing the establishing method of any one of the above second method embodiments; and inserting the target via stack structure template into the circuit unit.

[0019] For example, in the processing method provided by an embodiment of the present disclosure, based on the geometry of the input port of the circuit unit, for at least one metal layer of the circuit unit, the processing method of any one of the first method embodiments is performed, including: obtaining a first part corresponding to each of the at least one metal layer of the circuit unit, and the via stack structure corresponding to the circuit unit is composed of at least one first part.

[0020] For example, in the processing method provided by an embodiment of the present disclosure, based on the geometry of the input port of the circuit unit, the target via stack structure template corresponding to the circuit unit is obtained from the library obtained by performing the establishing method of any one of the second method embodiments, including: based on the geometry of the input port of the circuit unit, searching at least one candidate of the via stack structure template corresponding to the geometry from the library; and according to the characteristic parameters of the circuit unit, screening the at least one candidate to obtain the target via stack structure template corresponding to the circuit unit, the characteristic parameters including electrical parameters and / or winding resources.

[0021] For example, in the processing method provided by an embodiment of the present disclosure, according to the electrical parameters and / or winding resources of the circuit unit, the at least one candidate is screened, including: according to the characteristic parameters, performing pattern matching on the at least one candidate to obtain one candidate with the highest pattern matching degree as the target via stack structure template corresponding to the circuit unit.

[0022] For example, in the processing method provided by an embodiment of the present disclosure, based on the geometry of the input port of the circuit unit, at least one candidate of the via stack structure template corresponding to the geometry is searched from the library, including: based on the geometry, searching all via stack structure templates in the library; and when the density of the metal wire segments and / or vias is less than a preset threshold, returning the corresponding via stack structure template of the metal wire segments and / or vias with the density less than the preset threshold as the candidate, wherein the via stack structure template is composed of the metal wire segments and the vias.

[0023] For example, in the processing method provided by an embodiment of the present disclosure, the target via stack structure template is inserted into the circuit unit, including: merging the target via stack structure template with the circuit unit; establishing a logical connection between the target via stack structure template and the electronic devices inside the circuit unit; and establishing a connection between the target via stack structure template and the input and / or output outside the circuit unit.

[0024] At least one embodiment of the present disclosure provides a processing device, including a processor and a memory, the memory storing one or more computer program instruction modules; wherein the one or more computer program instruction modules are executed by the processor to implement the processing method or the establishing method described above.

[0025] The at least one embodiment of the present disclosure provides a computer readable storage medium, which is non-transitory and stores computer executable instructions, wherein the computer executable instructions, when executed by a processor, implement a processing method or a building method described above.

[0026] As described above, the embodiments of the present disclosure respectively provide a method for generating a via stack structure of a multi-layer metal, a method for building a library for the via stack structure, a method for inserting the via stack structure to a circuit unit, a processing device and a storage medium. The method or device provided by the at least one embodiment of the present disclosure can overcome the defects of the method for inserting the via stack structure provided by the existing EDA tool, which has many limited conditions and poor performance, and achieve the technical effects of defining a high-quality via stack structure, making the insertion of the via stack structure independent of the PDK and the standard cell library and facilitating the use of the user. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0028] Figure 1 A flowchart of a method for generating a via stack structure of a multi-layer metal provided by the at least one embodiment of the present disclosure;

[0029] Figure 2A A unit schematic diagram of a via stack structure to be inserted for a plurality of output pins provided by the at least one embodiment of the present disclosure;

[0030] Figure 2B A schematic diagram of a via stack structure generated for a bottom metal layer provided by the at least one embodiment of the present disclosure;

[0031] Figure 2C A schematic diagram of a via stack structure generated for a middle metal layer provided by the at least one embodiment of the present disclosure;

[0032] Figure 2D A schematic diagram of a via stack structure generated for a top metal layer provided by the at least one embodiment of the present disclosure;

[0033] Figure 3A A unit schematic diagram of a via stack structure to be inserted for a single output pin provided by the at least one embodiment of the present disclosure;

[0034] Figure 3B Another schematic diagram of a via stack structure generated for a bottom metal layer provided by the at least one embodiment of the present disclosure;

[0035] Figure 4A flowchart of determining the closest track provided for at least one embodiment of the present disclosure;

[0036] Figure 5 A flowchart of a method of establishing a library for via stack structures provided for at least one embodiment of the present disclosure;

[0037] Figure 6 A flowchart of a method of inserting a via stack structure to a circuit unit provided for at least one embodiment of the present disclosure;

[0038] Figure 7 A schematic diagram of a processing device provided for at least one embodiment of the present disclosure;

[0039] Figure 8A An equivalent resistance diagram of a via stack structure provided for at least one embodiment of the present disclosure;

[0040] Figure 8B A result diagram of a via stack structure for reducing resistance provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0042] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as the common meanings of those terms to those skilled in the art of the present disclosure. The terms "first", "second", and similar terms used in the present disclosure do not necessarily mean any order, number, or importance, but are used to distinguish different components. Similarly, the terms "one", "a", or "the" and similar terms do not mean a quantity restriction, but mean that there is at least one. The terms "include", "comprise", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0043] The method for generating a via stack structure of a multi-layer metal provided by at least one embodiment of the present disclosure includes: determining a first part of a via stack structure connecting a first metal layer and a second metal layer based on an alignment reference of the first metal layer, the second metal layer being a lower metal layer of the first metal layer, the alignment reference being a second part of the via stack structure, the second part connecting the second metal layer and a lower metal layer of the second metal layer, and determining whether to adjust a position of the first part based on a metal layer mode of the first metal layer; and wherein the position of the first part is adjusted when the metal layer mode is a double pitch mode.

[0044] The method for establishing a library for a via stack structure provided by at least one embodiment of the present disclosure includes: obtaining parameter information of a plurality of via stack structures; classifying the plurality of via stack structures according to electrical parameters and winding resources; marking the plurality of via stack structures based on a geometry of an input port of each of the plurality of via stack structures; and performing pattern extraction on the plurality of via stack structures after classification and marking to obtain a plurality of via stack structure templates; wherein the pattern extraction includes extracting a plurality of preset parameters.

[0045] The method for inserting a via stack structure into a circuit unit provided by at least one embodiment of the present disclosure includes: performing the method of any one of the above first method embodiments for at least one metal layer of the circuit unit based on a geometry of an input port of the circuit unit; or obtaining a target via stack structure template corresponding to the circuit unit from the library obtained by performing the method of any one of the above second method embodiments based on the geometry of the input port of the circuit unit; and inserting the target via stack structure template into the circuit unit.

[0046] The processing device provided by at least one embodiment of the present disclosure includes a processor and a memory having one or more computer program instruction modules stored therein; wherein the one or more computer program instruction modules are executed by the processor to implement the above processing method or library establishment method.

[0047] The method or device provided by at least one embodiment of the present disclosure can overcome the defects of the method for inserting a via stack structure provided by the existing EDA tool, such as multiple limitation conditions and poor performance, and achieve the technical effects of defining a high-quality via stack structure, making the insertion of the via stack structure independent of a PDK and a standard cell library, and facilitating user use.

[0048] The embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that the same patterns in the drawings represent the same metal layer, the same via, the same pin, or the same metal line segment, and similar reference numerals can represent the same or similar components.

[0049] Figure 1A flow chart of a method of generating a via stack structure of multi-layer metal is shown according to at least one embodiment of the present disclosure.

[0050] As shown in Figure 1 The method 100 of generating a via stack structure of multi-layer metal includes:

[0051] At step S101, a first part of the via stack structure connecting the first metal layer and the second metal layer is determined based on an alignment reference of the first metal layer. The second metal layer is a lower metal layer of the first metal layer, and the alignment reference is a second part of the via stack structure connecting the second metal layer and a lower metal layer of the second metal layer.

[0052] In embodiments of the present disclosure, the via stack structure includes a plurality of vias and a plurality of metal segments. For example, there are metal segments in each of the 6 metal layers of the via stack structure, or there are metal segments in 5 of the 6 metal layers, etc. The metal segments in embodiments of the present disclosure can also be referred to as traces, wires, etc. The width of the metal segments is determined by the manufacturing process, such as PDK, and the length is determined according to the width of the cell where the via stack structure is located, which can also be a preset value.

[0053] For integrated circuit design involving semiconductors, the circuit is composed of multiple metal layers, such as 6 layers, 8 layers, 9 layers, etc. In step S101, the first metal layer can be a metal layer of the multiple metal layers that does not have a via. For example, for 8 metal layers, since the output pin between M0 and M1 has been determined, the first metal layer cannot be M0 and M1, but can be M2-M7. The alignment reference can be a via, a track, or a metal segment. The output pin belongs to the via, and the position of the output pin is predetermined or pre-set and cannot be changed. In this embodiment, the alignment reference can be the output end of a standard cell, which can also be a metal layer of the multiple metal layers that has a via, where the output end of the standard cell is the top metal layer of the standard cell. The standard cell is realized by a substrate and an oxide layer thereon when the semiconductor is manufactured, which is packaged into a standardized standard cell and included in a standard cell library. It can be understood that different processes or different manufacturers have different standard cells. For example, for all metal layers of the multiple metal layers, the alignment reference can be the output end of the standard cell. For example, for the lower metal layers of the multiple metal layers, the alignment reference can be the output end of the standard cell, and for the higher metal layers, the alignment reference can be a metal layer of the multiple metal layers that has a via and is lower than the bottom layer of the higher metal layer. It can be understood that the alignment reference can also be referred to as a reference layer.

[0054] For example, when the first metal layer is M2 and the second metal layer is Ml, the alignment reference is the via between M0 and Ml. For another example, when the first metal layer is M3 and the second metal layer is still Ml, the alignment reference is the via between M0 and Ml. For another example, when the first metal layer is M4-M7, the second metal layer corresponds to M2-M5 respectively, and the alignment reference corresponds to the metal line segment in M2-M5 respectively. For another example, when the first metal layer is M8 and the second metal layer is M6, the alignment reference is the middle position of the metal line segment in M6.

[0055] After step S101 is performed, the first part of the via stack structure connecting the first metal layer and the second metal layer is determined. A complete via stack structure of a multi-layer metal includes a plurality of first parts. For example, a via stack structure of a 6-layer metal includes 5 first parts.

[0056] Optionally, the first part includes at least one via between the first metal layer and the second metal layer and at least one metal line segment in the first metal layer.

[0057] For example, when the first metal layer is M2 and the second metal layer is Ml, the first part is 6 vias and 2 metal line segments between Ml and M2.

[0058] In addition to determining the position of the metal line segment, the center position of the at least one via can also be determined based on the orthogonal projection of the at least one metal line segment and the alignment reference. Thus, according to the center position of the via, the via can be generated.

[0059] Optionally, when step S101 is performed, the at least one track closest to the horizontal coordinate or the vertical coordinate of the alignment reference is determined from a plurality of preset tracks in the first metal layer based on the horizontal coordinate or the vertical coordinate.

[0060] For example, when the first metal layer is M4, N tracks are preset in M4, and the vertical coordinates of 2 metal line segments in M2 are the alignment reference, at least 2 tracks closest to the 2 vertical coordinates are determined from the N tracks respectively, i.e. at least 1 track closest to each vertical coordinate needs to be determined. N is a positive integer and the value of N is usually determined by the process.

[0061] For another example, when the first metal layer is M7, N tracks are preset in M7, and the horizontal coordinates of 2 metal line segments in M5 are the alignment reference, at least 1 track closest to each of the 2 horizontal coordinates is determined from the N tracks.

[0062] Optionally, when the closest track is determined, a mapping table including a mapping relationship between track identifiers and track positions can be established, wherein each track in the plurality of tracks has a different track identifier, and the track positions are represented by a plurality of horizontal coordinates or a plurality of vertical coordinates. A position of the alignment reference is determined, and the position of the alignment reference includes a horizontal coordinate and a vertical coordinate. According to the horizontal coordinate or the vertical coordinate of the position of the alignment reference, a plurality of horizontal coordinates or a plurality of vertical coordinates recorded in the mapping table are searched, at least one horizontal coordinate closest to the horizontal coordinate of the position of the alignment reference or at least one vertical coordinate closest to the vertical coordinate of the position of the alignment reference is determined. At least one track corresponding to the at least one horizontal coordinate is determined as the at least one track closest to the horizontal coordinate, or at least one track corresponding to the at least one vertical coordinate is determined as the at least one track closest to the vertical coordinate.

[0063] In the embodiment, the track identifier can be the number of the track, and the track position can be represented by a horizontal coordinate or a vertical coordinate where the track is located, for example, the track in the metal layer M0 is represented by a horizontal coordinate, and the track in the metal layer M1 is represented by a vertical coordinate. It should be noted that the tracks in the same metal layer are not represented by different types of coordinates. The alignment reference can be a via or a track, and thus the position of the alignment reference corresponding thereto is (horizontal coordinate, vertical coordinate) or a single horizontal coordinate / vertical coordinate. Even if the alignment reference is a via, only the horizontal coordinate or the vertical coordinate is used when searching the mapping table.

[0064] After the horizontal coordinate or the vertical coordinate of the alignment reference is known, more than one horizontal coordinate or vertical coordinate can be found from the mapping table by using the horizontal coordinate and the vertical coordinate. For example, the horizontal coordinate of the alignment reference is Xi, and 201 horizontal coordinates X0, X1, …, X200 are recorded in the mapping table in advance. According to Xi, X50 and X51 are determined as the two closest horizontal coordinates to Xi, i.e., |Xi-X50| = |Xi-X51|, and thus two closest tracks are obtained.

[0065] Returning to continue referring to Figure 1 , in step S103, whether to adjust the position of the first part is determined based on a metal layer mode of the first metal layer.

[0066] For example, the metal layer mode is pre-set for each layer of the multi-layer metal, including a single pitch mode and a double pitch mode. In the single pitch mode, there is one track between two metal line segments, and in the double pitch mode, there are two tracks between two metal line segments. Thus, whether to adjust the position of the first part is determined according to the pre-set metal layer mode.

[0067] In step S105, when the metal layer mode is the double pitch mode, the position of the first part is adjusted.

[0068] For example, if all the metal line segments in the first part determined in step S101 are in the default single pitch mode, then when the metal layer mode is determined to be the double pitch mode, the positions of the metal line segments in the first part are adjusted. When the metal layer mode is the single pitch mode, the positions of the metal line segments in the first part do not need to be adjusted.

[0069] Optionally, when the metal layer mode is the double pitch mode, at least one metal line segment is moved so that each two metal line segments among the at least one metal line segment are spaced apart by two tracks.

[0070] For example, when the metal layer mode of M3 is determined to be the double pitch mode, and there are 3 metal line segments in M3, then by moving only 2 metal line segments among the 3 metal line segments, the distance between each two metal line segments among the 3 metal line segments can be adjusted to be spaced apart by two tracks. For another example, when the metal layer mode of M4 is determined to be the double pitch mode, and there are 2 metal line segments in M4, then by moving only 1 metal line segment among the 2 metal line segments, the distance between the 2 metal line segments can be adjusted to be spaced apart by two tracks.

[0071] Further optionally, any at least one metal line segment among the plurality of metal line segments is selected to adjust the distance between each two metal line segments.

[0072] After step S105 is performed, the length of the metal line segment can also be adjusted, for example, based on the preset size of the via stack structure, the length of at least one metal line segment is adjusted. When the length of the metal line segment is adjusted, it includes increasing and decreasing the length of the metal line segment. Decreasing the length of the metal line segment is beneficial to reduce the overall size of the via stack structure, while increasing the length of the metal line segment is beneficial to the design of the via stack structure being simpler and more convenient and facilitating the layout of the winding.

[0073] Optionally, in addition to the double pitch mode and the single pitch mode specified by the metal layer mode, the distance between each two metal line segments among the at least one metal line segment is greater than or equal to a preset threshold value. That is, a minimum distance value can be set between the metal line segments, so as to ensure that the metal line segments can be correctly separated and not disconnected during manufacturing.

[0074] In some embodiments, there are some rule restrictions for the design of the via stack structure, such as a minimum spacing rule or a cross-metal layer spacing rule. It can be determined whether each metal line segment among the at least one metal line segment meets the minimum spacing rule or meets the cross-metal layer spacing rule. When the determination result is yes, the metal line segment that meets the minimum spacing rule or meets the cross-metal layer spacing rule is moved away from the preset track. When the determination result is no, the metal line segment does not need to be moved.

[0075] For example, in M2, there are two metal line segments, and it is needed to determine whether both of the two metal line segments meet the minimum spacing rule or the cross-metal layer spacing rule. If one of the two metal line segments does not meet the minimum spacing rule, the metal line segment is moved away from the original track, so that the central axis of the orthographic projection of the metal line segment is not coincident with the original track. In this embodiment, the priority of the minimum spacing rule and the cross-metal layer spacing rule is higher than the requirement of the metal layer mode for the spacing between the metal line segments.

[0076] The method in this embodiment provides a general scheme for generating a via stack structure of a multi-layer metal, so that the same method can be applied to generate a via stack structure regardless of the type of process, the position of the metal layer in the multi-layer metal, or the number of different output pins, so that the via stack structure is not related to the process or EDA tool, thereby widening the application range of the method in this embodiment and improving the insertion rate of the via stack structure.

[0077] Figure 2A A schematic diagram of a unit of a via stack structure to be inserted for a plurality of output pins is provided for at least one embodiment of the disclosure.

[0078] In Figure 2A Unit 200 includes metal layer M0, metal layer M1, and output pin 201. Metal layer M0 is the bottommost metal layer, and metal layer M1 is the metal layer above metal layer M0. Metal layer M1 is not necessarily the metal layer immediately adjacent to metal layer M0. As an example, output pin 201 has a total of 6, and output pin 201 is a 2-fold redundant structure between metal layer M0 and metal layer M1. That is, output pin 201 is a via connecting metal layer M0 and metal layer M1. The number of output pins 201 is greater than or equal to 2.

[0079] Figure 2A Some dashed lines are also shown in the figure, which are tracks in the metal layer (also referred to as traces, winding tracks, etc.). It should be understood that, Figure 2A Not all tracks are shown in the figure, and the distance between the tracks is only schematic.

[0080] Figure 2B A schematic diagram of a via stack structure generated for a bottom metal layer is shown.

[0081] In Figure 2B In this embodiment, via stack structure 210 includes metal layer M0, metal layer M1, metal layer M2, metal layer M3, output pin 201, via 202, and via 203.

[0082] Generally speaking, for multi-layer metallization processes, the bottom metal layer typically refers to the first one-third to one-half of the metal layer, the middle metal layer refers to the middle one-third of the metal layer, and the top metal layer, in the disclosed embodiments, generally refers to the topmost metal layer. For example, if a multi-layer metallization process includes nine metal layers, the bottom metal layer may be four layers, M0-M3, the middle metal layer may be four layers, M4-M7, and the top metal layer may be M8.

[0083] and Figure 2A Similarly, metal layer M2 is located above metal layer M1, and metal layer M3 is located above metal layer M2. The number of vias 202 is 6, and the number of vias 203 is 6. Via 202 is a via between metal layer M1 and metal layer M2, and via 203 is a via between metal layer M2 and metal layer M3.

[0084] Tracks in two metal layers spaced apart have the same orientation. For example, the tracks in metal layers M0 and M2 are horizontal, while the tracks in metal layers M1 and M3 are vertical. Furthermore, as the number of metal layers increases, the spacing between tracks in the upper metal layer differs from that in the lower metal layer, and the projections of tracks in different layers do not necessarily completely overlap. For example, the tracks in metal layers M1 and M3 do not overlap, and the spacing between the tracks is also different.

[0085] Figure 2B The via stack structure 210 is generated or determined based on the unit 200 by the method for generating a multi-layer metal via stack structure in the above method embodiment.

[0086] For example, first determine the center position of output pin 201 as (X, Y). For metal layer M2, use the vertical coordinate "Y" of output pin 201 to determine the closest track in M2. If there are 3*2 output pins, a total of 2 tracks are determined and 2 metal segments are obtained. Then, if M2 is in double-pitch mode, 2 tracks are reserved between the metal segments of M2. For metal layer M3, use the horizontal coordinate "X" of output pin 201 to determine the closest track in M3. If there are 3*2 output pins, a total of 3 tracks are determined and 3 metal segments are obtained. Then, if M3 is in double-pitch mode, 2 tracks are reserved between 2 adjacent metal segments among the 3 metal segments of M3.

[0087] Figure 2C A schematic diagram of a via stack structure generated for a mid-level metal layer is provided for at least one embodiment of the present disclosure.

[0088] exist Figure 2C In the embodiment, the via stack structure 220 includes a metal layer M4, a metal layer M5 and a via 204.

[0089] The metal layer M4 is above the metal layer M3, the metal layer M5 is above the metal layer M4, and the number of the via holes 204 is 4. The via holes 204 are the via holes between the metal layer M4 and the metal layer M5, and the via holes between the metal layer M3 and the metal layer M4 are not shown in the figure, and the metal layers M0-M2 are also not shown in the figure.

[0090] Figure 2D A schematic diagram of a via hole stack structure generated for a top metal layer is provided for at least one embodiment of the present disclosure.

[0091] In Figure 2C , the via hole stack structure 220 includes the metal layer M6, the metal layer M7, the metal layer M8, the via hole 205, and the via hole 206.

[0092] The metal layer M6 is above the metal layer M5, the metal layer M7 is above the metal layer M6, the number of the via hole 205 is 4, and the number of the via hole 206 is 2. The via hole 205 is the via hole between the metal layer M6 and the metal layer M7, and the via hole 206 is the via hole between the metal layer M7 and the metal layer M8. The via holes between the metal layer M5 and the metal layer M6 are not shown in the figure, and the metal layers M0-M5 are also not shown in the figure.

[0093] The via hole stack structure 220 and the via hole stack structure 230 are also determined or produced based on the unit 200 by using, for example, the method in Figure 1 . For details, refer to the above method embodiment part and Figure 2B related description, and the difference is that the alignment reference can be the output pin 201 or the metal line segment in the second layer metal layer below the current metal layer.

[0094] Figure 3A A unit schematic diagram of a via hole stack structure to be inserted for a single output pin is provided for at least one embodiment of the present disclosure.

[0095] In Figure 3A , the unit 300 includes the metal layer M0, the metal layer M1, the output pin 301, and the via hole 302. The metal layer M0 is the bottommost metal layer, and the metal layer M1 is the metal layer above the metal layer M0. The metal layer M1 is not necessarily the metal layer immediately adjacent to the metal layer M0.

[0096] In Figure 3A , the output pin 301 is 1 in total, and according to the scheme of the present embodiment, it needs to be expanded to expand the symmetrical 2 via holes 302. The via hole 302 is the via hole connecting the metal layer M0 and the metal layer M1. The via hole 302 can be understood as a 2-fold redundant output pin, and by expanding a single output pin, Figure 3A The unit 300 in may also apply the method in the above method embodiment to generate the via hole stack structure.

[0097] Figure 3A Some dashed lines are also shown in the figure, which are tracks in the metal layer, and it should be understood that, Figure 3A not all tracks are shown in the figure, and the distance between the tracks is only for illustration.

[0098] Figure 3B Another schematic diagram of the via stack structure generated for the underlying metal layer is provided for at least one embodiment of the disclosure.

[0099] In Figure 3B , the via stack structure 310 includes a metal layer M0, a metal layer M1, a metal layer M3, an output pin 301, a via 302, and a via 303. The via 303 is a via between the metal layer M1 and the metal layer M2, and there are 4 in total.

[0100] Based on the unit 300, the alignment reference of the metal layer M2 is one metal line segment in the metal layer M0, one metal line segment is determined on each side of the metal line segment, and the via 303 is determined based on the two metal line segments and the metal line segment in M1.

[0101] For the unit 300 with only a single output pin, the via stack structure to be generated for the underlying metal layer or the upper metal layer (top metal layer) is similar to the via stack structure of the middle layer and the top layer in Figure 2C and Figure 2D , and the generation method can also refer to the description of the related method in Figure 1 , which will not be described here.

[0102] Figure 4 A flowchart of a method for determining the position of a via in a via stack structure is shown.

[0103] As shown in Figure 4 , the method 400 includes the following steps:

[0104] Step S401, a mapping table including a mapping relationship between track identification and track position is established.

[0105] Step S402, the target position (Sx, Sy) of the via is calculated.

[0106] Step S403, the closest track Sy' in the metal layer M2 is found using Sy, and the closest track Sx' in the metal layer M3 is found using Sx.

[0107] Step S404, it is judged whether the metal layer M2 belongs to a double-pitch mode.

[0108] Step S405, it is judged whether the metal layer M3 belongs to a double-pitch mode.

[0109] Step S406, adjust the distance of Sy' to keep 2 tracks between two metal line segments in the metal layer M2.

[0110] Step S407, adjust the distance of Sx' to keep 2 tracks between two metal line segments in the metal layer M3.

[0111] Step S408, move the position of the via from (Sx, Sy) to (Sx', Sy').

[0112] In step S401, the way of establishing the mapping table can refer to the description above, which will not be repeated here.

[0113] In step S402, the target position (Sx, Sy) of the via is preliminarily determined based on the alignment reference. For example, the alignment reference is the coordinates (Sx0, Sy0) of the output pin of the metal layer M0, then Sy = Sy0, and Sx needs to be determined according to the number of output pins. When the number of output pins is multiple, Sx = Sx0, and when the number of output pins is 1, Sx = Sx0 + track spacing, or Sx = Sx0 - track spacing.

[0114] Step S403 can also refer to the description above, which will not be expanded here.

[0115] Step S404 and step S405 are not limited in order. When it is determined that the metal layer M2 belongs to the double-spacing mode, step S406 is continued to be executed, otherwise step S408 is directly executed. When it is determined that the metal layer M3 belongs to the double-spacing mode, step S407 is continued to be executed, otherwise step S408 is directly executed.

[0116] For any via in the via stack structure Figure 2A - Figure 3B , the method shown in Figure 4 can be used to determine. Figure 4 The metal layer M2 and the metal layer M3 in are only examples, which can be changed to any other metal layer except the bottommost metal layers M0 and M1.

[0117] Figure 5 A flowchart of a method for establishing a library for a via stack structure according to at least one embodiment of the present disclosure.

[0118] In Figure 5 , the method 500 includes:

[0119] Step S501, obtaining parameter information of a plurality of via stack structures.

[0120] Step S503, classifying the plurality of via stack structures according to the electrical parameters and the winding resources.

[0121] Step S505, based on the geometry of the input port of each of the plurality of via stack structures, marking the plurality of via stack structures.

[0122] Step S507, pattern extraction is performed on the classified and marked plurality of via stack structures to obtain a plurality of via stack structure templates; wherein the pattern extraction includes extracting a plurality of preset parameters. The template can be used for searching or applying, for example, after the template is generated, the most matching template can be obtained by searching the template, so that adjustment or direct use can be directly based on the retrieved template.

[0123] Firstly, step S501 is performed, and optionally, the plurality of via stack structures can be the via stack structures generated historically, the via stack structures generated by performing the method on the circuit unit Figure 1

[0124] The parameter information includes the bottommost metal layer, the top metal layer, the number of metal line segments in each metal layer, the minimum spacing between the metal line segments, the density of the metal layer, the metal layer pattern, the identification of the track in the metal layer, the electrical parameters, the winding resources and other parameters that help to describe the via stack structure. The number of parameter information to be obtained is not limited here, the more the number, the more accurate the library established.

[0125] In this embodiment, step S503 classifies the via stack structure once using the electrical parameters and the winding resources, so that subsequent retrieval of the via stack structure in the library can be performed using the electrical parameters and the winding resources. The electrical parameters in this embodiment include resistance and capacitance. The winding resources include the number of tracks and track identification, etc.

[0126] Continuing to perform step S505, the corresponding via stack structure is marked according to the geometry of the input port of the via stack structure. The input port is also referred to as the output pin in the above, and the geometry thereof includes a single pin and a plurality of pins, wherein the plurality of pins need to represent the form of the plurality of pins, for example, 3*2 represents 3 columns of pins, each column has 2 pins, and a total of 6 pins. Optionally, a single pin can also be represented as a 1*1 array.

[0127] Step S507 is performed, and the classified and marked via stack structure can be extracted according to a plurality of preset parameters, so as to obtain a template of each via stack structure. The plurality of preset parameters can be part or all of the parameter information described above. The selection of the preset parameters mainly considers the importance of the preset parameters for the via stack structure, for example, the bottommost metal layer and the top metal layer are indispensable, and the metal layer pattern can be selectively reserved.

[0128] According to Figure 5 ​An embodiment of the library established by the method in the present embodiment is data that can be invoked, for example, implemented as a module describing the library and the cell, the library including, for example, processing mode, voltage, operating condition, and the like. For example, Cell is a cell, and VL_M1_M6_2_2_2_2_2_1 is the name of the cell. VL in VL_M1_M6_2_2_2_2_2_1 indicates that the cell is a via stack structure cell, M1 is the bottom metal layer (i.e., the via stack structure needs to be generated from this layer), M6 is the top metal layer, and 2_2_2_2_2_1 are the numbers of metal segments in the metal layers M1-M6, respectively, i.e., there are 2 metal segments in M1, 2 metal segments in M2-M5, respectively, and 1 metal segment in M6.

[0129] The method in the present embodiment analyzes and extracts the via stack structure and establishes a library including a template of the via stack structure, which can be used in subsequent generation or establishment of the via stack structure, so as to further simplify or help the generation or establishment of the via stack structure.

[0130] Figure 6 A method for inserting a via stack structure into a circuit cell is provided according to at least one embodiment of the present disclosure.

[0131] In the method 600, Figure 6 The method 600 includes the following steps:

[0132] In step S601, based on the geometry of the input port of the circuit cell, the method of any one of the above first method embodiments is performed for at least one metal layer of the circuit cell.

[0133] In step S602, based on the geometry of the input port of the circuit cell, the target via stack structure template corresponding to the circuit cell is obtained from the library obtained by performing the method of any one of the above second method embodiments.

[0134] In step S603, the target via stack structure template is inserted into the circuit cell.

[0135] Step S602 and step S603, or step S601, are selectively performed, and finally the via stack structure corresponding to the circuit cell is obtained. For step S601, the via stack structure is generated in the circuit cell during the execution. For step S602 and S603, after the target via stack structure template is inserted into the circuit cell, the template also needs to be adjusted to adapt to the circuit cell.

[0136] The circuit unit involved in at least one embodiment of the present disclosure can be a circuit module implementing certain functions, such as an amplifier circuit and the like. The circuit unit is logically or physically divided, for example, it can be an inseparable part in certain circuit system, or a separate circuit device.

[0137] Specifically, when performing step S601, a first part corresponding to each metal layer in at least one metal layer of the circuit unit can be obtained, and the via stack structure corresponding to the circuit unit is composed of at least one first part. For example, the circuit unit has 7 metal layers, and the method shown in Figure 1 is performed on metal layers M1 to M6 in turn (without performing on metal layer M0), and the first part of the via stack structure corresponding to metal layers M1-M6 is obtained respectively, and the first part of the via stack structure of metal layers M1-M6 combines the output pin and the input pin of metal layer M0 itself to form the via stack structure for the circuit unit.

[0138] When performing step S602, at least one candidate of the via stack structure template corresponding to the geometry structure can be searched from the library based on the geometry structure of the input port of the circuit unit. For example, the geometry structure is a 2*3 or 1*1 output pin array, and a plurality of candidate templates conforming to the output pin array can be searched from the library.

[0139] Optionally, all via stack structure templates in the library can be searched based on the geometry structure. When the density of the metal line segment and / or the via is less than a preset threshold, the via stack structure template corresponding to the metal line segment and / or the via with the density less than the preset threshold is returned as a candidate, wherein the via stack structure template is composed of the metal line segment and the via.

[0140] Only using the geometry structure can obtain an excessive number of via stack structure templates, therefore, the embodiments of the present disclosure can also selectively use the density of the metal line segment and / or the density of the via as a further screening condition. Generally, an upper limit of the density can be selected, so that the templates exceeding the upper limit are necessarily not applicable to the circuit unit.

[0141] Then, at least one candidate is screened according to the characteristic parameters of the circuit unit, and a target via stack structure template corresponding to the circuit unit is obtained, the characteristic parameters including electrical parameters and / or winding resources. The electrical parameters and winding resources can be used to efficiently screen the candidate templates, so as to quickly obtain the required template.

[0142] Further, optionally, pattern matching is performed on at least one candidate based on the characteristic parameters, and the candidate with the highest pattern matching degree is obtained as the target via stack structure template corresponding to the circuit unit. When screening using electrical parameters and winding resources, pattern matching can be used for screening, thereby preventing all candidate templates from being screened out or multiple candidates from remaining.

[0143] When executing step 603, the target via stack structure template may be merged with the circuit unit, a logical connection may be established between the target via stack structure template and the electronic components inside the circuit unit, and a connection may be established between the target via stack structure template and the input and / or output outside the circuit unit.

[0144] For example, the position of the metal line segment of the template via stack structure template and the position of the center axis of the track of the circuit unit are merged. After the template is inserted, the bottom metal and top metal of the via stack structure need to be connected to the devices in the circuit unit, and external connections need to be completed.

[0145] like Figure 7 As shown, at least one embodiment of the present disclosure provides a processing device 700. The processing device 700 includes a processor 710 and a memory 720. The above method embodiments can all be executed by the processor 710. The memory 720 can store computer executable instructions, which are, for example, one or more computer program instruction modules, which implement the scheme described in the above method embodiments when executed by the processor 710. The memory 720 and the processor 710 can be interconnected through a bus system and / or other forms of connection mechanisms (not shown). For example, a device for generating a via stack structure of multi-layer metal, a device for establishing a library for a via stack structure, and / or a device for inserting a via stack structure into a circuit unit can all be implemented using the processing device 700.

[0146] Correspondingly, at least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-executable instructions, wherein when the computer-executable instructions are executed by a processor, the processing method or library building method described above is implemented.

[0147] For example, the processor 710 may be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) may be an X86 or ARM architecture. The processor 710 may be a general-purpose processor or a dedicated processor, and may control other components in the electronic device 700 to perform desired functions.

[0148] For example, the memory 720 can include any combination of one or more computer program products that can include various forms of computer-readable storage media, for example, volatile memory and / or non-volatile memory. Volatile memory, for example, can include random access memory (RAM), and / or a cache, etc. Non-volatile memory, for example, can include read only memory (ROM), hard disk, erasable programmable read only memory (EPROM), compact disc read only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules can be stored on the computer-readable storage media, and the processor 710 can run the one or more computer program modules to implement various functions of the electronic device 700. Various application programs and various data used and / or generated by the application programs, etc. can also be stored in the computer-readable storage media.

[0149] The processing device in the embodiment can overcome the defects of the method for inserting the via stack structure provided by the existing EDA tool, which has many limited conditions and poor performance, and achieve the technical effects of defining a high-quality via stack structure, making the insertion of the via stack structure independent of the PDK and the standard cell library, and facilitating user use by performing the method described in the above method embodiment.

[0150] Figure 8A An equivalent resistance graph of the via stack structure provided for at least one embodiment of the present disclosure is shown.

[0151] Figure 8A The via stack structure and its corresponding equivalent resistance are shown in the figure. Figure 8A In the figure, A is an input port, M2 is the equivalent resistance of the metal line segment in the metal layer 2, V2 is the equivalent resistance of the via between the metal layer 2 and the metal layer 3, M3 is the equivalent resistance of the metal line segment in the metal layer 3, V3 is the equivalent resistance of the via between the metal layer 3 and the metal layer 4, M4 is the equivalent resistance of the metal line segment in the metal layer 4, V4 is the equivalent resistance between the metal layer 4 and the top metal, M5 is the equivalent resistance of the metal line segment in the top metal layer (metal layer 5), and B is an output port in the top metal.

[0152] Figure 8B A result graph of the via stack structure provided for at least one embodiment of the present disclosure for reducing resistance is shown.

[0153] In Figure 8B In the figure, VL Res. Saving is the saved resistance value, Res. last. vl is the resistance value corresponding to the existing via stack structure, and Res. current. vl is the resistance value corresponding to the via stack structure implemented by the embodiment of the present disclosure.

[0154] InFigure 8B In the table, the value "67" is an example of a corresponding reduced resistance value when the via stack structure between the metal layer M2 and the metal layer M3 is provided, the value "34.4" is an example of a corresponding reduced resistance value when the via stack structure between the metal layer M2 and the metal layer M4 is provided, the value "11.45" is an example of a corresponding reduced resistance value when the via stack structure between the metal layer M2 and the metal layer M5 is provided, and the three values "8.25" are in turn examples of corresponding reduced resistance values when the via stack structure between the metal layer M2 and the metal layer M6, the metal layer M2 and the metal layer M7, and the metal layer M2 and the metal layer M8 is provided.

[0155] From Figure 8B It can be seen that, with the increase of the number of layers of the via stack structure, the resistance value that can be reduced gradually stabilizes. Therefore, for circuit units with a small number of metal layers, the via stack structure can effectively reduce the resistance value and improve the performance of the circuit. For circuit units with a large number of metal layers, the via stack structure also reduces the resistance value to a certain extent, which improves the performance of the circuit.

[0156] The following points need to be explained:

[0157] (1) The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the usual design.

[0158] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0159] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for generating a multi-layer metal via stack structure, comprising: Determining, based on an alignment reference of a first metal layer, a first portion of a via stack structure connecting the first metal layer and a second metal layer, where the second metal layer is a lower metal layer of the first metal layer, and the alignment reference is a second portion of the via stack structure, where the second portion connects the second metal layer and the lower metal layer of the second metal layer, wherein the first portion includes at least one via between the first metal layer and the second metal layer and a plurality of metal line segments in the first metal layer; determining, based on the alignment reference of the first metal layer, the first portion of the via stack structure connecting the first metal layer and the second metal layer, comprises: determining, based on a horizontal coordinate or a vertical coordinate of the alignment reference, at least one track closest to the horizontal coordinate or the vertical coordinate from a plurality of tracks preset in the first metal layer; Based on the metal layer mode of the first metal layer, determine whether to adjust the position of the first part; wherein, when the metal layer mode is a double-pitch mode, adjust the position of the first part, including: moving at least one metal wire segment among the multiple metal wire segments so that two tracks are spaced between every two metal wire segments among the multiple metal wire segments.

2. The processing method according to claim 1, wherein The method further comprises: Based on a preset size of the via stack structure, a length of at least one metal line segment among the plurality of metal line segments is adjusted.

3. The processing method according to claim 1, wherein: The method further comprises: The center position of the at least one via is determined based on an orthographic projection of at least one metal line segment among the plurality of metal line segments and the alignment reference.

4. The processing method according to claim 1, wherein: The method further comprises: The distance between every two metal line segments in the plurality of metal line segments is greater than or equal to a preset threshold.

5. The processing method according to claim 1, wherein: The method further comprises: Determining whether each of the plurality of metal line segments complies with a minimum spacing rule or a cross-metal layer spacing rule; When the judgment result is yes, the metal line segments that meet the minimum spacing rule or the cross-metal layer spacing rule are moved away from the preset track.

6. The processing method according to claim 1, wherein: The step of determining, based on the abscissa or ordinate of the alignment reference, at least one track closest to the abscissa or ordinate from a plurality of tracks preset in the first metal layer comprises: establishing a mapping table including mapping relationships between track identifiers and track positions, wherein each track of the plurality of tracks has a different track identifier, and the track positions are represented by a plurality of pre-stored abscissas or a plurality of ordinates; Determining a position of the alignment reference, wherein the position of the alignment reference includes a horizontal coordinate and a vertical coordinate; searching, according to the abscissa or ordinate of the position of the alignment reference, a plurality of abscissas or a plurality of ordinates pre-recorded in the mapping table, and determining at least one abscissa closest to the abscissa of the position of the alignment reference or determining at least one ordinate closest to the ordinate of the position of the alignment reference; The at least one track corresponding to the at least one horizontal coordinate is determined to be the at least one track closest to the horizontal coordinate, or the at least one track corresponding to the at least one vertical coordinate is determined to be the at least one track closest to the vertical coordinate.

7. A method for establishing a library for a via stack structure, comprising: Obtain parameter information of multiple via stack structures; classifying the plurality of via stack structures according to electrical parameters and winding resources; labeling the plurality of via stack structures based on a geometry of an input port of each of the plurality of via stack structures; performing pattern extraction on the classified and marked plurality of via stack structures to obtain a plurality of via stack structure templates; Wherein, the pattern extraction includes extracting a plurality of preset parameters; The obtaining of parameter information of a plurality of via stack structures comprises: executing the processing method according to any one of claims 1 to 6 on a circuit unit, establishing a via stack structure for the circuit unit and obtaining the parameter information.

8. The method of establishing as claimed in claim 7, wherein: The obtaining of parameter information of the plurality of via stack structures further includes: The parameter information is obtained from a historically generated via stack structure.

9. A method for inserting a via-stack structure into a circuit unit, comprising: Based on the geometric structure of the input port of the circuit unit, performing the processing method according to any one of claims 1 to 6 on at least one metal layer of the circuit unit; or, Based on the geometric structure of the input port of the circuit unit, obtaining a target via stack structure template corresponding to the circuit unit from a library obtained by executing the establishment method according to claim 7 or 8; Inserting the target via stack structure template into the circuit unit.

10. The processing method according to claim 9, wherein: The processing method according to any one of claims 1 to 6 is performed on at least one metal layer of the circuit unit based on the geometric structure of the input port of the circuit unit, comprising: A first portion corresponding to each metal layer in at least one metal layer of the circuit unit is obtained, and a via stacked structure corresponding to the circuit unit is formed by the at least one first portion.

11. The processing method according to claim 9, wherein: The step of obtaining a target via stack structure template corresponding to the circuit unit from a library obtained by executing the establishment method according to claim 7 or 8 based on the geometric structure of the input port of the circuit unit comprises: Based on the geometric structure of the input port of the circuit unit, searching from the library for at least one candidate of a via stack structure template corresponding to the geometric structure; The at least one candidate is screened according to characteristic parameters of the circuit unit to obtain the target via stack structure template corresponding to the circuit unit, wherein the characteristic parameters include electrical parameters and / or winding resources.

12. The processing method according to claim 11, wherein: The screening of the at least one candidate according to the electrical parameters and / or winding resources of the circuit unit includes: According to the characteristic parameters, pattern matching is performed on the at least one candidate, and a candidate with the highest pattern matching degree is obtained as the target via stack structure template corresponding to the circuit unit.

13. The processing method according to claim 11, wherein: Based on the geometric structure of the input port of the circuit unit, searching the library for at least one candidate of a via stack structure template corresponding to the geometric structure, comprising: Based on the geometric structure, searching all via stack structure templates in the library; When the density of metal segments and / or vias is less than a preset threshold, the via stack structure template corresponding to the metal segments and / or vias with a density less than the preset threshold is returned as a candidate, wherein the via stack structure template consists of metal segments and vias.

14. The processing method according to claim 9, wherein: Inserting the target via-hole stacked structure template into the circuit unit comprises: merging the target via stack structure template with the circuit unit; Establishing a logical connection between the target via stack structure template and the electronic device inside the circuit unit; A connection is established between the target via stack structure template and an input and / or output outside the circuit unit.

15. A processing device comprising: processor, a memory storing one or more computer program instruction modules; Wherein, when the one or more computer program instruction modules are executed by the processor, the processing method according to any one of claims 1 to 6, the establishment method according to claim 7 or 8, or the processing method according to any one of claims 9 to 14 is implemented.

16. A computer-readable storage medium non-transitorily storing computer-executable instructions, wherein: When the computer executable instructions are executed by a processor, the processing method according to any one of claims 1 to 6, the establishment method according to claim 7 or 8, or the processing method according to any one of claims 9 to 14 is implemented.

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