TMBS device and preparation method thereof

Abstract

The present invention provides a TMBS device and a method for preparing the same, wherein the method comprises: etching an ONO layer using two lateral etching processes; forming a gate oxide layer; forming a polysilicon layer; etching back a portion of the polysilicon layer; forming an interlayer dielectric layer; and removing the interlayer dielectric layer, the ONO layer, and a portion of the polysilicon layer in the trench to obtain a gate in the trench. In the present application, the ONO layer is etched using the lateral etching process, and the bottom of the ONO layer is connected to the gate oxide layer and covers the top of the gate oxide layer, thereby protecting the gate oxide layer on the trench sidewalls from being mistakenly etched by the etching back process when etching back a portion of the polysilicon layer. This avoids excessive loss of the gate oxide layer and increases in leakage, thereby improving the yield of the TMBS device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a TMBS device and a method for preparing the same. Background Art

[0002] A TMBS (Trench MOS Barrier Schottky rectifier) ​​is a power device that incorporates a trench MOS gate structure. By utilizing the "charge coupling" effect to reduce the electric field strength at the Schottky barrier, it reduces the forward voltage drop and achieves lower reverse leakage current. In practical applications such as freewheeling diodes, smartphone chargers, and solar cells, lower TMBS forward voltage drop and reverse leakage current result in reduced power loss and higher efficiency. Therefore, the current market demand for even lower forward voltage drop and reverse leakage is driving demand.

[0003] When the gate polysilicon material of the TMBS device is actually etched back (CT DRO ETCH), the gate oxide layer on the trench sidewall is easily damaged by etching. If the gate oxide layer is damaged, it will cause the leakage of the device to increase, thereby causing the device IR failure. Summary of the Invention

[0004] The present application provides a TMBS device and a method for preparing the same, which can solve the problem of device failure caused by incorrect etching of the gate oxide layer on the trench sidewall.

[0005] On the one hand, the embodiments of the present application provide a method for preparing a TMBS device, comprising:

[0006] Providing a substrate, on which a stacked epitaxial layer and an ONO layer are formed, wherein trenches are formed in the ONO layer and the epitaxial layer;

[0007] Etching the ONO layer using two lateral etching processes;

[0008] forming a gate oxide layer, wherein the gate oxide layer covers the bottom wall and the sidewall of the trench, wherein the bottom of the ONO layer is connected to the gate oxide layer and covers the top of the gate oxide layer;

[0009] forming a polysilicon layer, wherein the polysilicon layer fills the trench and covers the ONO layer;

[0010] etching back the polysilicon layer on the ONO layer and the polysilicon layer of the first thickness in the trench;

[0011] forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the polysilicon layer and the ONO layer; and

[0012] The interlayer dielectric layer, the ONO layer, and the polysilicon layer with a second thickness in the trench are removed to obtain a gate in the trench.

[0013] Optionally, in the method for preparing the TMBS device, the ONO layer includes, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.

[0014] Optionally, in the method for preparing the TMBS device, the step of etching the ONO layer using two lateral etching processes includes:

[0015] The second silicon oxide layer of a certain width is etched using a first lateral etching process, wherein the process parameters of the first lateral etching process include: an etching solution including an NH4F solution; an etching time of 3 minutes to 5 minutes;

[0016] A second lateral etching process is used to etch the silicon nitride layer of a certain width, wherein the side of the silicon nitride layer close to the groove protrudes from the side of the second silicon oxide layer, and the side of the first silicon oxide layer protrudes from the side of the silicon nitride layer, wherein the process parameters of the second lateral etching process include: the etching solution includes: phosphoric acid solution; the etching time is 19 minutes to 21 minutes.

[0017] Optionally, in the method for preparing the TMBS device, the lateral size of the first silicon oxide layer etched and removed by the first lateral etching process is

[0018] Optionally, in the method for preparing the TMBS device, the lateral size of the silicon nitride layer etched and removed by the second lateral etching process is

[0019] Optionally, in the method for preparing the TMBS device, the thickness of the first silicon oxide layer is The thickness of the silicon nitride layer is The thickness of the second silicon oxide layer is

[0020] Optionally, in the method for preparing the TMBS device, after etching back the polysilicon layer on the ONO layer and the polysilicon layer of the first thickness in the trench and before forming the interlayer dielectric layer, the surface of the remaining thickness of the polysilicon layer is lower than the surface of the ONO layer.

[0021] Optionally, in the method for preparing the TMBS device, a high-temperature thermal oxidation process is used to form the gate oxide layer.

[0022] On the other hand, an embodiment of the present application further provides a TMBS device, including:

[0023] substrate;

[0024] an epitaxial layer, the epitaxial layer covering the substrate, and having a trench formed therein;

[0025] a gate oxide layer, wherein the gate oxide layer covers the sidewalls and bottom wall of the trench;

[0026] A gate covers the gate oxide layer and fills the trench.

[0027] The technical solution of this application has at least the following advantages:

[0028] The present application etches the ONO layer through two lateral etching processes, so that the side of the silicon nitride layer in the ONO layer protrudes from the side of the second silicon oxide layer, and the side of the first silicon oxide layer protrudes from the side of the silicon nitride layer, and the bottom of the ONO layer is connected to the gate oxide layer and covers the top of the gate oxide layer, thereby protecting the gate oxide layer on the side wall of the trench from being mistakenly etched by the etching back process when etching back part of the polysilicon layer, thereby avoiding excessive loss of the gate oxide layer and causing increased leakage, and improving the yield of the TMBS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 is a flow chart of a method for preparing a TMBS device according to an embodiment of the present invention;

[0031] Figure 2-Figure 8 Schematic diagram of the semiconductor structure in each process step of preparing a TMBS device according to an embodiment of the present invention;

[0032] in,

[0033] 10-substrate, 20-epitaxial layer, 21-trench, 30-ONO layer, 31-first silicon oxide layer, 32-silicon nitride layer, 33-second silicon oxide layer, 321-bird's beak-shaped silicon oxide structure, 40-gate oxide layer, 50-polysilicon layer, 51-remaining thickness of polysilicon layer, 52-gate, 60-interlayer dielectric layer. DETAILED DESCRIPTION

[0034] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0035] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0037] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0038] This application embodiment provides a method for preparing a TMBS device, please refer to Figure 1 , Figure 1 1 is a flow chart of a method for preparing a TMBS device according to an embodiment of the present invention, wherein the method for preparing a TMBS device comprises:

[0039] S10: providing a substrate, on which a stacked epitaxial layer and an ONO layer are formed, wherein trenches are formed in the ONO layer and the epitaxial layer;

[0040] S20: Etching the ONO layer using two lateral etching processes;

[0041] S30: forming a gate oxide layer, wherein the gate oxide layer covers the bottom wall and sidewalls of the trench, wherein the ONO layer covers the top of the gate oxide layer;

[0042] S40: forming a polysilicon layer, wherein the polysilicon layer fills the trench and covers the ONO layer;

[0043] S50: etching back the polysilicon layer on the ONO layer and the polysilicon layer of the first thickness in the trench;

[0044] S60: forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the polysilicon layer and the ONO layer; and

[0045] S70: removing the interlayer dielectric layer, the ONO layer, and the polysilicon layer of the second thickness in the trench to obtain a gate in the trench.

[0046] For details, please refer to Figure 2-Figure 8 , Figure 2-Figure 8 It is a schematic diagram of the semiconductor structure in each process step of preparing a TMBS device according to an embodiment of the present invention.

[0047] First, if Figure 2 As shown, a substrate 10 is provided, on which a stacked epitaxial layer 20 and an ONO layer 30 are formed, wherein a groove 21 is formed in the ONO layer 30 and the epitaxial layer 20. Specifically, the conductivity type of the epitaxial layer 20 can be N-type (doped with phosphorus ions or arsenic ions, etc.), and its conductivity type can also be P-type (doped with boron ions, etc.). Preferably, the ONO layer 30 includes, from bottom to top, a first silicon oxide layer 31, a silicon nitride layer 32, and a second silicon oxide layer 32. In this embodiment, the thickness of the first silicon oxide layer 31 is The thickness of the silicon nitride layer 32 is The thickness of the second silicon oxide layer 33 is

[0048] Then, if Figure 3 As shown, two lateral etching processes are used to etch the ONO layer 30. Specifically, in this embodiment, a first lateral etching process can be used to etch a certain width of the second silicon oxide layer 33, wherein the process parameters of the first lateral etching process include: etching solution including NH4F solution; etching time is 3 minutes to 5 minutes, for example, 4 minutes;

[0049] A second lateral etching process is then used to etch the silicon nitride layer 32 of a certain width, wherein the side of the silicon nitride layer 32 close to the groove 21 protrudes from the side of the second silicon oxide layer 33, and the side of the first silicon oxide layer 31 protrudes from the side of the silicon nitride layer 32, wherein the process parameters of the second lateral etching process include: the etching solution includes: phosphoric acid solution; the etching time is 19 minutes to 21 minutes, for example, 20 minutes.

[0050] Furthermore, the lateral size of the first silicon oxide layer 31 etched and removed by the first lateral etching process can be The lateral size of the silicon nitride layer 32 removed by the second lateral etching process is Because the etching solution used in this application has different etching selectivities for silicon oxide and silicon nitride, the side surfaces of the silicon nitride layer 32 can be made to protrude beyond the side surfaces of the second silicon oxide layer 33, and the side surfaces of the first silicon oxide layer 31 can be made to protrude beyond the side surfaces of the silicon nitride layer 32, thereby resulting in stepped side surfaces of the ONO layer. The formation of the stepped ONO layer 32 facilitates the subsequent deposition of the polysilicon layer 50 in the trench 21, facilitating the subsequent formation of a high-quality polysilicon layer 50.

[0051] Then, if Figure 4 As shown, a gate oxide layer 40 is formed, the gate oxide layer 40 covers the bottom wall of the trench 21 and the lower half of the side wall (the side wall where the epitaxial layer 20 is located), wherein the bottom of the ONO layer 30 is connected to the gate oxide layer 40 and the ONO layer 30 covers the top of the gate oxide layer 40, wherein the bottom of the ONO layer 30 is connected to the gate oxide layer 40 to form a bird's beak-shaped silicon oxide structure 321 between the epitaxial layer 20 and the silicon nitride layer 32. Specifically, in this embodiment, a high-temperature thermal oxidation process can be used to form the gate oxide layer 40, from Figure 4 It can be seen that the gate oxide layer 40 will penetrate into the partial thickness of the epitaxial layer 20 and connect with the first silicon oxide layer 31 at the bottom of the ONO layer 30 to thicken the silicon oxide material between the epitaxial layer 20 and the silicon nitride layer 32 near the groove 21, thereby forming a bird's beak-shaped silicon oxide structure 321 between the epitaxial layer 20 and the silicon nitride layer 32. The bird's beak-shaped silicon oxide structure 321 can play a certain blocking role in the subsequent polysilicon layer etching back process, so that the morphology of the gate oxide layer 40 that needs to be retained on the side wall of the groove 21 is intact, thereby reducing or even avoiding leakage. Further, the thickness of the gate oxide layer 40 can be Further, such as Figure 5 As shown, a polysilicon layer 50 is formed, and the polysilicon layer 50 fills the trench 21 and covers the ONO layer 30 .

[0052] Then, if Figure 6 As shown, the polysilicon layer 50 on the ONO layer 30 and the first thickness of the polysilicon layer 50 in the trench 21 are etched back using an etch-back process, leaving only the remaining thickness of the polysilicon layer 51 in the trench 21. At this time, the surface of the remaining thickness of the polysilicon layer 51 can be lower than the surface of the ONO layer 30. In this embodiment, the etch-back process may be a dry etching process.

[0053] The present application etches the ONO layer 30 through two lateral etching processes, so that the side of the silicon nitride layer 32 protrudes from the side of the second silicon oxide layer 33, and the side of the first silicon oxide layer 31 protrudes from the side of the silicon nitride layer 32, and the bottom of the ONO layer 30 is connected to the gate oxide layer and covers the top of the gate oxide layer 40, thereby protecting the gate oxide layer 40 on the side wall of the trench 21 from being mistakenly etched by the etching back process when etching back the polysilicon layer 50 of the first thickness, thereby avoiding excessive loss of the gate oxide layer 40 and causing increased leakage, thereby improving the yield of the TMBS device.

[0054] Further, such as Figure 7 As shown, an interlayer dielectric layer 60 is formed, and the interlayer dielectric layer 60 covers the remaining thickness of the polysilicon layer 51 and the ONO layer 30. Because the side surfaces of the silicon nitride layer 32 in the ONO layer 30 protrude from the side surfaces of the second silicon oxide layer 33, and the side surfaces of the first silicon oxide layer 31 protrude from the side surfaces of the silicon nitride layer 32, the side surfaces of the ONO layer 30 can also be considered to be stepped. Therefore, the interlayer dielectric layer 60 forms a relatively smooth obtuse angle at the top of the trench 21.

[0055] Finally, if Figure 8 As shown, a dry etching process is used to remove the interlayer dielectric layer 60 , the ONO layer 30 and the polysilicon layer of the second thickness in the trench 21 to obtain a gate 52 in the trench 21 .

[0056] Based on the same inventive concept, the embodiment of the present application further provides a TMBS device, such as Figure 8 As shown, the TMBS device includes:

[0057] substrate 10;

[0058] an epitaxial layer 20 , the epitaxial layer 20 covering the substrate 10 , and having a trench 21 formed therein;

[0059] a gate oxide layer 40 , wherein the gate oxide layer 40 covers the sidewalls and bottom wall of the trench 21 ;

[0060] A gate 52 covers the gate oxide layer 40 and fills the trench 21 .

[0061] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing a TMBS device, characterized in that: include: Providing a substrate, on which a stacked epitaxial layer and an ONO layer are formed, wherein trenches are formed in the ONO layer and the epitaxial layer; Etching the ONO layer using two lateral etching processes, wherein the ONO layer includes, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer; forming a gate oxide layer, wherein the gate oxide layer covers the bottom wall and sidewalls of the trench, wherein the bottom of the ONO layer is connected to the gate oxide layer and covers the top of the gate oxide layer, and the thickness of the gate oxide layer is 100Å to 800Å; forming a polysilicon layer, wherein the polysilicon layer fills the trench and covers the ONO layer; etching back the polysilicon layer on the ONO layer and the polysilicon layer of the first thickness in the trench; forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the polysilicon layer and the ONO layer; and removing the interlayer dielectric layer, the ONO layer, and the polysilicon layer of the second thickness in the trench to obtain a gate in the trench; The step of etching the ONO layer using two lateral etching processes includes: The second silicon oxide layer of a certain width is etched using a first lateral etching process, wherein the process parameters of the first lateral etching process include: an etching solution including NH4F solution, and an etching time of 3 minutes to 5 minutes; A second lateral etching process is used to etch the silicon nitride layer of a certain width, wherein the side of the silicon nitride layer close to the groove protrudes from the side of the second silicon oxide layer, and the side of the first silicon oxide layer protrudes from the side of the silicon nitride layer, wherein the process parameters of the second lateral etching process include: the etching solution includes: phosphoric acid solution, and the etching time is 19 minutes to 21 minutes.

2. The method for preparing a TMBS device according to claim 1, wherein: The first silicon oxide layer etched and removed by the first lateral etching process has a lateral size of 50Å to 200Å.

3. The method for preparing a TMBS device according to claim 1, wherein: The lateral size of the silicon nitride layer etched and removed by the second lateral etching process is 20 Å to 150 Å.

4. The method for preparing a TMBS device according to claim 1, wherein: The thickness of the first silicon oxide layer is 300Å~500Å; the thickness of the silicon nitride layer is 1000Å~2000Å; and the thickness of the second silicon oxide layer is 3000Å~5000Å.

5. The method for preparing a TMBS device according to claim 1, wherein: After etching back the polysilicon layer on the ONO layer and the polysilicon layer of the first thickness in the trench and before forming the interlayer dielectric layer, the surface of the remaining thickness of the polysilicon layer is 1200Å~1500Å lower than the surface of the ONO layer.

6. The method for preparing a TMBS device according to claim 1, wherein: The gate oxide layer is formed by a high-temperature thermal oxidation process.

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