Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate, the substrate having an initial gate structure formed thereon, the substrate comprising a device region and a separation region; performing a doping treatment on the initial gate structure of the separation region, a portion of the initial gate structure doped with ions serving as a sacrificial layer, wherein the doping treatment is configured to make the etching rate of the sacrificial layer in each crystal direction the same; removing the sacrificial layer of the separation region to form a separation opening in the initial gate structure, the separation opening separating the initial gate structure in an extension direction of the initial gate structure to form gate structures respectively located in the device region. The flatness of the end of the gate structure formed in the device region in the extension direction thereof is improved, the probability of the end of the gate structure in the extension direction thereof being curved in appearance is reduced, and thus the performance of the semiconductor is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] With the gradual development of semiconductor process technology, semiconductor process nodes are continuously shrinking in accordance with Moore's Law. To adapt to the shrinking process nodes and the development of highly integrated semiconductor devices, the critical dimensions of metal-oxide-semiconductor (MOS) devices are also constantly shrinking, with gate length and gate pitch also shrinking to even smaller dimensions. Correspondingly, the manufacturing process of semiconductor devices is also constantly being improved to meet people's requirements for device performance.

[0003] Currently, the gate structure forming process typically employs gate cutting technology to cut the strip gate. The cut gate corresponds to different transistors, which can improve the transistor integration density. In addition, when multiple gates are arranged in a row along the extension direction, gate cutting technology can precisely reduce the spacing in the mating direction between the disconnected gates after gate cutting (Gate Cut CD). Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve semiconductor performance.

[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate on which an initial gate structure is formed, the substrate including a device region and an isolation region; performing a doping process on the initial gate structure in the isolation region, wherein the portion of the initial gate structure doped with ions serves as a sacrificial layer, wherein the doping process is used to ensure that the sacrificial layer is etched at the same rate in each crystal orientation; removing the sacrificial layer in the isolation region, forming an isolation opening in the initial gate structure, the isolation opening dividing the initial gate structure in the extension direction of the initial gate structure to form gate structures respectively located in the device region.

[0006] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0007] This invention provides a method for forming a semiconductor structure, wherein an initial gate structure in an isolation region is doped, and the portion of the initial gate structure doped with ions serves as a sacrificial layer, wherein the doping process is used to make the sacrificial layer etched at the same rate in each crystal orientation; the sacrificial layer in the isolation region is removed, and an isolation opening is formed in the initial gate structure, the isolation opening dividing the initial gate structure in the extension direction of the initial gate structure to form gate structures located in the device region respectively. In this embodiment of the invention, by doping the initial gate structure of the isolation region, the ion-doped initial gate structure (i.e., the sacrificial layer) material is etched at the same rate in each crystal orientation. Therefore, during the subsequent removal of the sacrificial layer in the isolation region, the etching rate of the isotropic sacrificial layer is consistent, thereby improving the uniformity of the etching rate of the sacrificial layer in the isolation region. This correspondingly improves the flatness of the isolation opening sidewall, that is, improves the flatness of the end (head) of the gate structure formed in the device region in its extension direction, and reduces the probability of morphological bending at the end of the gate structure in its extension direction, thereby improving the performance of the semiconductor. Attached Figure Description

[0008] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0009] Figures 4 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0010] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of a semiconductor structure needs further improvement, using a specific semiconductor structure formation method as an example.

[0011] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] refer to Figure 1 A substrate is provided, the substrate including a substrate 10 and fins 11 protruding from the substrate 10. An isolation layer 12 is formed on the substrate 10 exposed by the fins 11, the isolation layer 12 covering part of the sidewalls of the fins 11. A gate structure 15 is formed on the top of the substrate 10, spanning the fins 11 and covering part of the top and part of the sidewalls of the fins 11. A mask layer 23 is formed on the top of the gate structure 15. Source and drain epitaxial layers (not shown) are formed in the fins 11 on both sides of the gate structure 15. Sidewall layers 14 are formed on the sidewalls of the gate structure 15. Interlayer dielectric layers 13 are formed on the sidewalls of the sidewall layers 14. The substrate includes a device region 10A and a blocking region 10B.

[0013] refer to Figure 2 A mask opening 30 is formed in the mask layer 23 of the partition region 10B, and the mask opening 30 exposes the top of the gate structure 15 of the partition region 10B.

[0014] refer to Figure 3 Using the mask layer 23 as a mask, the gate structure 15 in the isolation region 10B is etched away along the mask opening 30 to form an isolation opening 50 that exposes the isolation layer 12.

[0015] Research has revealed that after forming a gate structure 15 on the substrate 10 that spans the fin 11 and covers part of the top and sidewalls of the fin 11, the formation of the source / drain epitaxial layer and sidewall layer 14 involves high-temperature processing, leading to uneven recrystallization of the gate structure 15 and inconsistent grain size. For example, when the gate structure 15 is made of amorphous silicon, significant recrystallization occurs above 565°C, resulting in inconsistent grain size.

[0016] The isolation opening 50 is formed by etching the gate structure 15 in the isolation region 10B. The gate structure 15 undergoes uneven recrystallization, resulting in an uneven etching rate during the etching process to remove the gate structure 15 from the isolation region 10B to form the isolation opening 50. Consequently, this can easily lead to bending of the sidewalls of the isolation opening 50 (e.g., ...). Figure 3 (As shown in the dashed box), this reduces the flatness of the end (head) of the gate structure 15 formed in the device region 10A in its extension direction, increases the probability of the gate structure 15 bending at its extension direction end, and thus reduces the performance of the semiconductor.

[0017] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate on which an initial gate structure is formed, the substrate including a device region and an isolation region; performing a doping process on the initial gate structure in the isolation region, wherein the portion of the initial gate structure doped with ions serves as a sacrificial layer, wherein the doping process is used to ensure that the sacrificial layer is etched at the same rate in each crystal orientation; removing the sacrificial layer in the isolation region, forming an isolation opening in the initial gate structure, the isolation opening dividing the initial gate structure in the extension direction of the initial gate structure to form gate structures respectively located in the device region.

[0018] In the formation method provided by the embodiments of the present invention, the initial gate structure of the isolation region is doped, and the portion of the initial gate structure doped with ions serves as a sacrificial layer. The doping process is used to make the etching rate of the sacrificial layer the same in each crystal orientation. The sacrificial layer of the isolation region is removed, and an isolation opening is formed in the initial gate structure. The isolation opening divides the initial gate structure in the extension direction of the initial gate structure to form gate structures located in the device region respectively. In this embodiment of the invention, by doping the initial gate structure of the isolation region, the ion-doped initial gate structure (i.e., the sacrificial layer) material is etched at the same rate in each crystal orientation. Therefore, during the subsequent removal of the sacrificial layer in the isolation region, the etching rate of the isotropic sacrificial layer is consistent, thereby improving the uniformity of the etching rate of the sacrificial layer in the isolation region. This correspondingly improves the flatness of the isolation opening sidewall, that is, improves the flatness of the end (head) of the gate structure formed in the device region in its extension direction, and reduces the probability of morphological bending at the end of the gate structure in its extension direction, thereby improving the performance of the semiconductor.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Figures 4 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure fabrication method of the present invention.

[0021] refer to Figure 4 A substrate is provided on which an initial gate structure 105 is formed, the substrate including a device region 100A and an isolation region 100B.

[0022] The substrate is used to provide a process platform for subsequent process manufacturing.

[0023] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100.

[0024] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0025] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0026] In this embodiment, the substrate includes a device region 100A and a partition region 100B.

[0027] The device region 100A is used to form a device gate structure, and the isolation region 100B is used to isolate adjacent device regions 100A.

[0028] Continue to refer to Figure 4 In this embodiment, the method for forming the semiconductor structure further includes: after forming the fin 101, forming an isolation layer 102 on the substrate 100 exposed by the fin 101, the isolation layer 102 covering part of the sidewall of the fin 101.

[0029] The isolation layer 102 is used to isolate adjacent devices. The material of the isolation layer 102 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 102 is silicon oxide.

[0030] In this embodiment, the initial gate structure 105 includes a pseudo-gate structure.

[0031] The initial gate structure 105 provides a process basis for the subsequent formation of an isolation opening in the isolation region 100B and the formation of a gate structure in the device region 100A. The initial gate structure 105 is also used to occupy space for the subsequent formation of a device gate structure (e.g., a metal gate structure).

[0032] In this embodiment, the initial gate structure 105 spans the fin 101 and covers part of the top and part of the sidewalls of the fin 101.

[0033] In this embodiment, the material of the initial gate structure 105 is amorphous silicon.

[0034] In this embodiment, during the step of providing the substrate, a hard mask layer 120 is formed on the top of the initial gate structure 105.

[0035] The hard mask layer 120 serves as an etching mask for forming the initial gate structure 105, and also as an etching mask for subsequently etching the initial gate structure 105 of the isolation region 100B. In addition, it protects the initial gate structure 105 of the device region 100A during the subsequent doping process of the initial gate structure 105 of the isolation region 100B.

[0036] In this embodiment, the material of the hard mask layer 120 includes one or more of SiO2, SiN and SiON.

[0037] As an example, the hard mask layer 120 includes a silicon nitride layer (not shown) and a silicon oxide layer (not shown) located on the silicon nitride layer.

[0038] It should be noted that after forming the initial gate structure 105, the method further includes: forming a sidewall 104 on the sidewall of the initial gate structure 105; after forming the sidewall 104, forming source / drain epitaxial layers (not shown) in the fins 101 on both sides of the initial gate structure 105.

[0039] The sidewall 104 is used to protect the sidewall of the initial gate structure 105.

[0040] In this embodiment, the sidewall 104 also covers the sidewall of the hard mask layer 120.

[0041] The sidewall 104 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 104 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 104 is a single-layer structure, and the material of the sidewall 104 is silicon nitride.

[0042] In this embodiment, during the step of providing the substrate, an interlayer dielectric layer 103 is also formed on the substrate on the side of the initial gate structure 105, and the interlayer dielectric layer 103 covers the sidewall of the initial gate structure 105.

[0043] Specifically, after the source and drain epitaxial layers are formed, an interlayer dielectric layer 103 is formed on the substrate 100 exposed by the initial gate structure 105, and the top of the interlayer dielectric layer 103 is flush with the top of the hard mask layer 120.

[0044] The interlayer dielectric layer 103 is used to isolate adjacent devices. The material of the interlayer dielectric layer 103 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 103 is silicon nitride.

[0045] refer to Figures 5 to 6 Before doping the initial gate structure 105 of the isolation region 100B, the formation method further includes: forming a mask opening 130 penetrating the hard mask layer 120 in the hard mask layer 120 of the isolation region 100B.

[0046] Specifically, during the subsequent doping process of the initial gate structure 105 of the isolation region 100B, the mask opening 130 defines the doping region.

[0047] In this embodiment, the step of forming the mask opening 130 includes: forming an organic material layer 121 on top of the hard mask layer 120; forming a patterned photoresist layer 122 on top of the organic material layer 121, wherein the photoresist layer 122 exposes the organic material layer 121 of the isolation region 100B; and sequentially etching the organic material layer 121 and the hard mask layer 120 using the patterned photoresist layer 122 as a mask to form a mask opening 130 penetrating the hard mask layer 120.

[0048] The organic material layer 121 is made of organic materials. In this embodiment, the organic material layer 121 is made of spin-on carbon (SOC). In other embodiments, the organic material layer may also be made of other organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0049] refer to Figure 7 The initial gate structure 105 of the isolation region 100B is doped, and the portion of the initial gate structure 105 doped with ions serves as a sacrificial layer 131. The doping process is used to make the sacrificial layer etched at the same rate in each crystal orientation.

[0050] In this embodiment, by doping the initial gate structure 105 of the isolation region 100B, the ion-doped initial gate structure 105 (i.e., sacrificial layer 131) material is etched at the same rate in each crystal orientation. Therefore, during the subsequent removal of the sacrificial layer 131 of the isolation region 100B, the etching rate of the isotropic sacrificial layer 131 is consistent, thereby improving the uniformity of the etching rate of the sacrificial layer 131 of the isolation region 100B. Consequently, the flatness of the sidewall of the subsequently formed isolation opening 132 is improved, that is, the flatness of the end (head) of the gate structure 150 subsequently formed in the device region 100A in its extension direction is improved, reducing the probability of morphological bending of the end of the gate structure 150 in its extension direction, thereby improving the performance of the semiconductor.

[0051] In particular, during the step of forming the initial gate structure 105, the material of the initial gate structure 105 is an amorphous material. However, during the formation of the source / drain epitaxial layer and the sidewall layer 104, the initial gate structure 105 undergoes a related high-temperature process, which can easily lead to uneven recrystallization of the initial gate structure 105 and uneven grain size. Therefore, by doping the initial gate structure 105 of the isolation region 100B, the material of the ion-doped initial gate structure 105 (i.e., sacrificial layer 131) can be transformed into an amorphous material.

[0052] In this embodiment, in the step of doping the initial gate structure 105 of the isolation region 100B, the material of the sacrificial layer 131 is an amorphous material.

[0053] That is, by doping, the ordered interconnection bonds between the individual grains are disrupted, so that the grains inside the sacrificial layer change from an ordered state to a disordered state. Since the internal grains of the amorphous material are disordered, they are etched at a uniform rate. Therefore, in the subsequent removal of the sacrificial layer 131 of the isolation region 100B, the relevant etching processes have a uniform etching rate for the isotropic sacrificial layer 131, thereby improving the uniformity of the etching rate of the sacrificial layer 131 of the isolation region 100B.

[0054] In this embodiment, in the step of doping the initial gate structure 105 of the isolation region 100B, the initial gate structure 105 exposed by the mask opening 130 is doped using the hard mask layer 120 as a mask.

[0055] It should be noted that, since only the initial gate structure 105 of the isolation region 100B needs to be cut off, the hard mask layer 120 in the device region 100A protects the initial gate structure 105 during the doping process.

[0056] It should be noted that in the step of doping the initial gate structure 105 of the isolation region 100B, the doping ions include one or more of Si, Ge and Sb ions.

[0057] During the doping process, the high-speed ions disrupt the ordered interconnection bonds between the individual grains in the initial gate structure 105, causing the grains inside the initial gate structure 105 in the isolation region 100B to change from an ordered state to a disordered state.

[0058] Among them, Si, Ge and Sb ions are commonly used ions in semiconductor processes. They have lower process risks, higher compatibility, and help avoid ion contamination problems.

[0059] As an example, in the step of doping the initial gate structure 105 of the isolation region 100B, the dopant ion is Si.

[0060] It should be noted that the doping ions are not limited to Ge and Sb ions. In other embodiments, the doping ions may also be other ions capable of changing the ordered state of the grains inside the initial gate structure in the isolation region to a disordered state.

[0061] In this embodiment, during the step of doping the initial gate structure 105 of the isolation region 100B, the sidewall of the sacrificial layer 131 protrudes relative to the sidewall of the mask opening 130.

[0062] Subsequent etching removes the sacrificial layer 131 of the isolation region 100B to form an isolation opening. This opening divides the initial gate structure along its extension direction, forming gate structures located in the device region. The sacrificial layer 131 is made of an amorphous material, meaning its etching rate is uniform in all directions (crystal orientations). Conversely, the initial gate structure 105 in the device region 100A is made of a polycrystalline material, meaning its etching rate is inconsistent in all directions (crystal orientations). By making the sidewall of the sacrificial layer 131 protrude relative to the sidewall of the mask opening 130, during the subsequent formation of the isolation opening in the isolation region 100B, the portion of the sacrificial layer 131 formed in the device region 100A protects the sidewall of the initial gate structure 105 of the device region 100A. This reduces the probability of damage to the initial gate structure 105 in the device region 100A caused by the complete removal of the sacrificial layer due to related etching processes. This helps to ensure the flatness of the isolation opening sidewall and improves the flatness of the gate structure formed in the device region 100A at its extension direction end.

[0063] In this embodiment, the sidewall of the sacrificial layer 131 protrudes from the sidewall of the mask opening 130 by an amount of 0.3 nanometers to 2 nanometers.

[0064] It should be noted that the protrusion of the sidewall of the sacrificial layer 131 relative to the sidewall of the mask opening 130 should not be too large or too small. After the isolation opening is formed, in subsequent high-temperature process steps, the material of the sacrificial layer 131 in the device region 100A will change from an amorphous material back to a polycrystalline material. This can easily lead to crystallization shrinkage of the sacrificial layer 131. If the protrusion of the sidewall of the sacrificial layer 131 relative to the sidewall of the mask opening 130 is too large, it can easily lead to an increase in the linewidth of the subsequently formed isolation opening in the gate structure extension direction, that is, an increase in the spacing (Gate Cut) of adjacent gate structures in the mating direction. If the sidewall of the sacrificial layer 131 protrudes too little relative to the sidewall of the mask opening 130, the etching process in the subsequent formation of the isolation opening in the isolation region 100B will easily remove the sacrificial layer 131 in the device region 100A, thereby increasing the probability that the sidewall of the initial gate structure 105 in the device region 100A will be exposed. Consequently, the flatness of the sidewall of the formed isolation opening will be worse, which will reduce the flatness of the gate structure formed in the device region 100A at its extension direction, thus affecting the performance of the semiconductor. Therefore, in this embodiment, the sidewall of the sacrificial layer 131 protrudes from the sidewall of the mask opening 130 by 0.3 nanometers to 2 nanometers.

[0065] In this embodiment, the doping process includes ion implantation.

[0066] In this embodiment, the doping process for the initial gate structure 105 of the isolation region 100B is an ion implantation process.

[0067] The ion implantation process has advantages such as precise control over the content and distribution of ions and excellent control over the penetration depth of solid materials. In this embodiment, the ion implantation process is used to form a sacrificial layer 131 in the initial gate structure 105 of the isolation region 100B, which helps to improve the uniformity of the distribution of implanted ions in the sacrificial layer 131.

[0068] Specifically, the doping process includes a first sub-doping process and a second sub-doping process performed sequentially, with the first and second sub-doping processes having different implantation angles. Therefore, by sequentially performing the first and second sub-doping processes, the ion implantation region in the initial gate structure 105 is expanded, causing the material of the sacrificial layer 131 in the isolation region 100B to become entirely amorphous, thereby improving the flatness of the subsequently formed isolation opening sidewall.

[0069] Specifically, by performing a first sub-doping process and a second sub-doping process, the sidewall of the sacrificial layer 131 protrudes relative to the sidewall of the mask opening 130.

[0070] In this embodiment, the ion implantation direction of the first sub-doping treatment is perpendicular to the top surface of the initial gate structure 105.

[0071] By making the ion implantation direction of the first sub-doping treatment perpendicular to the top surface of the initial gate structure 105, it is beneficial to transform the material of the entire thickness of the initial gate structure 105 in the isolation region 100B into an amorphous material, so that the initial gate structure 105 in the isolation region 100B can be completely cut off in the future.

[0072] In this embodiment, the ion implantation direction of the second sub-doping treatment has an acute angle with the normal of the top surface of the initial gate structure 105.

[0073] It should be noted that, in order to form the sacrificial layer in a portion of the device region 100A at the junction of the device region 100A and the isolation region, i.e., to form an ion implantation region at the end (head) of the initial gate structure 105 in the device region 100A, the ion implantation direction of the second sub-doping process needs to have an acute angle with the normal to the top surface of the initial gate structure 105.

[0074] In this embodiment, the angle between the ion implantation direction of the second sub-doping treatment and the normal of the top surface of the initial gate structure 105 is 1 degree to 5 degrees.

[0075] It should be noted that the angle between the ion implantation direction of the second sub-doping process and the normal to the top surface of the initial gate structure 105 should not be too large or too small. If the angle between the ion implantation direction of the second sub-doping process and the normal to the top surface of the initial gate structure 105 is too large, it will easily lead to an excessively large ion implantation region formed at the end (head) of the initial gate structure 105 in the device region 100A, which will correspondingly affect the spatial position of the gate structure subsequently formed in the device region 100A. If the angle between the ion implantation direction of the second sub-doping process and the normal to the top surface of the initial gate structure 105 is too small, it will easily lead to an excessively small ion implantation region formed at the end (head) of the initial gate structure 105 in the device region 100A, that is, the sacrificial layer 131 formed in the device region 100A will be too small. During the subsequent formation of the isolation interface, the relevant etching process will easily damage the initial gate structure in the device region 100A, thereby reducing the performance of the semiconductor.

[0076] In this embodiment, the energy range of the ion implantation is from 15 keV to 80 keV.

[0077] It should be noted that the ion implantation energy should not be too high or too low. If the ion implantation energy is too high, the lateral range of ion implantation may be too large, making the process difficult to control, and the linewidth range of the sacrificial layer 131 in the extension direction of the initial gate structure may be too large. If the ion implantation energy is too low, the ion implantation depth may be insufficient, making it difficult for the initial gate structure 105 of the isolation region 100B to completely transform into the amorphous sacrificial layer 131, thus failing to achieve the desired process effect. Therefore, in this embodiment, the ion implantation energy range is 15 keV to 80 keV.

[0078] In this embodiment, the ion implantation dose range is 1E13atom / cm². 2 Up to 1E17atom / cm 2 .

[0079] It should be noted that the ion implantation dose range should not be too large or too small. If the ion implantation dose is too large, the lateral range of ion implantation may be too large, making the process difficult to control and resulting in an excessively large linewidth of the sacrificial layer 131 in the direction of the initial gate structure extension. If the ion implantation dose is too small, the reaction time of ion implantation may be too long, reducing the efficiency of the process and making it difficult to achieve the amorphization effect, thus making it easy for the etching rate of the sacrificial layer 131 to be inconsistent. Therefore, in this embodiment, the ion implantation dose range is 1E13atom / cm. 2 Up to 1E17atom / cm 2 .

[0080] refer to Figures 8 to 9 Remove the sacrificial layer 131 of the isolation region 100B, and form an isolation opening 132 in the initial gate structure 105. The isolation opening 132 divides the initial gate structure 105 in the extending direction of the initial gate structure 105 to form gate structures 150 located in the device region 100A.

[0081] The isolation opening 132 is mainly used to isolate adjacent device areas 100A.

[0082] like Figure 8 As shown, in this embodiment, the step of removing the sacrificial layer 131 of the partition region 100B includes: using the hard mask layer 120 as a mask, etching the sacrificial layer 131 of the partition region 100B along the mask opening 130.

[0083] In this embodiment, during the step of removing the sacrificial layer 131 from the partition area 100B, the sidewall of the remaining sacrificial layer 131 is flush with the sidewall of the mask opening 130.

[0084] It should be noted that after the isolation opening 132 is formed, the remaining initial gate structure 105 and sacrificial layer 131 in the device region 100A constitute the gate structure 150. The sidewall of the remaining sacrificial layer 131 is flush with the sidewall of the mask opening 130, which correspondingly improves the flatness of the sidewall of the isolation opening 132, that is, improves the flatness of the end (head) of the gate structure 150 formed in the device region 100A in its extension direction, reduces the probability of the gate structure 150 bending at its extension direction end, thereby improving the performance of the semiconductor.

[0085] Specifically, after the device gate structure is subsequently formed at the position of the gate structure 150, the flatness of the device gate structure at its end in the extension direction is relatively high.

[0086] In this embodiment, the process for removing the sacrificial layer 131 of the partition region 100B includes a dry etching process.

[0087] The dry etching process includes anisotropic dry etching. Because of its anisotropic etching characteristics, the longitudinal etching rate is much higher than the transverse etching rate, resulting in highly accurate pattern transformation and thus improving the flatness of the sidewalls of the partition opening 132.

[0088] In other embodiments, the process of removing the sacrificial layer 131 of the partition region 100B may also include a wet etching process.

[0089] In this embodiment, during the process of forming the isolation opening 132 in the initial gate structure 105, the isolation structure 102 of the isolation region 100B is used as the etching stop position.

[0090] It should be noted that, as Figure 9 As shown, after forming the partition opening 132 in the partition region 100B, the process further includes removing the organic material layer 121 and the photoresist layer 122 in the device region 100A, thereby preparing for subsequent processes.

[0091] It should also be noted that after forming the mask opening 130, the doping process and the process of forming the isolation opening are performed. After forming the isolation opening, the organic material layer 121 and the photoresist layer 122 in the device region 100A are removed. Therefore, adding the doping process before forming the isolation opening has little impact on the current process and high process compatibility. Moreover, at least one of the organic material layer 121 and the photoresist layer 122 can also protect the hard mask layer 120 during the doping process, reducing the impact of dopant ions on the performance of the hard mask layer 120 and reducing the impact on the subsequent process of removing the hard mask layer 120. At the same time, the probability of dopant ions being implanted into the device region 100A is lower.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which an initial gate structure is formed, the substrate including a device region and a partition region; The initial gate structure of the isolation region is doped, and the portion of the initial gate structure doped with ions serves as a sacrificial layer. The doping process is used to make the sacrificial layer etched at the same rate in each crystal orientation. The sacrificial layer of the isolation region is removed, and an isolation opening is formed in the initial gate structure. The isolation opening divides the initial gate structure in the extension direction of the initial gate structure to form gate structures located in the device region respectively.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of doping the initial gate structure of the isolation region, the material of the sacrificial layer is an amorphous material.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, a hard mask layer is formed on top of the initial gate structure. Before doping the initial gate structure of the isolation region, the formation method further includes: forming a mask opening penetrating the hard mask layer in the hard mask layer of the isolation region; In the step of doping the initial gate structure of the isolation region, the initial gate structure exposed by the mask opening is doped using the hard mask layer as a mask. The step of removing the sacrificial layer of the partition region includes: using the hard mask layer as a mask, etching the sacrificial layer of the partition region along the mask opening.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of doping the initial gate structure of the isolation region, the sidewall of the sacrificial layer protrudes relative to the sidewall of the mask opening; In the step of removing the sacrificial layer from the partition area, the sidewalls of the remaining sacrificial layer are flush with the sidewalls of the mask opening.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of doping the initial gate structure of the isolation region, the doping ions include Si, Ge, or Sb ions.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of doping the initial gate structure of the isolation region, the doping process is an ion implantation process, and the doping process includes a first sub-doping process and a second sub-doping process performed sequentially. The ion implantation direction of the first sub-doping treatment is perpendicular to the top surface of the initial gate structure; The ion implantation direction of the second sub-doping treatment has an acute angle with the normal of the top surface of the initial gate structure.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The angle between the ion implantation direction of the second sub-doping treatment and the normal of the top surface of the initial gate structure is 1 degree to 5 degrees.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing the substrate, an interlayer dielectric layer is also formed on the substrate on the side of the initial gate structure, and the interlayer dielectric layer covers the sidewall of the initial gate structure.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The doping process includes ion implantation.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The doping process is an ion implantation process, and the parameters of the ion implantation process include: ion implantation energy range of 15 keV to 80 keV; ion implantation dose range of 1E13 atom / cm 2 Up to 1E17 atom / cm 2 .

11. The method for forming a semiconductor structure as described in claim 4, characterized in that, The sidewall of the sacrificial layer protrudes from the sidewall of the mask opening by an amount ranging from 0.3 nanometers to 2 nanometers.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the sacrificial layer from the partition region includes a dry etching process.

13. The method for forming a semiconductor structure as described in claim 3, characterized in that, The material of the hard mask layer includes one or more of SiO2, SiN, and SiON.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the initial gate structure includes amorphous silicon.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The initial gate structure includes a pseudo-gate structure.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of providing a substrate, the substrate includes a substrate and fins protruding from the substrate.

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