MOS layout and MOS tube unit and power MOS tube using it

Abstract

The invention discloses a MOS board pattern, and a MOS tube unit and a power MOS tube applied thereto; in terms of the layout, the layout is designed according to the layout rules, and includes a substrate layer, a source-drain layer, a gate layer and a metal layer; wherein the source-drain layer includes a long strip and a short strip, the gate layer and the long strip form a parallel unit, a plurality of first drains and first sources are formed on the long strip, and the adjacent first source and second drain are merged into the same position; the gate layer and the short strip form a series unit, a plurality of sequentially arranged second drains, series connection points and second sources are formed on the short strip, and the adjacent second source and second drain are merged into the same position; when the long strip and the short strip form the source and the drain, the drain and the source can be understood as overlapping and jointly arranged, so that the position can be used as the drain and also as the source of the next MOS, thereby reducing the area of ​​the layout design.

Description

Technical Field

[0001] The present invention relates to the application field of MOS tube layout, and in particular to a MOS board layout, and a MOS tube unit and a power MOS tube applied thereto. Background Art

[0002] With the rapid and explosive growth of smart terminal products, in order to support the implementation of different functional components, there is also a huge demand for power management chips. The power management chips used in mobile smart terminals usually contain multiple operating voltages. In order to meet the needs of multiple operating voltages, multiple DC voltage converters are required to complete the voltage conversion. Common DC voltage converter chips include DC-DC, LDO, charge pump and other types. Considering the actual use needs, it is necessary to maximize its battery life, so high requirements are placed on the efficiency of DC voltage converter chips. Among DC converters, DC-DC switching power converters have the highest efficiency. The DC-DC switching power supply voltage converter is flexible and has multiple structures such as buck, boost, buck-boost, etc. It can realize multiple functions such as step-down, step-up, step-down and step-down, and can provide a large load drive current. ,

[0003] Among them, the power MOS tube is the core component of the DC-DC switching power converter and is a type of field effect tube. It plays a role in providing a stable voltage for the motherboard or components. At present, the power MOS can be composed of multiple groups of MOS tube units. Although multiple MOS tube units can effectively increase the voltage resistance of the power MOS tube, they will increase the volume of the components. Therefore, how to effectively reduce and compress the area of ​​the layout in the MOS layout design has become a problem worthy of deep consideration and solution. Summary of the invention

[0004] The present invention provides a solution to the problem that the area of ​​MOS layout design cannot be effectively compressed in the above-mentioned technology.

[0005] To achieve the above-mentioned purpose, the present invention provides a MOS layout, which is designed according to a layout rule, and includes a substrate layer, a source and drain layer, a gate layer and a metal layer; wherein the source and drain layer includes long strips and short strips, the gate layer and the long strips form a parallel unit, a plurality of first drains and first sources are formed on the long strips, and adjacent first sources and first drains are merged into the same position; the gate layer and the short strips form a series unit, a plurality of second drains, series points and second sources are formed on the short strips, and adjacent second sources and second drains are merged into the same position.

[0006] The gate layer is composed of a plurality of gate units that are repeatedly arranged, and the number of arranged gate units is adapted according to the number and length of groups of long strips and short strips.

[0007] The gate unit includes an upper region and a lower region, the area of ​​the upper region is larger than that of the lower region; the upper region and the long strip form a parallel unit, and the lower region and the short strip form a series unit.

[0008] The metal layer is formed by repeatedly arranging a plurality of groups of metal units, and the number of arranged metal units is adapted according to the number of series units and parallel units.

[0009] It also includes a cutting layer, which is provided with a plurality of cutting points for forming layout wiring positions, and the cutting points are located on the positions of the merged first drain and the first source, and on the positions of the merged second source and the second drain.

[0010] The present invention also provides a MOS tube unit, which is manufactured according to the above MOS layout.

[0011] The present invention also provides a power MOS tube, comprising a plurality of groups of repeatedly arranged matrix units, wherein the matrix units are obtained by arranging the above-mentioned MOS tube units in a certain proportion, and the number of MOS tube units is adjusted according to the size of the external current required.

[0012] Among them, the arrangement ratio of the MOS tube units in the matrix unit is 40*20.

[0013] Wherein, a protection diode is also arranged between the drain and the source of the plurality of groups of MOS tube units.

[0014] The beneficial effects of the present invention are as follows: compared with the prior art, the present invention provides a MOS board pattern, and a MOS tube unit and a power MOS tube used therein; in terms of layout, the layout is designed according to the layout rules, including a substrate layer, a source and drain layer, a gate layer and a metal layer; wherein the source and drain layer includes a long strip and a short strip, the gate layer and the long strip form a parallel unit, a plurality of first drains and first sources are formed on the long strip, and the adjacent first source and second drain are merged into the same position; the gate layer and the short strip form a series unit, a plurality of second drains, series connection points and second sources arranged in sequence are formed on the short strip, and the adjacent second source and second drain are merged into the same position; when the long strip and the short strip form the source and the drain, the drain and the source can be understood as overlapping and jointly arranged, so that the position can be used as both the drain and the source of the next MOS, thereby reducing the area of ​​the layout design; and in the series unit, a series connection point is provided between the drain and the source, and since there is no need for wiring at the series connection point, the area required for the wiring point can be directly omitted, thereby further reducing the layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A bottom lining layer diagram of the layout of the present invention;

[0016] Figure 2 A diagram of the drain and source layer of the present invention;

[0017] Figure 3 A diagram of a gate layer of the present invention;

[0018] Figure 4 This is an enlarged view of region A of the present invention;

[0019] Figure 5 A metal layer diagram of the present invention;

[0020] Figure 6 The cutting layer of the present invention;

[0021] Figure 7 The overall MOS layout of the present invention;

[0022] Figure 8 This is an enlarged view of region B of the present invention;

[0023] Fig. 9 It is the principle diagram of the power MOS tube of the present invention;

[0024] Fig.10 It is an enlarged view of the C region of the present invention.

[0025] The main component symbols are described as follows:

[0026] 1. Source and drain layer; 11. Long strip; 12. Short strip; 2. Gate layer; 21. Upper region; 22. Lower region;

[0027] 3. Metal layer; 31. First metal line; 32. Second metal line;

[0028] 4. Parallel unit; 41. First drain; 42. First source;

[0029] 5. Series unit; 51. Second drain; 52. Series point; 53. Second source;

[0030] 6. Cutting point; 7. Protection diode. DETAILED DESCRIPTION

[0031] In order to more clearly illustrate the present invention, the present invention is further described below in conjunction with the accompanying drawings.

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0033] In the application, the word "exemplary" is used to mean "serving as an example, illustration, or description". Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is given to enable any technician in the field to implement and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present invention can be implemented without using these specific details. In other instances, known structures and processes are not described in detail to avoid obscuring the description of the invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles disclosed in this application.

[0034] The power MOS tube is the core component of the DC-DC switching power converter and is a type of field effect tube. It plays the role of providing a stable voltage for the motherboard or components. Currently, the power MOS can be composed of multiple groups of MOS tube units. Although multiple MOS tube units can effectively increase the voltage resistance of the power MOS tube, they will increase the volume of the components. Therefore, how to effectively compress the design area of ​​the layout without causing defects in the overall performance of the MOS tube unit has become a technical problem that needs to be solved urgently.

[0035] In order to solve the above problems, the present invention provides a MOS layout, please refer to Figures 1 to 10 , the layout is designed according to the layout rules, including a substrate layer, a source-drain layer 1, a gate layer 2 and a metal layer 3; wherein the source-drain layer 1 includes a long strip 11 and a short strip 12, the gate layer 3 and the long strip 11 form a parallel unit 4, a plurality of first drains 41 and first sources 42 are formed on the long strip 11, and the adjacent first sources 42 and second drains 41 are merged into the same position; the gate layer 2 and the short strip 12 form a series unit 5, a plurality of second drains 51, series points 52 and second sources 51 arranged in sequence are formed on the short strip 12 3, and the second source 51 and the second drain 53 arranged adjacently are merged into the same position; when the long strip 11 and the short strip 12 form the source and the drain, the drain and the source can be understood as overlapping and arranged together, so that the position can be used as both the drain and the source of the next MOS, thereby reducing the area of ​​the layout design; further, in the series unit 5, a series connection point is provided between the drain and the source, and the series connection point 52 has no need for wiring, so the area required for the wiring point can be directly omitted, further reducing the layout area.

[0036] In this embodiment, the gate layer 2 is composed of a plurality of gate units repeatedly arranged, which can be understood as arranging a gate unit on the same plane in the form of a mirror image or a copy, so as to obtain the gate layer 2; the number of arranged gate units is adapted according to the number and length of the groups of the long strips 11 and the short strips 12; further, the gate unit includes an upper area 21 and a lower area 22, and since the series connection point 52 does not need to reserve a wiring position, the area of ​​the upper area 21 is larger than that of the lower area 22, further reducing the area of ​​the layout design; the upper area 21 and the long strip 11 form a parallel unit, and the lower area 22 and the short strip 12 form a series unit.

[0037] In this embodiment, the metal layer 3 is composed of a plurality of groups of metal units repeatedly arranged, and the number of arranged metal units is adapted according to the number of series units 5 and parallel units 4; the metal units can be divided into a first metal wire 31 and a second metal wire 32, the first metal wire 31 is used to connect the same parallel unit 4 or the same series unit 5, and the second metal wire 32 connects the second drain 51 or the second source 53 in the series unit with the first source 41 or the first drain 42 in the parallel part 4 to ensure the current conduction of the subsequent MOS.

[0038] In this embodiment, a cutting layer is also included, and the cutting layer is provided with a plurality of cutting points 6 for forming wiring positions of the layout, and the cutting points 6 are located at the positions on the merged first source 41 and the second drain 42, and at the positions on the merged second source and the second drain; the cutting layer is used to form wiring positions in specific applications, which is achieved by setting a plurality of cutting points 6. It can be understood that the drain and source of the parallel unit 4 and the series unit 5 in this embodiment can be regarded as being set together. When the drain and the source are in the same position, a group of wiring positions can be formed to meet the needs; and in the series unit 5, a series point is formed between the second drain 51 and the second source 53, and the series point 52 does not need to contact any metal. Therefore, the wiring position directly saves the wiring position, further reducing the layout area.

[0039] The present invention also provides a MOS tube unit, which is made according to the above-mentioned MOS layout; a substrate material is selected, and a substrate is formed through epitaxial growth, diffusion, injection and exposure processes according to substrate layer rules and requirements, and then a drain and a source are formed through a source and drain layer, and a gate layer forms a gate, a metal layer is used to form a connection between the source and the drain, and a cutting layer forms a connection position and a connection end.

[0040] The present invention also provides a power MOS tube, comprising a plurality of groups of repeatedly arranged matrix units, wherein the matrix units are obtained by arranging the above-mentioned MOS tube units in proportion, and the number of components of the MOS tube units is adjusted according to the size of the external current required;

[0041] In this embodiment, the arrangement ratio of the MOS tube units in the matrix unit is 40*20; the required arrangement ratio of the MOS tube units can be adjusted according to the external current to balance the relationship between the withstand voltage and the application area.

[0042] In the present embodiment, a protection diode is further provided between the drain and source of the multiple groups of MOS tube units; the protection diode 7 can prevent damage caused by a higher access load during the access, test and application stages. When a high pulse breaks out, the protection diode 7 is directly turned on to protect the power MOS tube, and has a certain number of recovery times to achieve multiple protections; and the MOS tube unit used in the present invention is obtained according to the MOS layout, wherein the series unit 5, the parallel unit 4 and the metal unit cooperate to form a stable connection state with strong impact resistance, so it is not necessary to add an electrostatically simulated diode for protection.

[0043] The advantages of the present invention are:

[0044] When the long strips and the short strips form the source and the drain, the drain and the source can be understood as overlapping and set together, so that the position can be used as both the drain and the source of the next MOS, thereby reducing the area of ​​the layout design; further, in the series unit, a series connection point is provided between the drain and the source. Since there is no need for wiring at the series connection point, the area required for the wiring point can be directly omitted, further reducing the layout area.

[0045] The above disclosures are only several specific embodiments of the present invention, but the present invention is not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A MOS layout, It is characterized in that A layout is designed according to the layout rules, including a substrate layer, a source-drain layer, a gate layer and a metal layer; wherein the source-drain layer includes a long strip and a short strip, the gate layer and the long strip form a parallel unit, a plurality of first drains and first sources are formed on the long strip, and the adjacent first sources and first drains are merged into the same position; the gate layer and the short strip form a series unit, a plurality of sequentially arranged second drains, series points and second sources are formed on the short strip, and the adjacent second sources and second drains are merged into the same position; The gate layer is obtained by arranging a gate unit in the same plane in the form of mirroring or copying; the number of arranged gate units is adapted according to the number and length of groups of long strips and short strips; the gate unit includes an upper area and a lower area, and the area of ​​the upper area is larger than the area of ​​the lower area; the upper area and the long strip form a parallel unit, and the lower area and the short strip form a series unit; Among them, a plurality of second drains, series points and second sources arranged in sequence are formed on the short strip, and the adjacent second sources and second drains are merged into the same position; when the source and drain are formed in the long strip and the short strip, the drain and the source are overlapped and arranged together, so that the position can be used as both the drain and the source of the next MOS.

2. The MOS layout according to claim 1, It is characterized in that The gate layer is composed of a plurality of gate units that are repeatedly arranged, and the number of arranged gate units is adapted according to the number and length of groups of long strips and short strips.

3. The MOS layout according to claim 2, It is characterized in that The gate unit includes an upper region and a lower region, the area of ​​the upper region is larger than that of the lower region; the upper region and the long strip form a parallel unit, and the lower region and the short strip form a series unit.

4. The MOS layout according to claim 1, It is characterized in that The metal layer is formed by repeatedly arranging a plurality of groups of metal units, and the number of arranged metal units is adapted according to the number of series units and parallel units.

5. The MOS layout according to claim 1, It is characterized in that It also includes a cutting layer, which is provided with a plurality of cutting points for forming layout wiring positions, and the cutting points are located on the positions of the merged first drain and first source, and on the positions of the merged second source and second drain.

6. A MOS tube unit, It is characterized in that Made according to any one of claims 1 to 5 of the MOS layout.

7. A power MOS tube, It is characterized in that It comprises a plurality of groups of repeatedly arranged matrix units, wherein the matrix units are obtained by arranging the MOS tube units according to claim 6 in proportion, and the number of the MOS tube units is adjusted according to the size of the external current required.

8. The power MOS tube according to claim 7, It is characterized in that The arrangement ratio of the MOS tube units in the matrix unit is 40*20.

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