Semiconductor device

Abstract

Provided is a semiconductor device capable of improving withstand voltage. The semiconductor device has a first semiconductor region and a third semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a structure body, a gate electrode, and a high-resistance portion. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion of the structure body is arranged side by side with a part of the first semiconductor region, the second semiconductor region, and the third semiconductor region. The conductive portion of the structure body is provided in the insulating portion and has a part that opposes the first semiconductor region. The gate electrode opposes the second semiconductor region. The high-resistance portion has a higher resistance than the first semiconductor region. The structure body is provided in a plurality of directions. The plurality of structure bodies has a first structure body to a third structure body. The high-resistance portion overlaps a center of an imaginary circle in a first direction, the imaginary circle passing through centers in a second direction and a third direction of the first structure body, the second structure body, and the third structure body, respectively.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0002] Vertically oriented Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and other semiconductor devices are used in applications such as power conversion. For these semiconductor devices, there is a requirement for increased voltage withstand capability.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-47742 Summary of the Invention

[0006] The technical problem to be solved by the present invention

[0007] The technical problem to be solved by the present invention is to provide a semiconductor device that can improve voltage resistance.

[0008] Means for solving technical problems

[0009] The semiconductor device according to the embodiment includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a structure, a gate electrode, and a high-resistance portion. The second semiconductor region is disposed above the first semiconductor region. The third semiconductor region is selectively disposed above the second semiconductor region. The structure includes an insulating portion and a conductive portion. The insulating portion is arranged side-by-side with a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region and a third direction perpendicular to the first direction and intersecting the second direction. The conductive portion is disposed in the insulating portion and has portions opposite to the first semiconductor region in the second and third directions. The gate electrode is opposite to the second semiconductor region in the second and third directions. The high-resistance portion is disposed in the first semiconductor region and has a higher resistance than the first semiconductor region. The structure includes a plurality of portions disposed along the second and third directions. The plurality of said structures include a first structure, a second structure, and a third structure. The second structure is adjacent to the first structure in the second direction. The third structure is adjacent to the first structure in the third direction. The high-resistivity portion overlaps with the center of an imaginary circle in the first direction, the imaginary circle passing through the centers of the first structure, the second structure, and the third structure in the second and third directions, respectively. Attached Figure Description

[0010] Figure 1 This is a top view showing a portion of the semiconductor device according to the first embodiment.

[0011] Figure 2 yes Figure 1 Sectional view II-II.

[0012] Figure 3 This is a top view showing a portion of the semiconductor device according to the second embodiment.

[0013] Figure 4 yes Figure 3 Sectional view IV-IV. Detailed Implementation

[0014] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0015] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of the parts, the ratio of the sizes between the parts, etc., are not limited to the same situation as in reality. Even when representing the same parts, sometimes the dimensions and ratios between them are shown differently according to the accompanying drawings.

[0016] In this application specification and figures, elements that are the same as those already described are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0017] In the following description and accompanying figures, n + n － and p + The markings "p" indicate the relative levels of impurity concentration. Specifically, a "+" marking indicates a relatively higher impurity concentration compared to any marking without "+" or "-", while a "-" marking indicates a relatively lower impurity concentration. These markings, when these regions contain both acceptor and donor impurities, indicate the relative levels of net impurity concentration after these impurities compensate for each other.

[0018] The embodiments described below can be implemented by inverting the p-type and n-type of each semiconductor region.

[0019] (First Embodiment)

[0020] Figure 1 This is a top view showing a portion of the semiconductor device according to the first embodiment.

[0021] Figure 2 yes Figure 1 Sectional view II-II.

[0022] The semiconductor device 100 according to the first embodiment is, for example, a vertically oriented MOSFET. The semiconductor device 100 is a so-called dot-structure MOSFET.

[0023] like Figure 1 and Figure 2 As shown, the semiconductor device 100 has n － Type 1 (first conductivity type) drift region 1 (first semiconductor region), p-type (second conductivity type) substrate region 2 (second semiconductor region), n + Type source region 3 (third semiconductor region), n + Type drain region 5, gate electrode 10, structure 20 and high resistance section 30.

[0024] In the following descriptions of the various embodiments, the first direction D1, the second direction D2, and the third direction D3 will be used. (The last part, "from n," appears to be a fragment and doesn't translate directly. It seems to be a list of directions or concepts.) － The direction from the p-type drift region 1 toward the p-type base region 2 is designated as the first direction D1. A direction perpendicular to the first direction D1 is designated as the second direction D2. A direction perpendicular to the first direction D1 and intersecting the second direction D2 is designated as the third direction D3. Furthermore, for illustration, from n...－ The direction from the p-type drift region 1 toward the p-type base region 2 is called "up," and the opposite direction is called "down." These directions are based on n. － The relative positional relationship between the p-type drift region 1 and the p-type base region 2 is independent of the direction of gravity.

[0025] like Figure 1 and Figure 2 As shown, n is provided at the lower part of the semiconductor device 100. + Type 5 drain region. In n + An n-type drain region 5 is provided above it. － Type-aspect drift region 1. In n － A p-type base region 2 is provided above the p-type drift region 1. An n-type base region is selectively provided above the p-type base region 2. + Type source pole region 3.

[0026] The structure 20 has an insulating portion 21 and a conductive portion 22. The insulating portion 21 is connected to n in the second direction D2 and the third direction D3. － Part of type-1 drift region, p-type base region 2 and n + The source electrode regions 3 are arranged side by side. A conductive portion 22 is disposed within the insulating portion 21. At least a portion of the conductive portion 22 is connected to n in the second direction D2 and the third direction D3. － A portion of the p-type drift region 1 is arranged side-by-side. A portion of the conductive part 22, on the second direction D2 and the third direction D3, can further connect with the p-type substrate region 2 and the n-type substrate region 2. + The source pole regions are arranged in three parallel rows.

[0027] In the semiconductor device 100, a gate electrode 10 is also disposed in the insulating portion 21. The gate electrode 10 is disposed around the upper part of the conductive portion 22 in the second direction D2 and the third direction D3. A portion of the insulating portion 21 is disposed between the gate electrode 10 and the conductive portion 22. Thus, the gate electrode 10 and the conductive portion 22 are electrically isolated from each other.

[0028] The gate electrode 10 is positioned opposite the p-type substrate region 2 in the second direction D2 and the third direction D3, separated by the gate insulating layer 11. The gate electrode 10 may also be further positioned opposite the n-type substrate region 2, separated by the gate insulating layer 11. － Type drift regions 1 and n + The source region 3 is opposite to the source region 3. In the semiconductor device 100, a portion of the insulating portion 21 functions as the gate insulating layer 11.

[0029] The high resistance section 30 is provided at n － In type drift region 1. In this example, the high-resistance part 30 is provided in n. － In type-1 drift region, in type-2 base region, and in type-n +In source region 3, the high-resistivity section 30 does not overlap with the structure 20 in the first direction D1. The resistance of the high-resistivity section 30 is higher than n. － The resistance of drift region 1.

[0030] n － Type-drift region 1 via n + The drain region 5 is electrically connected to the drain electrode 41. The drain electrode 41 is, for example, disposed in n... + Below the type drain region 5.

[0031] p-type basal region 2 and n + The p-type substrate region 3 is electrically connected to the source electrode 42. The conductive portion 22 is electrically connected to the source electrode 42. The source electrode 42 is, for example, disposed in the p-type substrate region 2, n-type substrate region 3, n-type substrate region 42 ... + The source region 3, the gate electrode 10, and the structure 20 are located above.

[0032] The gate electrode 10 is electrically connected to the gate pad 43. The gate pad 43 is electrically disconnected from the source electrode 42.

[0033] like Figure 1 As shown, in the semiconductor device 100, the conductive portion 22 is shaped like a regular hexagonal prism. Furthermore, when viewed from the first direction D1, the gate electrode 10 surrounds the conductive portion 22. The gate electrode 10 is also shaped like a regular hexagonal cylinder. Additionally, the outer surface of the structure 20 is shaped like a regular hexagonal prism. The structure 20 is hexagonal when viewed along the first direction D1. The cross-sectional shape of the structure 20 in the planes along the second direction D2 and the third direction D3 is also hexagonal.

[0034] like Figure 1 As shown, multiple gate electrodes 10 and structures 20 are respectively provided along the second direction D2 and the third direction D3. For example, p-type substrate regions 2 and n + The p-type source region 3 is disposed around the structure 20. Additionally, the p-type base region 2 and the n-type source region 3 are also present. + The source pole region 3 is disposed between the multiple structures 20, surrounding each structure 20.

[0035] The plurality of structures 20 arranged along the second direction D2 and the third direction D3 includes a first structure 20a, a second structure 20b, and a third structure 20c. The first structure 20a is one of the plurality of structures 20. The second structure 20b is adjacent to the first structure 20a in the second direction D2. The third structure 20c is adjacent to the first structure 20a in the third direction D3. In this example, the angle between the second direction D2 and the third direction D3 is 60 degrees.

[0036] exist Figure 1In the diagram, the first center C1 represents the center of the first structure 20a in the second direction D2 and the third direction D3. The second center C2 represents the center of the second structure 20b in the second direction D2 and the third direction D3. The third center C3 represents the center of the third structure 20c in the second direction D2 and the third direction D3. Here, consider an imaginary circle IC1 passing through the first center C1, the second center C2, and the third center C3. In the semiconductor device 100, the first center C1, the second center C2, and the third center C3 exist on the circumference of one imaginary circle IC1. The distance between the center C0 of the imaginary circle IC1 and the first center C1 is equal to the distance between the center C0 and the second center C2 and the distance between the center C0 and the third center C3, respectively.

[0037] The angle between the first line direction LD1 connecting the center C0 to the first center C1 and the second line direction LD2 connecting the center C0 to the second center C2 is 120 degrees. The angle between the first line direction LD1 and the third line direction LD3 connecting the center C0 to the third center C3 is 120 degrees. The angle between the second line direction LD2 and the third line direction LD3 is 120 degrees. That is, in this example, the triangle formed by connecting the first center C1, the second center C2, and the third center C3 is an equilateral triangle. In other words, in this example, the first structure 20a, the second structure 20b, and the third structure 20c are configured as an equilateral triangle when viewed along the first direction D1.

[0038] The distance between the first center C1 and the second center C2 is equal to the distance between the first center C1 and the third center C3, and the distance between the second center C2 and the third center C3, respectively. That is, the first structure 20a, the second structure 20b, and the third structure 20c are arranged at certain intervals in the second direction D2 and the third direction D3. For example, if the distance between the first center C1 and the second center C2 is set as P1, and the width of the first structure 20a (the second structure 20b) in the second direction D2 is set as W1, then the distance L1 between the first structure 20a and the second structure 20b is represented by L1 = P1 - W1.

[0039] The high-resistance section 30 is positioned in the first direction D1, overlapping with the center C0. In this example, the cross-sectional shape of the high-resistance section 30 in the plane along the second direction D2 and the third direction D3 is an equilateral triangle centered at the center C0. This equilateral triangle faces opposite to the equilateral triangle formed by connecting the first center C1, the second center C2, and the third center C3. The length of one side of this equilateral triangle is, for example, less than or equal to a distance L1.

[0040] The high-resistance portion 30 may be provided entirely between adjacent structures 20, or it may be provided only in a portion between adjacent structures 20. That is, for example, the high-resistance portion 30 may not be provided between other structures adjacent to the first structure 20a and the second structure 20b, or between the first structure 20a and the second structure 20b.

[0041] The operation of the semiconductor device 100 will be explained.

[0042] With a positive voltage applied to the drain electrode 41 relative to the source electrode 42, a voltage above a threshold value is applied to the gate electrode 10. This forms a channel (inversion layer) in the p-type substrate region 2, and the semiconductor device 100 becomes conductive. Electrons flow through the channel from the source electrode 42 to the drain electrode 41. Then, if the voltage applied to the gate electrode 10 becomes lower than the threshold value, the channel in the p-type substrate region 2 disappears, and the semiconductor device 100 becomes cut off.

[0043] If the semiconductor device 100 switches to the off state, the positive voltage applied to the drain electrode 41 relative to the source electrode 42 increases. That is, n － The potential difference between the drift region 1 and the conductive part 22 increases. Due to the increase in potential difference, the depletion layer moves from the insulating part 21 to the conductive part 22. － The interface of drift region 1 faces n － The drift region 1 expands. That is, the conductive portion 22 functions as an FP (field plate) electrode. The depletion layer reaches the high-resistivity portion 30. Due to the expansion of this depletion layer, the withstand voltage of the semiconductor device 100 can be improved. Alternatively, while maintaining the withstand voltage of the semiconductor device 100, the n-value can be increased. － The concentration of impurities that become donors in the drift region 1 reduces the on-resistance of the semiconductor device 100.

[0044] An example of the material of each component of the semiconductor device 100 will be described.

[0045] n － Type 1 drift region, p-type base region 2, n + Type source pole regions 3 and n + The drain region 5 is a semiconductor material comprising silicon, silicon carbide, gallium nitride, or gallium arsenide. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the donor impurity. Boron can be used as the acceptor impurity.

[0046] The gate electrode 10 and the conductive portion 22 are made of a conductive material such as polysilicon. Impurities may be added to the conductive material. The insulating portion 21 is made of an insulating material. For example, the insulating portion 21 is made of silicon oxide or silicon nitride. The drain electrode 41 and the source electrode 42 are made of metals such as aluminum or copper.

[0047] The high-resistivity portion 30 may, for example, comprise an insulating material. More specifically, the high-resistivity portion 30 may, for example, comprise at least one of silicon oxide and silicon nitride. Alternatively, the high-resistivity portion 30 may, for example, comprise a semiconductor material. More specifically, the high-resistivity portion 30 may, for example, comprise at least one of silicon and silicon germanium. When the high-resistivity portion 30 comprises a semiconductor material, the concentration of impurities contained in the high-resistivity portion 30 is less than n. － The concentration of impurities contained in the drift region 1. The high-resistivity section 30 preferably has tensile stress along the first direction D1.

[0048] The effects of the semiconductor device 100 according to the first embodiment will be explained.

[0049] In a dot-shaped structure with multiple structures 20 arranged along the second direction D2 and the third direction D3, for example, a strip-shaped structure extending the structures along the third direction D3, the symmetry of the depletion layer extension is disrupted, creating regions that are difficult to deplete between adjacent structures 20. If the voltage is further increased in order to deplete these regions, problems such as increased electric field strength and decreased withstand voltage arise.

[0050] According to the semiconductor device 100 of the first embodiment, by providing a high-resistivity portion 30 in a region that is not easily depleted, it is possible to suppress the decrease in withstand voltage caused by the non-depleted region. Furthermore, by providing a high-resistivity portion 30 having tensile stress along the first direction D1, it is possible to reduce the voltage drop in the n-th region adjacent to the high-resistivity portion 30. － Tensile strain is generated in the drift region 1 along the first direction D1. As a result, by generating tensile strain along the first direction D1 through which the charge carriers flow, the mobility of the charge carriers is increased, and the on-resistance can be reduced.

[0051] Furthermore, when the first structure 20a, the second structure 20b, and the third structure 20c are configured as an equilateral triangle when viewed along the first direction D1, the reduction in withstand voltage can be more effectively suppressed by setting the cross-sectional shape of the high-resistance portion 30 in the plane along the second direction D2 and the third direction D3 to an equilateral triangle centered at the center C0.

[0052] In addition, the high-resistivity section 30 includes an insulating material (e.g., at least one of silicon oxide and silicon nitride), which can more effectively suppress the decrease in withstand voltage.

[0053] In addition, the high-resistivity section 30 contains a semiconductor material with low impurity concentration (e.g., at least one of silicon and silicon germanium), thereby more effectively suppressing the decrease in withstand voltage.

[0054] (Second Implementation)

[0055] Figure 3 This is a top view showing a portion of the semiconductor device according to the second embodiment.

[0056] Figure 4 yes Figure 3 Sectional view IV-IV.

[0057] The semiconductor device 200 according to the second embodiment is, for example, a vertically oriented MOSFET. The semiconductor device 200 is a so-called dot-structure MOSFET.

[0058] like Figure 3 and Figure 4 As shown, the semiconductor device 200 has n － Type 1 drift region, p-type base region 2, n + Type source pole region 3, n + Type drain region 5, gate electrode 10, structure 20 and high resistance section 30.

[0059] like Figure 3 As shown, in the semiconductor device 200, the conductive portion 22 is shaped like a regular square prism. Furthermore, when viewed from the first direction D1, the gate electrode 10 surrounds the conductive portion 22. The gate electrode 10 is also shaped like a regular square cylinder. Additionally, the outer surface of the structure 20 is shaped like a regular square prism. The structure 20 is quadrilateral when viewed along the first direction D1. The cross-sectional shape of the structure 20 in the planes along the second direction D2 and the third direction D3 is also quadrilateral.

[0060] The plurality of structures 20 arranged along the second direction D2 and the third direction D3 include a first structure 20a, a second structure 20b, a third structure 20c, and a fourth structure 20d. The first structure 20a is one of the plurality of structures 20. The second structure 20b is adjacent to the first structure 20a in the second direction D2. The third structure 20c is adjacent to the first structure 20a in the third direction D3. The fourth structure 20d is adjacent to the third structure 20c in the second direction D2 and to the second structure 20b in the third direction D3. In this example, the angle between the second direction D2 and the third direction D3 is 90 degrees.

[0061] exist Figure 3In the diagram, the first center C11 represents the center of the first structure 20a in the second direction D2 and the third direction D3. The second center C12 represents the center of the second structure 20b in the second direction D2 and the third direction D3. The third center C13 represents the center of the third structure 20c in the second direction D2 and the third direction D3. The fourth center C14 represents the center of the fourth structure 20d in the second direction D2 and the third direction D3. Here, consider an imaginary circle IC2 passing through the first center C11, the second center C12, the third center C13, and the fourth center C14. In the semiconductor device 200, the first center C11, the second center C12, the third center C13, and the fourth center C14 exist on the circumference of one imaginary circle IC2. The distances between the center C10 and the first center C11 of the imaginary circle IC2 are equal to the distances between the center C10 and the second center C12, the distances between the center C10 and the third center C13, and the distances between the center C10 and the fourth center C14, respectively.

[0062] The angle between the first line direction LD11 connecting the center C10 to the first center C11 and the second line direction LD12 connecting the center C10 to the second center C12 is 90 degrees. The angle between the first line direction LD11 and the third line direction LD13 connecting the center C10 to the third center C13 is 90 degrees. The angle between the second line direction LD12 and the fourth line direction LD14 connecting the center C10 to the fourth center C14 is 90 degrees. The angle between the third line direction LD13 and the fourth line direction LD14 is 90 degrees. That is, in this example, the quadrilateral formed by connecting the first center C11, the second center C12, the third center C13, and the fourth center C14 is a square. In other words, in this example, the first structure 20a, the second structure 20b, the third structure 20c, and the fourth structure 20d are arranged as a square when viewed along the first direction D1.

[0063] The distance between the first center C11 and the second center C12 is equal to the distance between the first center C11 and the third center C13, the distance between the second center C12 and the fourth center C14, and the distance between the third center C13 and the fourth center C14, respectively. That is, the first structure 20a, the second structure 20b, the third structure 20c, and the fourth structure 20d are arranged at certain intervals in the second direction D2 and the third direction D3. For example, if the distance between the first center C11 and the second center C12 is set as P2, and the width of the second direction D2 of the first structure 20a (the second structure 20b) is set as W2, then the distance L2 between the first structure 20a and the second structure 20b is represented by L2 = P2 - W2. In addition, the distance L3 between the first structure 20a and the fourth structure 20d is represented by L3 = (√2) × (P2 - W2).

[0064] The high-resistance portion 30 is disposed at a position overlapping the center C10 in the first direction D1. In this example, the cross-sectional shape of the high-resistance portion 30 in the plane along the second direction D2 and the third direction D3 is a cross shape extending in the second direction D2 and the third direction D3 with the center C10 as the center. The length of the cross shape in the second direction D2 is, for example, a distance L2 or more. The length of the cross shape in the third direction D3 is, for example, a distance L2 or more. That is, the high-resistance portion 30 is located between the first structure 20a and the third structure 20c in the third direction D3. In addition, the high-resistance portion 30 is located between the second structure 20b and the fourth structure 20d in the third direction D3. In addition, the high-resistance portion 30 is located between the first structure 20a and the second structure 20b in the second direction D2. In addition, the high-resistance portion 30 is located between the third structure 20c and the fourth structure 20d in the second direction D2. The length of the direction in which the cross-shaped structure connects the first structure 20a and the fourth structure 20d is, for example, less than or equal to a distance L3.

[0065] In the semiconductor device 200, the high-resistance section 30 can be disposed entirely between adjacent structures 20, or it can be disposed only between a portion of adjacent structures 20.

[0066] In the semiconductor device 200 according to the second embodiment, by providing a high-resistivity portion 30 in a region that is not easily depleted, the decrease in withstand voltage caused by the non-depleted region can be suppressed. Furthermore, by providing a high-resistivity portion 30 having tensile stress along the first direction D1, the n-th region adjacent to the high-resistivity portion 30... － In the drift region 1, tensile strain can be generated along the first direction D1. As a result, by generating tensile strain along the first direction D1 through which the charge carriers flow, the mobility of the charge carriers is increased, and the on-resistance can be reduced.

[0067] Furthermore, when the first structure 20a, the second structure 20b, the third structure 20c, and the fourth structure 20d are arranged as squares when viewed along the first direction D1, the cross-sectional shape of the high-resistance portion 30 in the plane along the second direction D2 and the third direction D3 is set as a cross shape centered on the center C10 and extending along the second direction D2 and the third direction D3, thereby more effectively suppressing the reduction of withstand voltage.

[0068] As described above, according to the embodiments, a semiconductor device capable of improving voltage withstand capability is provided.

[0069] The above examples illustrate several embodiments of the present invention, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are encompassed by the invention as described in the claims and its equivalents. Furthermore, the foregoing embodiments can be combined with each other for implementation.

[0070] Explanation of reference numerals in the attached figures

[0071] 1n － Type 1 drift region, 2p-type base region, 3n + Type source pole region, 5n + Type Drain Region, 10 Gate Electrode, 11 Gate Insulating Layer, 20 Structure, 20a First Structure, 20b Second Structure, 20c Third Structure, 20d Fourth Structure, 21 Insulating Part, 22 Conductive Part, 30 High Resistance Part, 41 Drain Electrode, 42 Source Electrode, 43 Gate Pad, 100, 200 Semiconductor Device, C0, C10 Center, C1, C11 First Center, C2, C12 Second Center, C3, C13 Third Center, C14 Fourth Center, D1 First Direction, D2 Second Direction, D3 Third Direction, IC1, IC2 Imaginary Circles, LD1, LD11 First Line Direction, LD2, LD12 Second Line Direction, LD3, LD13 Third Line Direction, LD14 Fourth Line Direction

Claims

1. A semiconductor device, wherein, have: The first semiconductor region of the first conductivity type; A second semiconductor region of a second conductivity type is disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is selectively disposed on the second semiconductor region; The structure has an insulating portion and a conductive portion. The insulating portion is arranged side by side with a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region and in a third direction perpendicular to the first direction and intersecting the second direction. The conductive portion is disposed in the insulating portion and has portions opposite to the first semiconductor region in the second and third directions. A gate electrode is positioned opposite the second semiconductor region in the second direction and the third direction; as well as A high-resistance portion is disposed in the first semiconductor region, and its resistance is higher than that of the first semiconductor region. Multiple structures are provided along the second and third directions. The plurality of said structures include a first structure, a second structure adjacent to the first structure in the second direction, and a third structure adjacent to the first structure in the third direction. The high-resistivity portion overlaps with the center of an imaginary circle in the first direction, and this imaginary circle passes through the centers of the first structure, the second structure, and the third structure in the second and third directions, respectively. The shape formed by connecting the centers of the first, second, and third structures is an equilateral triangle when viewed along the first direction. The cross-sectional shape of the high-resistivity portion in the plane along the second and third directions is an equilateral triangle centered at the center of the circle.

2. The semiconductor device of claim 1, wherein, The high-resistivity section contains insulating material.

3. The semiconductor device as claimed in claim 2, wherein, The high-resistivity section comprises at least one of silicon oxide and silicon nitride.

4. The semiconductor device of claim 1, wherein, The high-resistivity section contains semiconductor material. The concentration of impurities contained in the high-resistivity region is lower than the concentration of impurities contained in the first semiconductor region.

5. The semiconductor device of claim 4, wherein, The high-resistivity section contains at least one of silicon and silicon-germanium.

6. A semiconductor device, wherein, have: The first semiconductor region of the first conductivity type; A second semiconductor region of a second conductivity type is disposed on the first semiconductor region; The third semiconductor region of the first conductivity type is selectively disposed on the second semiconductor region; The structure has an insulating portion and a conductive portion. The insulating portion is arranged side by side with a portion of the first semiconductor region, the second semiconductor region, and the third semiconductor region in a second direction perpendicular to a first direction from the first semiconductor region toward the second semiconductor region and in a third direction perpendicular to the first direction and intersecting the second direction. The conductive portion is disposed in the insulating portion and has portions opposite to the first semiconductor region in the second and third directions. A gate electrode is positioned opposite the second semiconductor region in the second direction and the third direction; as well as A high-resistance portion is disposed in the first semiconductor region, and its resistance is higher than that of the first semiconductor region. Multiple structures are provided along the second and third directions. The plurality of said structures include a first structure, a second structure adjacent to the first structure in the second direction, and a third structure adjacent to the first structure in the third direction. The plurality of said structures also have a fourth structure, which is adjacent to the third structure in the second direction and to the second structure in the third direction. The high-resistivity portion overlaps with the center of an imaginary circle in the first direction, and this imaginary circle passes through the centers of the first structure, the second structure, the third structure, and the fourth structure in the second and third directions, respectively. The shape formed by connecting the centers of the first, second, third, and fourth structures is a square when viewed along the first direction. The cross-sectional shape of the high-resistivity portion in the plane along the second and third directions is a cross shape centered on the circle and extending in the second and third directions.

7. The semiconductor device of claim 6, wherein, The high-resistivity section contains insulating material.

8. The semiconductor device of claim 7, wherein, The high-resistivity section comprises at least one of silicon oxide and silicon nitride.

9. The semiconductor device of claim 6, wherein, The high-resistivity section contains semiconductor material. The concentration of impurities contained in the high-resistivity region is lower than the concentration of impurities contained in the first semiconductor region.

10. The semiconductor device of claim 9, wherein, The high-resistivity section contains at least one of silicon and silicon-germanium.

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