Array substrate and manufacturing method thereof

Abstract

The application relates to an array substrate and a manufacturing method thereof, and belongs to the technical field of display. The array substrate comprises a substrate, a gate electrode, a gate electrode insulation layer, an active layer and source and drain electrodes arranged on the active layer which are sequentially stacked along a first direction. The substrate is provided with a groove, the gate electrode is embedded in the groove, and the side surface of the gate electrode close to the gate electrode insulation layer is flush with the side surface of the substrate close to the gate electrode insulation layer. According to the array substrate, the gate electrode is completely embedded in the substrate, the width of the signal line can be increased according to requirements, the array substrate is flattened, the risk of various thin film line climbing faults in the subsequent film plating line manufacturing process is reduced, the process difficulty is reduced, and the product yield is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to an array substrate and a manufacturing method thereof. BACKGROUND

[0002] With the gradual maturity of liquid crystal display technology, people have higher requirements for liquid crystal display: high resolution, large size, high refresh rate, etc. Due to the existence of impedance in the internal metal signal line of the panel, the signal gradually attenuates from one end to the end, and with the increase of the panel size and refresh rate, the degree of attenuation is gradually amplified, causing a large difference in signal between the starting end and the end of the signal line, resulting in display difference of the panel.

[0003] To avoid this phenomenon, the most direct method is to reduce the impedance of the signal line. The methods of reducing the impedance of the signal line mainly include: increasing the width of the signal line, but this method increases the width of the signal line, resulting in a decrease in the effective display area and a decrease in the light transmission area, which will sacrifice the transmittance of the panel. At the same time, the increase in the line width will also increase the parasitic capacitance. Using low-impedance materials, the current mainstream uses Al, Cu and other materials, and the prices of Au, Ag and other metals with lower impedance are relatively high, and the processing technology is complex and impractical. Increasing the thickness of the signal line, the increase in the thickness of the film is limited, because the signal line is a metal thin film which is patterned by etching process, and the etching process has a serious side etching characteristic. The increase in the thickness of the film will increase the etching time, and the more serious the side etching, the thinner the line width. Finally, the cross section of the etched signal line is in a trapezoidal shape, and the thickness of the film will have a limited thickness, which cannot meet the demand. SUMMARY

[0004] The present application aims to at least solve the technical problems existing in the prior art. To this end, the present application provides an array substrate which can increase the thickness of the gate electrode according to the demand while facilitating the planarization of the array substrate and reducing the risk of various thin film line fault climbing in the subsequent film plating process.

[0005] The array substrate according to the embodiments of the present application comprises a substrate, a gate electrode, a gate insulating layer, an active layer and source and drain electrodes arranged on the active layer, which are stacked in sequence along a first direction. The substrate is provided with a groove, and the gate electrode is embedded in the groove. The side surface of the gate electrode close to the gate insulating layer is flush with the side surface of the substrate close to the gate insulating layer.

[0006] According to the array substrate of the embodiments of the present application, the active layer and the source electrode and the active layer and the drain electrode are both provided with an ohmic contact layer.

[0007] Optionally, the ohmic contact layer is provided with a receiving groove, and at least a part of the source electrode and at least a part of the drain electrode are respectively embedded in the corresponding receiving groove.

[0008] Optionally, the side surface of the source electrode away from the active layer is flush with the side surface of the corresponding ohmic contact layer away from the active layer, and the side surface of the drain electrode away from the active layer is flush with the side surface of the corresponding ohmic contact layer away from the active layer.

[0009] Optionally, the ohmic contact layer comprises a first layer and a second layer stacked in sequence, the first layer defines the bottom wall of the corresponding accommodation groove, and the second layer defines the side wall of the corresponding accommodation groove.

[0010] Optionally, the thickness of the first layer is and / or the thickness of the second layer is

[0011] According to the array substrate of the embodiment of the present application, the gate insulating layer comprises one of SiO2 or SiNX, and the thickness of the gate insulating layer is

[0012] According to the array substrate of the embodiment of the present application, the thickness of the active layer is

[0013] According to the manufacturing method of the array substrate of the embodiment of the present application, for the above-mentioned array substrate, the method comprises:

[0014] A substrate is provided, a photoresist layer is coated on the substrate, a groove is etched on the corresponding position of the substrate through a photoetching process, the substrate is cleaned and pre-baked;

[0015] The photoresist layer is patterned by a photolithography process;

[0016] A first metal layer is deposited on the photoresist layer, and the thickness of the first metal layer is the same as the depth of the groove;

[0017] The photoresist layer is cleaned by a stripping liquid, and the first metal layer deposited in the groove is obtained as a gate electrode;

[0018] A gate insulating film is deposited, and the gate insulating film is patterned as a gate insulating layer by a photolithography process;

[0019] A semiconductor film layer is deposited on the gate insulating layer, and the semiconductor film layer is patterned as an active layer by a photolithography process;

[0020] An ohmic contact layer is deposited on the active layer;

[0021] A second metal layer is deposited on the ohmic contact layer, and the second metal layer is patterned to obtain a source electrode and a drain electrode by a photolithography process.

[0022] Optionally, the deposition of the ohmic contact layer on the active layer comprises: depositing an ohmic contact layer on the active layer as a first layer; and depositing an ohmic contact layer on the first layer, and patterning the ohmic contact layer by a photolithography process to obtain a second layer.

[0023] According to the array substrate of the embodiment of the present application, the signal line width can be increased, i.e. the thickness of the gate electrode can be increased, by embedding the gate electrode completely in the substrate, which is beneficial to the planarization of the array substrate, reduces the risk of various thin film line climbing faults in the subsequent film plating process, reduces the process difficulty, and improves the product yield.

[0024] According to the manufacturing method of the array substrate of the embodiment of the present application, the gate electrode is completely embedded in the substrate, which reduces the risk of various thin film line climbing faults in the subsequent film plating process, and the process is simple, and the product yield is high. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0027] Figure 1 is a cross-sectional view of the array substrate according to the embodiment one of the present application;

[0028] Figure 2 is a cross-sectional view of the array substrate according to the embodiment two of the present application;

[0029] Figures 3-6 is a structure schematic diagram corresponding to the same process of the manufacturing method according to the embodiment one and the embodiment two of the present application;

[0030] Figures 7-9 is a structure schematic diagram corresponding to different processes of the manufacturing method according to the embodiment one of the present application;

[0031] Figures 10-13 is a structure schematic diagram corresponding to different processes of the manufacturing method according to the embodiment two of the present application;

[0032] Figure 14 is a flowchart of the manufacturing method according to some embodiments of the present application.

[0033] Reference signs:

[0034] array substrate 1,

[0035] Substrate 10, groove 11, gate 20, gate insulating layer 30, active layer 40, source electrode 50, drain electrode 60, ohmic contact layer 70, first layer 71, second layer 72, accommodating groove 722, insulating protective layer 80, via 81, pixel electrode 90,

[0036] Photoresist layer 1a, first metal layer 1b. DETAILED DESCRIPTION

[0037] To make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0038] As shown in Figure 1 The array substrate 101 according to the embodiments of the present application includes, in sequence along a first direction, a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, and a source electrode 50 and a drain electrode 60 disposed on the active layer 40. Among them, along the first direction, the source electrode 50 and the drain electrode 60 are disposed on the active layer 40 away from the side of the gate insulating layer 30.

[0039] Specifically, the substrate 10 is provided with a groove 11, and the gate 20 is embedded in the groove 11. The side surface of the gate 20 close to the gate insulating layer 30 is flush with the side surface of the substrate 10 close to the gate insulating layer 30. Generally, the thickness of the substrate 10 is much greater than the thickness of the signal line. Thus, embedding the gate 20 in the substrate 10 can facilitate the planarization of the array substrate 101 while increasing the thickness of the gate 20 as needed, reduce the risk of various thin film lines climbing faults in the subsequent film plating process, reduce the process difficulty, and improve the product yield.

[0040] It can be understood that "the side surface of the gate 20 close to the gate insulating layer 30 is flush with the side surface of the substrate 10 close to the gate insulating layer 30" means within the range of processing error tolerance.

[0041] Among them, the groove 11 can be any shape, for example, the groove 11 is a cylindrical groove, a rectangular groove, a trapezoidal groove, an elliptical cylindrical groove, etc. The shape of the gate 20 completely matches the shape of the groove 11, and the complete match here means within the range of processing error tolerance.

[0042] In addition, the substrate 10 comprises one of a glass substrate, a silicon wafer substrate, a transparent polyimide flexible plastic substrate, an epoxy resin substrate 10, etc. The gate electrode 20 comprises a metal or an alloy of multiple metals such as Cu, Al, Mo, etc. The main consideration is that the material for forming the gate electrode 20 needs to have good electrical conductivity, good adhesion and fixing performance with the substrate 10, and a simple patterning processing method, which can be selected according to actual needs.

[0043] Optionally, the gate insulating layer 30 comprises one of SiO2 or SiNX, and the thickness of the gate insulating layer 30 is 0.1-1.0 μm. For example, the thickness of the gate insulating layer 30 is 0.2-0.5 μm. and the like.

[0044] Optionally, the active layer 40 comprises one of amorphous silicon (a-Si), polycrystalline silicon (p-Si), metal oxide semiconductor material, etc., and the thickness of the active layer 40 is 0.01-0.1 μm. For example, the thickness of the active layer 40 is 0.01-0.05 μm. and the like.

[0045] As shown in FIG. 1, the thin film transistor further comprises an insulating protective layer 80 and a pixel electrode 90. In the first direction, the insulating protective layer 80 is located on the side of the source electrode 50 and the drain electrode 60 away from the active layer 40, and part of the insulating protective layer 80 extends to between the source electrode 50 and the drain electrode 60 and covers the active layer 40. The insulating protective layer 80 separates the oppositely arranged source electrode 50 and the drain electrode 60 to prevent short circuit. The pixel electrode 90 is located on the side of the insulating protective layer 80 away from the active layer 40. The insulating protective layer 80 is provided with a via hole 81, and the pixel electrode 90 extends into the via hole 81 and contacts the source electrode 50. In addition, the insulating layer also separates the source electrode 50 from other parts of the pixel electrode 90 except the part contacting the via hole 81, thereby protecting the pixel electrode 90. Figure 1

[0046] As shown in FIG. 1, the thin film transistor further comprises an insulating protective layer 80 and a pixel electrode 90. In the first direction, the insulating protective layer 80 is located on the side of the source electrode 50 and the drain electrode 60 away from the active layer 40, and part of the insulating protective layer 80 extends to between the source electrode 50 and the drain electrode 60 and covers the active layer 40. The insulating protective layer 80 separates the oppositely arranged source electrode 50 and the drain electrode 60 to prevent short circuit. The pixel electrode 90 is located on the side of the insulating protective layer 80 away from the active layer 40. The insulating protective layer 80 is provided with a via hole 81, and the pixel electrode 90 extends into the via hole 81 and contacts the source electrode 50. In addition, the insulating layer also separates the source electrode 50 from other parts of the pixel electrode 90 except the part contacting the via hole 81, thereby protecting the pixel electrode 90. Figure 1 Figure 2 As shown in FIG. 1, the thin film transistor further comprises an insulating protective layer 80 and a pixel electrode 90. In the first direction, the insulating protective layer 80 is located on the side of the source electrode 50 and the drain electrode 60 away from the active layer 40, and part of the insulating protective layer 80 extends to between the source electrode 50 and the drain electrode 60 and covers the active layer 40. The insulating protective layer 80 separates the oppositely arranged source electrode 50 and the drain electrode 60 to prevent short circuit. The pixel electrode 90 is located on the side of the insulating protective layer 80 away from the active layer 40. The insulating protective layer 80 is provided with a via hole 81, and the pixel electrode 90 extends into the via hole 81 and contacts the source electrode 50. In addition, the insulating layer also separates the source electrode 50 from other parts of the pixel electrode 90 except the part contacting the via hole 81, thereby protecting the pixel electrode 90.

[0047] As shown in FIG. 1, the thin film transistor further comprises an insulating protective layer 80 and a pixel electrode 90. In the first direction, the insulating protective layer 80 is located on the side of the source electrode 50 and the drain electrode 60 away from the active layer 40, and part of the insulating protective layer 80 extends to between the source electrode 50 and the drain electrode 60 and covers the active layer 40. The insulating protective layer 80 separates the oppositely arranged source electrode 50 and the drain electrode 60 to prevent short circuit. The pixel electrode 90 is located on the side of the insulating protective layer 80 away from the active layer 40. The insulating protective layer 80 is provided with a via hole 81, and the pixel electrode 90 extends into the via hole 81 and contacts the source electrode 50. In addition, the insulating layer also separates the source electrode 50 from other parts of the pixel electrode 90 except the part contacting the via hole 81, thereby protecting the pixel electrode 90. Figure 2 ​​​​As shown, optionally, the ohmic contact layer 70 is provided with receiving grooves 722, and at least a portion of the source electrode 50 and at least a portion of the drain electrode 60 are respectively embedded in the corresponding receiving grooves 722. This increases the thickness of the source electrode 50 and the drain electrode 60, and at the same time increases the contact area between the source electrode 50 and the corresponding ohmic contact layer 70, and between the drain electrode 60 and the corresponding ohmic contact layer 70, thereby ensuring good ohmic contact between the active layer 40 and the source electrode 50 and the drain electrode 60 respectively, reducing impedance, and facilitating current transmission. The thickness of the ohmic contact layer 70 can be adjusted according to the thickness of the source electrode 50 and the drain electrode 60.

[0048] In some embodiments, a portion of the source electrode 50 is embedded in a corresponding receiving groove 722, a portion of the drain electrode 60 is embedded in the receiving groove 722, the source electrode 50 extends beyond the thickness of the corresponding receiving groove 722 in a first direction, and the drain electrode 60 extends beyond the thickness of the corresponding receiving groove 722 in a first direction.

[0049] In other embodiments, such as Figure 2 As shown, the surface of the source electrode 50 furthest from the active layer 40 is flush with the surface of the corresponding ohmic contact layer 70 furthest from the active layer 40, and the surface of the drain electrode 60 furthest from the active layer 40 is flush with the surface of the corresponding ohmic contact layer 70 furthest from the active layer 40. That is to say, within the allowable range of processing errors, the source electrode 50 and the drain electrode 60 are completely embedded in their respective receiving grooves 722. Figure 2 As shown, the source electrode 50 is embedded in the receiving groove 722 on the right side, and the drain electrode 60 is embedded in the receiving groove 722 on the left side.

[0050] Optionally, such as Figure 2 As shown, the ohmic contact layer 70 includes a first layer 71 and a second layer 72 stacked sequentially. The first layer 71 defines the bottom wall of the corresponding receiving groove 722, and the second layer 72 defines the side wall of the corresponding receiving groove 722. Along the first direction, the surface of the first layer 71 near the active layer 40 is parallel to the surface of the first layer 71 away from the active layer 40, and the surface of the first layer 71 near the active layer 40 forms the bottom wall of the corresponding receiving groove 722. This simplifies the etching process of the receiving groove 722 and improves the product yield.

[0051] Optionally, the thickness of the first layer 71 is For example, the thickness of the first layer 71 is as well as wait.

[0052] Optionally, the thickness of the second layer 72 is For example, the thickness of the second layer 72 is as well as etc.

[0053] Embodiment One:

[0054] The manufacturing method of the array substrate 101 is used for the array substrate 101 described above, as shown in the following steps: Figure 14

[0055] Step S1: providing a substrate 10, coating a photoresist layer 1a on the substrate 10, and cleaning and pre-baking the substrate 10;

[0056] Step S2: patterning the photoresist layer 1a by using the photolithography process;

[0057] Step S3: depositing a first metal layer 1b on the photoresist layer 1a, and the thickness of the first metal layer 1b is the same as the depth of the groove 11 as shown in the following figure: Figure 3

[0058] Step S4: cleaning the photoresist layer 1a by using a stripping liquid, and obtaining the first metal layer 1b deposited in the groove 11 as the gate electrode 20 as shown in the following figure: Figure 4

[0059] Step S5: depositing a gate insulating film and patterning the gate insulating film as a gate insulating layer 30 by using the photolithography process as shown in the following figure: Figure 5

[0060] Step S6: depositing a semiconductor film layer on the gate insulating layer 30, and patterning the semiconductor film layer as an active layer 40 by using the photolithography process as shown in the following figure: Figure 6

[0061] Step S7: depositing an ohmic contact layer 70 on the active layer 40 as shown in the following figure: Figure 7

[0062] Step S8: depositing a second metal layer on the ohmic contact layer 70, and patterning the second metal layer to obtain a source electrode 50 and a drain electrode 60 by using the photolithography process as shown in the following figure: Figure 8

[0063] Step S9: depositing an insulating film layer by using the chemical vapor deposition process, and patterning the insulating film layer to obtain an insulating protective layer 80 by using the photolithography process (coating, exposure, development, etching, and stripping), and the insulating protective layer 80 includes SiO2 or SiNX, and the thickness is controlled as shown in the following figure: Figure 9

[0064] ​​​​​​​​​Step S10: depositing a layer of transparent conductive layer by physical vapor deposition process or chemical vapor deposition process, and then patterning the transparent conductive layer by coating photoresist layer, exposure, development, etching and other technologies to obtain transparent conductive pixel electrode 90. The pixel electrode 90 usually adopts ITO (transparent indium tin oxide).

[0065] Embodiment two:

[0066] Steps S1-S6 are the same as in embodiment one, which will not be repeated here. Step S7 includes: depositing an ohmic contact layer as a first layer 71 on the active layer 40, as shown in Figure 10 ; depositing an ohmic contact layer 70 on the first layer 71 by physical vapor deposition process (PVD) or chemical vapor deposition process (CVD), and obtaining a second layer 72 with island-shaped cross-section after patterning by photo-lithography process (coating, exposure, development, etching, stripping), as shown in Figure 11 . At this time, the schematic diagram of the structure obtained in the corresponding step S8 is as shown in Figure 12 , and the schematic diagram of the structure obtained in the corresponding step S9 is as shown in Figure 13 .

[0067] In step S1, taking the substrate 10 as a glass substrate 10 as an example, the photoresist can be patterned by photo-lithography process (coating, exposure, development) to protect the area which does not need to be etched to form the groove 11, and then the groove 11 is etched in the area which is not protected by the photoresist by hydrofluoric acid wet etching or dry etching by chlorine gas and oxygen.

[0068] In step S3, the first metal layer 1b is deposited by physical vapor deposition method, part of the first metal layer 1b is deposited on the photoresist, and part of the first metal layer 1b is deposited in the groove 11, and the first metal layer 1b deposited in the groove 11 serves as the gate 20 embedded in the groove 11.

[0069] In step S4, the photoresist layer is cleaned by stripping liquid, so as to clean the first metal layer 1b deposited on the photoresist layer, so as to realize the deposition of the first metal layer 1b only in the groove 11, without depositing the first metal layer 1b to other areas of the substrate 10.

[0070] In step S5, the gate insulating film is deposited by chemical vapor deposition, and then the gate insulating layer 30 is patterned by photo-lithography process (coating, exposure, development, etching, stripping).

[0071] In step S6, a semiconductor thin film layer is deposited on the gate insulating layer 30 by a physical vapor deposition process or a chemical vapor deposition process, and the semiconductor thin film layer is patterned as the active layer 40 by a photolithography process (gluing, exposure, development, etching, and glue removal). Generally, the semiconductor thin film layer material includes one of amorphous silicon (a-Si), polycrystalline silicon (p-Si), metal oxide semiconductor material, etc., wherein the semiconductor thin film layer is amorphous silicon (a-Si) or polycrystalline silicon (p-Si), and a chemical vapor deposition process (CVD) is generally used for deposition, and the semiconductor thin film layer is metal oxide semiconductor material, and a physical vapor deposition (PVD) is generally used for deposition.

[0072] The island-shaped second layer 72 is located at positions where the source electrode 50 and the drain electrode 60 are prepared on both sides of the channel, and the island-shaped second layer 72 is positioned to define a receiving groove 722 at the positions where the source electrode 50 and the drain electrode 60 are prepared, so that the etching preparation process of the receiving groove 722 can be simplified, and the product yield can be improved.

[0073] In step S8, a second metal layer is deposited by a physical vapor deposition process, and the second metal layer is patterned by a photolithography process (gluing, exposure, development, etching, and glue removal) to obtain the source electrode 50 and the drain electrode 60.

[0074] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", "inner", "outer", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0075] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, and it can be the communication between the two elements inside. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0076] In the description of the specification, reference to "one embodiment", "some embodiments", "an exemplary embodiment", "an example", "a specific example", or "some examples" means that a particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the application. The appearances of the phrases "in one embodiment", "in some embodiments", "in an exemplary embodiment", "an example", "a specific example", or "some examples" in various places in the specification are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics being described can be combined in any suitable manner in one or more embodiments or examples.

Claims

1. An array substrate, comprising a substrate, a gate, a gate insulating layer, an active layer, and a source electrode and a drain electrode disposed on the active layer, sequentially stacked along a first direction, characterized in that, The substrate has a groove, the gate is embedded in the groove, and the gate is directly formed by depositing a first metal layer with the same thickness as the groove depth. The side surface of the gate near the gate insulating layer is flush with the side surface of the substrate near the gate insulating layer. An ohmic contact layer is provided between the active layer and the source electrode, and between the active layer and the drain electrode; The ohmic contact layer is provided with receiving grooves, and at least a portion of the source electrode and at least a portion of the drain electrode are respectively embedded in the corresponding receiving grooves; The ohmic contact layer includes a first layer and a second layer that are stacked sequentially and formed by deposition, the first layer defining the bottom wall of the corresponding receiving groove and the second layer defining the side wall of the corresponding receiving groove.

2. The array substrate according to claim 1, characterized in that, The surface of the source electrode away from the active layer is flush with the surface of the corresponding ohmic contact layer away from the active layer, and the surface of the drain electrode away from the active layer is flush with the surface of the corresponding ohmic contact layer away from the active layer.

3. The array substrate according to claim 1, characterized in that, The ohmic contact layer includes a first layer and a second layer stacked sequentially, the first layer defining the bottom wall of the corresponding receiving groove, and the second layer defining the side wall of the corresponding receiving groove.

4. The array substrate according to claim 3, characterized in that, The thickness of the first layer is 100~500 Å, and / or the thickness of the second layer is 2000~6000 Å.

5. The array substrate according to claim 1, characterized in that, The gate insulating layer comprises either SiO2 or SiNX, and the thickness of the gate insulating layer is 2000~6000 Å.

6. The array substrate according to claim 1, characterized in that, The thickness of the active layer is 900~3000 Å.

7. A method for manufacturing an array substrate, used to manufacture the array substrate as described in any one of claims 1-6, characterized in that, include: A substrate is provided, a photoresist layer is coated on the substrate, grooves are etched at corresponding positions on the substrate through a photolithography process, and the substrate is cleaned and pre-baked. The photoresist is patterned using a photolithography process. A first metal layer is deposited on the photoresist layer, the thickness of the first metal layer being the same as the depth of the groove; The photoresist layer is cleaned by a stripping solution to obtain a first metal layer deposited in the groove as a gate. A gate insulating film is deposited and patterned as a gate insulating layer using a photolithography process. A semiconductor thin film layer is deposited on the gate insulating layer, and the semiconductor thin film layer is patterned as an active layer by photolithography. An ohmic contact layer is deposited on the active layer; Depositing an ohmic contact layer on the active layer includes: depositing an ohmic contact layer on the active layer as a first layer; and depositing an ohmic contact layer on the first layer and then patterning it using a photolithography process to form a second layer. A second metal layer is deposited on the ohmic contact layer, and the second metal layer is patterned by photolithography to obtain the source electrode and the drain electrode.

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