Epitaxial Structure, Its Preparation Method, and Semiconductor Device

Abstract

The present invention discloses an epitaxial structure, a preparation method thereof, and a semiconductor device. The epitaxial structure includes: a substrate; a buffer layer located on the substrate; an n-type nitride layer located on the buffer layer; a nitride light-emitting layer located on the n-type nitride layer; a low-temperature p-type nitride layer located on the nitride light-emitting layer, comprising a coherent growth process layer and at least one p-type nitride process layer, wherein the coherent growth process layer comprises a first coherent growth layer and a second coherent growth layer alternately stacked; a nitride electron blocking layer located on the low-temperature p-type nitride layer; and a p-type nitride layer located on the nitride electron blocking layer. Using the low-temperature p-type nitride layer with the above-described structure, the coherent growth process layer can adjust the lattice of the low-temperature p-type nitride layer so that its lattice better matches that of the nitride electron blocking layer, thereby reducing the generation of dislocation defects and reducing growth warping of the nitride electron blocking layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor light emitting technology, and in particular to an epitaxial structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] As a wide bandgap semiconductor material, AlGaN can achieve continuously adjustable bandgap width between 3.4eV and 6.2eV. It is widely used in structures such as carrier blocking layers, ultraviolet light-emitting layers and high electron gas heterojunctions, and has important application value in many fields.

[0003] Due to the lack of homogeneous substrates, AlGaN materials are typically grown epitaxially on heterogeneous substrates. Due to the significant differences in lattice constant and thermal expansion coefficient between the AlGaN and substrates, the epitaxial growth process generates numerous dislocations, warping of the epitaxial film, and even cracking. This can directly lead to leakage and other device failures in semiconductor devices. In nitride light-emitting diode (LED) epitaxial structures, the AlGaN electron blocking layer is often placed above the quantum well light-emitting layer. Especially for long-wavelength epitaxial structures such as those emitting blue and green light, the electron blocking layer is subject to greater tensile stress, which accumulates continuously during growth and is ultimately released through the formation of dislocation defects or cracks, seriously affecting the optoelectronic performance of the LED device. Summary of the Invention

[0004] The purpose of the present invention is to provide an epitaxial structure and its preparation method and semiconductor device, which are used to reduce the tensile stress of the nitride electron blocking layer during the growth process, reduce the generation of dislocation defects, reduce the growth warping of the electron blocking layer, improve the uniformity of the film, and avoid the generation of cracks.

[0005] The purpose of the present invention is achieved by the following technical solutions:

[0006] An epitaxial structure comprising:

[0007] substrate;

[0008] a buffer layer, located on the substrate;

[0009] an n-type nitride layer located on the buffer layer;

[0010] a nitride light-emitting layer, located on the n-type nitride layer;

[0011] A low-temperature p-type nitride layer is located on the nitride light-emitting layer, comprising a coherent growth process layer and at least one p-type nitride process layer, wherein the coherent growth process layer comprises a first coherent growth layer and a second coherent growth layer alternately stacked, wherein the first coherent growth layer is selected from MgN x layer, ZnN x layer, CdNx layer, HgN x layer, CaN x layer, TiN x At least one of the layers, the second coherent growth layer is selected from SiN y layer, GeN y at least one of the layers;

[0012] a nitride electron blocking layer, located on the low-temperature p-type nitride layer,

[0013] The p-type nitride layer is located on the nitride electron blocking layer.

[0014] In a specific embodiment, the single layer thickness of the first coherent growth layer is 0.5-1 nm, and the single layer thickness of the second coherent growth layer is 1-2 nm.

[0015] In a specific embodiment, the coherent growth process layer includes 2-10 first coherent growth layers and 2-10 second coherent growth layers;

[0016] The thickness of the p-type nitride process layer is 40-120 nm.

[0017] In a specific embodiment, the coherent growth process layer is located above or below the p-type nitride process layer, or between two p-type nitride process layers; when the coherent growth process layer is located below the p-type nitride process layer, the bottommost layer of the coherent growth process layer is the first coherent growth layer.

[0018] In a specific embodiment, the nitride electron blocking layer includes a 5-25 nm non-doped nitride electron blocking layer and a 15-55 nm p-type doped nitride layer along the growth direction, or includes a 20-80 nm non-doped nitride electron blocking layer.

[0019] In a specific embodiment, the buffer layer is a non-doped nitride layer and has a thickness of 1-3 μm; the thickness of the n-type nitride layer is 1-4 μm;

[0020] The nitride light-emitting layer comprises alternately stacked nitride quantum well layers and nitride quantum barrier layers, wherein the nitride light-emitting layer comprises 2-15 nitride quantum well layers and 2-15 nitride quantum barrier layers, the thickness of a single layer of the nitride quantum well layer is 1-6 nm, and the thickness of a single layer of the nitride quantum barrier layer is 6-15 nm;

[0021] The thickness of the nitride electron blocking layer is 20-100 nm;

[0022] The thickness of the p-type nitride layer is 60-150 nm.

[0023] A method for preparing an epitaxial structure, comprising:

[0024] Step S1: providing a substrate;

[0025] Step S2: growing a buffer layer on the substrate;

[0026] Step S3: growing an n-type nitride layer on the buffer layer;

[0027] Step S4: growing a nitride light-emitting layer on the n-type nitride layer;

[0028] Step S5: growing a low-temperature p-type nitride layer on the nitride light-emitting layer, wherein the low-temperature p-type nitride layer comprises a p-type nitride process layer and a coherent growth process layer, wherein the coherent growth process layer comprises a first coherent growth layer and a second coherent growth layer alternately stacked, wherein the first coherent growth layer is selected from MgN x layer, ZnN x layer, CdN x layer, HgN x layer, CaN x layer, TiN x At least one of the layers, the second coherent growth layer is selected from SiN y layer, GeN y at least one of the layers;

[0029] Step S6: growing a nitride electron blocking layer on the low-temperature p-type nitride layer;

[0030] Step S7: growing a p-type nitride layer on the nitride electron blocking layer.

[0031] In a specific embodiment, step S5 includes:

[0032] First, a p-type nitride process layer is grown on the nitride light-emitting layer, and then the coherent growth process layer is grown on the p-type nitride process layer; or,

[0033] First, the coherent growth process layer is grown on the nitride light-emitting layer, the bottom layer of the coherent growth process layer is a first coherent growth layer, and then the p-type nitride process layer is grown on the coherent growth process layer; or,

[0034] First, a p-type nitride process layer is grown on the nitride light emitting layer, then the coherent growth process layer is grown on the p-type nitride process layer, and finally, a p-type nitride process layer is grown on the coherent growth process layer.

[0035] In a specific embodiment, growing the coherent growth process layer includes: alternately growing 2-10 first coherent growth layers and 2-10 second coherent growth layers;

[0036] The thickness of the p-type nitride process layer is 40-120 nm.

[0037] In a specific embodiment, the single layer thickness of the first coherent growth layer is 0.5-1 nm, and the single layer thickness of the second coherent growth layer is 1-2 nm.

[0038] A semiconductor device comprises the epitaxial structure described in any one of the above items.

[0039] Compared with the prior art, the beneficial effects of the present invention include at least:

[0040] By arranging a low-temperature p-type nitride layer on the nitride light-emitting layer, which includes a coherent growth process layer and at least one p-type nitride process layer, the coherent growth process layer includes a first coherent growth layer and a second coherent growth layer that are alternately stacked. The coherent growth process layer can adjust the lattice of the low-temperature p-type nitride layer so that its lattice better matches the nitride electron blocking layer, reduce the tensile stress of the nitride electron blocking layer during the growth process, greatly reduce the generation of dislocation defects, reduce the growth warping of the nitride electron blocking layer, improve the uniformity of the film, and avoid the generation of cracks.

[0041] In addition, the coherent growth of the periodically alternately stacked first coherent growth layer and the second coherent growth layer can also roughen the surface of the p-type nitride layer, thereby improving the light extraction efficiency of the epitaxial structure.

[0042] Furthermore, the first coherent growth layer is MgN x layer, the second coherent growth layer is SiN y For example, when the first coherent growth layer of the coherent growth process layer is adjacent to the nitride light-emitting layer, the first MgN x During the growth process, Mg atoms diffuse toward the nitride light-emitting layer, which improves the injection efficiency of holes into the nitride light-emitting layer. x The SiN layer also plays a role in y The effect of blocking the diffusion of Si atoms into the nitride light-emitting layer during the layer growth process prevents the recombination of Si atoms with holes after injection, thereby improving the brightness of the epitaxial structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic structural diagram of an epitaxial structure according to an embodiment of the present invention.

[0044] Figure 2 It is a schematic structural diagram of an epitaxial structure according to another embodiment of the present invention.

[0045] Figure 3 It is a schematic structural diagram of an epitaxial structure according to another embodiment of the present invention.

[0046] Figure 4 It is a schematic flow chart of a method for preparing an epitaxial structure according to an embodiment of the present invention.

[0047] In the figure: 10, substrate; 20, buffer layer; 30, n-type nitride layer; 40, nitride light-emitting layer; 50, low-temperature p-type nitride layer; 51, p-type nitride process layer; 52, MgN x Layer; 53, SiN y layer; 60, a nitride electron blocking layer; 70, a p-type nitride layer. DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concepts of the example embodiments to those skilled in the art. Identical reference numerals in the drawings represent identical or similar structures, and thus repeated descriptions thereof will be omitted.

[0049] The words expressing positions and directions described in the present invention are all explained with reference to the accompanying drawings as examples, but can be modified as needed, and all such modifications are within the scope of protection of the present invention.

[0050] Reference Figure 1 The present invention provides an epitaxial structure, comprising a substrate 10, a buffer layer 20, an n-type nitride layer 30, a nitride light-emitting layer 40, a low-temperature p-type nitride layer 50, a nitride electron blocking layer 60 and a p-type nitride layer 70 stacked in sequence.

[0051] The substrate 10 may be a sapphire substrate 10 , and may also be formed of zinc oxide (ZnO), gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN), or the like.

[0052] A buffer layer 20 is located on the substrate 10, and an n-type nitride layer 30 is located on the buffer layer 20. The buffer layer 20 improves lattice matching and crystal quality with the substrate 10 before the n-type nitride layer 30 is grown on the substrate 10. The buffer layer 20 can be an undoped nitride layer, such as AlN or GaN. In one embodiment, the buffer layer 20 has a thickness of 1-3 μm.

[0053] The n-type nitride layer 30 , the nitride light emitting layer 40 and the p-type nitride layer 70 may be made of Al a In b Ga 1-a-bThe n-type nitride layer 30 may be formed of a GaN layer or a GaN / AlGaN layer doped with n-type conductive impurities, and the n-type conductive impurities may be Si, Ge, Sn, O, S, etc., with Si being the preferred n-type conductive impurity. The p-type nitride layer 70 may be formed of a GaN layer or a GaN / AlGaN layer doped with p-type conductive impurities, and the p-type conductive impurities may be Mg, Be, Zn, Cd, Hg, Ca, Ti, etc., with Mg being the preferred p-type conductive impurity. The nitride light-emitting layer 40 may be formed of an InGaN / GaN layer having a multi-quantum well structure. In a specific embodiment, the thickness of the n-type nitride layer 30 is 1-4 μm, and the thickness of the p-type nitride layer 70 is 60-150 nm; the nitride light-emitting layer 40 includes alternatingly stacked nitride quantum well layers and nitride quantum barrier layers, and the nitride light-emitting layer 40 includes 2-15 nitride quantum well layers and 2-15 nitride quantum barrier layers, the single layer thickness of the nitride quantum well layer is 1-6 nm, and the single layer thickness of the nitride quantum barrier layer is 6-15 nm.

[0054] The nitride electron blocking layer 60 can be used to prevent electrons, which have a relatively higher mobility than holes, from passing through the nitride light-emitting layer 40 and overflowing into the p-type nitride layer 70. By preventing the overflow of electrons, electron-hole recombination is increased, and the luminescence performance is improved. The electron blocking layer can be formed of a material with a higher band gap than the band gap of the nitride light-emitting layer 40, and can specifically be formed of materials such as AlGaN, GaN, and InGaN. The thickness of the nitride electron blocking layer 60 can be 20-80 nm. In one embodiment, the nitride electron blocking layer 60 includes a 5-25 nm undoped nitride electron blocking layer 60 and a 15-55 nm p-type doped nitride layer along the growth direction, or includes a 20-80 nm undoped nitride electron blocking layer 60.

[0055] The low temperature p-type nitride layer 50 is located on the nitride light emitting layer 40, and includes a coherent growth process layer and at least one p-type nitride process layer 51. The coherent growth process layer includes a first coherent growth layer and a second coherent growth layer alternately stacked. The first coherent growth layer is selected from MgN x Layer 52, ZnN x layer, CdN x layer, HgN x layer, CaN x layer, TiN x At least one of the layers, the second coherent growth layer is selected from SiN y Layer 53, GeN yAt least one of the layers. The material properties of the selected coherent growth layers in the first coherent growth layer are similar or close. x The material properties of the selected coherent growth layers in the second coherent growth layer are similar or close. y The detailed description is given by taking layer 53 as an example. It can be understood that the conclusions drawn are also applicable to the coherent growth layers of other materials due to the similar or close material properties.

[0056] The coherent growth process layer includes alternating layers of MgN x Layer 52 and SiN y Layer 53, 0≤x≤1, 0≤y≤1. The p-type nitride process layer 51 can be made of Al a In b Ga 1-a-b N (0≤a≤1, 0≤b≤1, 0≤1-ab≤1) semiconductor material is formed. x Layer 52 and SiN y The coherent growth process layer of layer 53 can adjust the lattice of the low-temperature p-type nitride layer 50 so that its lattice better matches the nitride electron blocking layer 60, reduce the tensile stress on the nitride electron blocking layer 60 during the growth process, greatly reduce the generation of dislocation defects, reduce the growth warping of the nitride electron blocking layer 60, improve the uniformity of the film, and avoid the generation of cracks.

[0057] In addition, the present invention uses periodically alternately stacked MgN x Layer 52 and SiN y The coherent growth of the layer 53 can also roughen the surface of the p-type nitride layer 70 , thereby improving the light extraction efficiency of the epitaxial structure.

[0058] Specifically, the coherent growth process layer can be located above or below the p-type nitride process layer 51, or between two p-type nitride process layers 51, thereby changing the insertion position of the coherent growth process layer. By changing the insertion position of the coherent growth process layer, the surface roughness of the p-type nitride layer can be adjusted. In addition, the periodically alternately stacked MgN x Layer 52 and SiN y The coherent growth structure of layer 53 does not affect the crystal quality of the p-type nitride layer, improves the optoelectronic performance of the epitaxial structure, and realizes the separation of the nitride surface roughening process from the crystal quality process control, thereby expanding the epitaxial growth process window for roughening the surface of the nitride epitaxial layer, thereby meeting different epitaxial technology requirements.

[0059] When the coherent growth process layer is located below the p-type nitride process layer 51, the bottom layer of the coherent growth process layer is MgNx Layer 52, at this time, the first MgN x During the growth of the layer 52, Mg atoms diffuse toward the nitride light emitting layer 40, which improves the injection efficiency of holes into the nitride light emitting layer 40. x Layer 52 also plays a role in the SiN y During the growth process of the layer 53 , the diffusion of Si atoms into the nitride light-emitting layer 40 is blocked, thereby preventing the Si atoms from being recombined with holes after being injected, and improving the brightness of the epitaxial structure.

[0060] In one embodiment, the MgN x The thickness of the single layer of layer 52 is 0.5-1 nm. y The thickness of the single layer of layer 53 is 1-2nm, and the thickness of MgN x Layer 52 and SiN y Layer 53 can better achieve coherent growth. The coherent growth process layer can include 2-10 MgN x Layer 52 and 2-10 SiN y Layer 53, each layer of MgN x The thickness of the layer 52 can be the same or different, and each layer of SiN y The thickness of layer 53 can be the same or different, and the thickness of the p-type nitride process layer 51 can be 40 to 120 nm. Using the above-mentioned number of layers and thickness of coherent growth process layers and p-type nitride process layer 51 can effectively reduce the tensile stress of the nitride electron blocking layer 60 during the growth process, and have the effect of roughening the surface of the p-type nitride layer 70.

[0061] The present invention further provides a semiconductor device comprising any one of the above-mentioned epitaxial structures, and the semiconductor device is, for example, an LED light-emitting device.

[0062] The present invention also provides a method for preparing an epitaxial structure, comprising steps S1 to S7. The preparation of the epitaxial structure can be completed by using MOCVD epitaxial growth equipment.

[0063] Step S1: providing a substrate 10.

[0064] The substrate 10 may be a sapphire substrate 10 , and may also be formed of zinc oxide (ZnO), gallium nitride (GaN), silicon carbide (SiC), aluminum nitride (AlN), or the like.

[0065] Step S2 : growing a buffer layer 20 on the substrate 10 .

[0066] Specifically, a non-doped nitride layer with a thickness of 1-3 μm is grown on the substrate 10 under the conditions of a temperature of 1100-1125° C. and a pressure of 100-300 Torr.

[0067] Step S3 : growing an n-type nitride layer 30 with a thickness of 1-4 μm on the buffer layer 20 .

[0068] Specifically, under the conditions of a temperature of 1090-1110° C. and a pressure of 100-300 Torr, an n-type nitride layer 30 with a thickness of 1-4 μm is grown on the buffer layer 20 .

[0069] Step S4 : growing a nitride light emitting layer 40 on the n-type nitride layer 30 .

[0070] Specifically, under a pressure of 200-400 torr, a nitride quantum well layer with a single layer thickness of 1-6 nm and a nitride quantum barrier layer with a thickness of 6-15 nm are alternately grown 2-15 times on the n-type nitride layer 30. The growth temperature of the nitride quantum well layer can be 700-900° C., and the growth temperature of the nitride quantum barrier layer can be 760-980° C.

[0071] Step S5: growing a low-temperature p-type nitride layer 50 on the nitride light-emitting layer 40, wherein the low-temperature p-type nitride layer 50 comprises a p-type nitride process layer 51 and a coherent growth process layer, wherein the coherent growth process layer comprises alternately stacked MgN x Layer 52 and SiN y Layer 53.

[0072] Specifically, under the temperature condition of 720-780°C and the pressure condition of 100-200 Torr, a p-type nitride process layer 51 with a thickness of 40-120 nm is grown. The growth of the coherent growth process layer may specifically include: alternately growing 2-10 MgN x Layer 52 and 2-10 SiN y Layer 53, the MgN x The thickness of the single layer of layer 52 is 0.5-1 nm. y The thickness of the single layer of layer 53 is 1-2 nm.

[0073] The coherent growth process layer may be located above or below the p-type nitride process layer 51 , or between two p-type nitride process layers 51 . Step S5 may specifically include:

[0074] First, a p-type nitride process layer 51 is grown on the nitride light emitting layer 40. The bottom layer of the coherent growth process layer is MgN x Layer 52, and then grow the coherent growth process layer on the p-type nitride process layer 51. Or,

[0075] First, the coherent growth process layer is grown on the nitride light emitting layer 40, and then the p-type nitride process layer 51 is grown on the coherent growth process layer. Alternatively,

[0076] First, a p-type nitride process layer 51 is grown on the nitride light emitting layer 40 , then the coherent growth process layer is grown on the p-type nitride process layer 51 , and finally, the p-type nitride process layer 51 is grown on the coherent growth process layer.

[0077] When the coherent growth process layer is located below the p-type nitride process layer 51, the bottom layer of the coherent growth process layer is MgN x Layer 52, at this time, the first MgN x During the growth of the layer 52, Mg atoms diffuse toward the nitride light emitting layer 40, which improves the injection efficiency of holes into the nitride light emitting layer 40. x Layer 52 also plays a role in the SiN y During the growth process of the layer 53 , the diffusion of Si atoms into the nitride light-emitting layer 40 is blocked, thereby preventing the Si atoms from being recombined with holes after being injected, and improving the brightness of the epitaxial structure.

[0078] Step S6 : growing a nitride electron blocking layer 60 on the low-temperature p-type nitride layer 50 .

[0079] Specifically, a nitride electron blocking layer 60 with a thickness of 20-100 nm is grown on the low-temperature p-type nitride layer 50 under the conditions of a temperature of 900-1050° C. and a pressure of 50-150 Torr.

[0080] Step S7 : growing a p-type nitride layer 70 on the nitride electron blocking layer 60 .

[0081] Specifically, a p-type nitride layer 70 with a thickness of 60-150 nm is grown on the nitride electron blocking layer 60 under the conditions of a temperature of 980-1100° C. and a pressure of 200-600 Torr.

[0082] Example 1:

[0083] Step S11: providing a sapphire substrate 10 .

[0084] Step S21: growing a 2 μm thick non-doped GaN layer on the substrate 10 at a temperature of 1115° C. and a pressure of 200 Torr.

[0085] Step S31: growing a 4 μm n-type GaN layer on the non-doped GaN layer at a temperature of 1105° C. and a pressure of 200 Torr.

[0086] Step S41: growing a nitride light-emitting layer 40 on the n-type GaN layer at a pressure of 400 Torr, including periodically growing 8 times of a 2.5 nm thick InGaN quantum well layer and a 12 nm thick GaN quantum barrier layer at growth temperatures of 760° C. and 880° C. respectively.

[0087] Step S51: Under the conditions of temperature of 725°C and pressure of 200 torr, a low-temperature p-type GaN process layer is grown on the nitride light-emitting layer 40, including growing a p-type GaN process layer on the nitride light-emitting layer 40, and then growing a coherent growth process layer on the p-type GaN process layer, wherein the thickness of the p-type GaN process layer is 80nm, and the coherent growth process layer is a MgN monolayer with a thickness of 0.8nm that is grown five times in a periodic cycle. x Layer 52 and a single layer of SiN with a thickness of 1.5 nm y Layer 53.

[0088] Step S61: growing an AlGaN electron blocking layer with a thickness of 40 nm on the low-temperature p-type GaN layer under the conditions of a temperature of 925° C. and a pressure of 100 Torr.

[0089] Step S71 : growing a p-type GaN layer 70 with a thickness of 120 nm on the AlGaN electron blocking layer under the conditions of a temperature of 980° C. and a pressure of 400 Torr.

[0090] Example 2

[0091] The preparation process of Example 2 is basically the same as that of Example 1, and the difference from Example 1 is: Step S51: growing a low-temperature p-type GaN process layer on the nitride light-emitting layer 40, including growing a 40nm low-temperature p-type GaN process layer on the nitride light-emitting layer 40, then growing a coherent growth process layer, and then growing a 40nm p-type GaN process layer. The rest is the same as Example 1.

[0092] Example 3

[0093] The preparation process of Example 3 is basically the same as that of Example 1, and the difference from Example 1 is that: Step S51: growing a low-temperature p-type GaN process layer on the nitride light-emitting layer 40, including growing a coherent process layer on the nitride light-emitting layer 40, and then growing a p-type GaN process layer on the coherent growth process layer, and the rest is the same as Example 1. Example 4

[0094] The preparation process of Example 4 is basically the same as that of Example 1, except that the thickness of the electron blocking layer is 20 nm.

[0095] Example 5

[0096] The preparation process of Example 5 is basically the same as that of Example 1, except that the thickness of the electron blocking layer is 100 nm.

[0097] Comparative Example 1

[0098] The preparation process of Comparative Example 1 is substantially the same as that of Example 1, and the only difference from Example 1 is that no coherent growth process layer is provided in step S51.

[0099] Comparative Example 2

[0100] The preparation process of Comparative Example 2 is substantially the same as that of Example 4, and the only difference from Example 4 is that no coherent growth process layer is provided in step S51.

[0101] Comparative Example 3

[0102] The preparation process of Comparative Example 3 is substantially the same as that of Example 5, and the only difference from Example 5 is that no coherent growth process layer is provided in step S51.

[0103] The surface roughness of the embodiments and comparative examples was tested by AFM, and the warpage was measured by online monitoring of warpage during the growth process. LED devices with the same specifications were prepared using the same device process for each embodiment and comparative example, and the voltage, brightness, and leakage performance were measured, as shown in Table 1 below:

[0104] Table 1

[0105] Example Surface roughness / nm <![CDATA[Yingqiao / km -1 > Voltage / V Brightness / mW Leakage yield / % Example 1 9.82 60 2.95 12.8 98 Example 2 7.45 61 2.95 12.4 99 Example 3 3.98 62 2.94 12.2 99 Example 4 8.84 50 2.93 13.1 96 Example 5 10.28 63 2.95 12.5 100 Comparative Example 1 1.02 78 2.96 11.4 95 Comparative Example 2 0.43 68 2.94 11.1 92 Comparative Example 3 1.58 84 2.97 11.9 96

[0106] From Table 1, it can be seen that the LED devices of Examples 1 to 5 have greater surface roughness, higher brightness and lower warpage, as well as lower leakage current. Therefore, in the epitaxial structure, by alternately stacking MgN x Layer 52 and SiN y The coherent growth of layer 53 can not only reduce the growth warping of the nitride electron blocking layer 60, but also roughen the surface of the p-type nitride layer 70, thereby improving the light extraction efficiency of the LED device containing the epitaxial structure and improving the leakage yield.

[0107] In addition, it can be seen from the above data that as the position of the coherent growth process layer changes, the epitaxial structure of the embodiment has a relatively large surface roughness and corresponds to high brightness performance, while the epitaxial structure with low surface roughness corresponds to relatively low brightness, but has relatively high leakage performance. Therefore, the specific application needs can select the corresponding process according to the actual performance requirements.

[0108] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limiting the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the invention without departing from the principles and purpose of the present invention. All such changes shall fall within the scope of protection of the claims of the present invention.

Claims

1. An epitaxial structure, characterized in that include: substrate; a buffer layer, located on the substrate; an n-type nitride layer located on the buffer layer; a nitride light-emitting layer, located on the n-type nitride layer; The low-temperature p-type nitride layer is located on the nitride light-emitting layer and includes a coherent growth process layer and at least one p-type nitride process layer. The coherent growth process layer includes a first coherent growth layer and a second coherent growth layer alternately stacked. The first coherent growth layer is MgN x layer, the second coherent growth layer is SiN y layer; a nitride electron blocking layer, located on the low-temperature p-type nitride layer, The p-type nitride layer is located on the nitride electron blocking layer.

2. The epitaxial structure according to claim 1, wherein: The thickness of a single layer of the first coherent growth layer is 0.5-1 nm, and the thickness of a single layer of the second coherent growth layer is 1-2 nm.

3. The epitaxial structure according to claim 2, wherein: The coherent growth process layer includes 2-10 first coherent growth layers and 2-10 second coherent growth layers; The thickness of the p-type nitride process layer is 40-120 nm.

4. The epitaxial structure according to claim 1, wherein: The coherent growth process layer is located above or below the p-type nitride process layer, or between two p-type nitride process layers; when the coherent growth process layer is located below the p-type nitride process layer, the bottom layer of the coherent growth process layer is the first coherent growth layer.

5. The epitaxial structure according to claim 1, wherein: The buffer layer is a non-doped nitride layer with a thickness of 1-3 μm; the thickness of the n-type nitride layer is 1-4 μm; The nitride light-emitting layer comprises alternately stacked nitride quantum well layers and nitride quantum barrier layers, wherein the nitride light-emitting layer comprises 2-15 nitride quantum well layers and 2-15 nitride quantum barrier layers, the thickness of a single layer of the nitride quantum well layer is 1-6 nm, and the thickness of a single layer of the nitride quantum barrier layer is 6-15 nm; The thickness of the nitride electron blocking layer is 20-100 nm; The thickness of the p-type nitride layer is 60-150 nm.

6. A method for preparing an epitaxial structure, characterized in that: include: Step S1: providing a substrate; Step S2: growing a buffer layer on the substrate; Step S3: growing an n-type nitride layer on the buffer layer; Step S4: growing a nitride light-emitting layer on the n-type nitride layer; Step S5: growing a low-temperature p-type nitride layer on the nitride light-emitting layer, wherein the low-temperature p-type nitride layer comprises a p-type nitride process layer and a coherent growth process layer, wherein the coherent growth process layer comprises a first coherent growth layer and a second coherent growth layer alternately stacked, wherein the first coherent growth layer is MgN x layer, the second coherent growth layer is SiN y layer; Step S6: growing a nitride electron blocking layer on the low-temperature p-type nitride layer; Step S7: growing a p-type nitride layer on the nitride electron blocking layer.

7. The method for preparing an epitaxial structure according to claim 6, wherein: The step S5 comprises: First, a p-type nitride process layer is grown on the nitride light-emitting layer, and then the coherent growth process layer is grown on the p-type nitride process layer; or, First, the coherent growth process layer is grown on the nitride light-emitting layer, the bottom layer of the coherent growth process layer is a first coherent growth layer, and then the p-type nitride process layer is grown on the coherent growth process layer; or, First, a p-type nitride process layer is grown on the nitride light emitting layer, then the coherent growth process layer is grown on the p-type nitride process layer, and finally, a p-type nitride process layer is grown on the coherent growth process layer.

8. The method for preparing an epitaxial structure according to claim 7, wherein: Growing the coherent growth process layer includes: alternately growing 2-10 first coherent growth layers and 2-10 second coherent growth layers; The thickness of the p-type nitride process layer is 40-120 nm.

9. The method for preparing an epitaxial structure according to claim 6, wherein: The thickness of a single layer of the first coherent growth layer is 0.5-1 nm, and the thickness of a single layer of the second coherent growth layer is 1-2 nm.

10. A semiconductor device, characterized in that: The epitaxial structure comprises the epitaxial structure according to any one of claims 1 to 5.

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