Wiring substrate, back sheet, and electronic device

Abstract

Embodiments of the present disclosure provide a wiring substrate, a back plate and an electronic device, and relate to the technical field of display. The wiring substrate comprises a substrate, a plurality of connection traces arranged on one side of the substrate, and a pad set. At least one of the plurality of connection traces arranged on one side of the substrate comprises a first connection end, and at least one other connection trace comprises a second connection end. The first connection end and the second connection end are arranged oppositely. The pad set is located in an area where the first connection end and the second connection end are located. The pad set comprises at least one first sub-pad and at least two second sub-pads. The at least one first sub-pad is located in an area where the first connection end is located, and the at least two second sub-pads are located in an area where the second connection end is located. The at least one first sub-pad and the at least two second sub-pads are arranged spaced apart from each other. The wiring substrate is used for displaying an image.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a wiring substrate, backplane, and electronic device. Background Technology

[0002] Mini light-emitting diodes (Mini LEDs) are approximately less than 500μm in size. Due to their smaller size, ultra-high brightness, and long lifespan, their use in the display field is increasing significantly. Summary of the Invention

[0003] The purpose of this disclosure is to provide a wiring substrate, a backplane, and an electronic device to accommodate various arrangements of electronic components on the wiring substrate.

[0004] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a wiring substrate is provided, comprising: a substrate, a plurality of connection traces disposed on one side of the substrate, and a pad group. The plurality of connection traces disposed on one side of the substrate include at least one connection trace including a first connection terminal and at least another connection trace including a second connection terminal, the first connection terminal and the second connection terminal being disposed opposite to each other. The pad group is located in the region where the first connection terminal and the second connection terminal are located, and the pad group includes at least one first sub-pad and at least two second sub-pads; at least one first sub-pad is located in the region where the first connection terminal is located, and at least two second sub-pads are located in the region where the second connection terminal is located, the at least one first sub-pad and the at least two second sub-pads being disposed at intervals.

[0006] At least two second sub-pads can provide more connection points and arrangement directions for electronic components, which can improve the flexibility of electronic component arrangement on the wiring board.

[0007] One of the first sub-pads is arranged adjacent to one of the at least two second sub-pads along a first direction, and the first sub-pad is arranged adjacent to the other of the at least two second sub-pads along a second direction; the first direction and the second direction intersect.

[0008] In some embodiments, each of the at least one first sub-pad is disposed adjacent to two of the at least two second sub-pads in a first direction and a second direction, respectively.

[0009] In some embodiments, a first sub-pad and a second sub-pad that are adjacent to each other in a first direction are separated by a first distance, and a first sub-pad and a second sub-pad that are adjacent to each other in a second direction are separated by a second distance, wherein the first distance is 0.9 to 1.1 times the second distance.

[0010] In some embodiments, the number of at least one first sub-pad is N, and the number of at least two second sub-pads is M, where N and M are positive integers, N≥1, and N=M-1.

[0011] In some embodiments, the substrate is a parallelogram, with a first direction parallel to the longer side of the substrate.

[0012] In some embodiments, the edges of the first connecting end and the second connecting end that are close to each other have the same shape.

[0013] In some embodiments, the edges of the first connecting end and the second connecting end that are close to each other have a stepped structure.

[0014] In some embodiments, any one of the at least one first sub-pads is not adjacent to any other first sub-pad in a first direction and / or a second direction.

[0015] In some embodiments, any one of the at least two second sub-pads is not adjacent to the other two second sub-pads in a first direction and / or a second direction.

[0016] In some embodiments, each of the multiple connection traces includes a main body portion. In two connection traces disposed opposite to a first connection end and a second connection end, the main body portion of one connection trace extends along a first direction, and the main body portion of the other connection trace extends along a second direction.

[0017] In some embodiments, a passivation layer is provided on the side of the plurality of pad groups away from the substrate, and a plurality of openings are provided on the passivation layer, wherein the orthographic projection of each of the plurality of openings on the substrate overlaps with the orthographic projection of a first sub-pad or a second sub-pad in the pad group on the substrate.

[0018] On the other hand, a backplane includes a wiring substrate as described in any of the above embodiments and a plurality of electronic components. The plurality of electronic components are disposed on one side of a pad group of the wiring substrate, and the electronic components are connected to at least one first sub-pad and one second sub-pad disposed adjacent to each other in the pad group along a first direction or a second direction.

[0019] The backplane described above has the same structure and advantages as the wiring substrate provided in some of the above embodiments, and will not be repeated here.

[0020] In some embodiments, the plurality of electronic components includes at least two electronic components, one of which is electrically connected to a first sub-pad and a second sub-pad disposed along a first direction in a pad group. The other electronic component is electrically connected to a first sub-pad and a second sub-pad disposed along a second direction in the pad group.

[0021] In some embodiments, the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the second direction in the pad group is greater than the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the first direction in the pad group.

[0022] In some embodiments, the plurality of pad groups include a passivation layer with a plurality of openings, and a plurality of electronic components are disposed on the side of the passivation layer away from the substrate, with the electrode of each electronic component electrically connected to the pad group through the opening. The backplane also includes a protective adhesive layer disposed on the side of the plurality of electronic components away from the wiring substrate. The protective adhesive layer fills the gaps between adjacent electronic components and the openings among the plurality of openings that are not covered by electronic components.

[0023] In another aspect, an electronic device includes a backplane as described in any of the above embodiments.

[0024] The electronic device described above has the same structure and advantages as the backplane provided in some of the above embodiments, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 A structural diagram of a display device provided for some embodiments of this disclosure;

[0027] Figure 2 A structural diagram of a backplate provided for some embodiments of this disclosure;

[0028] Figure 3 for Figure 2 Cross-sectional view along the AA direction;

[0029] Figure 4 An arrangement diagram of a wiring substrate on a master board provided for some embodiments of the present disclosure;

[0030] Figure 5 Another arrangement of the wiring substrate on the master plate provided for some embodiments of this disclosure;

[0031] Figure 6 A structural diagram of a wiring substrate provided for some embodiments of this disclosure;

[0032] Figure 7 for Figure 6 A magnified view of region C in the middle;

[0033] Figure 8 A structural diagram of a partial region of a circuit layer is provided for some embodiments of this disclosure;

[0034] Figure 9 Another structural diagram of a wiring substrate provided for some embodiments of this disclosure;

[0035] Figure 10 for Figure 9 A magnified view of region D in the middle;

[0036] Figure 11 Another structural diagram of a partial region of the circuit layer provided for some embodiments of this disclosure;

[0037] Figure 12 Another structural diagram of a partial region of the circuit layer provided for some embodiments of this disclosure;

[0038] Figure 13 A structural diagram of a first connecting end and a second connecting end is provided for some embodiments of this disclosure;

[0039] Figure 14 Another structural diagram of the first connection end and the second connection end provided for some embodiments of this disclosure;

[0040] Figure 15 Another structural diagram of a first connecting end and a second connecting end provided for some embodiments of this disclosure;

[0041] Figure 16 A structural diagram of another electronic device provided for some embodiments of this disclosure;

[0042] Figure 17 for Figure 16 Enlarged view of the chip region G;

[0043] Figure 18 A structural diagram of the connection wiring of a functional area provided for some embodiments of this disclosure;

[0044] Figure 19 Another structural diagram of the connection routing of the functional area provided for some embodiments of this disclosure;

[0045] Figure 20 Another structural diagram of a backplate provided for some embodiments of this disclosure;

[0046] Figure 21 for Figure 20 Cross-sectional view in the EE direction;

[0047] Figure 22 Another structural diagram of a backplate provided for some embodiments of this disclosure;

[0048] Figure 23 Another structural diagram of a backplate provided for some embodiments of this disclosure;

[0049] Figure 24 This is a structural diagram of another backplate provided for some embodiments of the present disclosure. Detailed Implementation

[0050] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0051] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, a particular feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0052] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0053] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0054] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0055] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0056] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0057] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0058] In addition, the use of "based on" implies openness and inclusivity, because processes, steps, calculations or other actions "based on" one or more conditions or values ​​can in practice be based on additional conditions or values ​​beyond those conditions.

[0059] As used herein, “about,” “approximately,” or “approximately” includes the value stated and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0060] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0061] Some embodiments of this disclosure provide an electronic device, which is an electronic device including a wiring substrate and a plurality of electronic components, wherein the electronic components are electrically connected to and fixed to the wiring substrate by soldering.

[0062] In some examples, the electronic device can be a display device employing a liquid crystal display, such as a television, laptop computer, tablet computer, mobile phone, personal digital assistant (PDA), navigator, wearable device, augmented reality (AR) device, virtual reality (VR) device, or any product or component with display functionality. For example, Figure 1 The electronic device 2000 shown is a mobile phone that uses a liquid crystal display 1000.

[0063] In some embodiments, the electronic device may include components such as a backplate and a housing fixed to the backplate. For example, Figure 2 As shown, the backplane 1100 includes a wiring substrate 100 and a plurality of electronic components 200 disposed on the wiring substrate 100.

[0064] like Figure 2 and Figure 3 As shown, where, Figure 3 yes Figure 2 Cross-sectional view along the AA direction. The backplane 1100 includes a wiring substrate 100 and electronic components 200 such as integrated circuit (IC) chips, capacitors, resistors, inductors, sensors, and miniature light-emitting diodes mounted on the wiring substrate 100.

[0065] In some embodiments, such as Figure 3As shown, the wiring substrate 100 includes a substrate 10, a wiring layer 20, and an insulating layer 30 stacked sequentially. The substrate 10 can be any of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, etc.; or a semiconductor substrate such as a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon-germanium, or an SOI (Silicon On Insulator) substrate. The substrate 10 may also include organic resin materials such as epoxy resin, triazine, silicone resin, or polyimide. In some examples, the substrate 10 can be an FR4 type printed circuit board (PCB), or a flexible PCB that is easily deformable. In some examples, the substrate 10 can include ceramic materials such as silicon nitride, AlN, or Al2O3, or a metal or metal compound, or any of a metal core printed circuit board (MCPCB) or a metal-copper clad laminate (MCCL). The circuit layer 20 includes traces for transmitting electrical signals. An opening 40 is provided on the insulating layer 30, at least exposing the end of a portion of the trace as a pad for bonding with the electronic component 200. The insulating layer 30 is used to isolate traces in the circuit layer 20 that do not have an electrical connection, and to protect the surface of the traces located away from the substrate 10.

[0066] In some examples, the wiring substrate 100 can be a quadrilateral structure, and multiple electronic components 200 are arrayed on the wiring substrate 100, wherein the electronic components 200 can be miniature light-emitting diodes. The wiring layer of the wiring substrate 100 includes multiple connection traces L, such as... Figure 8 As shown, any one of the multiple connecting traces L includes a main body 21 and a connecting end D. The main body 21 is used to ensure that the electrical performance of the connecting trace L, such as signal transmission speed and power consumption, meets the design requirements. The line width of the main body 21 is basically the same at all points. The connecting end D can be the end area of ​​the connecting trace L, and the line width is not greater than the line width of the main body.

[0067] Among the multiple connection traces L, there are two connection traces L that are close to each other, that is, the two connection traces L each include two connection terminals D that are close to each other. For example, at least one of the multiple connection traces L includes a first connection terminal D1, and at least another connection trace L includes a second connection terminal D2. The first connection terminal D1 and the second connection terminal D2 are close to each other, for example, they are arranged opposite each other.

[0068] Exemplarily, an opening 40 is provided on the insulating layer 30, the opening 40 exposing at least a portion of the end of the trace as a pad. The material of the insulating layer 30 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, in two adjacent connection traces L, one connection trace L includes a first connection terminal D1, and the other connection trace L includes a second connection terminal D2. A portion of the first connection terminal D1 is exposed by an opening 40 of the insulating layer 30 to form a first sub-pad 51, and a portion of the second connection terminal D2 is exposed by another opening 40 of the insulating layer 30 to form a second sub-pad 52. Accordingly, the orthographic projection of each of the plurality of openings 40 on the substrate 10 overlaps with the orthographic projection of a first sub-pad 51 or a second sub-pad 52 in the pad group 50 on the substrate 10. The first sub-pads 51 and second sub-pads 52 exposed by the adjacent first connection terminal D1 and second connection terminal D2 constitute a pad group 50.

[0069] In some embodiments, such as Figure 2 and Figure 3 As shown, the miniature light-emitting diode includes a first pin and a second pin, wherein the first pin is electrically connected to a first sub-pad 51 and the second pin is electrically connected to a second sub-pad 52.

[0070] In some embodiments, such as Figure 4 and Figure 5 As shown, a wiring substrate 100 to be connected to multiple micro light-emitting diodes is cut from a master substrate 300. Exemplarily, to reduce production costs and improve production efficiency, one implementation involves providing a master substrate, which may be a substrate made of glass, quartz, sapphire, ceramic, or a wafer made of silicon or silicon carbide, or a printed circuit board, flexible printed circuit board, or a substrate made of metal or metal compound. Material film deposition and patterning processes are performed on the master substrate, thereby forming a wiring pattern and an insulating layer covering the wiring pattern in each of the multiple regions to be cut to form multiple wiring substrates.

[0071] Next, the master panel 300 is cut into multiple wiring substrates 100. On each wiring substrate 100, a nickel-gold solder pad process, a white oil coating process, and an electronic component bonding process are performed. Then, the wiring substrates 100 with bonded electronic components are further cut and edge-ground to form a single panel. For example, such as... Figure 4 As shown, a master board 300 can be cut into 6 wiring substrates 100, and each wiring substrate 100 can be cut into 2 single panels, or, as... Figure 5As shown, the master board 300 can be cut into 8 wiring substrates 100, and each wiring substrate 100 can be cut into 1 single panel. The more single panels contained in each wiring substrate 100, the higher the efficiency and the lower the cost in subsequent processes.

[0072] like Figure 4 and Figure 5 As shown, to highlight the orientation and arrangement of each structure, only one pad group 50 is shown in the enlarged diagram. Pad group 50 includes a first sub-pad 51 and a second sub-pad 52 spaced apart from each other. Taking a miniature light-emitting diode (LED) as an example, the arrangement and orientation of the miniature LEDs on each single panel are the same. Since the miniature LEDs are formed by cutting the motherboard into a wiring substrate before die bonding, all pad groups 50 on a wiring substrate 100, including the first sub-pad 51 and the second sub-pad 52 with the same orientation, show the same arrangement and orientation of the miniature LEDs on the wiring substrate 100. Figure 4 and Figure 5 As shown, a first sub-pad 51 and a second sub-pad 52 in the pad group 50 are spaced apart from each other along the long side direction of the wiring substrate 100. The long side extension direction of the micro light-emitting diode to be connected to a pad group 50 is parallel to the long side direction of the wiring substrate 100 where the micro light-emitting diode is located.

[0073] In the process of die bonding the wiring substrate 100 using equipment, to improve efficiency, multiple micro LEDs are typically die bonded at once. For example, the equipment has a gantry, which can be used to die bond multiple micro LEDs arranged in a certain direction at a time. Therefore, when the wiring substrate 100 includes multiple micro LEDs arranged in an array, the gantry needs to be moved multiple times to die bond all the micro LEDs. However, displacement errors are inevitable during the displacement process. Increasing the number of displacements will reduce the die bonding accuracy of the micro LEDs, which is not conducive to improving product quality, and production efficiency will also decrease accordingly.

[0074] In comparison, during the die bonding process of miniature light-emitting diodes (LEDs) on the wiring substrate 100, the most efficient method is to align the arrangement of the two pins of the LEDs with the extension direction of the long side of the wiring substrate 100, and to use a support to bond multiple LEDs arranged in a direction parallel to the extension direction of the long side of the wiring substrate 100 each time (hereinafter referred to as the optimal die bonding direction T). Die bonding on the wiring substrate 100 along the optimal die bonding direction T has the advantages of high die bonding efficiency and high die bonding precision.

[0075] In some related technologies, such as Figure 4 The master 300 shown in the image and Figure 5 During the film preparation process, the master 300 shown can share a single mask to expose various areas. The arrangement of the wiring substrate 100 and the single panel needs to be determined according to the actual distribution of the traces and pads on the master.

[0076] It should be noted that, due to the shared mask, the arrangement direction of the first and second sub-pads in the pad group may not be consistent with the long side direction of the wiring substrate 100. In other words, the die bonding direction of the micro-LEDs during die bonding may differ from the optimal die bonding direction T. For example, the arrangement direction of the first sub-pad 51 and the second sub-pad 52 in the pad group may be parallel to the short side direction of the wiring substrate 100. In this case, each time the bracket is used to bond multiple micro-LEDs arranged in a direction parallel to the extension direction of the short side of the wiring substrate 100, the bracket needs to be relocated more times, resulting in decreased efficiency. At the same time, due to the accumulation of process errors, the yield rate may further decrease.

[0077] Based on this, some embodiments of the present disclosure provide a wiring substrate, which includes a substrate, a circuit layer and an insulating layer, wherein the arrangement structure of the substrate, the circuit layer and the insulating layer is described in detail in the above embodiments and will not be repeated here.

[0078] like Figure 6 , Figure 7 and Figure 8 As shown, where, Figure 7 for Figure 6 A magnified view of region C in the middle. Figure 8 This is a structural diagram of a portion of the circuit layer 20. The wiring substrate 100 also includes a pad group 50, which includes at least one first sub-pad 51 and at least two second sub-pads 52. The at least one first sub-pad 51 is located in the area where the first connection terminal D1 is located, and the at least two second sub-pads 52 are located in the area where the second connection terminal D2 is located. The at least one first sub-pad 51 and the at least two second sub-pads 52 are spaced apart from each other.

[0079] like Figure 7 and Figure 8 As shown, in a pad group 50, one of the first sub-pads 51 is arranged adjacent to one of the at least two second sub-pads 52 along a first direction X, and the first sub-pad 51 is arranged adjacent to the other of the at least two second sub-pads 52 along a second direction Y, wherein the first direction X intersects the second direction Y.

[0080] In some examples, a plurality of pad groups 50 are arrayed on the wiring substrate 100. Each pad group 50 may include at least one first sub-pad 51 and at least two second sub-pads 52. At least one first sub-pad 51 is located in the region where the first connection terminal D1 is located, i.e., the region where the insulating layer 30 covers the first connection terminal D1, and has at least one opening 40. The portion of the first connection terminal D1 exposed by each opening 40 is a first sub-pad 51. At least two second sub-pads 52 are located in the region where the second connection terminal D2 is located, i.e., the region where the insulating layer 30 covers the second connection terminal D2, and has at least two openings 40. The portion of the second connection terminal D2 exposed by each opening is a second sub-pad 52. Wherein, any one of the at least one first sub-pads 51 has one of the at least two second sub-pads 52 arranged in the first direction X, and the other of the at least two second sub-pads 52 arranged in the second direction Y.

[0081] It should be noted that, in this disclosure, "coverage" means that the orthographic projections of the two components on the substrate overlap, and the two components can be in direct contact or isolated from each other. For example, "coverage" in the insulating layer 30 covering the first connection terminal D1 means that the orthographic projection of the insulating layer 30 on the substrate overlaps with the orthographic projection of the first connection terminal D1 on the substrate.

[0082] The first sub-pad 51 and a second sub-pad 52 are arranged in a first direction X, and the first sub-pad 51 and the other second sub-pad 52 are arranged in a second direction Y. Therefore, an electronic component with two pins disposed on the wiring substrate can be electrically connected to either the first sub-pad 51 and the second sub-pad 52 arranged along the first direction X, or it can be electrically connected to the first sub-pad 51 and the second sub-pad 52 arranged along the second direction Y, thus allowing the electronic component to be disposed in either direction. The first direction X and the second direction Y intersect.

[0083] For example, such as Figure 8 As shown, a pad group 50 includes a first sub-pad 51 located in the region of the first connection terminal D1, and two second sub-pads 52 located in the region of the second connection terminal D2. The first sub-pad 51 and the second sub-pad 52 are arranged in the first direction X, and the first sub-pad 51 and the other second sub-pad 52 are arranged in the second direction Y.

[0084] Taking a miniature light-emitting diode (LED) as an example, an electronic component with two pins mounted on a wiring substrate, the first pin of the miniature LED is electrically connected to a first sub-pad 51, and the second pin is electrically connected to a second sub-pad 52. Thus, the miniature LED is arranged along a first direction X, meaning its die-bonding direction is the same as the first direction X. The second pin of the miniature LED is electrically connected to another second sub-pad 52, thus the miniature LED is arranged along a second direction Y, meaning its die-bonding direction is the same as the second direction Y. The first direction X and the second direction Y can be orthogonal.

[0085] In some embodiments, such as Figure 8 and Figure 11 As shown, each of the at least one first sub-pad 51 is arranged adjacent to two of the at least two second sub-pads 52 in the first direction X and the second direction Y, respectively.

[0086] For example, if a first sub-pad 51 or a second sub-pad 52 in a pad group 50 is damaged or detached, it cannot form an electrical connection with the corresponding electronic component. Therefore, a pad group 50 may also include two or more first sub-pads 51 and two or more second sub-pads 52. For example, each first sub-pad 51 is arranged adjacent to one second sub-pad 52 in a first direction X and adjacent to another second sub-pad 52 in a second direction Y. Figure 11 The pad group 50 shown includes two first sub-pads 51. The first first sub-pad 51' has a second sub-pad 52 arranged in both the first direction X and the second direction Y, and the second first sub-pad 51" has a second sub-pad 52 arranged in both the first direction X and the second direction Y.

[0087] In some embodiments, such as Figure 8 , Figure 11 and Figure 12 As shown, the number of at least one first sub-pad 51 is N, and the number of at least two second sub-pads 52 is M, where N and M are positive integers, and N ≥ 1. In some embodiments, N = M - 1.

[0088] In some examples, the number of at least one first sub-pad 51 in a pad group 50 can be 1, 2 or 3. Figure 8 The number of first sub-pads 51 shown is one, and there are two second sub-pads 52: a first second sub-pad 52' and a second second sub-pad 52'. The first sub-pad 51 and the second second sub-pad 52' are arranged in the first direction X, and the first sub-pad 51 and the first second sub-pad 52' are arranged in the second direction Y.

[0089] In other examples, such as Figure 11 As shown, when there are two first sub-pads 51, the two first sub-pads 51 are: the first first sub-pad 51' and the second first sub-pad 51". Correspondingly, there are three second sub-pads 52: the first second sub-pad 52', the second second sub-pad 52" and the third second sub-pad 52"'. The first first sub-pad 51' and the first second sub-pad 52' are arranged in the second direction Y, and the first first sub-pad 51' and the second second sub-pad 52" are arranged in the first direction X; the second first sub-pad 51" and the third second sub-pad 52"' are arranged in the first direction X, and the second first sub-pad 51" and the second second sub-pad 52" are arranged in the second direction Y.

[0090] In some other examples, such as Figure 12 As shown, when there are three first sub-pads 51, the three first sub-pads 51 are: the first first sub-pad 51', the second first sub-pad 51" and the third first sub-pad 51"'. Correspondingly, there are four second sub-pads 52: the first second sub-pad 52', the second second sub-pad 52"', the third second sub-pad 52"' and the fourth second sub-pad 52". Specifically, the first first sub-pad 51' and the first second sub-pad 52' are arranged in the second direction Y, and the first first sub-pad 51' and the second second sub-pad 52" are arranged in the first direction X; the second first sub-pad 51" and the third second sub-pad 52"' are arranged in the first direction X, and the second first sub-pad 51" and the second second sub-pad 52"' are arranged in the second direction Y; the third first sub-pad 51"' and the fourth second sub-pad 52"' are arranged in the first direction X, and the third first sub-pad 51"' and the third second sub-pad 52"' are arranged in the second direction Y.

[0091] In some embodiments, such as Figure 7 , Figure 9 and Figure 10 As shown, the first sub-pad 51 and the second sub-pad 52, which are adjacent to each other in the first direction X, are separated by a first distance X1. The first sub-pad 51 and the second sub-pad 52, which are adjacent to each other in the second direction Y, are separated by a second distance X2. The first distance X1 is 0.9 to 1.1 times the second distance X2. The first distance X1 refers to the closest distance in the first direction X between the edges of the first sub-pad 51 and the edges of the second sub-pad 52. The second distance X2 refers to the closest distance in the second direction Y between the edges of the first sub-pad 51 and the edges of the second sub-pad 52.

[0092] In some examples, the electrodes of electronic components are electrically connected to the first sub-pad 51 and the second sub-pad 52 in the first direction X, or to the first sub-pad 51 and the second sub-pad 52 in the second direction Y. When the first sub-pad 51 and the second sub-pad 52 in the first direction X and the first sub-pad 51 and the second sub-pad 52 in the second direction Y are connected to the same type of electronic component, and the distance between the electrodes of the electronic component remains stable, the first distance X1 and the second distance X2 should remain the same or substantially the same to ensure accurate connection between the electrodes and the corresponding pads when the arrangement direction of the same type of electronic component changes. In actual processes, the positions of the first sub-pad 51 and the second sub-pad 52 have a certain deviation, that is, the first distance X1 is 0.9 to 1.1 times the second distance X2. For example, the first distance X1 is 0.9 times the second distance X2, the first distance X1 is 1.0 times the second distance X2, or the first distance X1 is 1.1 times the second distance X2.

[0093] It should be noted that when there is a deviation of 0.9 to 1.1 times between the first distance X1 and the second distance X2, the electrodes of the electronic components set on the pad group 50 are electrically connected to the corresponding first sub-pad 51 and second sub-pad 52.

[0094] In some embodiments, such as Figure 13 , Figure 14 or Figure 15 As shown, the edges of the first connecting end D1 and the second connecting end D2 that are close to each other have the same shape.

[0095] In some examples, the edges of the first connecting end D1 and the second connecting end D2 that are close to each other have a stepped structure. Specifically, the edge of the first connecting end D1 close to the second connecting end D2 is a first edge 23, which includes at least one first sub-edge 231 arranged along a first direction X and at least one second sub-edge 232 arranged along a second direction Y. Furthermore, the at least one first sub-edge 231 and the at least one second sub-edge 232 are alternately arranged and sequentially connected.

[0096] The edge of the second connecting end D2 near the first connecting end D1 is the second edge 24. The second edge 24 includes at least one third sub-edge 241 arranged along the first direction X and at least one fourth sub-edge 242 arranged along the second direction Y. The at least one third sub-edge 241 and the at least one fourth sub-edge 242 are arranged alternately and connected sequentially.

[0097] In some embodiments, such as Figure 13 , Figure 14 or Figure 15 As shown, any one of the at least one first sub-pads 51 is not adjacent to any other first sub-pad 51 in the first direction X and / or the second direction Y.

[0098] For example, such as Figure 11 and Figure 14 As shown, the first connection terminal D1 includes two first sub-pads 51, and the first edge 23 includes two first sub-edges 231 and two second sub-edges 232. The two first sub-edges 231 and the two second sub-edges 232 are alternately arranged and connected to form a stepped structure. Each first sub-edge 231 and one second sub-edge 232 intersect to form a first corner region Ar1. That is, the two first sub-edges 231 and the two second sub-edges 232 form two first corner regions Ar1. The two first corner regions Ar1 are arranged along the third direction Z. Each first corner region Ar1 is provided with a first sub-pad 51. That is, the two first sub-pads 51 are arranged along the third direction Z. Therefore, one of the two first sub-pads 51 is not adjacent to the other first sub-pad 51 in the first direction X and / or the second direction Y. The third direction Z intersects with the first direction X and the second direction Y.

[0099] In some embodiments, any one of the at least two second sub-pads 52 is not adjacent to the other second sub-pads 52 in the first direction X and / or the second direction Y.

[0100] For example, such as Figure 11 and Figure 14 As shown, the first connection terminal D1 includes two first sub-pads 51, and correspondingly, the second connection terminal D2 includes three second sub-pads 52. The second edge 24 includes three third sub-edges 241 and three fourth sub-edges 242. The three third sub-edges 241 and three fourth sub-edges 242 are arranged alternately and connected sequentially to form a stepped structure. In this case, a second sub-pad 52 is provided on the second corner area Ar2 formed by the intersection of each third sub-edge 241 and the fourth sub-edge 242. That is, the three third sub-edges 241 and the three fourth sub-edges 242 form three second corner areas Ar2. The three second corner areas Ar2 are arranged along the third direction Z. Each second corner area Ar2 is provided with a second sub-pad 52. In other words, the three second sub-pads 52 are arranged along the third direction Z. Therefore, one of the three second sub-pads 52 is not adjacent to the other two second sub-pads 52 in the first direction X and / or the second direction Y.

[0101] The first sub-pad 51 and the second sub-pad 52 are arranged along a third direction Z, such that one second sub-pad 52 and one first sub-pad 51 are arranged in the first direction X, and simultaneously with another adjacent first sub-pad 51 in the second direction Y. In other words, one first sub-pad 51 and two second sub-pads 52 allow electronic components to be arranged in either the first direction X or the second direction Y. Two first sub-pads 51 and three second sub-pads 52 allow electronic components to be arranged in either the two first directions X or the two second directions Y. And so on; each additional first sub-pad 51 and second sub-pad 52 adds one more position for the electronic component to be arranged in the first direction X and one more position in the second direction Y. The arrangement of the first sub-pad 51 and the second sub-pad 52 can ensure that at least one sub-pad is shared in a pad group. Thus, with a fixed number of sub-pads, the number of first sub-pads 51 and second sub-pads 52 arranged in pairs in the first direction X or the second direction Y in the pad group can be increased as much as possible, which can reduce the complexity of the process and improve the flexibility of electronic components on the wiring substrate.

[0102] In some examples, such as Figure 23 As shown, a plurality of electronic components 200 are arranged on the wiring substrate 100 along a first direction X or a second direction Y, and the orientation of the plurality of electronic components 200 on the wiring substrate 100 is the same. If it is necessary to replace one of the electronic components 200, then in the pad group corresponding to the electronic component, the first sub-pad and / or second sub-pad electrically connected to the replaced electronic component 200 is different from the first sub-pad and / or second sub-pad electrically connected to the original electronic component 200. In a pad group, there are at least two first sub-pads and second sub-pads arranged in pairs in the first direction X or the second direction Y. Therefore, the orientation of the replaced electronic component can be the same as the orientation of the original electronic component, for example, as shown in the figure. Figure 12 As shown, the first pin of the electronic component before replacement can be electrically connected to the first first sub-pad 51', and the second pin can be electrically connected to the first second sub-pad 52'. The first pin of the replaced electronic component can be electrically connected to the second first sub-pad 51', and the second pin can be electrically connected to the second second sub-pad 52', so that the newly fixed electronic component is aligned with the orientation of the previous electronic component.

[0103] Understandably, the electronic components before replacement were arranged sequentially and equally spaced along rows or columns, while the replaced electronic components were slightly offset from the rows or columns where the original components were located. For example... Figure 23As shown, multiple electronic components 200B are arranged in a row along the second direction Y. Any one of the multiple electronic components 200B is replaced with an electronic component 200C. The orientation of the newly fixed electronic component 200C is the same as that of the electronic component 200B. The newly fixed electronic component 200C is located in a row formed by the multiple electronic components 200B, and its position is relatively staggered.

[0104] It should be noted that the orientation of electronic component 200C is the same as that of electronic component 200B, meaning that in the same type of electronic components, all electronic components are arranged along a fixed direction on a certain edge.

[0105] In some examples, the electronic components can be miniature light-emitting diodes (LEDs). Multiple arrays of miniature LEDs arranged on a wiring substrate can serve as the backlight of a liquid crystal display (LCD). The replacement miniature LEDs are positioned relatively offset from the column or row formed by the multiple miniature LEDs. The offset is small enough not to affect the normal display of the LCD image, so this offset arrangement is acceptable.

[0106] In some embodiments, such as Figure 13 , Figure 14 or Figure 15 As shown, each of the multiple connection traces L includes a main body 21. In two connection traces L disposed opposite to a first connection terminal D1 and a second connection terminal D2, the main body 21 of one connection trace L extends along the first direction X, and the main body of the other connection trace L extends along the second direction Y. It is understood that in some embodiments, the extension direction of the main body 21 of a connection trace L is different from that of the first connection terminal D1 and the second connection terminal D2 of the connection trace L.

[0107] In some embodiments, such as Figure 16 and Figure 18 , Figure 19 As shown, the wiring substrate 100 includes multiple arrayed functional areas H, chip areas G, and multiple signal lines, with one chip area G arranged on one side of each functional area H. Each functional area H includes at least one pad group, and each pad group can be electrically connected to an electronic component, such as... Figure 17 As shown, each chip region G includes multiple chip pads 53, which can be: a first chip pad 54, a second chip pad 55, a third chip pad 56, and a fourth chip pad 57. Each chip pad 53 in each chip region G is electrically connected to a driver chip, wherein several of the multiple driver chips disposed on the wiring substrate are cascaded. Multiple signal lines can be, for example, a first power supply voltage trace VLED, a second power supply voltage trace GND, a third power supply voltage signal line PWR, an address signal line Addr, and a feedback signal line FB.

[0108] Combination Figure 16 and Figure 17 As shown, each functional area H is electrically connected to the first power supply voltage trace VLED, and each functional area H is also electrically connected to the second chip pad 55 of the corresponding chip area G. Several of the multiple chip areas G located on the wiring substrate 100 are sequentially electrically connected, i.e., the second chip pad 55 of the previous chip area G is electrically connected to the first chip pad 54 of the next chip area G. Specifically, the first chip pad 54 of the first chip area G in the sequentially connected multiple chip areas G is electrically connected to the address signal line Addr, and the second chip pad 55 of the last chip area G is electrically connected to the feedback signal line FB. The third chip pad 56 of each chip area G is electrically connected to the third power supply voltage signal line PWR, and the fourth chip pad 57 of each chip area G is electrically connected to the second power supply voltage trace GND.

[0109] Specifically, the first power supply voltage trace VLED is configured to transmit a first-level signal to the functional area H, the second power supply voltage trace GND is configured to transmit a second-level signal to the chip area G, the third power supply voltage signal line PWR is configured to transmit a third-level signal to the chip area G, the addressing signal line Addr is configured to transmit an addressing signal, and the feedback signal line FB is configured to receive the feedback signal output by the chip area G and transmit it to the upper-level chip.

[0110] The first and third level signals can be high-level signals with different or the same voltage, and the second level signal can be a low-level signal. In this disclosure, a "high-level signal" refers to the potential of an electrical signal received or output at a node, terminal, or output terminal in the circuit; for example, a high-level signal can be 3.3V or 5V. A "low-level signal" refers to the potential of an electrical signal received or output at a node, terminal, or output terminal in the circuit; for example, a low-level signal can refer to a ground signal, specifically, a low-level signal can be 0V.

[0111] Multiple electronic components are disposed on a wiring substrate, wherein Q electronic components are connected in series, where Q is a positive integer greater than 1. In some embodiments, such as Figure 18The diagram illustrates a structural diagram of a functional area H. In a pad group 50, the first sub-pad 51 and the second sub-pad 52 are arranged in only one direction. For example, the first sub-pad 51 and the second sub-pad 52 are arranged only in the first direction X, or the first sub-pad 51 and the second sub-pad 52 are arranged only in the second direction Y. To satisfy the requirement that the arrangement direction of the Q series-connected electronic components is either the first direction X or the second direction Y, and that the Q electronic components are arranged in an array on the array substrate, the main body of each connection trace extends along the first direction X or along the second direction Y. For example, in two connection traces L with the first connection terminal D1 and the second connection terminal D2 opposite each other, the main body of one connection trace L is arranged along the first direction X, and the main body of the other connection trace L is arranged along the second direction Y; or, the main body of one connection trace L is arranged along the second direction Y, and the main body of the other connection trace L is arranged along the first direction X. Figure 18 In this configuration, each pad group 50 includes only one first sub-pad 51 and one second sub-pad 52, and the first sub-pad 51 and the second sub-pad 52 of each pad group 50 are arranged in the same direction, i.e. Figure 18 The wiring substrate shown retains only a single die-bonding direction, for example, the optimal die-bonding direction, which can match the best die-bonding efficiency in some cases (e.g., when the die-bonding direction does not need to be changed during the die-bonding process).

[0112] In other embodiments, such as Figure 19 Another structural diagram of functional area H is shown. In a pad group 50, there is a first sub-pad 51 and two second sub-pads 52. The first sub-pad 51 and one second sub-pad 52 are arranged in a first direction X, and the other second sub-pad 52 is arranged in a second direction Y. The electronic components corresponding to this pad group 50 can be arranged in either the first direction X or the second direction Y. The main body of the connection trace L extends along the first direction X or along the second direction Y. Specifically, in two connection traces L with the first connection terminal D1 and the second connection terminal D2 opposite to each other, the main body of one connection trace L is arranged along the first direction X, and the main body of the other connection trace L is arranged along the second direction Y; or, the main body of one connection trace L is arranged along the second direction Y, and the main body of the other connection trace L is arranged along the first direction X. In this scheme, a pad group 50 includes a first sub-pad 51 and two second sub-pads 52. By reserving sub-pads required for die bonding in another direction, the actual die bonding direction requirements can be taken into account, and the die bonding direction of electronic components can be changed to maximize the die bonding efficiency of electronic components in the actual die bonding process.

[0113] Changes in the number and arrangement of the first or second sub-pad in pad group 50 do not affect the extension direction of the main body of the two connecting traces L that are arranged opposite to the first connecting terminal D1 and the second connecting terminal D2.

[0114] For example, such as Figure 18 and Figure 19 As shown, in the wiring substrate, multiple connection traces L are divided into multiple groups, each group including N connection traces. The N connection traces are arranged sequentially, with the connection end of the previous connection trace facing the connection end of the next connection trace. For example, a group of connection traces includes 5 connection traces. One end of the first connection trace L1 is the first connection end, and one end of the second connection trace L2 is the second connection end. The first connection end of the first connection trace L1 and the second connection end of the second connection trace L2 are facing each other. The other end of the second connection trace L2 is the first connection end, and one end of the third connection trace L3 is the second connection end. The first connection end of the second connection trace L2 and the second connection end of the third connection trace L3 are facing each other, and so on. The other end of the fourth connection trace L4 is the second connection end, and one end of the fifth connection trace L5 is the first connection end. The first connection end of the fifth connection trace L5 and the second connection end of the fourth connection trace L4 are facing each other. It should be noted that the other end of the first connecting trace L1 is electrically connected to the first power supply voltage trace VLED, and the other end of the fifth connecting trace L5 is electrically connected to the chip area G.

[0115] In each pad group 50, the first sub-pad 51 is located in the area where the first connector D1 is located, and the second sub-pad 52 is located in the area where the second connector D2 is located. Each pad group 50 is located in the areas where the first connector and the second connector are located opposite each other on two connection traces L. Five connection traces correspond to four pad groups.

[0116] Figure 18 and Figure 19 In the four pad groups 50 shown, four electronic components corresponding to each pad group 50 are connected in series. In the four pad groups 50, the connection trace L of the first sub-pad 51 in the first pad group 50 is electrically connected to the first power supply voltage trace VLED and can form an integral structure; the connection trace L of the second sub-pad in the last pad group 50 is electrically connected to the intermediate trace LL between the chip areas G and can form an integral structure. Each pad group 50 is provided with one electronic component, so that Q electronic components are connected in series.

[0117] like Figure 19 As shown, the main body of each connecting trace extends generally along a first direction or a second direction, for example, with Figure 19Taking the illustrated third connecting trace L3 and fourth connecting trace L4 as examples, the first connecting end D1 of the third connecting trace L3 and the second connecting end D2 of the fourth connecting trace L4 are positioned opposite each other. The main body of the third connecting trace L3 is arranged generally along the first direction X (for example, it may have a bent portion), and the main body of the fourth connecting trace L4 is arranged generally along the second direction Y (for example, it may have a bent portion). Alternatively, Figure 19 Taking the second connecting trace L2 and the third connecting trace L3 as examples, the first connecting end D1 of the second connecting trace L2 and the second connecting end D2 of the third connecting trace L3 are arranged opposite each other. The main body of the second connecting trace L2 is arranged along the second direction Y, and the main body of the third connecting trace L3 is arranged approximately along the first direction X (for example, it may have a bent portion). That is, when the pad group 50 includes at least one first sub-pad and at least one second sub-pad, the extension direction of the main body of the connecting trace is relative to... Figure 18 The design of the first sub-pad 51 and the second sub-pad 52 being arranged in only one direction remains unchanged. This satisfies the requirement to change the arrangement direction of electronic components while reducing changes to the overall design of the wiring layer of the wiring substrate, thus minimizing the impact on the manufacturing process.

[0118] On the other hand, some embodiments of this disclosure also provide a backplate 1100, such as Figure 20 and Figure 21 As shown, where, Figure 21 for Figure 20 A cross-sectional view in the EE direction. The backplane 1100 includes a wiring substrate 100 as provided in any of the above embodiments and a plurality of electronic components. The plurality of electronic components are disposed on one side of the pad group of the wiring substrate 100, and the electronic components are connected to at least a first sub-pad and a second sub-pad disposed adjacent to each other in the pad group along the first direction X or the second direction Y.

[0119] In some examples, the backplane 1100 includes a wiring substrate and a plurality of electronic components disposed on the wiring substrate 1100. The wiring substrate 1100 includes a plurality of pad groups, each pad group including at least one first sub-pad and at least two second sub-pads disposed along a first direction X and a second direction Y. The electrode of each electrical component is electrically connected to a corresponding pad group through an opening in the wiring substrate 1100. That is, the electronic component can be electrically connected to either the first sub-pad or the second sub-pad disposed along the first direction X.

[0120] For example, the electronic component can be a miniature light-emitting diode, and a reflective layer 60 is also provided on the side of the insulating layer 30 away from the substrate. The reflective film 60 serves to reflect light. For example, the material of the reflective film 60 includes photosensitive white ink or thermosetting white ink.

[0121] The reflective layer 60 has an opening 70 that exposes at least a portion of the first sub-pad 51 and the second sub-pad 52. That is, the orthogonal projection of the reflective layer opening 70 onto the substrate 10 overlaps with the orthogonal projection of the opening 40 of the insulating layer 30 onto the substrate 10. For the first sub-pad 51 and the second sub-pad 52 that are not connected to the pins of electronic components, the corresponding opening 40 of the insulating layer 30 can be covered by the reflective layer 50 to prevent the exposed sub-pads from becoming entry points for water and oxygen to erode the wiring substrate.

[0122] For example, such as Figure 20 or Figure 22 As shown, electronic component 200 can be a miniature light-emitting diode (LED). Each miniature LED includes a first pin and a second pin, and each LED is electrically connected to a pad group. During the die bonding process, to reduce the number of die bond holder rotations and improve die bonding efficiency, the miniature LED is die bonded using the optimal die bonding orientation T. For example, Figure 22 The first pin of the micro LED shown is electrically connected to a first sub-pad of the pad group, and the second pin is electrically connected to a second sub-pad of the first sub-pad arranged in the first direction X. Accordingly, on the wiring substrate 100, a plurality of micro LEDs are arranged along the first direction X with their long sides extending in the same direction, i.e., the micro LEDs are die bonded in the optimal die bonding direction T.

[0123] In some embodiments, because a single mask may be shared, the arrangement direction of the first and second sub-pads on the wiring substrate may not be consistent with the optimal die-bonding direction T, and the die-bonding direction of the micro-LED may not be consistent with the optimal die-bonding direction T. For example Figure 22 The first pin of the miniature light-emitting diode shown is electrically connected to a first sub-pad of the pad group, and the second pin is electrically connected to a second sub-pad of the first sub-pad arranged in the second direction Y. Accordingly, on the wiring substrate, a plurality of miniature light-emitting diodes are arranged with their long sides extending in the second direction Y.

[0124] The second sub-pad, which is arranged in the second direction Y with the first sub-pad, can provide a second arrangement direction for electronic components, such as a micro light-emitting diode. This can take into account the actual die bonding direction requirements. In some processes that require changing the die bonding direction of the micro light-emitting diode, a suitable pad group can be selected to adapt to the actual die bonding direction and improve efficiency.

[0125] In some embodiments, such as Figure 23As shown, the plurality of electronic components includes at least two electronic components 200. One of the at least two electronic components 200, electronic component 200A, is electrically connected to a first sub-pad and a second sub-pad arranged along a first direction X in the pad group. Another electronic component 200B of the at least two electronic components 200 is electrically connected to a first sub-pad and a second sub-pad arranged along a second direction Y in the pad group.

[0126] In some examples, the wiring substrate 100 includes multiple pad groups, each pad group having an electronic component 200 disposed thereon. In a portion of the pad groups, the electrodes of the electronic component 200 are electrically connected to a first sub-pad and a second sub-pad arranged along a first direction X; in another portion of the pad groups, the electrodes of the electronic component 200 are electrically connected to a first sub-pad and a second sub-pad arranged along a second direction Y.

[0127] For example, the electronic component 200 can be a miniature light-emitting diode (LED). The miniature LED includes a first pin and a second pin, and each miniature LED is electrically connected to a pad group. For instance, in a plurality of miniature LEDs, the first pin of a first type of miniature LED is electrically connected to a first sub-pad of the pad group, and the second pin is electrically connected to a second sub-pad of the first sub-pad arranged in a first direction X. Accordingly, on the wiring substrate, the long sides of the first type of miniature LEDs are arranged along the first direction X. Similarly, in a plurality of miniature LEDs, the first pin of a second type of miniature LED is electrically connected to a first sub-pad of the pad group, and the second pin is electrically connected to a second sub-pad of the first sub-pad arranged in a second direction Y. Accordingly, on the wiring substrate, the long sides of the plurality of miniature LEDs are arranged along the second direction Y.

[0128] In some embodiments, such as Figure 23 As shown, among the multiple electronic components 200, the number of electronic components 200 electrically connected to the first sub-pad and the second sub-pad arranged along the second direction Y in the pad group is greater than the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the first direction X in the pad group.

[0129] In some examples, the electronic component 200 is a miniature light-emitting diode (LED). To reduce the number of die-bonding steps on the die-bonding support during the die-bonding process and improve die-bonding efficiency, the miniature LED is die-bonded using an optimal die-bonding orientation. That is, on the wiring substrate 100, the long side direction of the wiring substrate 100 is a first direction X, and the long side extension direction of the multiple miniature LEDs is consistent with the first direction; or, the long side direction of the wiring substrate 100 is a second direction Y, and the long side extension direction of the multiple miniature LEDs is consistent with the second direction Y.

[0130] If defects such as cold solder joints, short circuits, or misalignment occur between electronic components and sub-pads, lateral shearing force is required to remove the electronic components and re-securely reconnect them in the correct position. During component removal, the sub-pads may be damaged, preventing them from reliably connecting to the electronic components again. Using the embodiments provided in this disclosure, since a pad group includes multiple pairs of first and second sub-pads, when repositioning electronic components, different first and / or second sub-pads can be selected for die bonding. In some cases, the orientation of the repositioned electronic components may differ from the original orientation, for example, they may be perpendicular. It is understood that the number of electronic components exhibiting the aforementioned defects on the entire backplane is very low; therefore, the number of electronic components positioned along one orientation on the backplane should be significantly greater than the number positioned along another orientation.

[0131] That is, two or more first sub-pads and second sub-pads can be used as spare pads in the repair process when the electronic component has a die bonding failure, so as to facilitate reliable die bonding of the electronic component again and greatly improve the yield.

[0132] In some embodiments, such as Figure 24 As shown, the backplane 1100 also includes a protective adhesive layer 400, which is disposed on the side of the plurality of electronic components 200 away from the wiring substrate 100. The protective adhesive layer 400 covers the electronic components 200 to form a protective layer.

[0133] In some examples, a protective adhesive layer 400 is provided on the side of multiple electronic components 200 away from the substrate. The protective adhesive layer 400 can cover multiple electronic components 200 and fill the gaps between adjacent electronic components 200.

[0134] The protective adhesive layer 400 can protect the electronic component 200 and prevent water and oxygen from corroding the backplate 1100 from the pins of the electronic component 200.

[0135] For example, taking the electronic component 200 as a miniature light-emitting diode, the protective adhesive layer 400 can be a transparent protective adhesive. The transparent protective adhesive covers the miniature light-emitting diode on the wiring substrate 100 and can fill the gaps between the miniature light-emitting diodes.

[0136] Furthermore, some embodiments of this disclosure also provide an electronic device, which includes a backplane of any of the embodiments described above.

[0137] The electronic device provided in this embodiment uses the backplane provided in the above embodiment, and has the same function and advantages as the backplane described in the above embodiment, which will not be repeated here.

[0138] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A wiring substrate, characterized by, include: Substrate; Multiple connection traces are disposed on one side of the substrate, at least one of the multiple connection traces includes a first connection terminal, at least another connection trace includes a second connection terminal, and the first connection terminal and the second connection terminal are disposed opposite to each other; A pad group is located in the area where the first connection end and the second connection end are located. The pad group includes at least one first sub-pad and at least two second sub-pads. The at least one first sub-pad is located in the area where the first connection end is located, and the at least two second sub-pads are located in the area where the second connection end is located. The at least one first sub-pad and the at least two second sub-pads are arranged at intervals between each other. One of the at least one first sub-pads is adjacent to one of the at least two second sub-pads along a first direction, and the first sub-pad is adjacent to the other of the at least two second sub-pads along a second direction; the first direction intersects the second direction.

2. The wiring substrate according to claim 1, wherein Each of the at least one first sub-pads is arranged adjacent to two of the at least two second sub-pads in the first direction and the second direction, respectively.

3. The wiring substrate according to claim 1 or 2, wherein The first sub-pad and the second sub-pad, which are adjacent to each other in the first direction, are separated by a first distance, and the first sub-pad and the second sub-pad, which are adjacent to each other in the second direction, are separated by a second distance, wherein the first distance is 0.9 to 1.1 times the second distance.

4. The wiring substrate according to claim 3, wherein The number of the at least one first sub-pad is N, and the number of the at least two second sub-pads is M, where N and M are positive integers, N≥1, and N=M-1.

5. The wiring substrate according to claim 4, wherein The substrate is a parallelogram, and the first direction is parallel to the longer side of the substrate.

6. The wiring substrate according to claim 1, wherein The edges of the first connecting end and the second connecting end that are close to each other have the same shape.

7. The wiring substrate according to claim 6, wherein The edges of the first connecting end and the second connecting end that are close to each other have a stepped structure.

8. The wiring substrate according to claim 7, characterized in that, Any of the at least one first sub-pads is not adjacent to any other first sub-pad in the at least one first sub-pad in the first direction and / or the second direction.

9. The wiring substrate according to claim 8, wherein Any one of the at least two second sub-pads is not adjacent to any other second sub-pad in the first direction and / or the second direction.

10. The wiring substrate according to claim 9, wherein Each of the multiple connection traces includes a main body. In two connection traces that are disposed opposite to the first connection end and the second connection end, the main body of one connection trace extends along the first direction, and the main body of the other connection trace extends along the second direction.

11. The wiring substrate according to any one of claims 6 to 10, wherein A passivation layer is provided on the side of the pad group away from the substrate. The passivation layer has multiple openings. The orthographic projection of each of the multiple openings on the substrate overlaps with the orthographic projection of a first sub-pad or a second sub-pad in the pad group on the substrate.

12. A backsheet characterized by, The back plate includes: The wiring substrate as described in any one of claims 1 to 11 above. Multiple electronic components are disposed on one side of the pad group of the wiring substrate, and the electronic components are connected to at least one first sub-pad and one second sub-pad disposed adjacent to each other in the pad group along a first direction or a second direction.

13. The backsheet of claim 12, wherein, The plurality of electronic components includes at least two electronic components, one of which is electrically connected to the first sub-pad and the second sub-pad arranged along the first direction in the pad group; Another electronic component of the at least two electronic components is electrically connected to the first sub-pad and the second sub-pad arranged along the second direction in the pad group.

14. The backsheet of claim 13, wherein, The number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the second direction in the pad group is greater than the number of electronic components electrically connected to the first sub-pad and the second sub-pad arranged along the first direction in the pad group.

15. The backsheet of claim 14, wherein, The pad group includes a passivation layer with multiple openings. Multiple electronic components are disposed on the side of the passivation layer away from the substrate, and the electrode of each electronic component is electrically connected to the pad group through the openings. The backplate also includes a protective adhesive layer, which is disposed on the side of the plurality of electronic components away from the wiring substrate; The protective adhesive layer fills the gaps between adjacent electronic components, as well as the openings among the plurality of openings that are not covered by the electronic components.

16. An electronic device, characterized in that, Includes the backplate as described in any one of claims 12 to 15 above.

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