A super high voltage under-voltage lockout and over-voltage protection circuit and a switching power supply

Abstract

The present invention discloses an ultra-high voltage under-voltage lockout and over-voltage protection circuit, i.e., a switching power supply. The ultra-high voltage under-voltage lockout and over-voltage protection circuit has four ports, namely, the VDD port, the EN port, the OVP port, and the V LVDD port; the ultra-high voltage under-voltage lockout and over-voltage protection circuit includes: a voltage divider, a clamper, a reference voltage device, an under-voltage lockout device, an EN logic lockout device, and an over-voltage protection device. The ultra-high voltage under-voltage lockout and over-voltage protection circuit provided by the present invention can perform operations on the VDD port within an ultra-wide voltage range of 0 to 100V, enabling it to not only complete the under-voltage lockout of VDD power-on and power-off, the protection of the switching power supply system against VDD over-voltage, and provide a low-voltage power supply V LVDD for the internal circuit, but also remove the 40V clamper in the traditional switching power supply. Therefore, the switching power supply system of the present invention maximally saves customer costs and ensures the safety of customer equipment.

Description

Technical Field

[0001] The present invention relates to the technical field of fast - charging switching power supplies, and particularly to an ultra - high - voltage under - voltage lock - out and over - voltage protection circuit and a switching power supply. Background Art

[0002] As a power supply device for all electronic products, it is necessary to meet strict safety standards and also pursue lower costs. As a rising star in the field of switching power supplies, fast - charging switching power supplies have been widely popularized in recent years. Due to the pursuit of power diversity and output voltage diversity of fast - charging switching power supplies, the fast - charging standard has been rapidly upgraded. Currently, it has been upgraded to the PD3.0 standard, with the maximum power upgraded from 15W to 65 - 140W, and the output voltage upgraded from 5V - 15V to 3.3 - 20V. Therefore, the output voltage of the power - supply auxiliary winding of the switching - power - supply system transformer has been upgraded from the traditional 12 - 40V to an ultra - wide power - supply range of 12 - 75V. In order to still be compatible with traditional switching power supplies, a 40V clamper is added after the rectifier diode of the auxiliary winding to prevent the voltage of the VDD port from exceeding the rated breakdown voltage of 40V, which increases a great cost for users.

[0003] Traditional fast - charging switching power supplies, such as Figure 1 described, Figure 1 depict a traditional fast - charging switching power supply 10, whose working waveform is as shown in Figure 4 and Figure 6 . By sampling the output voltage Vo of the secondary side of the transformer TR to the FB - foot port of the power converter 11 through a feedback device 12 and sampling the current Ip in the primary - side coil of the transformer through the power transistor M1 and the current - limiting resistor Rcs to the CS - foot port of the power converter 11, a square - wave signal (Vsw) with variable pulse width is generated to control the on - off of the power transistor (M1) to complete the energy transfer of the transformer TR. The breakdown voltage of the VDD port of the traditional switching power supply 10 is only 40V. Therefore, a 40V clamper 13 is externally connected in series and then connected to the resistor R1, the rectifier diode D2, and the auxiliary winding La. The waveform of the start - up process of the traditional switching power supply 10 during normal operation is as shown in Figure 4 . Each time the VDD is powered on and exceeds VDDON, the power - on reset of EN is completed, and it enters the normal operation mode. As shown in Figure 6 , each time the VDD is over - voltage, the chip shuts down and enters the auto - restart mode. Since the traditional switching power supply 10 adds a 40V clamper 13, it not only increases the cost but also increases the power consumption. Therefore, it is necessary to adopt special technologies to avoid the above problems, so as to achieve the low - cost nature of user equipment. Summary of the Invention

[0004] Based on this, the object of the present invention is to provide an ultra - high - voltage under - voltage lock - out and over - voltage protection circuit and a switching power supply.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A super high voltage under-voltage lockout and over-voltage protection circuit, the super high voltage under-voltage lockout and over-voltage protection circuit having four ports, namely the VDD terminal, the EN terminal, the OVP terminal, and the V LVDD terminal; the super high voltage under-voltage lockout and over-voltage protection circuit includes: a voltage divider, a clamp, a reference voltage generator, an under-voltage lockout, an EN logic lock, and an over-voltage protector;

[0007] The first end of the voltage divider is respectively connected to the VDD terminal and the first end of the clamp, the second end of the voltage divider is connected to the first end of the under-voltage lockout, the third end of the voltage divider is connected to the first end of the over-voltage protector, and the fourth end of the voltage divider is grounded;

[0008] The second end of the clamp is respectively connected to the first end of the reference voltage generator and the V LVDD terminal, and the third end of the clamp is grounded;

[0009] The second end of the reference voltage generator is connected to the second end of the EN logic lock, the third end of the reference voltage generator is connected to the first end of the EN logic lock, the fourth end of the reference voltage generator is respectively connected to the third end of the under-voltage lockout and the second end of the over-voltage protector, the fifth end of the reference voltage generator is connected to the second end of the under-voltage lockout, and the sixth end of the reference voltage generator is grounded;

[0010] The fourth end of the under-voltage lockout is connected to the third end of the EN logic lock, and the fifth end of the under-voltage lockout is respectively connected to the EN terminal and the third end of the over-voltage protector;

[0011] The fourth end of the EN logic lock is grounded;

[0012] The fourth end of the over-voltage protector is connected to the OVP terminal.

[0013] Optionally, the voltage divider includes: a first resistor, a second resistor, and a third resistor; one end of the first resistor is the first end of the voltage divider, the other end of the first resistor is the second end of the voltage divider, the other end of the second resistor is the third end of the voltage divider, and the other end of the third resistor is the fourth end of the voltage divider;

[0014] One end of the first resistor is respectively connected to the VDD terminal and the first end of the clamper, and the other end of the first resistor is respectively connected to one end of the second resistor and the first end of the undervoltage lockout; one end of the second resistor is respectively connected to one end of the third resistor and the first end of the overvoltage protector; the other end of the third resistor is grounded.

[0015] Optionally, the clamper includes: a fourth resistor, a second clamping transistor, a third clamping transistor, a fourth clamping transistor, a fifth clamping transistor, and a first high-voltage transistor; one end of the fourth resistor is the first end of the clamper, the source of the first high-voltage transistor is the second end of the clamper, and the anode of the second clamping transistor is the third end of the clamper;

[0016] One end of the fourth resistor is respectively connected to one end of the first resistor and the drain of the first high-voltage transistor, and the other end of the fourth resistor is respectively connected to the gate of the first high-voltage transistor, the cathode of the fourth clamping transistor, and the cathode of the fifth clamping transistor; the anode of the fourth clamping transistor is connected to the cathode of the third clamping transistor, the anode of the third clamping transistor is connected to the cathode of the second clamping transistor, and the anode of the second clamping transistor is grounded; the anode of the fifth clamping transistor is connected to the source of the first high-voltage transistor, and the source of the first high-voltage transistor is also respectively connected to the first end of the reference voltage generator and the V LVDD terminal.

[0017] Optionally, the reference voltage generator includes: a fifth resistor, a first clamping transistor, a second high-voltage transistor, and a bandgap reference; one end of the fifth resistor is the first end of the reference voltage generator, the source of the second high-voltage transistor is the second end of the reference voltage generator, the second end of the bandgap reference is the third end of the reference voltage generator, the third end of the bandgap reference is the fourth end of the reference voltage generator, the fourth end of the bandgap reference is the fifth end of the reference voltage generator, and the fifth end of the bandgap reference is the sixth end of the reference voltage generator;

[0018] One end of the fifth resistor is respectively connected to the source of the first high-voltage transistor, the V LVDD terminal, and the drain of the second high-voltage transistor, and the other end of the fifth resistor is respectively connected to the cathode of the first clamping transistor and the gate of the second high-voltage transistor, and the anode of the first clamping transistor is grounded; the source of the second high-voltage transistor is respectively connected to the second end of the EN logic lock and the first end of the bandgap reference; the second end of the bandgap reference is connected to the first end of the EN logic lock, the third end of the bandgap reference is respectively connected to the third end of the undervoltage lockout and the second end of the overvoltage protector, the fourth end of the bandgap reference is connected to the second end of the undervoltage lockout, and the fifth end of the bandgap reference is grounded.

[0019] Optionally, the under-voltage lockout includes a first low-voltage transistor, a second low-voltage transistor, a first comparator, a first inverter, and a second inverter; the non-inverting input terminal of the first comparator is the first terminal of the under-voltage lockout, the drain of the first low-voltage transistor is the second terminal of the under-voltage lockout, the drain of the second low-voltage transistor is the third terminal of the under-voltage lockout, the output terminal of the first comparator is the fourth terminal of the under-voltage lockout, and the output terminal of the second inverter is the fifth terminal of the under-voltage lockout;

[0020] The non-inverting input terminal of the first comparator is connected to the other end of the first resistor, the inverting input terminal of the first comparator is respectively connected to the source of the first low-voltage transistor and the source of the second low-voltage transistor, the output terminal of the first comparator is respectively connected to the input terminal of the first inverter, the gate of the first low-voltage transistor, and the third terminal of the EN logic lockout; the drain of the first low-voltage transistor is connected to the fourth terminal of the bandgap reference, the drain of the second low-voltage transistor is connected to the third terminal of the bandgap reference, and the gate of the second low-voltage transistor is respectively connected to the output terminal of the first inverter and the input terminal of the second inverter; the output terminal of the second inverter is respectively connected to the EN terminal and the third terminal of the over-voltage protector.

[0021] Optionally, the EN logic lockout includes a third low-voltage transistor, a fourth low-voltage transistor, a capacitor, and a sixth resistor; the gate of the third low-voltage transistor is the first terminal of the EN logic lockout, one end of the sixth resistor is the second terminal of the EN logic lockout, the drain of the fourth low-voltage transistor is the third terminal of the EN logic lockout, and the source of the third low-voltage transistor is the fourth terminal of the EN logic lockout;

[0022] The drain of the third low-voltage transistor is respectively connected to the other end of the sixth resistor, one end of the capacitor, and the gate of the fourth low-voltage transistor, the gate of the third low-voltage transistor is connected to the second terminal of the bandgap reference, and the source of the third low-voltage transistor is grounded; one end of the sixth resistor is connected to the source of the second high-voltage transistor; the drain of the fourth low-voltage transistor is connected to the output terminal of the first comparator, and the source of the fourth low-voltage transistor is grounded; the other end of the capacitor is grounded.

[0023] Optionally, the over-voltage protector includes a second comparator and a timer; the non-inverting input terminal of the second comparator is the first terminal of the over-voltage protector, the inverting input terminal of the second comparator is the second terminal of the over-voltage protector, the third terminal of the timer is the third terminal of the over-voltage protector, and the second terminal of the timer is the fourth terminal of the over-voltage protector;

[0024] The non-inverting input terminal of the second comparator is connected to the other end of the second resistor, the inverting input terminal of the second comparator is connected to the third terminal of the bandgap reference, the output terminal of the second comparator is connected to the first terminal of the timer, the second terminal of the timer is connected to the OVP terminal, and the third terminal of the timer is connected to the output terminal of the second inverter.

[0025] The present invention also provides a switching power supply, comprising: a transformer, a switching power supply controller integrated circuit, a power switch transistor, and a feedback device. The switching power supply controller integrated circuit includes: the above-mentioned ultra-high voltage under-voltage lockout and over-voltage protection circuit, a pulse width modulator, and a driving circuit; the VDD terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is connected to the power supply port of the switching power supply controller integrated circuit, the EN terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is respectively connected to the second terminal of the driving circuit and the fourth terminal of the pulse width modulator, the OVP terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is connected to the third terminal of the driving circuit, and the V LVDD terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is respectively connected to the third terminal of the pulse width modulator and the fourth terminal of the driving circuit; the first terminal of the pulse width modulator is connected to the CS terminal of the switching power supply controller integrated circuit, the second terminal of the pulse width modulator is connected to the FB terminal of the switching power supply controller integrated circuit, and the fifth terminal of the pulse width modulator is connected to the first terminal of the driving circuit; the fifth terminal of the driving circuit is connected to the DRV terminal of the switching power supply controller integrated circuit.

[0026] The present invention also provides a switching power supply, comprising: a transformer, a switching power supply controller integrated circuit, a power switch transistor, and a feedback device. The switching power supply controller integrated circuit includes: the above-mentioned ultra-high voltage under-voltage lockout and over-voltage protection circuit, a pulse width modulator, a driving circuit, and a high-voltage start-up circuit; the VDD terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is respectively connected to the power supply port of the switching power supply controller integrated circuit and the second terminal of the high-voltage start-up circuit, the EN terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is respectively connected to the second terminal of the driving circuit, the fourth terminal of the pulse width modulator, and the third terminal of the high-voltage start-up circuit, the OVP terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is connected to the third terminal of the driving circuit, and the V LVDDOne end is respectively connected to the third end of the pulse width modulator and the fourth end of the drive circuit; the first end of the pulse width modulator is connected to the CS end of the switching power supply controller integrated circuit, the second end of the pulse width modulator is connected to the FB end of the switching power supply controller integrated circuit, and the fifth end of the pulse width modulator is connected to the first end of the drive circuit; the fifth end of the drive circuit is connected to the DRV end of the switching power supply controller integrated circuit; the first end of the high-voltage startup circuit is connected to the HV end of the switching power supply controller integrated circuit.

[0027] According to the specific embodiments provided by the present invention, the following technical effects are disclosed:

[0028] (1) Through the control of other modules in the switching power supply controller integrated circuit by the ultra-high voltage undervoltage lockout and overvoltage protection circuit, the switching power supply provided by the present invention can have lower cost and higher safety.

[0029] (2) The switching power supply provided by the present invention can achieve undervoltage lockout of the VDD pin of the traditional switching power supply, overvoltage protection and the function of supplying low voltage power inside the chip without relying on an external 40V clamp, greatly reducing the cost of customers. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0031] Figure 1 is a circuit schematic diagram of a traditional switching power supply;

[0032] Figure 2 is a circuit schematic diagram of the switching power supply provided by the present invention;

[0033] Figure 3 is a schematic diagram of the ultra-high voltage undervoltage lockout and overvoltage protection circuit provided by the present invention;

[0034] Figure 4 is the timing waveform of the normal power-on operation of the VDD of a traditional switching power supply;

[0035] Figure 5 is the timing waveform of the normal power-on operation of the VDD of the switching power supply provided by the present invention;

[0036] Figure 6 is the timing waveform of the overvoltage protection operation of the VDD of a traditional switching power supply

[0037] Figure 7The working timing waveform of the VDD overvoltage protection provided by the present invention for the switching power supply

[0038] The symbols shown in the figure are explained as follows:

[0039] 10: Conventional switching power supply, applied in the PD3.0 fast charger

[0040] 10A: The switching power supply of the present invention, applied in the PD3.0 fast charger

[0041] 11: Conventional switching power supply controller integrated circuit

[0042] 11A: The switching power supply controller integrated circuit of the present invention

[0043] 12: Feedback device, i.e., FeedBack

[0044] 13: 40V clamper

[0045] 20: High-voltage startup circuit, i.e., HVStartup

[0046] 30: Pulse width modulator, i.e., PWM

[0047] 40: Driver circuit, i.e., DRIVER

[0048] 50: Ultra-high voltage undervoltage lockout and overvoltage protection circuit inside the switching power supply controller integrated circuit 11, i.e., UVLOVP

[0049] 50A: Ultra-high voltage undervoltage lockout and overvoltage protection circuit inside the switching power supply controller integrated circuit 11A, i.e., SuperUVLOVP

[0050] 60A: Normal working timing waveform diagram of the conventional switching power supply

[0051] 60B: Normal working timing waveform diagram of the switching power supply of the present invention

[0052] 70A: Timing waveform diagram of the VDD overvoltage protection of the conventional switching power supply

[0053] 70B: Timing waveform diagram of the VDD overvoltage protection of the switching power supply of the present invention

[0054] M1: External power switch tube

[0055] M51: First high-voltage tube (with a breakdown voltage of 100V)

[0056] M52: Second high-voltage tube

[0057] M53: First low-voltage tube

[0058] M54: Second low-voltage tube

[0059] M55: The third low-voltage pipe

[0060] M56: The fourth low-voltage pipe

[0061] TR: Transformer

[0062] Lp: The primary coil of TR

[0063] Ls: The secondary coil of TR

[0064] La: The auxiliary coil of TR, responsible for supplying power to the capacitor CVDD at the VDD port

[0065] VDD: Power supply port

[0066] FB: Feedback port

[0067] CS: Current monitoring port

[0068] DRV: Drive output port

[0069] GND: Ground port

[0070] VAC: AC input voltage

[0071] Vo: The DC output voltage of the switching power supply 10

[0072] Ip: The current in the primary coil Lp of the transformer TR

[0073] D1: The full-wave rectifier diode for AC input

[0074] D2, D3: Diodes

[0075] Rst: The starting resistor of the switching power supply systems 10, 10A

[0076] R1, Rx, Rcs, R51 (resistor with 100V withstand voltage), R52, R53, R54 (resistor with 100V withstand voltage), R55, R56: Resistors

[0077] C1, Cx, C VDD 、C2, C51: Capacitors

[0078] Z1, Z2, Z3, Z4, Z5: Zero-temperature-drift clamping diodes with a clamping voltage of VZ

[0079] 51: Voltage divider, which accurately divides the ultra-high voltage VDD and then inputs it to other modules for input voltage detection

[0080] 52: Clamper, which performs step-down clamping on the ultra-high voltage VDD so that it is more suitable for use by IC devices

[0081] 53: Reference voltage transformer, outputting a bias voltage VB3 and three reference voltage thresholds vref1, vref2, vref3

[0082] 54: Undervoltage lockout, used to complete the VDD power-on and power-off enable control actions

[0083] 55: EN logic locker, used to lock the EN logic before the reference voltage vref3 is established

[0084] 56: Overvoltage protector, used to determine whether VDD is overvoltage. If VDD is overvoltage, it shuts down the DRIVER for protection

[0085] 61: Bandgap reference, generating the reference voltage thresholds vref1, vref2, vref3

[0086] 62: First comparator

[0087] 65: Second comparator

[0088] 63: First inverter

[0089] 64: Second inverter

[0090] Vsw: Switching signal, i.e., the pulse-width voltage signal driving the gate of the power transistor M1

[0091] V FB : Feedback voltage

[0092] V CS : Current-limiting voltage of the CS port, source voltage of M1, equal to the product of the current Ip in Lp and Rcs, with the same frequency as Vsw

[0093] VDD: Power supply voltage at the VDD port

[0094] V PWM : PWM output logic signal, used to modulate the pulse width of Vsw

[0095] EN: Power-on and power-off enable logic signal for circuits 50 and 50A

[0096] EN1: Output logic signal of the first comparator 62

[0097] ENN: Output of the first inverter 63, i.e., the inversion of EN1

[0098] OVP: Logic control signal output from the third terminal of the timer 66

[0099] OVP1: Output logic signal of the second comparator 65

[0100] V DD1 、V DD2 : Positive proportional voltage division of VDD

[0101] UVLO VREF : Input voltage threshold at the inverting input terminal of the first comparator 62

[0102] VDD OFF : VDD under-voltage threshold

[0103] VDD ON : VDD over-voltage threshold

[0104] V FB_OPEN : Open-circuit voltage of the FB port

[0105] VB4: Voltage of capacitor C51, i.e., the gate voltage of the fourth low-voltage transistor M56 and the drain voltage of the third low-voltage transistor M55

[0106] VB3: Input bias voltage of the EN logic locker 55, i.e., the output bias voltage of the reference voltage device 53

[0107] vref1, vref2, vref3: Output reference voltages of the reference voltage device 53

[0108] VB2: Gate voltage of the second high-voltage transistor M52

[0109] VB1: Gate voltage of the first high-voltage transistor M51

[0110] V LVDD : Source voltage of the first high-voltage transistor M51

[0111] t OVP : VDD over-voltage protection shielding time, i.e., the timing time of the timer 66, to prevent OVP signal jitter

[0112] V THN : Gate turn-on threshold voltage of M53 - M56

[0113] "1": Logic high, corresponding to the voltage VB3

[0114] "0": Logic low, corresponding to the voltage 0. Detailed implementation manner

[0115] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0116] To make the above objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0117] As Figure 3 shown, the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A provided by the present invention has four ports, namely the VDD port, the EN port, the OVP port, and the V LVDD port; the VDD port of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A generates a lower-voltage power supply voltage source V LVDD at its V LVDD port for use by other circuit devices in the switching power supply controller integrated circuit 11A to reduce area and cost; the VDD port of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A generates an enable signal EN at the EN port, and the enable signal EN completes the under-voltage lockout function during the process of powering on VDD from 0 and powering off from the normal operating voltage to 0, and initializes the timer before powering on; the VDD port of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A generates an over-voltage protection signal OVP at the OVP port, and the over-voltage protection signal OVP can turn off the power transistor M1 when VDD exceeds the set voltage threshold, thereby protecting the safety of the switching power supply system; the VDD port of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A can withstand a voltage of up to 100V, and the upper limit of the operating voltage range can reach between 80 and 100V.

[0118] The ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A includes: a voltage divider 51, a clamp 52, a reference voltage generator 53, an under-voltage lockout 54, an EN logic lock 55, and an over-voltage protector 56.

[0119] The first end of the voltage divider 51 is respectively connected to the VDD port and the first end of the clamp 52, the second end of the voltage divider 51 is connected to the first end of the under-voltage lockout 54, the third end of the voltage divider 51 is connected to the first end of the over-voltage protector 56, and the fourth end of the voltage divider 51 is grounded; the second end of the clamp 52 is respectively connected to the first end of the reference voltage generator 53 and the V LVDDThe end is connected, and the third end of the clamper 52 is grounded; the second end of the reference voltage generator 53 is connected to the second end of the EN logic locker 55, the third end of the reference voltage generator 53 is connected to the first end of the EN logic locker 55, the fourth end of the reference voltage generator 53 is respectively connected to the third end of the undervoltage locker 54 and the second end of the overvoltage protector 56, the fifth end of the reference voltage generator 53 is connected to the second end of the undervoltage locker 54, and the sixth end of the reference voltage generator 53 is grounded; the fourth end of the undervoltage locker 54 is connected to the third end of the EN logic locker 55, and the fifth end of the undervoltage locker 54 is respectively connected to the EN end and the third end of the overvoltage protector 56; the fourth end of the EN logic locker 55 is grounded; the fourth end of the overvoltage protector 56 is connected to the OVP end.

[0120] Specifically, the voltage divider 51 includes: a first resistor R51 (a 100V withstand voltage resistor), a second resistor R52, and a third resistor R53; one end of the first resistor R51 is the first end of the voltage divider 51, the other end of the first resistor R51 is the second end of the voltage divider 51, the other end of the second resistor R52 is the third end of the voltage divider 51, and the other end of the third resistor R53 is the fourth end of the voltage divider 51; the voltage V of the first end VDD of the voltage divider 51 DD at the second end V DD1 and the third end V DD2 respectively generate partial voltages V DD1 and V DD2 .

[0121] One end of the first resistor R51 is respectively connected to the VDD end and the first end of the clamper 52, the other end of the first resistor R51 is respectively connected to one end of the second resistor R52 and the first end of the undervoltage locker 54, the other end of the second resistor R52 is respectively connected to one end of the third resistor R53 and the first end of the overvoltage protector 56, and the other end of the third resistor R53 is grounded.

[0122] Specifically, the clamper 52 includes: a fourth resistor R54 (a 100V withstand voltage resistor), a second clamping diode Z2, a third clamping diode Z3, a fourth clamping diode Z4, a fifth clamping diode Z5, and a first high-voltage transistor M51 (a 100V withstand voltage high-voltage NMOS transistor); one end of the fourth resistor R54 is the first end of the clamper 52, the source of the first high-voltage transistor M51 is the second end of the clamper 52, and the anode of the second clamping diode Z2 is the third end of the clamper 52; the first end VDD of the clamper 52 outputs a lower power supply voltage source V at its second end V LVDD at its second end VLVDD For other circuit devices to facilitate area reduction and cost reduction; the fifth clamping transistor Z5 can prevent the gate-source breakdown of the first high-voltage transistor M51.

[0123] One end of the fourth resistor R54 is respectively connected to one end of the first resistor R51 and the drain of the first high-voltage transistor M51, and the other end of the fourth resistor R54 is respectively connected to the gate of the first high-voltage transistor M51, the cathode of the fourth clamping transistor Z4, and the cathode of the fifth four-clamping transistor Z5; the anode of the fourth clamping transistor Z4 is connected to the cathode of the third clamping transistor Z3, the anode of the third clamping transistor Z3 is connected to the cathode of the second clamping transistor Z2, and the anode of the second clamping transistor Z2 is grounded; the anode of the fifth four-clamping transistor Z5 is connected to the source of the first high-voltage transistor M51, and the source of the first high-voltage transistor M51 is also respectively connected to the first end of the reference voltage device 53 and the V LVDD terminal connection.

[0124] Specifically, the reference voltage device 53 includes: a fifth resistor R55, a first clamping transistor Z1, a second high-voltage transistor M52 (a high-voltage NMOS transistor with a breakdown voltage of 20 - 30V), and a bandgap reference 61; one end of the fifth resistor R55 is the first end of the reference voltage device 53, the source of the second high-voltage transistor M52 is the second end of the reference voltage device 53, the second end of the bandgap reference 61 is the third end of the reference voltage device 53, the third end of the bandgap reference 61 is the fourth end of the reference voltage device 53, the fourth end of the bandgap reference 61 is the fifth end of the reference voltage device 53, and the fifth end of the bandgap reference 61 is the sixth end of the reference voltage device 53; the first end V of the reference voltage device 53 LVDD Generates reference voltages VB3, vref3, vref2, and vref1 at the second to fifth ends respectively.

[0125] One end of the fifth resistor R55 is respectively connected to the source of the first high-voltage transistor M51, the V LVDD terminal, and the drain of the second high-voltage transistor M52. The other end of the fifth resistor R55 is respectively connected to the cathode of the first clamping transistor Z1 and the gate of the second high-voltage transistor M52, and the anode of the first clamping transistor Z1 is grounded; the source of the second high-voltage transistor M52 is respectively connected to the second end of the EN logic lock 55 and the first end of the bandgap reference 61; the second end of the bandgap reference 61 is connected to the first end of the EN logic lock 55, the third end of the bandgap reference 61 is respectively connected to the third end of the undervoltage lock 54 and the second end of the overvoltage protector 56, the fourth end of the bandgap reference 61 is connected to the second end of the undervoltage lock 54, and the fifth end of the bandgap reference 61 is grounded.

[0126] Specifically, the under-voltage lockout 54 includes a first low-voltage transistor M53 (low-voltage NMOS transistor), a second low-voltage transistor M54 (low-voltage NMOS transistor), a first comparator 62, a first inverter 63, and a second inverter 64; the non-inverting input terminal of the first comparator 62 is the first terminal of the under-voltage lockout 54, the drain of the first low-voltage transistor M53 is the second terminal of the under-voltage lockout 54, the drain of the second low-voltage transistor M54 is the third terminal of the under-voltage lockout 54, the output terminal of the first comparator 62 is the fourth terminal of the under-voltage lockout 54, and the output terminal of the second inverter 64 is the fifth terminal of the under-voltage lockout 54; the first terminal V of the under-voltage lockout 54 DD1 , the second terminal vref1, the third terminal vref2, and the fourth terminal EN1 generate an enable logic signal EN at the fifth terminal EN.

[0127] The non-inverting input terminal of the first comparator 62 is connected to the other end of the first resistor R51, the inverting input terminal of the first comparator 62 is respectively connected to the source of the first low-voltage transistor M53 and the source of the second low-voltage transistor M54, the output terminal of the first comparator 62 is respectively connected to the input terminal of the first inverter 63, the gate of the first low-voltage transistor M53, and the third terminal of the EN logic lockout 55; the drain of the first low-voltage transistor M53 is connected to the fourth terminal of the bandgap reference 61, the drain of the second low-voltage transistor M54 is connected to the third terminal of the bandgap reference 61, and the gate of the second low-voltage transistor M54 is respectively connected to the output terminal of the first inverter 63 and the input terminal of the second inverter 64; the output terminal of the second inverter 64 is respectively connected to the EN terminal and the third terminal of the over-voltage protector 56.

[0128] Specifically, the EN logic lockout 55 includes a third low-voltage transistor M55 (low-voltage NMOS transistor), a fourth low-voltage transistor M56 (low-voltage NMOS transistor), a capacitor C51, and a sixth resistor R56; the gate of the third low-voltage transistor M55 is the first terminal of the EN logic lockout 55, one end of the sixth resistor R56 is the second terminal of the EN logic lockout 55, the drain of the fourth low-voltage transistor M56 is the third terminal of the EN logic lockout 55, and the source of the third low-voltage transistor M55 is the fourth terminal of the EN logic lockout 55; the first terminal vref3 and the second terminal VB3 of the EN logic lockout 55 generate an enable signal EN1 at its third terminal EN1, and the EN logic lockout 55 can prevent the enable logic signal EN from jittering.

[0129] The drain of the third low-voltage transistor M55 is respectively connected to the other end of the sixth resistor R56, one end of the capacitor C51, and the gate of the fourth low-voltage transistor M56. The gate of the third low-voltage transistor M55 is connected to the second end of the bandgap reference 61, and the source of the third low-voltage transistor M55 is grounded; one end of the sixth resistor R56 is connected to the source of the second high-voltage transistor M52; the drain of the fourth low-voltage transistor M56 is connected to the output end of the first comparator 62, and the source of the fourth low-voltage transistor M56 is grounded; the other end of the capacitor C51 is grounded.

[0130] Specifically, the overvoltage protector 56 includes a second comparator 65 and a timer 66; the positive-phase input terminal of the second comparator 65 is the first terminal of the overvoltage protector 56, the inverting input terminal of the second comparator 65 is the second terminal of the overvoltage protector 56, the third terminal of the timer is the third terminal of the overvoltage protector 56, and the second terminal of the timer 66 is the fourth terminal of the overvoltage protector 56; the first terminal V DD2 , the second terminal vref2, the third terminal EN generates a control signal OVP at the fourth terminal OVP, and the timer 66 can prevent the control signal OVP from jittering.

[0131] The positive-phase input terminal of the second comparator 65 is connected to the other end of the second resistor RM52, the inverting input terminal of the second comparator 65 is connected to the third end of the bandgap reference 61, the output terminal of the second comparator 65 is connected to the first end of the timer 66, the second end of the timer 66 is connected to the OVP terminal, and the third end of the timer 66 is connected to the output terminal of the second inverter 64.

[0132] A switching power supply provided by Embodiment OptionA of the present invention includes: a transformer TR, a switching power supply controller integrated circuit 11A, a power switch transistor M1, and a feedback device 12. The switching power supply controller integrated circuit 11A includes: the above-mentioned ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A, a pulse width modulator 30, and a drive circuit 40. The VDD terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is connected to the power supply port of the switching power supply controller integrated circuit 11A. The EN terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is respectively connected to the second end of the drive circuit 40 and the fourth end of the pulse width modulator 30. The OVP terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is connected to the third end of the drive circuit 40. The V LVDDOne end is respectively connected to the third end of the pulse width modulator 30 and the fourth end of the drive circuit 40; the first end of the pulse width modulator 30 is connected to the CS end of the switch power supply controller integrated circuit 11A, the second end of the pulse width modulator 30 is connected to the FB end of the switch power supply controller integrated circuit 11A, and the fifth end of the pulse width modulator 30 is connected to the first end of the drive circuit 40; the fifth end of the drive circuit 40 is connected to the DRV end of the switch power supply controller integrated circuit 11A.

[0133] As Figure 2 As shown, a switch power supply provided by Embodiment OptionB of the present invention includes: a transformer TR, a switch power supply controller integrated circuit 11A, a power switch tube M1, and a feedback device 12. The switch power supply controller integrated circuit 11A includes: the above-mentioned ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A, a pulse width modulator 30, a drive circuit 40, and a high-voltage startup circuit 20; the VDD end of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is respectively connected to the power supply port of the switch power supply controller integrated circuit 11A and the second end of the high-voltage startup circuit 20. The EN end of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is respectively connected to the second end of the drive circuit 40, the fourth end of the pulse width modulator 30, and the third end of the high-voltage startup circuit 20. The OVP end of the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is connected to the third end of the drive circuit. The V LVDD One end is respectively connected to the third end of the pulse width modulator 30 and the fourth end of the drive circuit 40; the first end of the pulse width modulator 30 is connected to the CS end of the switch power supply controller integrated circuit 11A, the second end of the pulse width modulator 30 is connected to the FB end of the switch power supply controller integrated circuit 11A, and the fifth end of the pulse width modulator 30 is connected to the first end of the drive circuit 40; the fifth end of the drive circuit 40 is connected to the DRV end of the switch power supply controller integrated circuit 11A; the first end of the high-voltage startup circuit 20 is connected to the HV end of the switch power supply controller integrated circuit 11A.

[0134] The CS end of the switch power supply controller integrated circuit 11A is connected to the first end of the sampling resistor Rcs and the source electrode of the power transistor M1. Its FB end is connected to the output end of the feedback device 12. Its DRV end is externally connected to the gate of the power transistor M1. Its VDD end is connected to the common end of Rst (Example OptionA), R1, and CVDD. In its Example OptionB, the HV end is connected to the common end of C1, D1, and TR. Its GND end is grounded; the second end of the sampling resistor Rcs is grounded; the drain of the power transistor M1 is connected to the primary coil Lp of the transformer.

[0135] The switching power supply controller integrated circuit 11A of the present invention has two optional startup methods at the VDD terminal. In Embodiment OptionA, the VDD is externally connected with a startup resistor Rst to the high-voltage input terminal. In Embodiment OptionB, as shown by the dashed line in Figure 2 , the port HV is externally connected to the common terminal of D1, C1, and TR, and the HV is internally connected to the HVStartup module to charge the VDD. When the VDD exceeds VDD ON , the HVStartup is turned off.

[0136] The principle of the undervoltage lockout function of the undervoltage lockout 54 in the ultra-high voltage undervoltage lockout and overvoltage protection circuit 50A is as follows:

[0137] Let R53 / (R51 + R52 + R53) = β, (R52 + R53) / (R51 + R52 + R53) = α, 0 < β <<< 1, the voltage at the VDD terminal is V DD , VDD ON is the power-on threshold, and VDD OFF is the power-off threshold. Then there are:

[0138] V DD1 = αV DD < 6V, 0 ≤ V DD ≤ 100V (1)

[0139] V DD2 = βV DD < V DD1 (2)

[0140] V DD = V DD1 / α = V DD2 / β (3)

[0141] VDD ON = vref2 / α (4)

[0142] VDD OFF = vref1 / α (5)

[0143] Here, VDD ON > VDD OFF , vref2 > vref1.

[0144] During the process of powering on VDD from 0, when V DD < VDD ON That is, when V DD1 < vref2, EN1 is logic "0". After being inverted by the first inverter 63, ENN is logic "1", the first low-voltage transistor M53 is turned off, and the second low-voltage transistor M54 is turned on. Then the reference voltage UVLO is input to the first comparator 62 VREFSelect vref2. ENN is inverted by the second inverter 64, EN is "0", the output OVP of the timer 66 is initialized to logic "0" by EN, and EN = "0" turns off the other module circuits.

[0145] When VDD > VDD ON That is, V DD1 > vref2, EN1 is "1", ENN is "0", EN is "1", the first low-voltage transistor M53 is turned on, and the second low-voltage transistor M54 is turned off. Then the reference voltage UVLO is input to the first comparator 62 VREF Select vref1, EN = "1" turns on the other module circuits, and the circuit enters normal operation, indicating the end of power-on.

[0146] VDD decreases from being greater than VDD ON That is, V DD1 During the descending process starting from being greater than vref2, when VDD < VDD OFF That is, V DD1 < vref1, EN1 is logic "0", ENN is "1", EN is "0", the first low-voltage transistor M53 is turned off, and the second low-voltage transistor M54 is turned on. Then the reference voltage UVLO is input to the first comparator 62 VREF Select vref2, EN = "0" turns off the other module circuits, and the circuit enters power-down and automatic restart.

[0147] The principle of the clamp 52 in the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is as follows:

[0148] The drain of the first high-voltage transistor M51 is connected to VDD, and a voltage clamping resistor, i.e., the fourth resistor R54, is connected between the gate and the drain to reduce the VDD voltage. The source outputs a lower supply voltage V LVDD to reduce the contact voltage of the internal circuit devices and lower the device cost. The supply voltage V LVDD powers the reference voltage transformer 53 and other module circuits. The clamping diodes Z2 to Z4 are connected in series between the ground and the gate of the first high-voltage transistor M51 to clamp the gate voltage of the first high-voltage transistor M51 at a lower voltage. The function of the fifth clamping diode Z5 is to clamp the gate-source voltage of the first high-voltage transistor M51 to prevent the gate oxide layer of the first high-voltage transistor M51 from being broken down. Let the clamping voltage threshold of each clamping diode be 5V < VZ < 6V. Since each clamping diode is a pair of back-to-back connected Zener diodes, its breakdown voltage threshold is close to zero temperature drift.

[0149] VB1 = V DD V DD < 3V Z (6)

[0150] VB1 = 3V Z V DD≥3V Z (7)

[0151] V LVDD =VB1 - V GS51 <19.3V (8)

[0152] Here, 0.7V < V GS51 <2V is the gate - source voltage difference of the first high - voltage transistor M51. Although Figure 3 three clamping transistors are used in , the implementation of the VDD voltage clamping function of the present invention is not limited to using three clamping transistors, and it can also be implemented with two or one clamping transistor. It can be seen from Equation (8) that the power supply voltage V LVDD of other circuits in the switching - power - supply controller integrated circuit 11A is a low - voltage power supply, far lower than the maximum voltage of 100V at the VDD pin. Therefore, the device size of other circuits inside the switching - power - supply controller integrated circuit 11A is minimized, and the chip cost is further reduced.

[0153] The principle of the reference voltage transformer 53 in the ultra - high - voltage undervoltage lock - out and over - voltage protection circuit 50A is as follows:

[0154] The drain of the second high - voltage transistor M52 is connected to V LVDD , and a voltage - clamping resistor, i.e., the fifth resistor R55, is connected between the drain and the gate to step down the voltage of V LVDD The source outputs a low - voltage power - supply voltage VB3 to the internal circuit to facilitate further reducing the cost of internal low - voltage devices. The first clamping transistor Z1 is connected between the gate of the second high - voltage transistor M52 and the ground to clamp the gate voltage of the second high - voltage transistor M52.

[0155] VB2 = V LVDD , V LVDD < V Z (9)

[0156] VB2 = V Z , V LVDD ≥ V Z (10)

[0157] VB3 = VB2 - V GS52 <5.3V (11)

[0158] Here, 0.7V < V GS52 <2V is the gate - source voltage difference of the second high - voltage transistor M52. After the band - gap reference 61 inputs the voltage VB3, it outputs the timing - synchronized reference voltages vref1, vref2, vref3 for use by the undervoltage lock - out 54, the EN logic lock - out 55, and the over - voltage protector 56. Among them, vref1 < vref2 < vref3 and they are in a proportional relationship, and at the same time vref3 < VB3.

[0159] The principle of the EN logic locker 55 in the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is as follows:

[0160] The drain of the third low-voltage transistor M55 inputs the voltage VB3 through the sixth resistor R56. The gate of the third low-voltage transistor M55 inputs vref3. The capacitor C51 is connected between the drain of the third low-voltage transistor M55 and the ground. The drain of the third low-voltage transistor M55 is connected to the gate of the fourth low-voltage transistor M56. The drain of the fourth low-voltage transistor M56 is connected to the EN1 terminal of the under-voltage lockout 54. The sources of the third low-voltage transistor M55 and the fourth low-voltage transistor M56 are grounded.

[0161] It is known that the gate turn-on threshold voltages of the third low-voltage transistor M55 and the fourth low-voltage transistor M56 are 0.6V < V THN < 1V, and the resistor R56 > 1 Megohm. When vref3 < V THN , the third low-voltage transistor M55 is turned off, VB4 = VB3 = V Z -V GS52 >> V THN , the fourth low-voltage transistor M56 is turned on, EN1 = "0", then after two inverters, EN = "0". When vref3 ≥ V THN , the third low-voltage transistor M55 is turned on, VB4 = 0V, the fourth low-voltage transistor M56 is turned off, the EN1 logic depends on the first comparator 62, and the EN logic locker 55 no longer functions.

[0162] Therefore, before the reference voltages vref1 to vref3 are established properly, the EN logic locker 55 will lock the EN output to "0" to prevent the EN from jittering during the VDD power-on process and causing errors in the operation of the switching power supply 10A.

[0163] The principle of the over-voltage protector 56 in the ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A is as follows:

[0164] During the VDD power-on process, EN = "0" initializes the output signal OVP of the timer 66 to "0". When an abnormality suddenly occurs during the normal operation of VDD, causing the VDD voltage VDD to rapidly rise above the set voltage threshold, that is, V DD2 is greater than vref2, the comparator 65 outputs OVP1 as logic "1". After the timer 66 times for the time T OVP , the protection signal OVP flips from "0" to "1", closes the power transistor M1 through the drive circuit 40, and VDD enters the automatic restart mode. It can enter the normal operation only after the over-voltage state of VDD is lifted and the next VDD restarts. Therefore, the over-voltage protector 56 protects the switching power supply 10A.

[0165] The ultra-high voltage under-voltage lockout and over-voltage protection circuit 50A provided by the present invention can operate on the VDD port within an ultra-wide voltage range of 0 to 100V, enabling it to complete under-voltage lockout during VDD power-on and power-off, protection of the switched-mode power supply system against VDD over-voltage, and providing a low-voltage power supply V for the internal circuit LVDD , and can also remove the 40V clamp 13 in the traditional switched-mode power supply 10. Therefore, the switched-mode power supply system 10A of the present invention maximally saves customer costs and ensures the safety of customer equipment.

[0166] For the timing waveforms of the switched-mode power supply system 10A of the present invention, please refer to Figure 5 and Figure 7 as shown, while the waveforms of the traditional switched-mode power supply 10 can be seen in Figure 4 and Figure 6 . Among them, Figure 4 and Figure 5 are respectively the comparison of the normal power-on working waveforms of the VDD pins of the traditional switched-mode power supply 10 and the switched-mode power supply 10A of the present invention; and Figure 6 and Figure 7 are the comparison of the over-voltage protection working waveforms of the VDD pins of the traditional switched-mode power supply 10 and the switched-mode power supply 10A of the present invention.

[0167] The switched-mode power supply 10A containing the present invention can achieve under-voltage lockout, over-voltage protection of the VDD pin of the traditional switched-mode power supply 10, and the function of supplying low voltage to the inside of the chip 11A without relying on an external 40V clamp 13, greatly reducing the customer's cost.

[0168] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0169] Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A super high voltage under-voltage lockout and over-voltage protection circuit, characterized in that, The ultra-high voltage under-voltage lockout and over-voltage protection circuit has four ports, namely the VDD port, the EN port, the OVP port, and the V LVDD port; The ultra-high voltage under-voltage lockout and over-voltage protection circuit includes: a voltage divider, a clamp, a reference voltage generator, an under-voltage lockout, an EN logic lockout, and an over-voltage protector; The first end of the voltage divider is respectively connected to the VDD terminal and the first end of the clamp, the second end of the voltage divider is connected to the first end of the under-voltage lockout, the third end of the voltage divider is connected to the first end of the over-voltage protector, and the fourth end of the voltage divider is grounded; the voltage divider generates voltage dividers at the second and third ends respectively; The second end of the clamp is respectively connected to the first end of the reference voltage device and the V LVDD end, and the third end of the clamp is grounded; The second end of the reference voltage generator is connected to the second end of the EN logic lockout, the third end of the reference voltage generator is connected to the first end of the EN logic lockout, the fourth end of the reference voltage generator is respectively connected to the third end of the under-voltage lockout and the second end of the over-voltage protector, the fifth end of the reference voltage generator is connected to the second end of the under-voltage lockout, and the sixth end of the reference voltage generator is grounded; the reference voltage generator generates reference voltages VB3, vref3, vref2, vref1 at the second to fifth ends respectively; where, vref1 < vref2 < vref3 and they are in a proportional relationship, and at the same time vref3 < VB3; The fourth end of the under-voltage lockout is connected to the third end of the EN logic lockout, and the fifth end of the under-voltage lockout is respectively connected to the EN terminal and the third end of the over-voltage protector; The fourth end of the EN logic lockout is grounded; The fourth end of the over-voltage protector is connected to the OVP terminal.

2. The over-voltage protection and under-voltage lockout circuit according to claim 1, wherein The voltage divider includes: a first resistor, a second resistor, and a third resistor; one end of the first resistor is the first end of the voltage divider, the other end of the first resistor is the second end of the voltage divider, the other end of the second resistor is the third end of the voltage divider, and the other end of the third resistor is the fourth end of the voltage divider; One end of the first resistor is respectively connected to the VDD terminal and the first end of the clamp, the other end of the first resistor is respectively connected to one end of the second resistor and the first end of the under-voltage lockout, the other end of the second resistor is respectively connected to one end of the third resistor and the first end of the over-voltage protector, and the other end of the third resistor is grounded.

3. The over-voltage protection and under-voltage lockout circuit according to claim 2, wherein The clamp includes: a fourth resistor, a second clamping transistor, a third clamping transistor, a fourth clamping transistor, a fifth clamping transistor, and a first high-voltage transistor; one end of the fourth resistor is the first end of the clamp, the source of the first high-voltage transistor is the second end of the clamp, and the anode of the second clamping transistor is the third end of the clamp; One end of the fourth resistor is respectively connected to one end of the first resistor and the drain of the first high-voltage transistor, and the other end of the fourth resistor is respectively connected to the gate of the first high-voltage transistor, the cathode of the fourth clamping transistor, and the cathode of the fifth clamping transistor; the anode of the fourth clamping transistor is connected to the cathode of the third clamping transistor, the anode of the third clamping transistor is connected to the cathode of the second clamping transistor, and the anode of the second clamping transistor is grounded; the anode of the fifth clamping transistor is connected to the source of the first high-voltage transistor, and the source of the first high-voltage transistor is also respectively connected to the first end of the reference voltage device and the V LVDD terminal connection.

4. The overvoltage protection circuit and ultrahigh voltage undervoltage locking according to claim 3, characterized in that The reference voltage generator includes: a fifth resistor, a first clamping diode, a second high-voltage transistor, and a bandgap reference; one end of the fifth resistor is the first terminal of the reference voltage generator, the source of the second high-voltage transistor is the second terminal of the reference voltage generator, the second terminal of the bandgap reference is the third terminal of the reference voltage generator, the third terminal of the bandgap reference is the fourth terminal of the reference voltage generator, the fourth terminal of the bandgap reference is the fifth terminal of the reference voltage generator, and the fifth terminal of the bandgap reference is the sixth terminal of the reference voltage generator; One end of the fifth resistor is respectively connected to the source of the first high-voltage transistor, the V LVDD terminal and the drain of the second high-voltage transistor. The other end of the fifth resistor is respectively connected to the cathode of the first clamping transistor and the gate of the second high-voltage transistor. The anode of the first clamping transistor is grounded. The source of the second high-voltage transistor is respectively connected to the second terminal of the EN logic locker and the first terminal of the bandgap reference. The second terminal of the bandgap reference is connected to the first terminal of the EN logic locker. The third terminal of the bandgap reference is respectively connected to the third terminal of the undervoltage locker and the second terminal of the overvoltage protector. The fourth terminal of the bandgap reference is connected to the second terminal of the undervoltage locker. The fifth terminal of the bandgap reference is grounded.

5. The overvoltage protection and undervoltage lockout circuit according to claim 4, characterized in that, The under-voltage lockout includes a first low-voltage transistor, a second low-voltage transistor, a first comparator, a first inverter, and a second inverter; the non-inverting input terminal of the first comparator is the first terminal of the under-voltage lockout, the drain of the first low-voltage transistor is the second terminal of the under-voltage lockout, the drain of the second low-voltage transistor is the third terminal of the under-voltage lockout, the output terminal of the first comparator is the fourth terminal of the under-voltage lockout, and the output terminal of the second inverter is the fifth terminal of the under-voltage lockout; The non-inverting input terminal of the first comparator is connected to the other end of the first resistor, the inverting input terminal of the first comparator is respectively connected to the source of the first low-voltage transistor and the source of the second low-voltage transistor, the output terminal of the first comparator is respectively connected to the input terminal of the first inverter, the gate of the first low-voltage transistor, and the third terminal of the EN logic lockout; the drain of the first low-voltage transistor is connected to the fourth terminal of the bandgap reference, the drain of the second low-voltage transistor is connected to the third terminal of the bandgap reference, the gate of the second low-voltage transistor is respectively connected to the output terminal of the first inverter and the input terminal of the second inverter; the output terminal of the second inverter is respectively connected to the EN terminal and the third terminal of the over-voltage protector.

6. The overvoltage protection and undervoltage lockout circuit according to claim 5, wherein The EN logic lockout includes a third low-voltage transistor, a fourth low-voltage transistor, a capacitor, and a sixth resistor; the gate of the third low-voltage transistor is the first terminal of the EN logic lockout, one end of the sixth resistor is the second terminal of the EN logic lockout, the drain of the fourth low-voltage transistor is the third terminal of the EN logic lockout, and the source of the third low-voltage transistor is the fourth terminal of the EN logic lockout; The drain of the third low-voltage transistor is respectively connected to the other end of the sixth resistor, one end of the capacitor, and the gate of the fourth low-voltage transistor, the gate of the third low-voltage transistor is connected to the second terminal of the bandgap reference, and the source of the third low-voltage transistor is grounded; one end of the sixth resistor is connected to the source of the second high-voltage transistor; the drain of the fourth low-voltage transistor is connected to the output terminal of the first comparator, and the source of the fourth low-voltage transistor is grounded; the other end of the capacitor is grounded.

7. The overvoltage protection and undervoltage lockout circuit according to claim 6, wherein The over-voltage protector includes a second comparator and a timer; the non-inverting input terminal of the second comparator is the first terminal of the over-voltage protector, the inverting input terminal of the second comparator is the second terminal of the over-voltage protector, the third terminal of the timer is the third terminal of the over-voltage protector, and the second terminal of the timer is the fourth terminal of the over-voltage protector; The non-inverting input terminal of the second comparator is connected to the other end of the second resistor, the inverting input terminal of the second comparator is connected to the third terminal of the bandgap reference, the output terminal of the second comparator is connected to the first terminal of the timer, the second terminal of the timer is connected to the OVP terminal, and the third terminal of the timer is connected to the output terminal of the second inverter.

8. A switching power supply, comprising: A transformer, a switching power supply controller integrated circuit, a power switch transistor, and a feedback device, characterized in that the switching power supply controller integrated circuit includes: an ultra-high voltage under-voltage lockout and over-voltage protection circuit as described in any one of claims 1-7, a pulse width modulator, and a driving circuit; the VDD terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is connected to the power supply port of the switching power supply controller integrated circuit, the EN terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is respectively connected to the second terminal of the driving circuit and the fourth terminal of the pulse width modulator, the OVP terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is connected to the third terminal of the driving circuit, and the V LVDD terminals of the ultra-high voltage under-voltage lockout and over-voltage protection circuit are respectively connected to the third terminal of the pulse width modulator and the fourth terminal of the driving circuit; the first terminal of the pulse width modulator is connected to the CS terminal of the switching power supply controller integrated circuit, the second terminal of the pulse width modulator is connected to the FB terminal of the switching power supply controller integrated circuit, the fifth terminal of the pulse width modulator is connected to the first terminal of the driving circuit; the fifth terminal of the driving circuit is connected to the DRV terminal of the switching power supply controller integrated circuit.

9. A switching power supply, comprising: A transformer, a switching power supply controller integrated circuit, a power switch tube, and a feedback device, characterized in that the switching power supply controller integrated circuit includes: an ultra-high voltage under-voltage lockout and over-voltage protection circuit, a pulse width modulator, a drive circuit, and a high-voltage start-up circuit as described in any one of claims 1-7; the VDD terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is respectively connected to the power supply port of the switching power supply controller integrated circuit and the second terminal of the high-voltage start-up circuit, the EN terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is respectively connected to the second terminal of the drive circuit, the fourth terminal of the pulse width modulator, and the third terminal of the high-voltage start-up circuit, the OVP terminal of the ultra-high voltage under-voltage lockout and over-voltage protection circuit is connected to the third terminal of the drive circuit, and the V LVDD terminals are respectively connected to the third terminal of the pulse width modulator and the fourth terminal of the drive circuit; the first terminal of the pulse width modulator is connected to the CS terminal of the switching power supply controller integrated circuit, the second terminal of the pulse width modulator is connected to the FB terminal of the switching power supply controller integrated circuit, the fifth terminal of the pulse width modulator is connected to the first terminal of the drive circuit; the fifth terminal of the drive circuit is connected to the DRV terminal of the switching power supply controller integrated circuit; the first terminal of the high-voltage start-up circuit is connected to the HV terminal of the switching power supply controller integrated circuit.

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