A self-calibration system for phase-locked loop frequency

Abstract

The application provides a self-calibration system of a phase-locked loop frequency, in the open loop state of the phase-locked loop, the frequency division reference clock and the frequency division feedback clock are converted into corresponding direct current voltages respectively, and then the direct current voltages are compared to obtain the relationship result reflecting the clock frequency, so that the whole self-calibration system does not need the assistance of a digital circuit, and thus is not limited by the calibration frequency, and is suitable for a pure analog chip and easy to integrate. The application adopts a successive approximation method, and the final current adjustment code is determined by the encoding output mode of the reference from the low bit to the high bit and then from the high bit to the low bit. Compared with the scheme of obtaining the corresponding current adjustment code by increasing or decreasing the code value from the middle bit, the application avoids the situation of calibration failure caused by the fact that the frequency of the oscillator exceeds the oscillation frequency limit of the frequency divider when the current adjustment code is the middle bit. Moreover, the technical scheme of the successive approximation method has the advantages of less calibration times and high calibration efficiency.

Description

Technical Field

[0001] This invention relates to the field of phase-locked loop (PLL) frequency calibration technology, and more specifically, to a self-calibration system for PLL frequency. Background Technology

[0002] High-performance phase-locked loops (PLLs) require low output clock jitter. VCO output clock jitter can be significantly improved by reducing the phase noise of the VCO (voltage-controlled oscillator) and the jitter of the charge pump output voltage. Introducing VCO calibration technology can achieve both goals simultaneously: firstly, the calibration voltage can be preset to the optimal voltage value for matching the charge pump's charging and discharging current, ensuring the PLL's closed-loop operating voltage is also at this value, resulting in low charge pump output voltage jitter; secondly, the VCO's phase noise can be greatly improved by adding a filter in the recalibration circuit; and thirdly, calibration methods can minimize the VCO's gain, reducing its sensitivity to noise.

[0003] Some applications require a large frequency tuning range for the phase-locked loop (PLL). If the output frequency of the VCO is adjusted solely by controlling the voltage, the VCO gain needs to be very high, resulting in significant jitter in the PLL's output clock. Moreover, the frequency tuning range of an LC oscillator is inherently small. Therefore, frequency calibration techniques are needed to divide the large frequency tuning range into several overlapping smaller frequency ranges, which greatly reduces the pressure on the VCO design. Summary of the Invention

[0004] In view of this, the present invention provides a self-calibration system for phase-locked loop frequency, which effectively solves the existing technical problems. The self-calibration system has the advantages of fewer calibration times, high calibration efficiency, no need for digital circuit assistance, no limitation on calibration frequency, and easy integration.

[0005] To achieve the above objectives, the technical solution provided by the present invention is as follows:

[0006] A self-calibration system for phase-locked loop frequency, comprising:

[0007] A loop divider, the input of which is connected to the output clock of the oscillator of the phase-locked loop; the loop divider is used to output a divided feedback clock.

[0008] A first frequency divider and a second frequency divider are used. The input of the first frequency divider is connected to a reference clock, and the input of the second frequency divider is electrically connected to the output of the loop frequency divider. The first frequency divider is used to divide the reference clock and output a divided reference clock, and the second frequency divider is used to divide the filtered feedback clock and output a divided feedback clock. The duty cycles of the divided reference clock and the divided feedback clock are the same.

[0009] A first frequency-to-voltage converter and a second frequency-to-voltage converter, wherein the input side of the first frequency-to-voltage converter is connected to the frequency-division reference clock, the main enable signal, and the voltage calibration code signal; and the input side of the second frequency-to-voltage converter is connected to the frequency-division feedback clock, the auxiliary enable signal, and the voltage calibration code signal; the first frequency-to-voltage converter is used to respond to the enable control of the main enable signal, and convert the frequency of the frequency-division reference clock into a reference voltage according to the voltage calibration code signal and the frequency-division reference clock, until the voltage calibration code signal is a target calibration code, and then convert the frequency of the frequency-division reference clock into a target reference voltage within a preset voltage range; and the second frequency-to-voltage converter is used to respond to the enable control of the auxiliary enable signal, and convert the frequency of the frequency-division feedback clock into a target feedback voltage according to the target calibration code and the frequency-division feedback clock;

[0010] A main comparator is connected to the target reference voltage and the target feedback voltage; the main comparator is used to compare the target reference voltage and the target feedback voltage, and outputs a work hold signal when the difference between the target reference voltage and the target feedback voltage is greater than a preset range, and outputs a work termination signal when the difference between the target reference voltage and the target feedback voltage is within the preset range;

[0011] A forward and reverse successive approximation encoder is provided. The input terminal of the forward and reverse successive approximation encoder is electrically connected to the output terminal of the main comparator and is connected to the auxiliary enable signal and the calibration interval clock signal. The forward and reverse successive approximation encoder is used to respond to the enable control of the auxiliary enable signal and, with reference to the encoding output mode from low bit to high bit and then from high bit to low bit, outputs current adjustment code successively according to the successively connected operation hold signal until the operation stop signal is connected and the current current adjustment code is maintained. The clock period of the calibration interval clock signal is used to define the duration of the current adjustment code.

[0012] A current adjustment circuit is provided, wherein the input terminal of the current adjustment circuit is electrically connected to the output terminal of the forward and reverse successive approximation encoder, and the output terminal of the current adjustment circuit is connected to the oscillator of the phase-locked loop; the current adjustment circuit is used to output a control current matching the current adjustment code to the oscillator of the phase-locked loop according to the current adjustment code.

[0013] An automatic voltage calibration module is provided, wherein its input side is electrically connected to the output of the first frequency-voltage converter and is connected to the main enable signal and the calibration interval clock signal. The automatic voltage calibration module is used to respond to the enable control of the main enable signal and output the voltage calibration code signal according to the difference between the reference voltage and the preset voltage range, until the first frequency-voltage converter outputs the target reference voltage and outputs a calibration completion signal. The clock period of the calibration interval clock signal is used to define the duration of the calibration code of the voltage calibration code signal.

[0014] A calibration module clock generator is provided, wherein the input side of the calibration module clock generator is connected to the main enable signal, the reference clock, and the calibration completion signal; the calibration module clock generator is used to respond to the enable control of the main enable signal, output the calibration interval clock signal according to the reference clock, and output the auxiliary enable signal with reference to the main enable signal and the calibration completion signal.

[0015] Compared with the prior art, the technical solution provided by the present invention has at least the following advantages:

[0016] This invention provides a self-calibration system for phase-locked loop (PLL) frequency. In the open-loop state of the PLL, the system converts the frequency-divided reference clock and frequency-divided feedback clock into their respective DC voltages, and then compares these DC voltages to derive the relationship between the response clock frequency and the actual frequency. This eliminates the need for digital circuitry, thus avoiding frequency limitations and making it suitable for pure analog chips and easy to integrate. Furthermore, this invention employs a successive approximation method, determining the final current adjustment code by referencing an encoding output method that proceeds from the least significant bit to the most significant bit and then from the most significant bit to the least significant bit. Compared to existing schemes that incrementally increase or decrease the code value starting from the middle bit, this invention avoids calibration failures caused by the oscillator frequency exceeding the divider's oscillation frequency limit when the current adjustment code is in the middle bit. Moreover, the successive approximation method of this invention also offers the advantages of fewer calibration cycles and higher calibration efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of a phase-locked loop frequency self-calibration system provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of the structure of a frequency-voltage converter provided in an embodiment of the present invention;

[0020] Figure 3 This is a schematic diagram of the structure of a voltage output module provided in an embodiment of the present invention;

[0021] Figure 4 This is a schematic diagram of the structure of an automatic voltage calibration module provided in an embodiment of the present invention;

[0022] Figure 5 This is a schematic diagram of the structure of a calibration module clock generator provided in an embodiment of the present invention;

[0023] Figure 6 A timing diagram provided for an embodiment of the present invention;

[0024] Figure 7 This is a schematic diagram of a forward and reverse successive approximation encoder provided in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] As described in the background section, some applications require a large frequency tuning range for the phase-locked loop (PLL). If the output frequency of the VCO is adjusted solely by controlling the voltage, the VCO gain needs to be very high, resulting in significant jitter in the PLL's output clock. Moreover, the frequency tuning range of an LC oscillator is inherently small. Therefore, frequency calibration techniques are needed to divide the large frequency tuning range into several overlapping smaller frequency ranges, which greatly reduces the pressure on the VCO design.

[0027] Based on this, the present invention provides a self-calibration system for phase-locked loop frequency, which effectively solves the existing technical problems. The self-calibration system has the advantages of fewer calibration times, high calibration efficiency, no need for digital circuit assistance, no limitation on calibration frequency, and easy integration.

[0028] To achieve the above objectives, the technical solutions provided by the embodiments of the present invention are as follows, in detail... Figures 1 to 7 The technical solutions provided in the embodiments of the present invention will be described in detail.

[0029] refer to Figure 1The diagram shown is a structural schematic of a phase-locked loop frequency self-calibration system provided in an embodiment of the present invention, wherein the self-calibration system includes:

[0030] A loop divider 200 is provided, the input of which is connected to the output clock of the phase-locked loop oscillator 100; the loop divider 200 is used to output the divided feedback clock fb_clk.

[0031] A first frequency divider 310 and a second frequency divider 320 are used. The input terminal of the first frequency divider 310 is connected to a reference clock ref_clk, and the input terminal of the second frequency divider 320 is electrically connected to the output terminal of the loop frequency divider 200. The first frequency divider 310 is used to divide the reference clock ref_clk and output a frequency-divided reference clock, and the second frequency divider 320 is used to divide the filtered feedback clock fb_clk and output a frequency-divided feedback clock. The frequency-divided reference clock and the frequency-divided feedback clock have the same duty cycle.

[0032] A first frequency-to-voltage converter 410 and a second frequency-to-voltage converter 420 are configured. The input side of the first frequency-to-voltage converter 410 is connected to the frequency-division reference clock, the main enable signal g_rstn, and the voltage calibration code signal fvc_iset. The input side of the second frequency-to-voltage converter is connected to the frequency-division feedback clock, the auxiliary enable signal rstn_cal, and the voltage calibration code signal fvc_iset. The first frequency-to-voltage converter is configured to convert the frequency of the frequency-division reference clock into a reference voltage Vref according to the voltage calibration code signal fvc_iset and the frequency-division reference clock in response to the enable control of the main enable signal g_rstn, until the voltage calibration code signal fvc_iset is the target calibration code, at which point the frequency of the frequency-division reference clock is converted into a target reference voltage Vref within a preset voltage range. The second frequency-to-voltage converter 420 is configured to convert the frequency of the frequency-division feedback clock into a target feedback voltage according to the target calibration code and the frequency-division feedback clock in response to the enable control of the auxiliary enable signal rstn_cal.

[0033] A main comparator 500 is connected to the target reference voltage and the target feedback voltage. The non-inverting input of the main comparator 500 is connected to the target reference voltage, and the inverting input is connected to the target feedback voltage. The main comparator 500 is used to compare the target reference voltage and the target feedback voltage. When the difference between the target reference voltage and the target feedback voltage is greater than a preset range, it outputs a work hold signal. When the difference between the target reference voltage Vref and the target feedback voltage is within the preset range, it outputs a work stop signal.

[0034] A forward and reverse successive approximation encoder 600 is used. The input terminal of the forward and reverse successive approximation encoder 600 is electrically connected to the output terminal of the main comparator 500, and is connected to the auxiliary enable signal rstn_cal and the calibration interval clock signal cal_interval_clk. The forward and reverse successive approximation encoder 600 is used to respond to the enable control of the auxiliary enable signal rstn_cal, and with reference to the encoding output mode from low bit to high bit and then from high bit to low bit, it outputs the current adjustment encoding band successively according to the successively connected working hold signal, until the working stop signal is connected and the current current adjustment encoding band is maintained. The clock period of the calibration interval clock signal cal_interval_clk is used to define the duration of the current adjustment encoding band.

[0035] A current adjustment circuit 700 is provided, the input terminal of which is electrically connected to the output terminal of the forward and reverse successive approximation encoder 600, and the output terminal of the current adjustment circuit 600 is connected to the oscillator of the phase-locked loop; the current adjustment circuit 700 is used to output a control current matching the current adjustment code band to the oscillator 100 of the phase-locked loop according to the current adjustment code band.

[0036] An automatic voltage calibration module 800 is provided. The input side of the automatic voltage calibration module 800 is electrically connected to the output terminal of the first frequency-voltage converter 410, and is connected to the main enable signal g_rstn and the calibration interval clock signal cal_interval_clk. The automatic voltage calibration module 800 is used to respond to the enable control of the main enable signal g_rstn, and output the voltage calibration code signal fvc_iset according to the difference between the reference voltage Vref and the preset voltage range, until the first frequency-voltage converter 410 outputs the target reference voltage Vref and outputs the calibration completion signal cal_en. The clock period of the calibration interval clock signal cal_interval_clk is used to define the duration of the calibration code of the voltage calibration code signal fvc_iset.

[0037] A calibration module clock generator 900 is provided, with its input side connected to the main enable signal g_rstn, the reference clock ref_clk, and the calibration completion signal cal_en. The calibration module clock generator 900 is used to respond to the enable control of the main enable signal g_rstn, output the calibration interval clock signal cal_interval_clk based on the reference clock ref_clk, and output the auxiliary enable signal rstn_cal with reference to the main enable signal g_rstn and the calibration completion signal cal_en.

[0038] Understandably, the working process of the phase-locked loop frequency self-calibration system provided in this embodiment of the invention is as follows: First, the phase-locked loop is opened, and the main start signal outputs an enable level to control the calibration module clock generator, the voltage automatic calibration module, and the first frequency-voltage converter to enter the working state. The reference clock is divided by a first frequency divider to obtain a frequency-divided reference clock. The frequency-divided reference clock is then converted by the first frequency-voltage converter to generate a reference voltage, which is output to the voltage automatic calibration module. The voltage automatic calibration module determines the difference between the reference voltage and a preset voltage range. If the reference voltage is outside the preset voltage range, it outputs a new voltage calibration code signal to the first frequency-voltage converter. The first frequency-voltage converter converts the frequency of the frequency-divided reference clock to a new reference voltage based on the new voltage calibration code signal and the frequency-divided reference clock. This reference voltage update process is repeated until the voltage automatic calibration module determines that the current reference voltage is within the preset voltage range. At this point, the voltage automatic calibration module outputs a calibration completion signal. Simultaneously, the current reference voltage is determined to be the target reference voltage, and the corresponding voltage calibration code signal is the target calibration code. The calibration module clock generator outputs an enable level for an auxiliary start signal based on the calibration completion signal.

[0039] Then, the enable level of the auxiliary start signal controls the start-up state of the second frequency voltage converter and the forward and reverse successive approximation encoder. The second frequency voltage converter converts the frequency of the frequency division feedback clock into the target feedback voltage by referencing the target calibration code and the frequency division feedback clock. The main comparator receives the target feedback voltage and compares it with the target reference voltage. If the difference between the target reference voltage and the target feedback voltage is greater than a preset range, it outputs a work hold signal to the forward and reverse successive approximation encoder. Each time the forward and reverse successive approximation encoder receives a work hold signal, it updates its output current adjustment code to control the output of the current adjustment circuit to match the updated current adjustment code. The control current for encoding matching is sent to the oscillator. The oscillator outputs a new clock, which, after passing through the loop divider and the second divider, outputs an updated frequency-divided feedback clock. Then, the second frequency-voltage converter, referring to the target calibration code and the updated frequency-divided feedback clock, converts the frequency of the updated frequency-divided feedback clock into a new target feedback voltage. This is then transmitted to the main comparator to compare the updated target feedback voltage with the target reference voltage. This process is repeated until the difference between the target reference voltage and the target feedback voltage is determined to be within a preset range. At this point, a work termination signal is output. The forward and reverse successive approximation encoders receive this work termination signal and determine that the calibration is complete. The phase-locked loop then begins closed-loop operation.

[0040] Understandably, the technical solution provided by this invention, in the open-loop state of the phase-locked loop, converts the frequency-divided reference clock and the frequency-divided feedback clock into their respective DC voltages, and then compares these DC voltages to obtain the relationship between the response clock frequencies. This eliminates the need for digital circuitry in the entire self-calibration system, thus avoiding frequency limitations and making it suitable for pure analog chips and easy to integrate. Furthermore, the successive approximation method provided by this invention, which determines the final current adjustment code by referencing the encoding output from low to high bits and then from high to low bits, compared to existing methods that incrementally increase or decrease the code value from the middle bit, avoids calibration failures caused by the oscillator frequency exceeding the frequency divider's oscillation frequency limit when the current adjustment code is in the middle bit. Moreover, the successive approximation method also offers advantages such as fewer calibration cycles and higher calibration efficiency.

[0041] In one embodiment of the present invention, the first frequency divider and the second frequency divider provided by the present invention are the same frequency divider, such as both being frequency dividers of two. The first frequency divider divides the reference clock by two, and the second frequency divider divides the feedback clock by two, adjusting the duty cycle of the divided voltage to 50%. This optimizes the timing of the frequency-to-voltage converter, meaning that the DC voltage obtained after conversion by the frequency-to-voltage converter is essentially equivalent to half the clock frequency of the reference clock or the feedback clock.

[0042] like Figure 2 The diagram shown is a structural schematic of a frequency-voltage converter provided in an embodiment of the present invention. Either the first frequency-voltage converter or the second frequency-voltage converter provided in this embodiment includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first delay module DE1, a second delay module DE2, a first AND gate AND1, a second AND gate AND2, a first differential module S2D1, a second differential module S2D2, and a voltage output module 401.

[0043] The input terminal of the first inverter INV1 is electrically connected to the first input terminal of the first AND gate AND1 to receive the input clock clk_in, which is the frequency division reference clock or the frequency division feedback clock. The output terminal of the first inverter INV1 is electrically connected to the input terminal of the first delay module DE1. The output terminal of the first delay module DE1 is electrically connected to the second input terminal of the first AND gate AND1 and the input terminal of the second inverter INV2. The output terminal of the first AND gate AND2 is electrically connected to the input terminal of the first differential module S2D1. The first output terminal and the second output terminal of the first differential module S2D1 are both electrically connected to the voltage output module 401. The first output terminal and the second output terminal of the first differential module S2D1 are used to output the first differential signal (differential clock S1 and S1_N, respectively).

[0044] The output terminal of the second inverter INV2 is electrically connected to the input terminal of the third inverter INV3 and the first input terminal of the second AND gate AND2. The output terminal of the third inverter INV3 is electrically connected to the input terminal of the second delay module DE2. The output terminal of the second delay module DE2 is electrically connected to the second input terminal of the second AND gate AND2. The output terminal of the second AND gate AND2 is electrically connected to the second differential module S2D2. The first output terminal and the second output terminal of the second differential module S2D2 are both electrically connected to the voltage output module 401. The first output terminal and the second output terminal of the second differential module S2D2 are used to output the second differential signal (differential clock S2 and S2_N, respectively).

[0045] The input terminal of the fourth inverter INV4 is connected to the response signal, which is either the main enable signal g_rstn or the auxiliary enable signal rstn_cal. The output terminal of the fourth inverter INV4 is electrically connected to the voltage output module 401. The fourth inverter INV4 inverts the response signal and outputs an inverted signal rst_fvc. The voltage output module 401 is used to generate an output voltage by referencing the first differential signal, the second differential signal, the output signal of the fourth inverter INV4 (inverted signal rst_fvc), the input clock clk_in, and the voltage calibration encoding signal fvc_iset. The output voltage is either the reference voltage Vref or the target feedback voltage.

[0046] like Figure 3 The diagram shown is a structural schematic of a voltage output module provided in an embodiment of the present invention. The voltage output module provided in this embodiment includes: a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, a fifth P-type transistor MP5, a sixth P-type transistor MP6, a seventh P-type transistor MP7, an eighth P-type transistor MP8, a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eleventh P-type transistor MP11, a twelfth P-type transistor MP12, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a fourth N-type transistor MN4, a first resistor R1, a first capacitor C1, and a second capacitor C2.

[0047] The first terminals of the first P-type transistor MP1, the second P-type transistor MP2, the third P-type transistor MP3, the fourth P-type transistor MP4, and the fifth P-type transistor MP5 are all electrically connected, and their gates are all electrically connected. The second terminal of the first P-type transistor MP1 is connected to a current source, and its gate is also electrically connected. The second terminal of the second P-type transistor MP2 is electrically connected to the first terminal of the sixth P-type transistor MP6, the second terminal of the third P-type transistor MP3 is electrically connected to the first terminal of the seventh P-type transistor MP7, and the second terminal of the fourth P-type transistor MP4 is electrically connected to the eighth P-type transistor MP5. The first terminal of transistor MP8 is electrically connected. The second terminal of the fifth P-type transistor MP5 is electrically connected to the first terminal of the ninth P-type transistor MP9. The second terminals of the sixth P-type transistor MP6, the seventh P-type transistor MP7, the eighth P-type transistor MP8, and the ninth P-type transistor MP9 are all electrically connected and electrically connected to the first terminal of the tenth P-type transistor MP10 and the first terminal of the first N-type transistor MN1. The gates of the sixth P-type transistor MP6, the seventh P-type transistor MP7, the eighth P-type transistor MP8, and the ninth P-type transistor MP9 are all connected to the voltage calibration encoding signal fvc_iset. In this embodiment, the voltage calibration encoding signal is a 4-bit encoding signal, and the gates of the sixth P-type transistor MP6 to the eighth P-type transistor MP8 are sequentially connected to the encoding signal fvc_iset. <3> ,ist <2> ist <1> andist <0> .

[0048] The gates of the tenth P-type transistor MP10 and the first N-type transistor MN1 are both connected to the input clock clk_in. The second terminal of the first N-type transistor MN1 is electrically connected to ground. The second terminal of the tenth P-type transistor MP10 is electrically connected to the first terminal of the first resistor R1, the first terminal of the first capacitor C1, the first terminal of the eleventh P-type transistor MP11, the first terminal of the second N-type transistor MN2, and the first terminal of the fourth N-type transistor MN4. The second terminal of the first resistor R1 is electrically connected to the first terminal of the twelfth P-type transistor MP12 and the first terminal of the third N-type transistor MN3. The second terminal of the twelfth P-type transistor MP12 is electrically connected to the first terminal of the third N-type transistor MN3. The second terminal of the body transistor MN3 is electrically connected to the ground terminal. The gate of the twelfth P-type transistor MP12 and the gate of the third N-type transistor MN3 are connected to the second differential signal. The second terminal of the first capacitor C1 and the second terminal of the fourth N-type transistor MN4 are both electrically connected to the ground terminal. The gate of the fourth N-type transistor MN4 is electrically connected to the output terminal of the fourth inverter INV4. The second terminal of the eleventh P-type transistor MP11 and the second terminal of the second N-type transistor MN2 are both electrically connected to the first terminal of the second capacitor C2. The gate of the eleventh P-type transistor MP11 and the gate of the second N-type transistor MN2 are connected to the first differential signal. The second terminal of the second capacitor C2 is electrically connected to the ground terminal.

[0049] It is understood that the first frequency-voltage converter and the second frequency-voltage converter provided in the embodiments of the present invention have the same composition. The frequency-voltage converter is used to convert the clock frequencies of the frequency division reference clock and the frequency division feedback clock into DC voltages and compare them in the main comparator of the analog circuit, thereby determining the frequency relationship between the frequency division reference clock and the frequency division feedback clock.

[0050] Combination Figure 2 and Figure 3 As shown, the working process of the frequency-to-voltage converter provided in this embodiment of the invention is as follows:

[0051] In the first stage, during the low-level phase of the nth cycle of the input frequency clk_in, MP10 is turned on, while MP11, MP12, MN1, MN2, and MN3 are turned off, charging C1. The charging current is set to I, and the charging voltage of C1 by the low-level devices at clk_in is:

[0052] Formula 1

[0053] In the second stage, at the rising edge of clk_in, MP10 is turned off, stopping the charging of C1. Simultaneously, MP11 and MN2 are turned on, and the charge on C1 is transferred to C2 until the voltages across C1 and C2 are equal. This process takes time Td, where...

[0054] Formula 2

[0055] In the third stage, after time Td, MP11 and MN3 are also disconnected, while MP12 and MN2 are turned on. C1 discharges to the ground terminal for a time Td, and the voltage across C1 after discharge is Vc1(nT). Then MP12 and MN3 are disconnected. At this point, MP10, MP11, MP13, MN2, and MN3 are all disconnected until the next falling edge of the clock arrives, at which point the above process is repeated.

[0056] Formula 3

[0057] Where △V is the charging voltage of C1 for each cycle, T is the clk_in clock cycle, Vo(nT) is the voltage across C1 in the nth cycle, Vc1[(n-1)T] is the voltage across C1 in the (n-1)th cycle, Ron is the parallel on-resistance of MP11 and MN2, R1 is the structure of the first resistor, C is the capacitance of C1 and C2, and Td is also equal to the high-level pulse duration of S1 and S2.

[0058] From equations two and three, assuming the output voltage is stable in the nth cycle, then:

[0059] Formula 4

[0060] Formula 5

[0061] Formula Six

[0062] From equations four, five, and six, we obtain:

[0063] Formula 7

[0064] Formula 8

[0065] Where T is the clock period of clk_in, and f is the clock frequency of clk_in. From equations 7 and 8, it can be seen that the output voltage after stabilization is inversely proportional to the input clock frequency, and the stabilization time is directly proportional to the resistance and capacitance.

[0066] refer to Figure 4 The diagram shown is a structural schematic of an automatic voltage calibration module provided in an embodiment of the present invention. The automatic voltage calibration module includes: a second resistor R2, a third resistor R3, a fourth resistor R4, a first comparator COMPB, a second comparator COMPA, and a successive approximation encoder 801.

[0067] The first end of the second resistor R2 is connected to the power supply voltage VDD. The second end of the second resistor R2 is electrically connected to the first end of the third resistor R3 and the non-inverting input of the first comparator COMPB. The second end of the third resistor R3 is electrically connected to the first end of the fourth resistor R4 and the inverting input of the second comparator COMPA. The second end of the fourth resistor R4 is electrically connected to the ground terminal.

[0068] The inverting input of the first comparator COMPB and the non-inverting input of the second comparator COMPA are both electrically connected to the output of the first frequency-to-voltage converter. The outputs of the first comparator COMPB and the second comparator COMPA are both electrically connected to the input side of the successive approximation encoder 801. The input side of the successive approximation encoder 801 is also connected to the main enable signal g_rstn and the calibration interval clock signal cal_interval_clk. The successive approximation encoder 801 is used to respond to the enable control of the main enable signal g_rstn, and outputs the voltage calibration code signal fvc_iset according to the comparison result of the first comparator COMPB and the second comparator COMPA, until the first frequency-to-voltage converter outputs the target reference voltage Vref, and outputs the calibration completion signal cal_en. The clock period of the calibration interval clock signal cal_interval_clk is used to define the duration of the calibration code of the voltage calibration code signal fvc_iset. The second resistor R2, the third resistor R3, and the fourth resistor R4 form a voltage divider circuit. The non-inverting input of the first comparator COMPB can be connected to a voltage of 9*VDD / 12, and the inverting input of the second comparator COMPA can be connected to a voltage of 5*VDD / 12. This invention does not impose specific limitations on these aspects.

[0069] In one embodiment of the present invention, the successive approximation encoder provided in the embodiment of the present invention is a 4-bit successive approximation encoder, that is, the voltage calibration encoding signal provided in the embodiment of the present invention is a 4-bit encoding signal.

[0070] Understandably, in the first and second frequency-to-voltage converters, the frequency-to-voltage conversion is affected by factors such as process technology, temperature, and power supply voltage. To eliminate these effects, this embodiment of the invention includes an automatic voltage calibration module. Before frequency calibration begins, the reference voltage of the frequency division reference clock is adjusted to a preset voltage range (e.g., 0.5V-0.9V). This optimizes the circuit's PVT performance and provides sufficient margin when comparing the target reference voltage and the target feedback voltage, preventing the inability to obtain comparison results due to excessively high or low reference voltages. Equation 7 shows that the DC voltage and charging current are directly proportional when stable. This invention can divide the charging current of the frequency-to-voltage converter into four levels: 4I, 2I, I, and 0.5I (e.g., 0.5V-0.9V). Figure 3 As shown, a 4-bit voltage calibration encoder signal is used to control and the reference voltage is calibrated using a successive approximation method. The 4-bit successive approximation encoder can be implemented using a shift register composed of D flip-flops.

[0071] Combination Figure 4 As shown, the working process of the automatic voltage calibration module provided in this embodiment of the invention is as follows:

[0072] Step 1: After the main enable signal g_rstn outputs the enable level, the initial code value of the voltage calibration encoding signal fvc_iset is 0000. At this time, the charging current of the frequency-to-voltage converter is 0, and the frequency will not be converted into a voltage value.

[0073] Step 2: At the first rising edge of the calibration interval clock signal cal_interval_clk, the code value of the voltage calibration encoding signal fvc_iset is set to 1000. At this time, the reference voltage Vref starts to rise from 0. After one cycle of cal_interval_clk, before the next rising edge of cal_interval_clk arrives, the DC current of the reference voltage Vref has three possibilities (taking a preset voltage range of 0.5V-0.9V as an example): The first case is Vref < 0.5V, indicating that Vref is too low and the current charging current needs to be increased. At this time, the output A of the second voltage comparator COMPA is 0, and the output B of CMOPB is 1. The successive approximation encoder 801 retains fvc_ based on the values ​​of A and B. The current code value of iset is changed to 1100 on the next rising edge of cal_interval_clk. In the second case, 0.5 < Vref < 0.9, A=1, B=1, which is the expected Vref value (i.e., the target reference voltage value). The successive approximation encoder 801 retains the current code value of fvc_iset according to the values ​​of A and B, sets the calibration completion signal cal_en to 1, and ends the voltage calibration. In the third case, Vref > 0.9, it means that Vref is too high and the current charging current needs to be reduced. In this case, A=1, B=0, and the successive approximation encoder 801 changes the code value of fvc_iset from 1000 to 0100 on the next rising edge of cal_interval_clk according to the values ​​of A and B.

[0074] Step 3: Repeat step 2 until A=1 and B=1. Set cal_en to 1 on the rising edge of the next cycle of cal_interval_clk to ensure the reference voltage value has stabilized. If all code values ​​of fvc_iset have been scanned without adjusting Vref to the preset voltage range, set cal_en to 1 when the code value of fvc_iset is 1111 or 0001 to end the calibration.

[0075] like Figure 5 The diagram shown is a structural schematic of a calibration module clock generator provided in an embodiment of the present invention. The calibration module clock generator provided in this embodiment of the present invention includes: an 1 / M frequency divider 901 and an AND gate circuit 902.

[0076] The input side of the 1 / M divider 901 is connected to the main enable signal g_rstn and the reference clock ref_clk. The 1 / M divider 901 is used to respond to the enable control of the main enable signal g_rstn, divide the reference clock ref_clk by M, and output the calibration interval clock signal cal_interval_clk.

[0077] The first input terminal of the AND gate circuit 902 is connected to the main enable signal g_rstn, and the second input terminal of the AND gate circuit 902 is connected to the calibration completion signal cal_en. The AND gate circuit is used to output the auxiliary enable signal rstn_cal by referring to the main enable signal g_rstn and the calibration completion signal cal_en.

[0078] Understandably, the clock generator of the calibration module provided in this embodiment of the invention controls the startup sequence of each component in the circuit and provides a calibration interval clock signal for defining the calibration duration of each calibration level for the frequency-voltage converter, the automatic voltage calibration module, and the forward and reverse successive approximation encoder. One clock cycle of the calibration interval clock signal calibrates one level. Since the frequency stabilization of the oscillator adjusted by the current adjustment code for each level requires a certain period of time, and the conversion from frequency to DC voltage by the frequency-voltage converter also requires a certain period of time to stabilize, the period of the calibration interval clock signal must be greater than the sum of the time t1 from the time the current adjustment code adjusts the oscillator frequency to stabilize, and the time t2 from the time the frequency-voltage converter converts the frequency to a stable DC voltage. The period of this calibration interval clock signal can be obtained through simulation or calculation. In the calibration module clock generator, the period is M-division of the reference clock (Tref / M, where Tref is the period of the reference clock), that is, Tref / M > t1 + t2.

[0079] Combination Figure 5 and Figure 6 As shown, before frequency calibration begins, the automatic voltage calibration module will automatically adjust the reference voltage to the optimal preset voltage range. After the main enable signal g_rstn outputs the enable level (set to 1), it begins to calibrate the reference voltage Vref output by the first frequency-voltage converter. Once the reference voltage Vref is adjusted to the preset voltage range and becomes the target reference voltage (e.g., ...), ... Figure 6 After the Vref automatic calibration time, the calibration completion signal cal_en of the voltage automatic calibration module is set to 1. At this moment, the auxiliary start signal rstn_cal outputs the enable level (set to 1) to control the entire system to start working.

[0080] refer to Figure 7 The diagram shown is a structural schematic of a forward and reverse successive approximation encoder provided in an embodiment of the present invention. The forward and reverse successive approximation encoder provided in this embodiment of the present invention includes: a fifth inverter INV5, a sixth inverter INV6, a Class D flip-flop DFF, an OR gate, a third AND gate AND3, a fourth AND gate AND4, a reverse successive approximation encoder B1, a forward successive approximation encoder B2, and a data selector MUX.

[0081] The D pin of the Class D flip-flop (DFF) is connected to a high level (1). The CLK pin of the Class D flip-flop (DFF) is electrically connected to the output of the fifth inverter (INV5). The enable terminal (RB) of the Class D flip-flop (DFF) is connected to the auxiliary enable signal (rstn_cal). The output terminal (Q) of the Class D flip-flop (DFF) is electrically connected to the input of the OR gate (OR). (It should be noted that the output terminal (Q) of the Class D flip-flop provided in this embodiment outputs an encoded signal. The number of bits of the encoded signal is the same as the number of bits of the output of the reverse successive approximation encoder (B1). The input of the OR gate (OR) is the same as the number of bits of the encoded signal, so as to perform OR logic processing on the encoded signal.) The output terminal of the OR gate (OR) is electrically connected to the input of the sixth inverter (INV6), the first input of the fourth AND gate (AND4), and the control selection terminal (en) of the data selector (MUX). The data selector (MUX) selects to output the encoded signal of B1 or B2 according to the control selection terminal signal.

[0082] The output of the sixth inverter INV6 is electrically connected to the second input of the third AND gate AND3. The first input of the third AND gate AND3 is connected to the calibration interval clock signal cal_interval_clk. The output of the third AND gate AND3 is electrically connected to the input side of the reverse successive approximation encoder B1. The input side of the reverse successive approximation encoder B1 is also electrically connected to the output of the main comparator COMP. The input side of the reverse successive approximation encoder B1 is also connected to the auxiliary enable signal rstn_cal. The output of the reverse successive approximation encoder B1 is electrically connected to the input of the fifth inverter INV5 and the input of the data selector MUX.

[0083] The second input terminal of the fourth AND gate AND4 is connected to the calibration interval clock signal cal_interval_clk. The output terminal of the fourth AND gate AND4 is electrically connected to the input side of the positive successive approximation encoder B2. The input side of the positive successive approximation encoder B2 is also electrically connected to the output terminal COMP of the main comparator. The input side of the positive successive approximation encoder B2 is also connected to the auxiliary enable signal rstn_cal. The output terminal of the positive successive approximation encoder B2 is electrically connected to the input side of the data selector MUX.

[0084] In one embodiment of the present invention, the fifth inverter and the Class D flip-flop are actually composed of multiple substructures, and the number of substructures is the same as the number of bits of the code output by the reverse successive approximation encoder. That is, the fifth inverter includes multiple sub-inverters, and the Class D flip-flop includes multiple sub-Class D flip-flops. The input of the sub-inverter is connected to one bit of the code output by the reverse successive approximation encoder, the output of the sub-inverter is electrically connected to the CLK pin of the sub-Class D flip-flop, the D pin of the sub-Class D flip-flop is connected to a high level, and the RB pin of the sub-Class D flip-flop is connected to an auxiliary enable signal. The reverse successive approximation encoder and the forward successive approximation encoder provided by the present invention are both 8-bit successive approximation encoders.

[0085] Understandably, the forward and reverse successive approximation encoder provided in this embodiment of the invention converts the comparison result of the DC voltages finally converted from the reference clock and the feedback clock into a current adjustment code. The current adjustment code controls the current adjustment circuit to output a matching current to adjust the output frequency of the oscillator. After multiple cycles, the frequency calibration is finally achieved. The algorithm of the forward and reverse successive approximation encoder is to first output the code value from the low bit to the high bit, at which point the frequency of the feedback clock is less than the frequency of the reference clock. When the code value increases to the point where the frequency of the feedback clock is greater than the frequency of the reference clock, the code value is then successively decreased from the current code value, that is, output from the high bit to the low bit, until the frequency of the feedback clock is adjusted to the corresponding range of the frequency of the reference clock.

[0086] Combination Figure 7 As shown, the working process of the forward and reverse successive approximation encoder provided in this embodiment of the invention is as follows:

[0087] Step 1: After the target reference voltage is obtained after the reference voltage Vref is calibrated, cal_en is set to 1, rstn_cal is set to 1, and the main comparator 500, the second frequency voltage converter 420, and the forward and reverse successive approximation encoder 600 start working. The corresponding clock of B1 is turned on and works first, while the corresponding clock of B2 is turned off and does not work. At this time, the code value band output by the data selector MUX is output by B1. The 8-bit band starts from 00000000. Before the rising edge of the next cal_interval_clk arrives, the relationship between the frequency Fref of the mapped ref_clk and the frequency Ffb of fb_clk is determined based on the output result of the main comparator 500. If the main comparator 500 outputs CO When MP=1 (i.e., the work termination signal), the band remains at 00000000 when the rising edge of the next cal_interval_clk arrives, and the calibration ends. If the main comparator 500 outputs COMP=0 (i.e., the work hold signal), the band becomes 00000001 when the rising edge of the next cal_interval_clk arrives. Repeat the above steps. Assuming that the main comparator 500 determines COMP=0 until the band becomes 00001111, the clock of B1 is turned off to stop working, the clock of B2 is turned on to start working, and the initial output band code value of B2 is set to 00010000. At the same time, the data selector MUX selects the code value of B2 for output.

[0088] Step 2: Before the rising edge of the next cal_interval_clk arrives, determine the relationship between Fref and Ffb when band is 00010000. If the difference between the two is within the allowable range, band remains at 00010000 when the rising edge of the next cal_interval_clk arrives; if the difference between Fref and Ffb is outside the allowable range, band becomes 00011000 when the rising edge of the next cal_interval_clk arrives.

[0089] Step 3: Continue the judgment and calibration process from Step 2 above until the band becomes the least significant bit of the code value. Once the judgment is completed and the difference between Fref and Ffb is within the allowable range, the calibration ends and the phase-locked loop begins closed-loop operation.

[0090] In one embodiment of the present invention, the oscillator provided by the present invention is a VCO or an OSC (active crystal oscillator), and the present invention does not impose specific limitations on it.

[0091] Compared with the prior art, the technical solution provided by the embodiments of the present invention has at least the following advantages:

[0092] This invention provides a self-calibration system for phase-locked loop (PLL) frequency. In the open-loop state of the PLL, the system converts the frequency-divided reference clock and frequency-divided feedback clock into their respective DC voltages, and then compares these DC voltages to derive the relationship between the response clock frequency and the actual frequency. This eliminates the need for digital circuitry, thus avoiding frequency limitations and making it suitable for pure analog chips and easy to integrate. Furthermore, this invention employs a successive approximation method, using a coding output method that proceeds from the least significant bit to the most significant bit and then from the most significant bit to the least significant bit to determine the final current adjustment code. Compared to existing schemes that obtain the current adjustment code by incrementing or decrementing the code value from the middle bit, this invention avoids calibration failures caused by the oscillator frequency exceeding the frequency divider's oscillation frequency limit when the current adjustment code is in the middle bit. Moreover, the successive approximation method in this invention also offers the advantages of fewer calibration cycles and higher calibration efficiency.

[0093] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A self-calibration system for the frequency of a phase-locked loop, characterized by, The application relates to a phase-locked loop (PLL) circuit, comprising: a loop divider, an input end of the loop divider being connected to an output clock of an oscillator of the phase-locked loop; the loop divider is used for outputting a divided feedback clock; a first frequency divider and a second frequency divider, an input end of the first frequency divider being connected to a reference clock, and an input end of the second frequency divider being electrically connected to an output end of the loop divider; the first frequency divider is used for outputting a divided reference clock after dividing the reference clock, and the second frequency divider is used for outputting a divided feedback clock after dividing the feedback clock, wherein duty cycles of the divided reference clock and the divided feedback clock are the same; a first frequency-voltage converter and a second frequency-voltage converter, an input side of the first frequency-voltage converter being connected to the divided reference clock, a main start signal and a voltage calibration code signal, and an input side of the second frequency-voltage converter being connected to the divided feedback clock, an auxiliary start signal and the voltage calibration code signal; the first frequency-voltage converter is used for converting a frequency of the divided reference clock into a reference voltage according to the voltage calibration code signal and the divided reference clock in response to enable control of the main start signal, until the frequency of the divided reference clock is converted into a target reference voltage in a preset voltage range when the voltage calibration code signal is a target calibration code; and the second frequency-voltage converter is used for converting a frequency of the divided feedback clock into a target feedback voltage according to the target calibration code and the divided feedback clock in response to enable control of the auxiliary start signal; a main comparator, the main comparator being connected to the target reference voltage and the target feedback voltage; the main comparator is used for comparing the target reference voltage and the target feedback voltage, and outputting a work holding signal when a difference between the target reference voltage and the target feedback voltage is greater than a preset range, and outputting a work termination signal when the difference between the target reference voltage and the target feedback voltage is within the preset range; a positive and negative successive approximation encoder, an input end of the positive and negative successive approximation encoder being electrically connected to an output end of the main comparator, and being connected to the auxiliary start signal and a calibration interval clock signal; the positive and negative successive approximation encoder is used for successively outputting current adjustment codes according to the work holding signal which is successively connected in response to enable control of the auxiliary start signal, and referring to an encoding output mode from low bits to high bits and then from high bits to low bits, until the current adjustment code is kept outputted when the work termination signal is connected, wherein a clock period of the calibration interval clock signal is used for defining a time length of the current adjustment code; a current adjustment circuit, an input end of the current adjustment circuit being electrically connected to an output end of the positive and negative successive approximation encoder, and an output end of the current adjustment circuit being connected to the oscillator of the phase-locked loop; the current adjustment circuit is used for outputting a control current matched with the current adjustment code to the oscillator of the phase-locked loop according to the current adjustment code. A voltage automatic calibration module, an input side of the voltage automatic calibration module is electrically connected with an output end of the first frequency-voltage converter, and accesses the main start signal and the calibration interval clock signal, the voltage automatic calibration module is used for outputting the voltage calibration code signal according to a difference between the reference voltage and the preset voltage range in response to the enable control of the main start signal, and outputting a calibration completion signal when the first frequency-voltage converter outputs the target reference voltage, wherein a clock period of the calibration interval clock signal is used for defining a time length of a calibration code of the voltage calibration code signal; A calibration module clock generator, an input side of the calibration module clock generator accesses the main start signal, the reference clock and the calibration completion signal; the calibration module clock generator is used for outputting the calibration interval clock signal according to the reference clock in response to the enable control of the main start signal; and outputting the auxiliary start signal in reference to the main start signal and the calibration completion signal.

2. The self-calibration system of phase-locked loop frequency as claimed in claim 1, wherein, The first frequency divider and the second frequency divider are both two-frequency dividers.

3. The self-calibrating system of phase-locked loop frequency as claimed in claim 1, wherein, Any one of the first frequency-voltage converter and the second frequency-voltage converter comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first delay module, a second delay module, a first AND gate, a second AND gate, a first difference module, a second difference module and a voltage output module; An input end of the first inverter and a first input end of the first AND gate are electrically connected to access an input clock, the input clock is the frequency-divided reference clock or the frequency-divided feedback clock, an output end of the first inverter is electrically connected with an input end of the first delay module, an output end of the first delay module is electrically connected with a second input end of the first AND gate and an input end of the second inverter, an output end of the first AND gate is electrically connected with an input end of the first difference module, a first output end of the first difference module and a second output end of the first difference module are both electrically connected with the voltage output module, and the first output end of the first difference module and the second output end of the first difference module are used for outputting a first difference signal; An output end of the second inverter is electrically connected with an input end of the third inverter and a first input end of the second AND gate, an output end of the third inverter is electrically connected with an input end of the second delay module, an output end of the second delay module is electrically connected with a second input end of the second AND gate, an output end of the second AND gate is electrically connected with the second difference module, a first output end of the second difference module and a second output end of the second difference module are both electrically connected with the voltage output module, and the first output end of the second difference module and the second output end of the second difference module are used for outputting a second difference signal; An input end of the fourth inverter is connected to a response signal, the response signal being the main start signal or the auxiliary start signal, and an output end of the fourth inverter is electrically connected to the voltage output module; wherein the voltage output module is configured to generate an output voltage by referring to the first differential signal, the second differential signal, the output signal of the fourth inverter, the input clock and the voltage calibration coding signal, the output voltage being the reference voltage or the target feedback voltage.

4. The self-calibration system of phase-locked loop frequency as claimed in claim 3, wherein, The voltage output module comprises a first P-type transistor, a second P-type transistor, a third P-type transistor, a fourth P-type transistor, a fifth P-type transistor, a sixth P-type transistor, a seventh P-type transistor, an eighth P-type transistor, a ninth P-type transistor, a tenth P-type transistor, an eleventh P-type transistor, a twelfth P-type transistor, a first N-type transistor, a second N-type transistor, a third N-type transistor, a fourth N-type transistor, a first resistor, a first capacitor and a second capacitor. First ends of the first P-type transistor, the second P-type transistor, the third P-type transistor, the fourth P-type transistor and the fifth P-type transistor are electrically connected, and gates of the first P-type transistor, the second P-type transistor, the third P-type transistor, the fourth P-type transistor and the fifth P-type transistor are electrically connected; a second end of the first P-type transistor is connected to a current source, and the second end of the first P-type transistor is electrically connected to the gate thereof; a second end of the second P-type transistor is electrically connected to a first end of the sixth P-type transistor, a second end of the third P-type transistor is electrically connected to a first end of the seventh P-type transistor, a second end of the fourth P-type transistor is electrically connected to a first end of the eighth P-type transistor, a second end of the fifth P-type transistor is electrically connected to a first end of the ninth P-type transistor, second ends of the sixth P-type transistor, the seventh P-type transistor, the eighth P-type transistor and the ninth P-type transistor are electrically connected and electrically connected to a first end of the tenth P-type transistor and a first end of the first N-type transistor, and gates of the sixth P-type transistor, the seventh P-type transistor, the eighth P-type transistor and the ninth P-type transistor are connected to the voltage calibration coding signal; The gate of the tenth P-type transistor and the gate of the first N-type transistor are connected to the input clock, and the second end of the first N-type transistor is electrically connected to the ground terminal; the second end of the tenth P-type transistor is electrically connected to the first end of the first resistor, the first end of the first capacitor, the first end of the eleventh P-type transistor, the first end of the second N-type transistor and the first end of the fourth N-type transistor, the second end of the first resistor is electrically connected to the first end of the twelfth P-type transistor and the first end of the third N-type transistor, the second end of the twelfth P-type transistor and the second end of the third N-type transistor are electrically connected to the ground terminal, the gate of the twelfth P-type transistor and the gate of the third N-type transistor are connected to the second differential signal, the second end of the first capacitor and the second end of the fourth N-type transistor are electrically connected to the ground terminal, the gate of the fourth N-type transistor is electrically connected to the output terminal of the fourth inverter, the second end of the eleventh P-type transistor and the second end of the second N-type transistor are electrically connected to the first end of the second capacitor, and the gate of the eleventh P-type transistor and the gate of the second N-type transistor are connected to the first differential signal; the second end of the second capacitor is electrically connected to the ground terminal.

5. The self-calibrating system of phase-locked loop frequency as claimed in claim 1, wherein, The voltage automatic calibration module comprises a second resistor, a third resistor, a fourth resistor, a first comparator, a second comparator and a successive approximation encoder. The first end of the second resistor is connected to a power supply voltage, the second end of the second resistor is electrically connected to the first end of the third resistor and the non-inverting terminal of the first comparator, the second end of the third resistor is electrically connected to the first end of the fourth resistor and the inverting terminal of the second comparator, and the second end of the fourth resistor is electrically connected to the ground terminal. The non-inverting terminal of the first comparator and the non-inverting terminal of the second comparator are electrically connected to the output terminal of the first frequency-voltage converter, the output terminal of the first comparator and the output terminal of the second comparator are electrically connected to the input side of the successive approximation encoder, and the input side of the successive approximation encoder is also connected to the main start signal and the calibration interval clock signal, wherein the successive approximation encoder is configured to output the voltage calibration code signal according to the comparison result of the first comparator and the second comparator in response to the enable control of the main start signal, and output the calibration completion signal when the first frequency-voltage converter outputs the target reference voltage, wherein the clock period of the calibration interval clock signal is used to define the duration of the calibration code of the voltage calibration code signal.

6. The self-calibration system of phase-locked loop frequency as claimed in claim 5, wherein, The successive approximation encoder is a 4-bit successive approximation encoder.

7. The self-calibrating system of phase-locked loop frequency as claimed in claim 1, wherein, The calibration module clock generator comprises a 1 / M frequency divider and an AND gate circuit. The input side of the 1 / M frequency divider is connected to the main start signal and the reference clock, and the 1 / M frequency divider is configured to output the calibration interval clock signal by performing M frequency division on the reference clock in response to the enable control of the main start signal. The first input end of the AND gate circuit is connected to the main opening signal, and the second input end of the AND gate circuit is connected to the calibration completion signal.

8. The self-calibrating system of phase-locked loop frequency as claimed in claim 1, wherein, The positive and negative successive approximation encoders comprise a fifth inverter, a sixth inverter, a D-type flip-flop, an OR gate, a third AND gate, a fourth AND gate, a negative successive approximation encoder, a positive successive approximation encoder and a data selector. The D pin of the D-type flip-flop is connected to a high level, the CLK pin of the D-type flip-flop is electrically connected to the output end of the fifth inverter, the enable end of the D-type flip-flop is connected to the auxiliary opening signal, the output end of the D-type flip-flop is electrically connected to the input end of the OR gate, and the output end of the OR gate is electrically connected to the input end of the sixth inverter, the first input end of the fourth AND gate and the control selection end of the data selector. The output end of the sixth inverter is electrically connected to the second input end of the third AND gate, the first input end of the third AND gate is connected to the calibration interval clock signal, the output end of the third AND gate is electrically connected to the input side of the negative successive approximation encoder, the input side of the negative successive approximation encoder is also electrically connected to the output end of the main comparator, and the input side of the negative successive approximation encoder is also connected to the auxiliary opening signal, the output end of the negative successive approximation encoder is electrically connected to the input end of the fifth inverter and the input side of the data selector. The second input end of the fourth AND gate is connected to the calibration interval clock signal, the output end of the fourth AND gate is electrically connected to the input side of the positive successive approximation encoder, the input side of the positive successive approximation encoder is also electrically connected to the output end of the main comparator, and the input side of the positive successive approximation encoder is also connected to the auxiliary opening signal, and the output end of the positive successive approximation encoder is electrically connected to the input side of the data selector.

9. The self-calibration system of phase-locked loop frequency as claimed in claim 8, characterized in that, The negative successive approximation encoder and the positive successive approximation encoder are both 8-bit successive approximation encoders.

10. The self-calibrating system of phase-locked loop frequency as claimed in claim 1, wherein, The oscillator is a VCO or an OSC.

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