Method for manufacturing circuit board and circuit board

Abstract

A method for manufacturing a circuit board includes the following steps: providing a carrier; forming a first circuit substrate on the surface of the carrier, the first circuit substrate including a to-be-removed area, and the to-be-removed area penetrates the first circuit substrate along the stacking direction of the first circuit substrate and the carrier; cutting the to-be-removed area along the stacking direction; covering the surface of the to-be-removed area away from the carrier with an isolation layer; forming a second circuit substrate on the surface of the first circuit substrate away from the carrier, the second circuit substrate covering the isolation layer; and removing the to-be-removed area and the carrier to form the circuit board with a cavity. The present application also provides a circuit board.

Description

Technical Field

[0001] The present application relates to the field of circuit boards, and in particular to a method for manufacturing a circuit board and a circuit board. Background Art

[0002] As people's demand for various electronic products such as computers, consumer electronics and communications increases, the signal transmission rate requirements for circuit boards in electronic products are also increasing.

[0003] The transmission rate of circuit board signals can be increased by setting high-frequency materials, but high-frequency materials are expensive and difficult to use on a large scale. The production cost can be reduced by mixing high-frequency materials with ordinary materials, but the production difficulty is high. Summary of the invention

[0004] In view of this, it is necessary to provide a method for manufacturing a circuit board and a circuit board with low cost and low manufacturing difficulty.

[0005] A method for manufacturing a circuit board comprises the following steps:

[0006] providing a carrier;

[0007] A first circuit substrate is formed on the surface of the carrier, wherein the first circuit substrate includes a to-be-removed area, and along the stacking direction of the first circuit substrate and the carrier, the to-be-removed area penetrates the first circuit substrate;

[0008] Cutting the to-be-removed area along the stacking direction;

[0009] Covering the surface of the to-be-removed area away from the carrier with an isolation layer;

[0010] forming a second circuit substrate on a surface of the first circuit substrate facing away from the carrier, wherein the second circuit substrate covers the isolation layer; and

[0011] The to-be-removed area and the carrier are removed to form the circuit board having a cavity.

[0012] In some embodiments, before the step of forming the first circuit substrate on the surface of the carrier, the step of forming a metal layer on the surface of the carrier is also included; in the step of forming the first circuit substrate, the first circuit substrate is formed on the surface of the metal layer facing away from the carrier.

[0013] In some embodiments, after the step of removing the area to be removed and the carrier, the step of etching the metal layer is further included to form the circuit board.

[0014] In some embodiments, the first circuit substrate includes a first dielectric layer and a first circuit layer buried in the first dielectric layer; and the area to be removed is composed of the first dielectric layer.

[0015] In some embodiments, the isolation layer further extends to the surface of the first dielectric layer around the area to be removed.

[0016] In some embodiments, the second circuit substrate includes a second dielectric layer and a second circuit layer buried in the second dielectric layer.

[0017] In some embodiments, a ratio of a dielectric constant to a dielectric loss factor of the second dielectric layer is smaller than a ratio of a dielectric constant to a dielectric loss factor of the first dielectric layer.

[0018] A circuit board comprises a first circuit substrate, a second circuit substrate and an isolation layer, wherein the second circuit substrate is stacked on a surface of the first circuit substrate; along the stacking direction of the first circuit substrate and the second circuit substrate, the first circuit substrate has a cavity penetrating the first circuit substrate; the isolation layer is located on the surface of the second circuit substrate facing the first circuit substrate and is exposed to the cavity.

[0019] In some embodiments, the first circuit substrate includes a first dielectric layer and a first circuit layer buried in the first dielectric layer; the second circuit substrate includes a second dielectric layer and a second circuit layer buried in the second dielectric layer; the second circuit layer is electrically connected to the first circuit layer, and the ratio of the dielectric constant to the dielectric loss factor of the second dielectric layer is smaller than the ratio of the dielectric constant to the dielectric loss factor of the first dielectric layer.

[0020] In some embodiments, a periphery of the isolation layer is embedded between the first circuit substrate and the second circuit substrate.

[0021] The manufacturing method of the circuit board provided by the present application provides a first circuit substrate with the same depth as the hole according to the depth of the hole to be formed; cuts are made in a specific area (i.e., the area to be removed) where the hole needs to be formed; an isolation layer is covered on the surface of the area to be removed; a second circuit substrate is formed on the surface of the first circuit substrate, and the cut area to be removed is removed to form a circuit board with a hole. That is, by controlling the thickness of the first circuit substrate and thus accurately controlling the depth of the hole, a hole of any depth can be made; in the process of cutting the area to be removed to form the hole, the cutting difficulty is low, the manufacturing difficulty is small, and the other first dielectric layers and the first circuit layer in the first circuit substrate will not be affected; in addition, the cutting step will not affect the second dielectric layer and the second circuit layer in the second circuit substrate before the second circuit substrate is formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A cross-sectional schematic diagram of forming a metal layer on the surface of a carrier provided in an embodiment of the present application.

[0023] Figure 2 For Figure 1 The metal layer surface shown is a schematic cross-sectional view of forming a first circuit substrate.

[0024] Figure 3 For cutting Figure 2 A schematic cross-sectional view of the area to be removed in the first circuit substrate.

[0025] Figure 4 For Figure 3 The schematic cross-sectional view of the surface of the area to be removed being covered with an isolation layer is shown.

[0026] Figure 5 For Figure 4 A schematic cross-sectional view of a second circuit substrate formed on the surface of the first circuit substrate.

[0027] Figure 6 To remove Figure 5 A schematic cross-sectional view of the area to be removed and the carrier is shown.

[0028] Figure 7 For etching Figure 6 Schematic diagram of the cross section of the circuit board obtained by the metal layer shown.

[0029] Main component symbols

[0030] Circuit Board 100 Carrier 10 Base material layer 12 Peeling layer 14 Metal layer 20 First circuit substrate 30 The first dielectric layer 32 First circuit layer 34 Area to be removed 36 Isolation layer 40 Second circuit substrate 50 Second dielectric layer 52 Second circuit layer 54 Hole 60 Overlay direction L

[0031] The following specific implementation methods will further illustrate the present application in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0032] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the present application is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other. In the following description, many specific details are set forth to facilitate a full understanding of the present application, and the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes all and any combination of one or more related listed items.

[0034] See also Figures 1 to 7 , an embodiment of the present application provides a method for manufacturing a circuit board 100, including steps S1-S7.

[0035] Step S1: Please refer to Figure 1 , a carrier 10 is provided, wherein the carrier 10 includes a substrate layer 12 and a peeling layer 14 located on a surface of the substrate layer 12 , and a metal layer 20 is formed on a surface of the peeling layer 14 away from the substrate layer 12 .

[0036] The carrier 10 plays a bearing role. The material of the substrate layer 12 is not limited as long as it meets a certain hardness.

[0037] The peeling layer 14 may be located on one surface of the substrate layer 12, or on two opposite surfaces of the substrate layer 12. In this embodiment, the peeling layer 14 is located on two opposite surfaces of the substrate layer 12. The peeling layer 14 and the metal layer 20 need to be separated from each other during subsequent processing, so the peeling layer 14 serves to temporarily connect the substrate layer 12 and the metal layer 20.

[0038] The peeling layer 14 may be made of a metal material or an insulating material. In this embodiment, the peeling layer 14 is made of copper, which can further enhance the hardness of the carrier 10 .

[0039] In this embodiment, the number of the metal layers 20 is two, which are respectively located on the surfaces of the two peeling layers 14 away from the substrate layer 12. The material of the metal layer 20 can be a conductive material such as copper, silver, nickel, etc. The metal layer 20 facilitates the formation of subsequent circuit layers. In some embodiments, the metal layer 20 can also be omitted.

[0040] Step S2: Please refer to Figure 2 A first circuit substrate 30 is formed on the surface of the carrier 10 , wherein the first circuit substrate 30 includes a to-be-removed area 36 , and along a stacking direction L of the first circuit substrate 30 and the carrier 10 , the to-be-removed area 36 penetrates the first circuit substrate 30 .

[0041] In some embodiments, the first circuit substrate 30 may be formed on the surface of one of the metal layers 20 . In other embodiments, the first circuit substrates 30 may be formed independently of each other on the surfaces of the two metal layers 20 .

[0042] In this embodiment, the first circuit substrates 30 are formed on the surfaces of the two metal layers 20. Each of the first circuit substrates 30 includes a first dielectric layer 32 and a first circuit layer 34. The number of layers of the first dielectric layer 32 and the first circuit layer 34 can be one or more layers. The number of layers of the first dielectric layer 32 and the first circuit layer 34 depends on the cavity 60 to be formed later (see Figure 7 ) is set. Wherein, along the stacking direction, the thickness of the first circuit substrate 30 is equal to the depth of the cavity 60 to be formed.

[0043] The first circuit layer 34 is connected to the metal layer 20 .

[0044] Along the stacking direction L, the first circuit layer 34 is not set in at least a partial area of ​​the first dielectric layer 32 to form the area to be removed 36, that is, the area to be removed 36 is completely composed of the first dielectric layer 32, so as to prevent damage to the first circuit layer 34 when a part of the first dielectric layer 32 (that is, the area to be removed 36) is cut along the stacking direction L later.

[0045] The material of the first dielectric layer 32 can be selected from E Glass series PP, such as E-770G, E-705G, EM-390, etc.

[0046] When the first circuit layer 34 is multi-layered, the multi-layered first circuit layers 34 are electrically connected to each other through conductive holes (not marked in the figure).

[0047] Step S3: Please refer to Figure 3 , along the stacking direction L, cutting the area to be removed 36.

[0048] When the to-be-removed area 36 is cut, the first circuit substrate 30 located on opposite sides of the carrier 10 is penetrated, and the metal layer 20 and the carrier 10 are also penetrated. It can be understood that during the process of cutting the to-be-removed area 36, ​​the first circuit layer 34 in the first circuit substrate 30 will not be damaged.

[0049] Step S4: Please refer to Figure 4 The surface of the to-be-removed area 36 facing away from the carrier 10 is covered with an isolation layer 40 .

[0050] Subsequently, a second circuit substrate 50 is formed on the surface of the first circuit substrate 30 (see Figure 5 ), the to-be-removed area 36 is not removed temporarily after cutting to prevent the formation of a cavity after removal. In the process of forming the second circuit substrate 50, the second circuit substrate 50 is recessed toward the cavity, thereby causing the formed second circuit substrate 50 to be uneven.

[0051] The isolation layer 40 is made of an insulating material and is used to isolate the first dielectric layer 32 of the area to be removed 36 and the second dielectric layer 52 subsequently formed on the surface of the first circuit substrate 30 to prevent the first dielectric layer 32 from adhering to the second dielectric layer 52 and making it difficult to remove the area to be removed 36 .

[0052] Furthermore, the isolation layer 40 covers the area to be removed 36 and extends to the surface of the first dielectric layer 32 around the area to be removed 36. Since the area to be removed 36 is composed of the first dielectric layer 32, the hardness of the area to be removed 36 is smaller than that of other areas with the first circuit layer 34. In the process of forming the second circuit substrate 50, the area to be removed 36 is more likely to be deformed. The isolation layer 40 extends to the surface of the first dielectric layer 32 around the area to be removed 36, which can ensure the flatness of the formed second circuit substrate 50 and prevent the isolation layer 40 from being recessed toward the carrier 10 along with the area to be removed 36 during the process of forming the second circuit substrate 50, thereby causing the second circuit substrate 50 to be recessed as well.

[0053] Step S5: Please refer again Figure 5 A second circuit substrate 50 is formed on a surface of the first circuit substrate 30 facing away from the carrier 10 , and the second circuit substrate 50 also covers the isolation layer 40 .

[0054] The second circuit substrate 50 includes a second dielectric layer 52 and a second circuit layer 54 embedded in the second dielectric layer 52. The number of layers of the second dielectric layer 52 and the second circuit layer 54 is not limited and can be one or more layers. The second circuit layer 54 is electrically connected to the first circuit layer 34.

[0055] The material of the second dielectric layer 52 can be selected from LD Glass series PP, ABF, etc., such as HL972LFG (LD), HS-200 (D). k ) and dielectric loss factor (D f ) ratio (D k / D f ) is less than the ratio of the dielectric constant to the dielectric loss factor of the first dielectric layer 32. That is, the transmission rate of the signal in the second dielectric layer 52 is greater than the transmission rate in the first dielectric layer 32.

[0056] Step S6: Please refer to Figure 6 , remove the to-be-removed area 36 and the carrier 10.

[0057] After the to-be-removed area 36 is removed, a cavity 60 is formed. The transmission rate of the signal in the cavity 60 is greater than the transmission rate in the first dielectric layer 32. By providing the cavity 60 in the first circuit substrate 30, the transmission rate of the signal in the first circuit substrate 30 is increased, thereby maintaining the consistency of the transmission rate of the signal in the first circuit substrate 30 and the second circuit substrate 50 while reducing the cost.

[0058] It can be understood that, along the stacking direction L, the depth of the cavity 60 is equal to the thickness of the first circuit substrate 30 .

[0059] After the to-be-removed area 36 is removed, the isolation layer 40 is exposed to the cavity 60 , and the periphery of the isolation layer 40 is embedded between the first circuit substrate 30 and the second circuit substrate 50 .

[0060] Step S7: Please refer to Figure 7 , etching the metal layer 20 to form the circuit board 100.

[0061] In some embodiments, when the metal layer 20 is not disposed on the surface of the carrier 10 , step S7 may be omitted accordingly.

[0062] Please refer again Figure 7 The present application also provides a circuit board 100 , which includes a first circuit substrate 30 , a second circuit substrate 50 and an isolation layer 40 , wherein the second circuit substrate 50 is stacked on a surface of the first circuit substrate 30 .

[0063] Along the stacking direction L of the first circuit substrate 30 and the second circuit substrate 50 , the first circuit substrate 30 has a cavity 60 penetrating the first circuit substrate 30 . That is, along the stacking direction L, the depth of the cavity 60 is equal to the thickness of the first circuit substrate 30 .

[0064] The isolation layer 40 is located on a surface of the second circuit substrate 50 facing the first circuit substrate 30 and is exposed to the cavity 60 . The periphery of the isolation layer 40 is embedded between the first circuit substrate 30 and the second circuit substrate 50 .

[0065] The first circuit substrate 30 includes a first dielectric layer 32 and a first circuit layer 34 buried in the first dielectric layer 32 .

[0066] The second circuit substrate 50 includes a second dielectric layer 52 and a second circuit layer 54 buried in the second dielectric layer 52. The second circuit layer 54 is electrically connected to the first circuit layer 34.

[0067] The material of the first dielectric layer 32 can be selected from E Glass series PP, such as E-770G, E-705G, EM-390, etc.; the material of the second dielectric layer 52 can be selected from LD Glass series PP, ABF, etc., such as HL972LFG (LD), HS-200 (D), etc. The dielectric constant (D k ) and dielectric loss factor (D f ) ratio (D k / D f ) is less than the ratio of the dielectric constant to the dielectric loss factor of the first dielectric layer 32. The transmission rate of the signal in the second dielectric layer 52 is greater than the transmission rate in the first dielectric layer 32. By setting a low-cost first dielectric layer 32 in the circuit board 100, the production cost of the circuit board 100 can be reduced; the cavity 60 is set in the first circuit substrate 30 to increase the transmission rate of the signal in the first circuit substrate 30, so that the consistency of the transmission rate of the signal in the first circuit substrate 30 and the second circuit substrate 50 can be maintained on the basis of reducing the cost.

[0068] The manufacturing method of the circuit board 100 provided in the present application provides a first circuit substrate 30 with the same depth as the cavity 60 according to the depth of the cavity 60 to be formed; cuts are made in a specific area (i.e., the area to be removed 36) where the cavity 60 is to be formed; covers the surface of the area to be removed 36 with an isolation layer 40; and then forms a second circuit substrate 50 on the surface of the first circuit substrate 30, and removes the cut area to be removed 36 to form a circuit board 100 with the cavity 60. That is, by controlling the thickness of the first circuit substrate 30 and thus accurately controlling the depth of the cavity 60, a cavity 60 of any depth can be manufactured; in the process of cutting the area to be removed 36 to form the cavity 60, the cutting difficulty is low, the manufacturing difficulty is small, and the other first dielectric layers 32 and the first circuit layer 34 in the first circuit substrate 30 will not be affected; in addition, the cutting step will not affect the second dielectric layer 52 and the second circuit layer 54 in the second circuit substrate 50 before the second circuit substrate 50 is formed.

[0069] The above implementation modes are only used to illustrate the technical solutions of the present application and are not intended to limit the present application. Although the present application has been described in detail with reference to the above preferred implementation modes, a person skilled in the art should understand that the technical solutions of the present application may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present application.

Claims

1. A method for manufacturing a circuit board, characterized in that: The following steps are involved: providing a carrier; A first circuit substrate is formed on the surface of the carrier, wherein the first circuit substrate includes a to-be-removed area, and along the stacking direction of the first circuit substrate and the carrier, the to-be-removed area penetrates the first circuit substrate; Cutting the to-be-removed area along the stacking direction; Covering the surface of the to-be-removed area away from the carrier with an isolation layer; forming a second circuit substrate on a surface of the first circuit substrate away from the carrier, wherein the second circuit substrate covers the isolation layer; as well as Removing the to-be-removed area and the carrier to form the circuit board having a cavity; Among them, the first circuit substrate includes a first dielectric layer and a first circuit layer buried in the first dielectric layer, and the area to be removed is composed of the first dielectric layer; the second circuit substrate includes a second dielectric layer and a second circuit layer buried in the second dielectric layer; the ratio of the dielectric constant to the dielectric loss factor of the second dielectric layer is smaller than the ratio of the dielectric constant to the dielectric loss factor of the first dielectric layer.

2. The method for manufacturing a circuit board according to claim 1, characterized in that: Before the step of forming the first circuit substrate on the surface of the carrier, the method further includes the step of forming a metal layer on the surface of the carrier; in the step of forming the first circuit substrate, the first circuit substrate is formed on the surface of the metal layer away from the carrier.

3. The method for manufacturing a circuit board according to claim 2, characterized in that: After the step of removing the to-be-removed area and the carrier, the method further includes a step of etching the metal layer to form the circuit board.

4. The method for manufacturing a circuit board according to claim 1, characterized in that: The isolation layer also extends to the surface of the first dielectric layer around the area to be removed.

5. A circuit board manufactured by the method for manufacturing a circuit board according to any one of claims 1 to 4, characterized in that: The circuit board includes a first circuit substrate, a second circuit substrate and an isolation layer, wherein the second circuit substrate is stacked on a surface of the first circuit substrate; along the stacking direction of the first circuit substrate and the second circuit substrate, the first circuit substrate has a cavity penetrating the first circuit substrate; the isolation layer is located on the surface of the second circuit substrate facing the first circuit substrate and is exposed to the cavity; the first circuit substrate includes a first dielectric layer and a first circuit layer buried in the first dielectric layer; the second circuit substrate includes a second dielectric layer and a second circuit layer buried in the second dielectric layer; the second circuit layer is electrically connected to the first circuit layer, and the ratio of the dielectric constant to the dielectric loss factor of the second dielectric layer is smaller than the ratio of the dielectric constant to the dielectric loss factor of the first dielectric layer.

6. The circuit board according to claim 5, characterized in that: The periphery of the isolation layer is embedded between the first circuit substrate and the second circuit substrate.

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