Memory Built-In Self-Test with Automatic Reference Fine-Tuning Feedback for Memory Sensing

Abstract

The present application discloses a memory built-in self-test system to prompt a storage device to sense a value of stored data using reference fine-tuning during a memory read operation. The memory built-in self-test system can automatically set reference fine-tuning for the storage device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the storage device to perform a memory read operation using different test values for reference fine-tuning. The memory built-in self-test system further includes a fine-tuning feedback circuit to determine when the storage device cannot correctly sense the value of the stored data using the test values for reference fine-tuning, and to set the reference fine-tuning for the storage device at least partially based on a failure event that the storage device cannot correctly sense the stored data.

Description

[0001] Cross - Reference to Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 62 / 945,335, filed on December 9, 2019, which is incorporated herein by reference. Technical Field

[0003] This application generally relates to electronic design automation, and more particularly, to built - in self - test with automatic reference fine - tuning feedback for memory sensing. Background Art

[0004] Magnetoresistive Random Access Memory (MRAM) has become an attractive non - volatile memory solution due to its small size, fast operation speed, and good durability. MRAM devices can store data in magnetic domains, e.g., as the spin polarities of magnets in their free layers. MRAM devices can write data in magnetic domains by setting the spin polarities of the magnets in their free layers (e.g., providing a spin - polarized current through a Magnetic Tunnel Junction (MTJ), which exerts a torque on the local magnetization in the free layer, commonly referred to as Spin Torque Transfer (STT)).

[0005] To read the stored data, an MRAM device can determine the spin polarities of the magnets in its free layer relative to a pinned reference layer below the corresponding free layer. When the spin polarities are parallel to the pinned reference layer, the resistivity on the reference bit - line (BL) of the MRAM device can be considered low and thus corresponds to a data "0" value. When the spin polarities are perpendicular or non - parallel to the pinned reference layer, the resistivity on the reference bit - line of the MRAM device can be considered high and thus corresponds to a data "1" value. An MRAM device can include a sensing circuit to detect the resistivity on the reference bit - line of the MRAM device and compare the detected resistivity with a reference resistance to determine whether the detected resistivity is considered low corresponding to a data "0" value or high corresponding to a data "1" value.

[0006] Many MRAM devices have a relatively small resistivity separation between a high-resistance state associated with a data “1” value and a low-resistance state associated with a data “0” value, which presents challenges for reliable data read operations. To overcome this lack of resistivity separation, some MRAM devices have included trim circuitry to adjust a reference resistance used by the MRAM device to distinguish between the high-resistance and low-resistance states of its memory cells. This trim circuitry can receive an external input corresponding to a reference trim (e.g., from a test engineer), which can adjust the reference resistance against which the MRAM device compares the resistance values read from its memory cells in order to determine whether the memory cell stores a data “1” value or a data “0” value. Test engineers typically determine the value for reference trim in an MRAM device through extensive testing over different environmental conditions (such as temperature variations) to identify the full distribution of bit characteristics for the MRAM device before performing engineering analysis to identify the reference trim. Such MRAM device testing has proven to be expensive or impractical in larger MRAM implementations. SUMMARY OF THE INVENTION

[0007] This application discloses a memory built-in self-test system to prompt a storage device to sense the value of stored data using reference trim during a memory read operation. The memory built-in self-test system can automatically set the reference trim for the storage device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the storage device to perform a memory read operation using different test values for reference trim. The memory built-in self-test system also includes a trim feedback circuit to use the test values for reference trim to determine when the storage device cannot correctly sense the value of the stored data and to set the reference trim for the storage device based at least in part on a failure event that the storage device cannot correctly sense the stored data. Embodiments will be described in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An exemplary storage system including a memory built-in self-test system with automatic trim feedback in accordance with various embodiments is illustrated.

[0009] Figure 2 A graph illustrating exemplary read characteristics of a magnetoresistive storage device in accordance with various embodiments is shown.

[0010] Figure 3 An exemplary trim feedback circuit implementing an automatic trim feedback process in accordance with various embodiments is illustrated.

[0011] Figure 4A A graph illustrating exemplary storage device failures at different sense reference values in accordance with various embodiments is shown.

[0012] Figure 4B and Figure 4C illustrate graphs of exemplary fine-tuning reference selection results using different failure thresholds according to respective embodiments.

[0013] Figure 5 illustrate a flowchart of an exemplary implementation showing a binary search of fine-tuning reference values during an automatic fine-tuning feedback process according to respective embodiments.

[0014] Figure 6 illustrate a flowchart of an exemplary implementation showing an automatic fine-tuning feedback process according to respective embodiments. Detailed Description

[0015] Memory Built-In Self-Test System with Automatic Fine-Tuning Feedback

[0016] Figure 1 illustrate an exemplary storage system 100 including memory built-in self-test with automatic fine-tuning feedback. Refer Figure 1 , the storage system 100 includes a storage device 130 to store data 101 during a data write operation and output the stored data 107 during a data read operation. In some embodiments, the storage device 130 may include a magnetoresistive random access memory (MRAM) to store the data 101 in magnetic domains, e.g., as the spin polarities of magnets in a free layer. The magnetoresistive random access memory may be a spin-transfer torque (STT) MRAM device that can write the data 101 by providing a spin-polarized current through a magnetic tunnel junction (MTJ), where the spin-polarized current applies a torque to a local magnetization portion in the free layer. In other embodiments, the storage device 130 may include other types of random access memory (RAM), such as dynamic random access memory (DRAM), static random access memory (SRAM), etc., or include other types of non-volatile memory, such as flash memory, resistive random access memory (ReRAM), etc.

[0017] The storage system 100 may include a memory built-in self-test controller 110 to control the memory access operations of the storage device 130. The memory built-in self-test controller 110 may generate a control signal 102 and an address signal 104, and when the control signal 102 and the address signal 104 are provided to the storage device 130, the control signal 102 and the address signal 104 may prompt the storage device 130 to perform a memory access operation, such as a data write operation or a data read operation, at the address indicated by the address signal 104. When the control signal 102 corresponds to a data write operation, the storage device 130 may store the data 101 from the memory built-in self-test controller 110 at the address indicated by the address signal 104 in response to the control signal 102. When the control signal 102 corresponds to a data read operation, the storage device 130 may locate and output the data 107 stored at the address indicated by the address signal 104 in response to the control signal 102. The storage device 130 may read the stored data 107 by sensing an electrical value (such as voltage, current, resistance, etc.) associated with the bit lines of the storage device 130 and comparing the sensed electrical value with a reference value to determine whether the stored data 107 corresponds to a high data value associated with the data "1" or a low data value associated with the data "0". In some embodiments, there may be one or more intermediate data values between the high data value and the low data value.

[0018] Because in some instances, the reference value used by the storage device 130 to sense the data value of the stored data 107 may not be aligned with the electrical characteristics of one or more memory cells in the storage device 130, the storage device 130 may utilize reference fine-tuning (such as in the fine-tuning signal 105 provided to the storage device 130) to adjust the reference value. The storage device 130 may use the adjusted reference value to determine whether the stored data 107 corresponds to a high data value or a low data value. The following refers to Figure 2 to describe an example of the read characteristics of a magnetoresistive storage device using a reference fine-tuning value.

[0019] Figure 2 Graph 200 illustrates the exemplary read characteristics of a magnetoresistive storage device according to various embodiments. Referring to Figure 2 , graph 200 has an x-axis corresponding to the bit line resistance 202 during the read operation of the magnetoresistive storage device, and a y-axis corresponding to the probability 201 or likelihood of each bit line resistance 202 occurring. In this example, the read characteristics may include two sets, one set for the bit line resistance associated with reading a stored data "0" value or reading zero 203, and another set for the bit line resistance associated with reading a stored data "1" value or reading one 204.

[0020] The magnetoresistive memory device may also include a reference resistance value 205 that can be used to determine whether the sensed bit line resistance value corresponds to a stored data "0" value or a stored data "1" value stored in the magnetoresistive memory device. In this example, the reference resistance 205 falls within the range corresponding to the bit line resistance associated with reading the stored data "1" value or reading a 204, which means that the magnetoresistive memory device will sense the resistance of the stored data "1" value and misassociate it with the stored data "0" value using the reference resistance 205. In some instances, the magnetoresistive memory device may use reference trimming 206 to adjust the reference resistance 205 to generate an adjusted reference resistance 207 that may be located between the read zero 203 characteristic and the read one 204 characteristic of the magnetoresistive memory device.

[0021] Return reference Figure 1 Returning to reference, the storage system 100 may include a built-in self-test interface 120 to generate a trimming signal 105 having a value for reference trimming. In some embodiments, the value for reference trimming may correspond to a resistance value, a voltage value, a current value, etc., to adjust a reference resistance, a reference voltage, a reference current, respectively. The built-in self-test interface 120 may provide the trimming signal 105 to the storage device 130, and the storage device 130 may utilize the value for reference trimming in the trimming signal 105 to adjust the reference value for reading the stored data 107.

[0022] The built-in self-test interface 120 may automatically set the value for reference trimming, where the storage device 130 may utilize the value for reference trimming to read the stored data 107. In some embodiments, the built-in self-test interface 120 may use an automatic trimming feedback process to set the value for reference trimming, for example, by receiving known test data values stored in the storage device 130 (the known test data values are read using different reference trimming values) and then setting the value for reference trimming based on the result of reading the known test data values.

[0023] The memory built-in self-test controller 110 may include a trimming setting unit 112 to initiate an automatic trimming feedback process that allows the built-in self-test interface 120 to set the value for reference trimming for the storage device 130. The trimming setting unit 112 may write test data (such as data 101) to the storage device 130, for example, by generating a control signal 102 and an address signal 104 to prompt the storage device 130 to perform a data write operation using the data 101. In some embodiments, the trimming setting unit 112 may write the same data value (such as data "1" or data "0") to the storage cells in the storage device 130.

[0024] The fine-tuning setting unit 112 can generate a fine-tuning setting signal 103 to prompt the built-in self-test interface 120 to select a value for reference fine-tuning and provide the selected value to the storage device 130 in the fine-tuning signal 105. The fine-tuning setting unit 112 can use the value for reference fine-tuning in the fine-tuning signal 105 to prompt the storage device 130 to perform a data read operation and output test data, such as the stored data 107.

[0025] The built-in self-test interface 120 can include a failure detection circuit 122 to determine when the storage device 130 fails to output the stored data 107 having the same value as the data 101. In some embodiments, the failure detection circuit 122 can compare the stored data 107 read from the storage device 130 with the type of test data (e.g., data "1" value or data "0" value), and detect a failure event that the storage device 130 fails to output the stored data 107 having the correct value based on the comparison.

[0026] The built-in self-test interface 120 can include a fine-tuning feedback circuit 300 to utilize the failure detected by the failure detection circuit 122 to select a different value for reference fine-tuning during subsequent reading of test data from the storage device 130. The fine-tuning feedback circuit 300 can generate a fine-tuning signal 105 having the selected value for reference fine-tuning for subsequent reading of test data from the storage device 130. The fine-tuning setting unit 112 and the built-in self-test interface 120 can iterate the process of selecting the reference fine-tuning value and reading test data from the memory until the fine-tuning feedback circuit 300 identifies the reference fine-tuning setting for the test data type. In some embodiments, the fine-tuning setting unit 112 can select a new type of data 101 to store in the memory and initiate an automatic feedback process to identify the reference fine-tuning setting for the new type of data. The fine-tuning feedback circuit 300 can use the reference fine-tuning setting (e.g., the aggregated reference fine-tuning setting) identified for the test data type to set the value for reference fine-tuning. Embodiments of the fine-tuning feedback circuit 300 will be described in more detail below with reference to Figure 3 to describe embodiments of the fine-tuning feedback circuit 300 in more detail.

[0027] Figure 3 An exemplary fine-tuning feedback circuit 300 for implementing an automatic fine-tuning feedback process according to various embodiments is illustrated. Referring to Figure 3 , the fine-tuning feedback circuit 300 can include an accumulator 310 to, for example, from Figure 1The failure detection circuit 122 shown receives bit failures 301. Each of the bit failures 301 can correspond to a data bit misread from the storage device using a specific reference trim value. For example, when data with a value of "0" is read from the storage device as having a value of "1", the bit failure 301 of that data can be provided to the accumulator 310. The accumulator 310 can add the bit failures 301 associated with the data reads using a specific reference trim, which results in a failure bit count 311. An example of the failure characteristics of a magnetoresistive storage device for various reference trim values is described below with reference to Figure 4A FIG.

[0028] Figure 4A FIG. illustrates a graph of exemplary storage device failures at different sense reference values according to various embodiments. Referring to Figure 4A FIG. 400, the graph has an x-axis and a y-axis, where the x-axis corresponds to a reference resistance 402 used by the magnetoresistive storage device during a read operation, and the y-axis corresponds to an accumulated failure 401 of the read operation using various reference resistances 402. The reference resistance 402 can vary between a minimum trim value 406 and a maximum trim value 407, which correspond to the lowest and highest values of the reference trim, respectively.

[0029] In this example, the magnetoresistive storage device can have a memory cell array, and one or more of the memory cells may fail regardless of the value of the reference trim. For example, when one or more failures in the magnetoresistive storage device correspond to a read zero failure, the accumulated failure 401 may not reach zero at the maximum trim value 407. In some embodiments, the accumulated failure 401 at the maximum trim value 407 can correspond to a baseline read zero failure count that exists regardless of the reference trim value. Since the read zero failure at the maximum trim value 407 can correspond to the minimum level of read zero failure regardless of the reference trim value, the accumulated failure 401 at the maximum trim value 407 can be disregarded when setting the reference trim value based on the read zero failure.

[0030] When one or more failures in the magnetoresistive storage device correspond to a read one failure, the accumulated failure 401 may not reach zero at the minimum trim value 406. In some embodiments, the accumulated failure 401 at the minimum trim value 406 can correspond to a baseline read one failure count that exists regardless of the reference trim value. Since the read one failure at the minimum trim value 406 can correspond to the minimum level of read one failure regardless of the reference trim value, the accumulated failure 401 at the minimum trim value 406 can be disregarded when setting the reference trim value based on the read one failure.

[0031] In this example, FIG. 400 shows a read zero failure 404 and a read one failure 403. The read zero failure 404 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value “0” using various reference resistors. The read zero failure 404 shows a high number of failures when the reference trim is closer to the minimum trim value 406, and a low number of failures when the reference trim is closer to the maximum trim value 407. The read one failure 403 may correspond to multiple cumulative failures where the storage device cannot correctly read the data value “1” using various reference resistors. The read one failure 403 shows a lower number of failures when the reference trim is close to the minimum trim value 406, and a higher number of failures when the reference trim is close to the maximum trim value 407.

[0032] Return reference Figure 3 , the trim feedback circuit 300 may include a comparator 320 to determine whether the number of failures for a reference trim value described by the failure bit count 311 exceeds a failure threshold 302. The comparator 320 may generate a trim failure result 321 based on a comparison of the failure bit count 311 with the failure threshold 302. In some embodiments, the trim failure result 321 may identify whether the failure bit count 311 exceeds the failure threshold 302.

[0033] In some embodiments, the trim feedback circuit 300 may implement an automatic trim value search using a failure tail as the failure threshold 302. An example of an automatic trim value search using a failure tail is described below with reference to Figure 4B . In some embodiments, the trim feedback circuit 300 may implement an automatic trim value search using a failure cliff as the failure threshold 302. An example of an automatic trim value search using a failure cliff is described below with reference to Figure 4C .

[0034] Figure 4B and Figure 4C illustrate graphs of exemplary trim reference selection results using different failure thresholds according to various embodiments. Referring to Figure 4B , graph 410 has an x-axis and a y-axis, where the x-axis corresponds to the reference resistors 412 used by the magnetoresistive storage device during a read operation, and the y-axis corresponds to the cumulative failures 411 of the read operations using various reference resistors 412. The reference resistors 412 may correspond to an initial reference resistor combined with various reference trim values.

[0035] In this example, the graph 410 shows a read zero failure 414 and a read one failure 413. The read zero failure 414 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistors. The read zero failure 414 shows a high number of failures when closer to a smaller reference trim value and a low number of failures when closer to a larger reference trim value. The read one failure 413 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistors. The read one failure 413 shows a low number of failures when closer to a smaller reference trim value and a high number of failures when closer to a larger reference trim value.

[0036] Use Figure 4B The trim feedback circuit that performs an automatic trim value search using the failure tails shown can set the failure threshold 416 to the failure tail corresponding to the low-level failures for the read zero failure 414 and the read one failure 413. In some embodiments, the read zero failure 414 can be Figure 4A the difference between the cumulative read zero failures 404 at the different reference resistors 402 shown in Figure 4A and the cumulative read zero failures 404 at the maximum trim value 407 shown in Figure 4A . The read one failure 413 can be the difference between the cumulative read one failures 403 at the different reference resistors 402 shown in Figure 4A and the cumulative read one failures 403 at the minimum trim value 406 shown in

[0037] Reference Figure 4C , the graph 420 has an x-axis and a y-axis, where the x-axis corresponds to the reference resistors 422 used by the magnetoresistive storage device during a read operation, and the y-axis corresponds to the cumulative failures 421 of the read operations using the various reference resistors 422. The reference resistors 422 can correspond to the initial reference resistors combined with various reference trim values.

[0038] In this example, graph 420 shows read zero failures 424 and read one failures 413. The read zero failures 424 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "0" using various reference resistors. The read zero failures 424 show a high number of failures when closer to a smaller reference trim value and a low number of failures when closer to a larger reference trim value. The read one failures 423 can correspond to multiple cumulative failures where the storage device cannot correctly read the data value "1" using various reference resistors. The read one failures 423 show a low number of failures when closer to a smaller reference trim value and a high number of failures when closer to a larger reference trim value.

[0039] The trim feedback circuit can use Figure 4C the failure cliffs shown to implement an automatic trim value search. The trim feedback circuit can perform an automatic search to identify a boundary trim value, e.g., where the read one failure count and the read zero failure count exceed a failure threshold 426. The failure threshold 426 can correspond to, for example, a failure level that can be repaired using redundant row-based repair and / or redundant column-based repair, or a failure level that can be corrected using read data correction with an error correction control process (ECC). In some embodiments, e.g., in response to a user input, the failure threshold 426 can be set by the trim feedback circuit. The trim feedback circuit can use the boundary trim value to select a final trim value 425 for the magnetoresistive storage device. The final trim value 425 can be different from Figure 4B the final trim value 415 shown. Figure 4B The final trim value 415 in

[0040] can correspond to the common low point of the read zero failures 414 and the read one failures 413, while the final trim value 425 can have a larger margin 427 from the intersection of the failure threshold 426 with the read zero failures 424 and the read one failures 423.

[0040] Returning to Figure 3 , the trim feedback circuit 300 can include a trim mask 330 to receive a trim failure result 321 from the comparator 320 and generate a trim bit value 331 based on the trim failure result 321. In some embodiments, the trim bit value 331 can correspond to a bit for a final reference trim value for reading data with a value of "0" or data with a value of "1". For example, when performing a binary search for a reference trim value, the trim mask 330 can set the trim bit value 331 to zero for the position of a specific bit in the reference trim when the trim failure result 321 corresponds to a failure, or set the trim bit value 331 to 1 for the position of a specific bit in the reference trim when the trim failure result 321 corresponds to a pass. Embodiments of the binary search will be described in more detail below with reference to Figure 5 .

[0041] Figure 5 A flowchart exemplifying an exemplary implementation of a binary search 500 for fine-tuning a reference value in an automatic fine-tuning feedback process according to various embodiments is shown. Refer to Figure 5 , the binary search 500 can start from the first-bit search 510 of the automatic fine-tuning feedback process that sets the reference fine-tuning value to "10000". The first-bit search 510 of the automatic fine-tuning feedback process can use "10000" to determine whether a plurality of read failures correspond to pass or fail relative to a failure threshold, and compare these failures.

[0042] In this example, when the first-bit search 510 corresponds to fail, the second-bit search 520 sets the most significant bit of the next reference fine-tuning value to "0", the second most significant bit to "1", and the remaining bits to "0". When the first-bit search 510 corresponds to pass, the second-bit search 520 sets the most significant bit of the next reference fine-tuning value to "1", the second most significant bit to "1", and the remaining bits to "0". The second-bit search 520 of the automatic fine-tuning feedback process can determine whether a plurality of read failures correspond to pass or fail relative to a failure threshold.

[0043] For the third-bit search 530 of the automatic fine-tuning feedback process, the reference fine-tuning can have the same value for the most significant bit as that in the second-bit search 520. The automatic fine-tuning feedback process can set the second most significant bit based on pass or fail during the second-bit search 520, set the third most significant bit to "1", and set the remaining two bits to "0". The third-bit search 530 of the automatic fine-tuning feedback process can determine whether a plurality of read failures correspond to pass or fail relative to a failure threshold. Similar operations can be performed on the fourth-bit search 540 and the last-bit search 550, and the fourth-bit search 540 and the last-bit search 550 can finally select the value for reference fine-tuning as the selected fine-tuning value. The automatic fine-tuning feedback process can iteratively perform multiple bit searches to identify the reference fine-tuning value to be used by the storage device during a read operation.

[0044] Return to reference Figure 3, the fine-tuning feedback circuit 300 may include a selection circuit 340 to store the fine-tuning bit value 331 into the read zero boundary register 350 or the read one boundary register 360 based on the data type 303 read from the storage device during the automatic reference fine-tuning setting process. For example, when the automatic fine-tuning feedback process stores data with a value of "0" into the storage device, the data type 303 may correspond to a zero data value, which may prompt the selection circuit 340 to store the fine-tuning bit value 331 from the fine-tuning mask 330 into the read zero boundary register 350. When the automatic fine-tuning feedback process stores data with a value of "1" into the storage device, the data type 303 may correspond to a one data value, which may prompt the selection circuit 340 to store the fine-tuning bit value 331 from the fine-tuning mask 330 into the read one boundary register 360.

[0045] The automatic fine-tuning feedback process may be iterated using a new reference fine-tuning value, which is provided to the storage device and the fine-tuning feedback circuit 300 sets an additional value of the read zero boundary register 350 or the read one boundary register 360 until reference fine-tuning values for reading data with a value of "0" and data with a value of "1" are determined during the automatic fine-tuning feedback process and stored in the read zero boundary register 350 and the read one boundary register 360 respectively.

[0046] The fine-tuning feedback circuit 300 may include a fine-tuning aggregator 370, which may combine the reference fine-tuning values from the read zero boundary register 350 and the read one boundary register 360 into an aggregated reference fine-tuning value. In some embodiments, the fine-tuning aggregator 370 may average, weighted average, combine, select between, aggregate, etc. the reference fine-tuning values from the read zero boundary register 350 and the read one boundary register 360.

[0047] The fine-tuning feedback circuit 300 may include a selection circuit 380 to receive the aggregated reference fine-tuning value from the fine-tuning aggregator 370 and the fine-tuning bit value 331 from the fine-tuning mask 330. The selection circuit 380 may select between the aggregated reference fine-tuning value or the fine-tuning bit value 331 in response to the final fine-tuning signal 304 and output the selected value as the reference fine-tuning value 305. The fine-tuning feedback circuit 300 may include a fine-tuning register 390 to store the reference fine-tuning value 305 from the selection circuit 380 and provide the reference fine-tuning value 305 to the storage device for use during a read operation.

[0048] Figure 6 A flowchart illustrating an exemplary implementation of an automatic fine-tuning feedback process according to various embodiments is illustrated. Refer to Figure 6, in block 601, the memory built-in self-test system can provide test data of a common data type to the storage device and can prompt the storage device to store the test data. The memory built-in self-test system can write the test data to the storage device by generating a control signal to prompt the storage device to perform a data write operation using the test data. In some embodiments, the memory built-in self-test system can write the same data value (e.g., all data values "1" or all data values "0") to the storage cells in the storage device.

[0049] In block 602, the memory built-in self-test system can provide a reference test trim to be used during a memory read operation to the storage device. The memory built-in self-test system can be in a test start mode or a test boundary mode. In the test start mode, the memory built-in self-test system can set the test reference trim value to the highest setting or the lowest setting based on the common data type stored in the storage device at block 601. For example, when the common data type corresponds to data level "0", the memory built-in self-test system can set the test reference trim value to the highest setting. Conversely, when the common data type corresponds to data level "1", the memory built-in self-test system can set the test reference trim value to the lowest setting.

[0050] In the test boundary mode, the memory built-in self-test system can select a value for the reference test trim based on, for example, the binary search process described above with reference to Figure 5 In some embodiments, the memory built-in self-test system can use different techniques or search methods to select the test reference trim value.

[0051] In block 603, the memory built-in self-test system can prompt the storage device to read the stored test data from the memory using the test reference trim. The memory built-in self-test system can generate a control signal to prompt the storage device to perform a data read operation. In response to the control signal, the storage device can sense the stored test data and compare the sensed data with a reference value to determine the value of the stored test data. In some embodiments, the reference value can correspond to an initial reference value of the storage device that has been adjusted based on the test reference trim.

[0052] In block 604, the memory built-in self-test system can identify a failure event where the storage device cannot correctly read the stored data using the test reference trim. The memory built-in self-test system can compare the data read from the storage device with the common data type of the stored data to determine whether the storage device correctly reads the stored data using the test reference trim.

[0053] In the test startup mode, the memory built-in self-test system can accumulate failure events where the storage device cannot correctly read the stored data using the test reference trim, and store them as the hard failure count of the common data type set in block 601. The execution can return to block 602, where the memory built-in self-test system can switch to the test boundary mode and select the test reference trim to be provided to the storage device.

[0054] In the test boundary mode, the memory built-in self-test system can accumulate failure events where the storage device cannot correctly read the stored data using the test reference trim, and then compare the accumulated failures with a baseline failure count (e.g., the read zero failure count at the maximum reference trim setting, or the read one failure count at the minimum reference trim setting). By comparing the accumulated failures with the baseline failure count, the memory built-in self-test system can avoid the influence of hard failures on the set reference trim value. In some embodiments, the memory built-in self-test system can also accumulate failures and then compare the accumulated failures with a failure screening threshold to determine the failure result. In some examples, the failure result can be used to set at least a part of the reference trim of the common data type. By comparing the accumulated failures with the failure screening threshold, the memory built-in self-test system can avoid the influence of the low statistical weak bit memory effect and can determine the setting of the reference trim with a wider read margin. In some embodiments, in the test boundary mode, the memory built-in self-test system can use the comparison result to set a bit of the boundary reference trim value of the common data type.

[0055] In block 605, the memory built-in self-test system can determine whether to perform an automated trim feedback process using at least one additional test reference trim. In some embodiments, the search process can include a specific number of iterative searches, where each search uses a new test reference trim that is partially based on the failure result of the previous search. When the memory built-in self-test system has partially set the boundary reference trim value for the common data type in block 604, in block 605, the memory built-in self-test system can determine whether to perform another search when the boundary reference trim value has not been fully set. When another search is to be performed using at least one additional test reference trim, the execution can return to block 602; otherwise, the execution can proceed to block 606.

[0056] In block 606, the memory built-in self-test system can determine whether to perform the automated trim feedback process using additional test data types. In some embodiments, the memory built-in self-test system can use multiple different data types (such as value "0" and value "1") and may use one or more other data types to perform the automated trim feedback process. When another search is to be performed using at least one additional data type, the execution can return to block 601; otherwise, the execution can proceed to block 607. When the execution returns to block 601, the memory built-in self-test system can switch from the test boundary mode to the test start mode to store the new test data type into the storage device.

[0057] In block 607, the memory built-in self-test system can set the reference trim for the storage device using the test reference trim based on the identified failures. The memory built-in self-test system can set the reference trim by leveraging the failure results identified in block 604, for example, using the failure boundary reference trim values for each data type and then aggregating or averaging the failure boundary reference trims for each data type into a final reference trim value. In some embodiments, the memory built-in self-test system can provide the final reference trim value to the storage device for subsequent memory read operations.

[0058] The systems and devices described above can use a dedicated processor system, a microcontroller, a programmable logic device, a microprocessor, or any combination thereof to perform some or all of the operations described herein. Some of the operations described above can be implemented in software, while other operations can be implemented in hardware. Any operation, any process, and / or any method described herein can be performed by a device, apparatus, and / or system that is substantially similar to the devices, apparatuses, and / or systems described herein and referenced to the illustrated drawings.

[0059] The processing device can execute instructions or "code" stored in the memory. The memory can also store data. The processing device can include, but is not limited to, an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc. The processing device can be part of an integrated control system or a system manager, or can be provided as a portable electronic device configured to dock locally or remotely with a networked system via wireless transmission.

[0060] The processor memory can be integrated with the processing device, such as RAM or FLASH memory provided within an integrated circuit microprocessor, etc. In other examples, the memory can include stand-alone devices, such as external disk drives, storage arrays, portable FLASH key fobs, etc. The memory and the processing device can be operatively coupled together or communicate with each other, for example, via I / O ports, network connections, etc., and the processing device can read files stored in the memory. Depending on the permission settings, the associated memory can be "read-only" (ROM) by design or not. Other examples of memory can include, but are not limited to, WORM, EPROM, EEPROM, FLASH, etc., which can be implemented in solid-state semiconductor devices. Other memories can include moving parts, such as known rotating disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0061] The operation instructions or commands can be implemented or embodied in a tangible form of stored computer software (also referred to as "computer program" or "code"). The program or code can be stored in a digital memory and can be read by the processing device. A "computer-readable storage medium" (or "machine-readable storage medium") can include all of the aforementioned types of memories and future new technologies, as long as the memory is capable of storing digital information, at least temporarily, in the nature of a computer program or other data, and as long as the stored information can be "read" by an appropriate processing device. The term "computer-readable" can be not limited to the historical use of "computer" which implies a complete mainframe, minicomputer, desktop computer or even laptop computer. Instead, "computer-readable" can include storage media readable by a processor, a processing device or any computing system. Such a medium can be any available medium that can be accessed locally and / or remotely by a computer or a processor, and can include volatile and non-volatile media, as well as removable and non-removable media, or any combination thereof.

[0062] The program stored in the computer-readable storage medium can include a computer program product. For example, the storage medium can be used as a convenient device for storing or transmitting a computer program. For convenience, the operations can be described as various interconnected or coupled functional blocks or schematic diagrams. However, there may be cases where these functional blocks or schematic diagrams can be equivalently aggregated into a single logical device, program or operation with ill-defined boundaries.

[0063] Conclusion

[0064] Although this application describes specific examples of embodiments of the present invention, those skilled in the art will understand that there are many variations and permutations of the above systems and techniques that fall within the spirit and scope of the present invention as set forth in the appended claims. For example, although specific terms have been used above to refer to electronic design automation processes, it should be understood that any desired combination of electronic design automation processes can also be used to implement various examples of the present invention.

[0065] Those skilled in the art will also recognize that the concepts taught herein can be customized to specific applications in many other ways. In particular, those skilled in the art will recognize that the illustrated examples are only one of many alternative embodiments that become apparent after reading this disclosure.

[0066] Although the terms "one," "another," or "some" examples may be referred to in several places in this application document, this does not necessarily mean that each such reference refers to the same one or more examples, or that the features apply only to a single example.

Claims

1. A system, comprising: a storage device configured to sense a value of stored data using reference trimming during a memory read operation; and a memory built-in self-test system configured to prompt the storage device to perform a plurality of memory read operations using a plurality of test values for the reference trimming; determining when the storage device cannot correctly sense the value of the stored data using the test values for the reference trimming by comparing the sensed value of the stored data with an expected value to identify a failure event, accumulating the failure events in which the storage device cannot correctly sense the stored data, and comparing the accumulated failures with a threshold failure amount corresponding to the accumulation of storage device failures when using boundary test values for the reference trimming; and setting bits for the reference trimming of the storage device based at least in part on a comparison of the accumulated failures with the threshold failure amount.

2. The system according to claim 1, wherein, The memory built-in self-test system is configured to iteratively select the test values for the reference trimming using binary search based at least in part on failure events in which the storage device cannot correctly sense the stored data.

3. The system according to claim 1, wherein The test values correspond to at least one of a resistance value, a current value, or a voltage value.

4. The system according to claim 1, wherein The storage device is a magnetoresistive random access memory (MRAM) device.

5. A method, comprising: sensing a value of stored data by a storage device using a plurality of test values for reference trimming during a memory read operation; determining, by a memory built-in self-test system, when the storage device cannot correctly sense the value of the stored data using the test values for the reference trimming by: comparing the sensed value of the stored data with an expected value to identify a failure event; accumulating the failure events in which the storage device cannot correctly sense the stored data; comparing the accumulated failures with a threshold failure amount corresponding to the accumulation of storage device failures when using boundary test values for the reference trimming; and setting, by the memory built-in self-test system, bits for the reference trimming of the storage device based at least in part on a comparison of the accumulated failures with the threshold failure amount.

6. The method according to claim 5, further comprising: Iteratively selecting, by the memory built-in self-test system, the test values for the reference trimming using binary search based at least in part on failure events in which the storage device cannot correctly sense the stored data.

7. The method according to claim 5, wherein, The test values correspond to at least one of a resistance value, a current value, or a voltage value.

8. The method according to claim 5, wherein The storage device is a magnetoresistive random access memory (MRAM) device.

9. An apparatus, comprising: a memory built-in self-test controller configured to prompt a storage device to perform a memory read operation using a plurality of test values for reference trimming, wherein the storage device is configured to sense a value of stored data using the reference trimming during the memory read operation; and A fine-tuning feedback circuit, which is configured to determine when the storage device cannot correctly sense the value of the stored data using the test value for the reference fine-tuning by comparing the sensed value of the stored data with an expected value to identify a failure event, accumulating the failure event that the storage device cannot correctly sense the stored data, and comparing the accumulated failure with a threshold failure amount corresponding to the accumulated storage device failures when using the boundary test value for the reference fine-tuning; and setting bits for the reference fine-tuning of the storage device at least partially based on the comparison of the accumulated failure with the threshold failure amount.

10. The device according to claim 9, wherein, The fine-tuning feedback circuit is configured to iteratively select the test value for the reference fine-tuning using binary search at least partially based on the failure event that the storage device cannot correctly sense the stored data.

11. The apparatus according to claim 9, wherein, The test value corresponds to at least one of a resistance value, a current value, or a voltage value.

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