Resistive random access memory integrated with stacked vertical transistors

Abstract

A method can include forming two vertical transfer field effect transistors stacked on top of one another and separated by a resistive random access memory structure. The two vertical transfer field effect transistors can include a source (104, 112), a channel (106, 110), and a drain, where a contact layer (152) of the resistive random access memory structure functions as the drain for both vertical transfer field effect transistors. Forming the two vertical transfer field effect transistors can further include forming a first source (104) and a second source (112). The first source (104) is a bottom source and the second source (112) is a top source. The method can include forming a gate conductor layer (138, 140) around the channels (106, 110). The resistive random access memory structure can include a faceted epitaxial body (144) defined by cusps. The cusps of the faceted epitaxial body (144) can extend vertically toward one another. The faceted epitaxial body (144) can be between the two vertical transfer field effect transistors.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a two-resistive random access memory (ReRAM) integrated with a stacked vertical transport field effect transistor (VTFET). BACKGROUND

[0002] Many modern electronic devices contain electronic memory. Electronic memory can be either volatile memory or non-volatile memory. Non-volatile memory retains its stored data without power, while volatile memory loses its stored data when power is lost. Resistive random access memory (ReRAM or RRAM) is a promising candidate for the next generation of non-volatile memory due to its simple structure and its compatibility with complementary metal-oxide semiconductor (CMOS) logic fabrication processes.

[0003] Resistive random access memory works by changing the resistance on a dielectric solid state material. A typical ReRAM consists of a bottom electrode, a top electrode, and an oxide layer between the two electrodes. SUMMARY

[0004] According to an aspect of the present application, there is provided a semiconductor structure comprising: a first vertical field effect transistor comprising a first source, a first channel, and a drain, the channel separating the source from the drain; a second vertical field effect transistor stacked above the first vertical field effect transistor, the second vertical field effect transistor comprising a second source, a second channel, and the drain, the second channel separating the second source from the drain; and a two-resistive random access memory structure between the first vertical field effect transistor and the second vertical field effect transistor, the two-resistive random access memory structure serving as a drain for the first and second vertical transport field effect transistors.

[0005] The first and second vertical field effect transistors can be n-type or p-type vertical field effect transistors. The doping level of the first source and the second source can be 4 x 10 20 cm -3 to 1.5 x 10 21 cm -3 The two-resistive random access memory structure can comprise: a faceted epitaxial body constrained by <111> facets defined by two cusp-shaped tips, wherein the two cusp-shaped tips of the faceted epitaxial body extend perpendicularly towards each other; a metal layer, the metal layer can be in direct contact with the two cusp-shaped tips of the faceted epitaxial body; and two electrodes in direct contact with the metal layer. The faceted epitaxial body can be doped with a dopant, and the doping level is 4 x 10 20 cm -3to 1.5 x 10 21 cm -3 The dopant can be phosphorous or arsenic. The semiconductor structure can include a contact layer between the two resistive random access memory structures. The contact layer connects the two resistive random access memory structures formed at the two pointed tips.

[0006] According to another aspect of the application, a method includes forming two vertical transfer field effect transistors, one stacked on top of the other and separated by a resistive random access memory structure. The two vertical transfer field effect transistors include a source, a channel, and a drain, where a contact layer of the resistive random access memory structure functions as a drain for the two vertical transfer field effect transistors.

[0007] Forming the two vertical transfer field effect transistors can further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method can include forming a gate conductor layer around the channel. The resistive random access memory structure can include a faceted epitaxial body bounded by a pointed tip. The pointed tip of the faceted epitaxial body can extend vertically toward each other. The faceted epitaxial body can be between the two vertical transfer field effect transistors. The resistive random access memory structure can further include a metal layer in direct contact with the pointed tip of the faceted epitaxial body and two electrodes in direct contact with the metal layer.

[0008] According to another aspect of the application, a method includes forming a fin extending upward from a first source, forming a material stack laterally adjacent to the fin, where the material stack includes, from bottom to top, a first spacer, a first sacrificial gate, a second spacer, a first placeholder, a third spacer, a second sacrificial gate, a fourth spacer, and a second placeholder, removing the first and second sacrificial gates to form a trench and physically expose portions of sidewalls of the fin, forming first and second conductor layers within the trench, removing portions of the first placeholder and a drain to create an opening, growing a faceted epitaxial body within the opening on an exposed surface of the drain, the faceted epitaxial body including two facets, depositing a metal layer on top of the faceted epitaxial body, depositing an electrode on top of the metal layer, and filling the opening between the first and second placeholders to create a contact layer.

[0009] Forming the fin can include epitaxially growing the following layers: a first source, a first channel, a drain, a second channel, and a second source by an integrated epitaxy process. Forming the fin can further include depositing a hard mask on top of the second source and patterning the hard mask to form the fin. The first source, the second source, and the drain can be doped with a dopant. The dopant can be a p-type dopant or an n-type dopant. The doping level of the first source and the second source can be 4 x 10 20 cm -3 to 1.5 x 10 21 cm -3. BRIEF DESCRIPTION OF DRAWINGS

[0010] The following detailed description will be best understood in conjunction with the drawings, which are given by way of illustration and are not intended to limit the application thereto, in which:

[0011] Figure 1 is a cross-sectional view illustrating a semiconductor structure according to an example embodiment;

[0012] Figure 2 is a cross-sectional view illustrating a fin structure according to an example embodiment;

[0013] Figure 3 is a cross-sectional view illustrating deposition of a liner and first spacers according to an example embodiment;

[0014] Figure 4 is a cross-sectional view illustrating deposition of a first sacrificial gate material layer according to an example embodiment;

[0015] Figure 5 is a cross-sectional view illustrating deposition of a second spacer, a first placeholder material layer, and a third spacer according to an example embodiment;

[0016] Figure 6 is a cross-sectional view illustrating deposition of a second sacrificial gate material layer, a fourth spacer, and a second placeholder material layer according to an example embodiment;

[0017] Figure 7 is a cross-sectional view illustrating removal of the first and second sacrificial gate material layers according to an example embodiment;

[0018] Figure 8 is a cross-sectional view illustrating deposition of a gate dielectric layer according to an example embodiment;

[0019] Figure 9 is a cross-sectional view illustrating deposition of a first gate conductor layer and a second gate conductor layer according to an example embodiment;

[0020] Figure 10 is a cross-sectional view according to an example embodiment illustrating removal of the first placeholder material and a portion of the oxide liner;

[0021] Figure 11 is a cross-sectional view illustrating recessing of a drain to form an opening according to an example embodiment;

[0022] Figure 12 is a cross-sectional view illustrating growth of epitaxy in the opening according to an example embodiment;

[0023] Figure 13 is a cross-sectional view illustrating deposition of a metal layer on the epitaxy according to an example embodiment;

[0024] Figure 14 FIG. 8 is a cross-sectional view illustrating deposition of an electrode on top of a metal layer, according to an example embodiment;

[0025] Figure 15 FIG. 9 is a cross-sectional view illustrating filling of an opening with a contact metal, according to an example embodiment;

[0026] Figure 16 FIG. 10 is a cross-sectional view illustrating formation of a contact, according to an example embodiment; and

[0027] Figure 17 FIG. 11 is a top view illustrating a contact, according to an example embodiment.

[0028] The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the application. The drawings are intended to depict only typical embodiments of the application. In the drawings, like numbers refer to like elements. DETAILED DESCRIPTION

[0029] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it is understood that the disclosed embodiments are merely examples of the claimed structures and methods which can be embodied in various forms. The application can be implemented in any of numerous ways, and is not limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the description, details of well-known features and techniques can be omitted to avoid unnecessarily obscuring the presented embodiments.

[0030] For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on,” “upon,” or “adjacent” mean that the first element (e.g., first structure) is present on the second element (e.g., second structure), where intervening elements (e.g., interfacial structure) can be present between the first element and the second element. The term “direct contact” means that the first element (e.g., first structure) and the second element (e.g., second structure) are connected without any intermediate conductive, insulating, or semiconductor layer at the interface of the two elements.

[0031] In order not to obscure the presentation of embodiments of the present application, in the following detailed description some processing steps or operations that are known in the art can be combined together for presentation and for explanation purposes and can not be described in detail in some instances. In other cases, some processing steps or operations that are known in the art can not be described at all. It should be understood that the following description is more focused on the distinctive features or elements of the various embodiments of the present application.

[0032] Embodiments of the present application generally relate to semiconductor structures and methods of forming the same. More specifically, the present application relates to a semiconductor structure including two resistive random access memories (ReRAMs) integrated with stacked vertical transport field effect transistors (VTFETs).

[0033] ReRAM is a random access computer memory that works by changing resistance on a dielectric solid state material. ReRAM is a promising technology for high speed content addressable memory. Some applications of ReRAM can include high speed searching in computer networks, such as for routing MAC addresses.

[0034] Generally, ReRAM can include a bottom electrode, a top electrode, and an oxide layer between the two electrodes. Embodiments of the present application propose a stacked vertical transport field effect transistor (VTFET), one on top of the other, with two ReRAMs located between the VTFETs. More specifically, embodiments of the present application relate to two stacked VTFETs in parallel, with a common drain that can include two ReRAM regions, separate gate contacts, and two sources. Embodiments of the present application allow the fin length of the VTFET to be substantially greater than the contact pitch, allowing the drive current to be nearly doubled for a given area.

[0035] Figure 1-1 9 shows an exemplary semiconductor structure including two resistive random access memories (ReRAMs) integrated with two stacked vertical transport field effect transistors (VTFETs).

[0036] Reference is now made to Figure 1 , showing a structure 100 according to an embodiment. The structure 100 can include a semiconductor material stack 200 located on a substrate 102. The semiconductor material stack 200 can include, from bottom to top, a first source 104, a first channel 106, a drain 108, a second channel 110, and a second source 112. The semiconductor material stack 200 is grown using an epitaxial growth process, such as molecular beam epitaxy (MBE). Other methods can also be used to grow the semiconductor material stack 200, such as rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD).

[0037] The substrate 102 can include one or more semiconductor materials. Non-limiting examples of suitable substrate 102 materials can include Si (silicon), strained Si, Ge (germanium), SiGe (silicon germanium), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II- VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride), or any combination thereof. In one embodiment, the substrate 102 can include silicon. In one embodiment, the substrate 102 is a bulk semiconductor substrate. The term "bulk semiconductor substrate" means a substrate that is entirely composed of one or more semiconductor materials. In one example, the bulk semiconductor substrate is entirely composed of Si.

[0038] The semiconductor substrate 102 can be a single crystalline semiconductor material. The semiconductor substrate 102 can have any of the well-known crystal orientations. For example, the crystal orientation of the semiconductor substrate 102 can be {100}, {110}, or {111}. Other crystal orientations can be used in the present application in addition to those specifically mentioned.

[0039] The first source 104 is a first layer epitaxially grown on top of the substrate 102 and doped in situ. The first source 104 can be heavily doped with a dopant, which can be an n-type dopant or a p-type dopant. As known to those skilled in the art, when the dopant is n-type, the first conductivity type is n-type, and when the dopant is p-type, the first conductivity type is p-type. The term "n-type" means the addition of an impurity to an intrinsic semiconductor that contributes a free electron. In silicon-containing semiconductor materials, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The term "p-type" means the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. In one embodiment, the first source 104 can be heavily doped with phosphorus. In an alternative embodiment, the first source 104 can be heavily doped with boron. The doping level of the first source 104 can be 4 x 1019cm-3to 1.5 x 1020cm-3. In one embodiment, the first source 104 can be heavily doped with phosphorus to a level of 1 x 1020cm-3. In an alternative embodiment, the first source 104 can be heavily doped with boron to a level of 1 x 1020cm-3. 20 cm -3 to 1.5 x 1020cm-3. In one embodiment, the first source 104 can be heavily doped with phosphorus to a level of 1 x 1020cm-3. In an alternative embodiment, the first source 104 can be heavily doped with boron to a level of 1 x 1020cm-3. 21 cm -3 .

[0040] Once the first source 104 is grown to a particular thickness, such as between 50 nm and 200 nm, the first channel 106 is epitaxially grown on top of the first source 104. In an embodiment, the first channel 106 can be made of silicon and is not doped with any dopants. The first channel 106 can have a thickness ranging from 20 nm to 100 nm. Other thicknesses are also possible and can be used as the thickness of the first channel 106.

[0041] The drain 108 is epitaxially grown on top of the first channel 106 and is in-situ doped with n-type dopants, such as phosphorous. In an alternative embodiment, the drain 108 can be in-situ doped with p-type dopants, such as boron. The drain 108 can be made of the same or different semiconductor material as the first source 104. For example, both the drain 108 and the first source 104 can be made of silicon. The drain 108 can be grown to a thickness that can support the formation of a two-resistor ReRAM region. The drain 108 can be grown to a thickness ranging from 50 nm to 100 nm. Other thicknesses are also possible and can be used as the thickness of the first source 104.

[0042] The second channel 110 is epitaxially grown on top of the drain 108. In an embodiment, the second channel 110 can be made of the same or different semiconductor material as the first channel 106. For example, the second channel 110 can be made of silicon and is not doped with any dopants. The second channel 110 can have a thickness ranging from 20 nm to 100 nm. Other thicknesses are also possible and can be used as the thickness of the second channel 110.

[0043] The second source 112 is epitaxially grown on top of the second channel 110 and is in-situ doped. The second source 112 can be heavily doped with dopants, which can be n-type dopants or p-type dopants. In an embodiment, the second source 112 can be doped with n-type dopants, such as phosphorous. The second source 112 can be grown to a thickness ranging from 50 nm to 200 nm. Other thicknesses are also possible and can be used as the thickness of the second source 112. The doping level of the second source 112 can be 4 x 1019cm-3to 1.5 x 1020cm-3. 20 cm -3 to 1.5 x 1020cm-3. 21 cm -3 .

[0044] The semiconductor material stack 200 can be formed by the sequential epitaxial growth of the first source 104, the first channel 106, the drain 108, the second channel 110, and the second source 112. In an embodiment of the present disclosure, the first source 104 and the second source 112 can be referred to as a first source-drain and a second source-drain, respectively. In addition, the drain 108 can be referred to as a third source-drain.

[0045] Reference is now made to Figure 2FIG. 1 shows a structure 100 with a fin 300 and a hard mask cap 114, in accordance with an embodiment. Once the semiconductor material stack 200 is formed Figure 1 Once the semiconductor material stack 200 is formed, a hard mask layer (not shown) can be deposited on the topmost surface of the semiconductor material stack 200. The hard mask can include any hard mask dielectric material, such as silicon dioxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the hard mask layer can be formed using a conventional deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In other embodiments, the hard mask layer can be formed using a thermal growth process, such as thermal oxidation. In other embodiments, the hard mask layer can be formed by a combination of a deposition process and a thermal growth process. The hard mask layer can have a thickness from 10 nm to 25 nm. Other thicknesses of the hard mask layer are possible and can be used in this application.

[0046] After the hard mask layer is formed on the topmost surface of the semiconductor material stack 200, the hard mask layer and the semiconductor material stack 200 are patterned. The patterning stops within the upper portion of the first source 104. The patterning can be performed by photolithography and etching, or a sidewall image transfer (SIT) process, or by a direct self-assembly (DSA) process in which a co-polymer capable of direct self-assembly is used. The remaining portion of the hard mask layer, i.e., the unetched portion, is referred to herein as a hard mask cap 114. The remaining portion of the semiconductor material stack 200, i.e., the unetched portion, is referred to herein as a fin 300. The fin 300 can also be referred to as a semiconductor material pillar. The fin 300 extending upward from the first source 104 includes the first source 104, the first channel 106, the drain 108, the second channel 110, and a portion of the second source 112.

[0047] The fin 300 includes a pair of vertical sidewalls that are parallel or substantially parallel to each other. Although described and illustrated as forming a single fin 300, multiple fins 300 can be formed. Each fin 300 can have a vertical height from 20 nm to 300 nm, a width from 5 nm to 30 nm, and a length from 20 nm to 300 nm. Other vertical heights and / or widths and / or lengths that are less than or greater than the ranges mentioned herein can also be used in this application. For example, the fin 300 should be sufficiently high and sufficiently wide to support a 2R ReRAM region that is subsequently formed.

[0048] Reference is now made to FIG. 2, which shows a structure 200 with a fin 300 and a hard mask cap 114, in accordance with an embodiment. Once the semiconductor material stack 200 is formed Figure 3Figure 1 1 shows a structure 100 having a liner 1 16 and a first spacer 1 18, according to an embodiment. Once the fins 300 are patterned, the liner 1 16 is conformally deposited onto the top surface of the fins 300. The liner 1 16 can be made of an oxide material, such as silicon oxide. The liner 1 16 can be formed using a conformal deposition process or a low temperature (500 °C or less) thermal growth process. The liner 1 16 can have a thickness from 1 nm to 10 nm. Other thicknesses are also possible and can be used as the thickness of the liner 1 16. In an embodiment, the liner 1 16 can be 2 nm thick.

[0049] Once the liner 1 16 is deposited, the first spacer 1 18 is deposited using known directional deposition techniques, such as chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The first spacer 1 18 is deposited on top of a portion of the liner 1 16 that is on top of the first source 104. The first spacer 1 18 can be made of a dielectric material, such as silicon nitride.

[0050] Referring now to Figure 13, Figure 4 Figure 1 1 shows a structure 100 having a liner 1 16 and a first spacer 1 18, according to an embodiment. Once the fins 300 are patterned, the liner 1 16 is conformally deposited onto the top surface of the fins 300. The liner 1 16 can be made of an oxide material, such as silicon oxide. The liner 1 16 can be formed using a conformal deposition process or a low temperature (500 °C or less) thermal growth process. The liner 1 16 can have a thickness from 1 nm to 10 nm. Other thicknesses are also possible and can be used as the thickness of the liner 1 16. In an embodiment, the liner 1 16 can be 2 nm thick.

[0051] Referring now to Figure 13, Figure 5 Figure 1 1 shows a structure 100 having a liner 1 16 and a first spacer 1 18, according to an embodiment. Once the fins 300 are patterned, the liner 1 16 is conformally deposited onto the top surface of the fins 300. The liner 1 16 can be made of an oxide material, such as silicon oxide. The liner 1 16 can be formed using a conformal deposition process or a low temperature (500 °C or less) thermal growth process. The liner 1 16 can have a thickness from 1 nm to 10 nm. Other thicknesses are also possible and can be used as the thickness of the liner 1 16. In an embodiment, the liner 1 16 can be 2 nm thick.

[0052] Once the second spacer 122 is deposited, a first placeholder 124 is deposited on top of the second spacer 122 using known directional deposition techniques. The first placeholder 124 can be made of an oxide, such as silicon oxide. The first placeholder 124 can be deposited such that the first placeholder 124 is laterally positioned near the middle portion of the drain 108. For example, in one embodiment, the first placeholder 124 can extend from the lower portion of the drain 108, but not beyond the top surface of the drain 108. During a subsequent manufacturing process, the structure 100 can undergo an etching process to expose only the drain 108. If the first placeholder 124 extends beyond the top surface of the drain 108, the subsequent etching of the placeholder 124 exposes not only the drain 108, but also a portion of the second channel 110. As such, the first placeholder 124 should not extend beyond the top surface of the drain 108. Furthermore, the first placeholder 124 should not extend below the bottom surface of the drain 108.

[0053] Using known directional deposition techniques described herein with reference to Figure 3 A third spacer 126 can be directionally deposited on top of the first placeholder 124 using known directional deposition techniques described herein with reference to

[0054] Referring now to Figure 6 , a structure 100 having a second sacrificial gate 128, a fourth spacer 130, and a second placeholder 132 is shown, in accordance with an embodiment. The second sacrificial gate 128 can be directionally deposited on top of the third spacer 126 using known directional deposition techniques described herein with reference to Figure 3

[0055] The first and second sacrificial gates (120, 128) can be made of the same material as the first sacrificial gate 120. For example, the second sacrificial gate 128 can be made of amorphous silicon. The second sacrificial gate 128 is laterally adjacent to the second channel 110, and is positioned between the third spacer 126 and the fourth spacer 130.

[0056] Next, a fourth spacer 130 is directionally deposited on top of the second sacrificial gate 128 using known directional deposition techniques described herein with reference to Figure 3

[0057] ​​The first, second, third, and fourth spacers (118, 122, 126, 130) can be composed of the same or different spacer dielectric materials. In an embodiment, the spacer dielectric materials of the first, second, third, and fourth spacers (118, 122, 126, 130) are composed of silicon nitride. The first, second, third, and fourth spacers (118, 122, 126, 130) can have a thickness from 10 nm to 50 nm. Other thicknesses for the first, second, third, and fourth spacers (118, 122, 126, 130) are also contemplated. In addition, the first, second, third, and fourth spacers (118, 122, 126, 130) can be composed of a spacer dielectric material that is different in composition from the liner 116.

[0058] After deposition of the fourth spacer 130, the second placeholder 132 is directionally deposited onto the top surface of the fourth spacer 130 using known directional deposition techniques described herein with reference to Figure 3 The second placeholder 132 has an uppermost surface that is generally coplanar with the uppermost surface of the liner 116 present on the uppermost surface of the fin 300. After formation of the second placeholder 132, a planarization process, such as chemical mechanical polishing (CMP), can be performed.

[0059] The first and second placeholders (124, 132), the first and second sacrificial gates (120, 128), and the first, second, third, and fourth spacers (118, 122, 126, 130) are composed of materials that are different in composition from one another. As a result, the first and second placeholders (124, 132) can have an etch rate that is different from the first and second sacrificial gates (120, 128) and the first, second, third, and fourth spacers (118, 122, 126, 130). In an embodiment, the first and second placeholders (124, 132) are composed of silicon oxide, the first and second sacrificial gates (120, 128) are composed of amorphous silicon, and each of the first, second, third, and fourth spacers (118, 122, 126, 130) is composed of silicon nitride. The first and second placeholders (124, 132), the first and second sacrificial gates (120, 128), and the first, second, third, and fourth spacers (118, 122, 126, 130) can be collectively referred to as a material stack.

[0060] Reference is now made to Figure 7FIG. 4, shows structure 100 with first and second sacrificial gates (120, 128) and underlying portions of liner 116 removed, in accordance with an embodiment. First and second sacrificial gates (120, 128) and underlying liner portions 116 are removed to physically expose sidewalls of first and second channels (106, 110) of fin 300, thereby creating trench 134.

[0061] First and second sacrificial gates (120, 128) can be removed using an etching process that selectively removes first and second sacrificial gates (120, 128) relative to other materials of the material stack and liner 116. Physically exposed portions of liner 116 can be removed using an etching process that is selective in removing the dielectric material that makes up liner 116.

[0062] Reference is now made to Figure 8 FIG. 5, shows structure 100 with trench 134 lined with gate dielectric layer 136, in accordance with an embodiment. Gate dielectric layer 136 is conformally deposited within trench 134 along exposed sidewalls of first, second, third, and fourth spacers (118, 122, 126, 130) and first and second channels (106, 110).

[0063] Gate dielectric layer 136 can be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for gate dielectric layer 136 can include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials can also include dopants such as lanthanum and aluminum.

[0064] Gate dielectric layer 136 can be formed by a suitable deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of gate dielectric layer 136 can vary depending on the deposition process and the composition and amount of high-k dielectric material used.

[0065] Reference is now made to Figure 9FIG. 1 illustrates a structure 100 having a gate conductor layer 138, 140 in accordance with an embodiment. Once the trenches 134 are lined with the gate dielectric layer 136, the gate conductor layer 138, 140 is directionally deposited into each trench 134 using known directional deposition techniques, such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. A planarization process, such as chemical mechanical polishing (CMP), can be performed after the formation of the second gate conductor layer 138, 140. The gate conductor layer 138, 140 surrounds the first channel 106 and the second channel 110, respectively.

[0066] The gate conductor layer 138, 140 can be composed of a conductive material, such as doped poly- or amorphous silicon, germanium, silicon-germanium, a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au)), a conductive metal compound material (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silicide (WSi), tungsten nitride (WN), ruthenium oxide (Ru02), cobalt silicide (CoSi), nickel silicide (NiSi), transition metal aluminides (e.g., Ti3Al, ZrAl), TaC, TaMgC), or any suitable combination of these materials.

[0067] Figure 9 The resulting structure 100 includes a first gate structure that contacts the sidewalls of the first channel 106 and a second gate structure that contacts the sidewalls of the second channel 110. The first gate structure includes the gate dielectric layer 136 and the gate conductor layer 138. The second gate structure includes the gate dielectric layer 136 and the gate conductor layer 140.

[0068] Referring now to FIG. 1 1, Figure 10 In accordance with an embodiment, a structure 100 is shown with portions of the first spacer 124 and the underlying liner 1 16 removed. The portions of the first spacer 124 and the underlying liner 1 16 are removed to physically expose the sidewalls of the drain 108. Prior to the removal of the portions of the first spacer 124 and the underlying liner 1 16, a sacrificial anchor structure (not shown) can be placed on top of the second spacer 132 such that a bottom surface of the anchor structure is in direct contact with the top surface of the second spacer 132 and the liner 1 16. In addition, the anchor structure can extend downward along a portion of the sidewalls of the second spacer 132. The anchor structure anchors the structure 100 such that the removal of the portions of the first spacer 124 and the underlying liner 1 16 can be performed. The anchor structure also protects the second spacer 132 during subsequent processes.

[0069] The first placeholder 124 can be removed with a lateral etch process that is selective in removing the dielectric material that makes up the first placeholder 124. The physically exposed portions of the liner 116 can be removed with a lateral etch process that is selective in removing the dielectric material of the liner 116.

[0070] Referring now to Figure 11 , a structure 100 is shown having an opening 142 according to an embodiment. A portion of the lateral etch of the drain 108 is formed to form the opening 142. The lateral etch process does not remove all of the drain 108 material. Rather, the lateral etch process removes some portions of the drain 108 such that a bottom portion of the drain 108 remains and a top portion of the drain 108 remains. The top portion of the drain 108 is laterally located proximate to the third spacer 126 and the bottom portion of the drain 108 is laterally located proximate to the second spacer 122. The opening 142 extends from a top surface of the second spacer 122 to a bottom surface of the third spacer 126.

[0071] Referring now to Figure 12 , a structure 100 is shown having faceted epitaxial bodies 144 according to an embodiment. The faceted epitaxial bodies 144 are grown from the exposed surfaces of the remaining portions of the drain 108. As a result, the faceted epitaxial bodies 144 are also doped and have a doping level of 4 x 10 20 cm -3 to 1.5 x 10 21 cm -3 . The faceted epitaxial bodies 144 are grown in a shape of a pointed diamond facet (<111 -plane constrained epitaxy) with the points of the faceted epitaxial bodies 144 extending perpendicular to each other such that one faceted epitaxial body 144 grows downward and a second faceted epitaxial body 144 grows upward. As a result, the epitaxy 144 of the facets can include, for example, four facets (although only two facets are visible in the figures). The pointed shape of the faceted epitaxial bodies 144 enhances the electric field at the pointed tips.

[0072] Referring now to Figure 13 , a structure 100 is shown having a metal layer 146 according to an embodiment. The metal layer 146 is conformally deposited on the exposed surfaces of the faceted epitaxial bodies 144 within the second spacer 122, the third spacer 126, and the opening 142 using known deposition techniques, such as atomic layer deposition. The metal layer 146 can also be referred to as a switching layer. The metal layer 146 can be made of a high-k material. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide, tantalum oxide, and titanium oxide. The metal layer 146 separates the faceted epitaxial bodies 144 from the electrodes.

[0073] Referring now to Figure 14, showing a structure with electrodes 148, 150 according to an embodiment. The electrodes 148, 150 can also be referred to as top and bottom electrodes in a ReRAM structure. The electrodes 148, 150 can be conformally deposited on top of the metal layer 146 within the opening 142. The electrodes 148, 150 can be deposited using known deposition techniques, such as atomic layer deposition. The electrodes 148, 150 can be made of materials such as titanium nitride and aluminum-doped titanium nitride.

[0074] Referring now to Figure 15 , a structure 100 with a contact layer 152 according to an embodiment is shown. Once the electrodes 148, 150 are conformally deposited on top of the metal layer 146, the opening 142 (shown in Figure 11-14 ) is filled to form the contact layer 152. The contact layer 152 can be deposited using known deposition techniques, such as atomic layer deposition. The contact layer 152 can be made of a suitable low resistivity material, such as tungsten or copper. The contact layer 152 serves as an electrical conductor between the electrodes 148, 150 and the drain formed within the contact layer 152.

[0075] Referring now to Figure 16 and Figure 17 , a structure 100 with source and gate contacts according to an embodiment is shown. Due to the nature of the structure 100, the structure 100 will have two source contacts 154, 162, two gate contacts 156, 158, and one drain contact 160. It should be noted that the two vertical transfer field effect transistors (VTFETs) share a single drain 108 as part of a resistive random access memory (ReRAM).

[0076] As shown in Figure 16 , the source contact 154 extends to the second source 112. The gate contact 156 extends through the second spacer 132, the fourth spacer 130, and the gate dielectric layer 136 to the gate conductor layer 140. The source contact 154 can represent one of the two source contacts, and the gate contact 156 can represent one of the two gate contacts.

[0077] There are three additional contacts (not shown as they are off the page). One of these contacts is another gate contact that extends to the gate conductor layer 140 laterally adjacent to the first channel 106. Another of these contacts is another source contact that extends to the first source 104. Figure 16 Another of these contacts, not shown in , is a drain contact that extends to the contact layer 152. The contact layer 152 is also referred to as a two-resistor ReRAM region that serves as a drain region for the two vertical transfer field effect transistors (VTFETs).

[0078] The various contact structures (154, 156, and three additional contact structures not shown) can be formed by first providing a contact trench (not shown) into the various layers such as the second spacer 132 or the hard mask cap 114. For example, to form the gate contact 156, some of the second spacer 132, some of the fourth spacer 130, and some of the gate dielectric layer 136 are removed. To remove portions of these layers and form the contact trench, a resist such as photoresist can be deposited and patterned. An etching process such as RIE can be performed using the patterned resist as an etch mask to remove these layers until the gate conductor layer 140 is exposed. The contact trench is then filled with a conductive material or a combination of conductive materials to form the gate contact 156. The conductive material fill can be a conductive metal such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material can be deposited by a suitable deposition process such as CVD, PECVD, PVD, electroplating, thermal or e-beam evaporation, or sputtering. A planarization process such as CMP is performed to remove any conductive material from the surface of the structure 100.

[0079] Other contact structures such as the source contact 154 can be formed using the lithography and etching processes described herein. In addition, other contact trenches can be filled with the same conductive material used to fill the contact trench to form the source and gate contacts 156.

[0080] Reference is now made to Figure 17 , which shows a top view of illustrative contacts according to an embodiment. In addition to the source contact 154 and the gate contact 156, there are three additional contacts. There is another gate contact 158, a drain contact 160, and another source contact 162. The gate contact 158 extends to the gate conductor layer 138. The drain contact 160 extends to the contact layer 152. The source contact 162 extends to the first source 104.

[0081] As Figure 16 and 17As shown, the resulting structure 100 includes two vertical transfer field effect transistors (VTFETs) separated by two resistive random access memory (2R ReRAM). The two VTFETs can be p-type vertical field effect transistors or n-type vertical field effect transistors. The 2R ReRAM structure includes portions of the faceted epitaxial body 144 in direct contact with the metal layer 146, the metal layer 146 and the electrodes 148, 150. The 2R ReRAM structure has two tip regions defined by the tips of the faceted epitaxial body 144, the metal layer 146 and the electrodes 148, 150 deposited conformally onto the tip regions of the faceted epitaxial body 144. The tip regions of the ReRAM enhance the electroforming of the current conduction filaments of the ReRAM. Thus, the ReRAM structure of the present application reduces the randomness of the electroforming of the current conduction filaments. Further, integrating the VTFETs with the ReRAM structure saves space, allowing more VTFETs to be fabricated on the same footprint.

[0082] While the application has been particularly shown and described with reference to particular embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details can be made therein without departing from the scope of the application. It will therefore be appreciated that the application should not be limited to the specific form and details herein, but should be accorded a full scope consistent with the appended claims.

Claims

1. A method for forming a semiconductor structure, comprising: forming a fin extending upward from a first source; forming a material stack laterally adjacent to the fin, wherein the material stack comprises, from bottom to top, a first spacer, a first sacrificial gate, a second spacer, a first placeholder, a third spacer, a second sacrificial gate, a fourth spacer, and a second placeholder; removing the first sacrificial gate and the second sacrificial gate to form a trench and to physically expose portions of sidewalls of the fin; forming a first conductor layer and a second conductor layer within the trench; removing the first placeholder and a portion of a drain to form an opening; growing a facet epitaxy within the opening on an exposed surface of the drain, the facet epitaxy comprising two facets and being defined by a cusp tip, the cusp tip of the facet epitaxy extending perpendicularly toward each other; depositing a metal oxide layer on top of the facet epitaxy; depositing an electrode on top of the metal oxide layer; and filling the opening between the electrodes to form a contact layer.

2. The method of claim 1, wherein forming the fin comprises: epitaxially growing, by an integrated epitaxy process, the following layers: a first source, a first channel, the drain, a second channel, and a second source; depositing a hard mask on top of the second source; and patterning the hard mask to form the fin.

3. The method of claim 2, wherein the first source, the second source, and the drain are doped with a dopant.

4. The method of claim 3, wherein the dopant is a p-type dopant.

5. The method of claim 3, wherein the dopant is an n-type dopant.

7. The method of claim 2, further comprising:

6. The method of claim 2, wherein, The first source and the second source have a doping level of 4x10 20 cm -3 to 1.5x10 21 cm -3 . depositing a gate dielectric layer within the trench, wherein the gate dielectric layer is in direct contact with sidewalls of the first channel and the second channel.

8. A method for forming a semiconductor structure, comprising: forming two vertical transfer field effect transistors stacked on top of each other and separated by two resistive random access memory structures, wherein the two vertical transfer field effect transistors comprise a source, a channel, and a drain, wherein a contact layer of the two resistive random access memory structures functions as a drain for the two vertical transfer field effect transistors, wherein the two resistive random access memory structures comprise a facet epitaxy defined by a cusp tip, and wherein the cusp tip of the facet epitaxy extends perpendicularly toward each other. forming the two vertical transfer field effect transistors further comprises:

9. The method of claim 8, wherein, forming a first source and a second source, wherein the first source is a bottom source and the second source is a top source; and forming a gate conductor layer around the channel.

10. The method of claim 8, wherein the resistive random access memory structure further comprises: a metal oxide layer in direct contact with each of the cusp tips of the facet epitaxy; and an electrode in direct contact with each metal oxide layer.

11. A semiconductor structure, comprising: ​ ​ a first vertical field effect transistor comprising a first source, a first channel separating the first source from a drain, and the drain; a second vertical field effect transistor stacked above the first vertical field effect transistor, the second vertical field effect transistor comprising a second source, a second channel separating the second source from the drain, and the drain; and a two-resistive random access memory structure between the first vertical field effect transistor and the second vertical field effect transistor, the two-resistive random access memory structure serving as a drain for the first vertical field effect transistor and the second vertical field effect transistor, wherein the two-resistive random access memory structure comprises a faceted epitaxial body defined by two cusp tips, and wherein the two cusp tips of the faceted epitaxial body extend perpendicularly toward each other.

12. The semiconductor structure of claim 11, wherein the two-resistive random access memory structure further comprises: a metal oxide layer in direct contact with each of the two cusp tips of the faceted epitaxial body; and two electrodes in direct contact with the metal oxide layer.

14. The semiconductor structure of claim 13, wherein the dopant is phosphorous or arsenic.

13. The semiconductor structure of claim 12, wherein the faceted epitaxy body is doped with a dopant and has a doping level of 4 x 1018cm-3 to 1.5 x 1019cm-3. 20 cm -3 -3. 21 cm -3 -3.

15. The semiconductor structure of claim 12, further comprising: a contact layer between the electrodes of the two-resistive random access memory structure, the contact layer connecting the two-resistive random access memory structure formed at the two cusp tips.

16. The semiconductor structure of claim 11, wherein the first vertical field effect transistor and the second vertical field effect transistor are n-type vertical field effect transistors.

17. The semiconductor structure of claim 11, wherein the first vertical field effect transistor and the second vertical field effect transistor are p-type vertical field effect transistors. ​ 18. The semiconductor structure of claim 11, wherein the first source and the second source have a doping level of 4 x 10 20 cm -3 to 1.5 x 10 21 cm -3 .

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