Thin film transistor including crystalline IZTO oxide semiconductor and method for manufacturing the same

Abstract

Provided are a crystalline IZTO oxide semiconductor and a thin-film transistor including the crystalline IZTO oxide semiconductor. The thin-film transistor includes: a gate; a crystalline In-Zn-Sn oxide (IZTO) channel layer having hexagonal grains and overlapping the upper or lower portion of the gate; a gate insulating film disposed between the gate and the IZTO channel layer; and a source electrode and a drain electrode connected to respective ends of the IZTO channel layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a transistor having an oxide semiconductor layer. Background Art

[0002] As a silicon film used as a semiconductor film for a transistor, an amorphous silicon film or a polycrystalline silicon film is used according to the application. For example, in the case of a transistor included in a large display device, an amorphous silicon film is preferably used because it can have relatively uniform characteristics even when formed over a large area. On the other hand, in the case of a device including a drive circuit or the like, a polycrystalline silicon film capable of exhibiting a high field-effect mobility is preferably used. As a method for forming a polycrystalline silicon film, a known method is to perform high-temperature heat treatment or laser treatment on an amorphous silicon film.

[0003] Recently, research has been conducted on using an oxide semiconductor as a channel layer of a transistor (JP-A 2006-165528). However, most oxide semiconductor layers are amorphous layers and are known to be electrically and chemically unstable. Summary of the Invention

[0004] Technical Problem

[0005] The problem to be solved by the present invention is to provide a thin-film transistor having a polycrystalline oxide semiconductor thin film that exhibits a high field-effect mobility.

[0006] The technical problem of the present invention is not limited to the above technical problem, and those skilled in the art will clearly understand other unmentioned technical problems from the following description.

[0007] Technical Solution

[0008] One aspect of the present invention provides a thin-film transistor. The thin-film transistor includes a gate, a crystalline In-Zn-Sn oxide (IZTO) channel layer having hexagonal grains that overlap the upper or lower portion of the gate, a gate insulating layer provided between the gate and the IZTO channel layer, and a source electrode and a drain electrode respectively connected to both ends of the IZTO channel layer.

[0009] The hexagonal grains may be grains having a (ZnO) k In2O3 (k is an integer from 3 to 11) phase. In the (ZnO) k In2O3 phase, k may be 5.

[0010] The IZTO channel layer may further have (x)ZnIn2O4-(1-x)Zn2SnO4 (0 < x < 0.45) as a sub-solid phase. SnO2 may be mixed in the (ZnO) k In2O3 (k is an integer from 3 to 11) phase in the form of a solid solution.

[0011] The hexagonal grains may have a JCPDS card number of 20-1440. The XRD pattern for the IZTO channel layer may show a diffraction peak corresponding to the (0021) plane. The full width at half maximum (FWHM) of the diffraction peak may be about 0.3 to 0.5 radians.

[0012] When the sum of the atomic amounts of indium, zinc, and tin is 100%, the IZTO channel layer may have 21 to 25 atomic % of indium (In), 54 to 57 atomic % of zinc (Zn), and 19 to 22 atomic % of tin (Sn). Specifically, when the sum of the atomic amounts of indium, zinc, and tin is 100%, the IZTO channel layer may have 22.5 to 23.5 atomic % of In, 54.7 to 55.5 atomic % of Zn, and 20.5 to 21.3 atomic % of Sn.

[0013] Another aspect of the present invention provides a method for preparing crystalline IZTO. First, an amorphous In-Zn-Sn oxide (IZTO) layer is formed on a substrate. Before forming the amorphous IZTO layer, a transition metal layer containing a transition metal having a greater oxidation tendency than In, Zn, and Sn is formed below the amorphous IZTO layer, or after forming the amorphous IZTO layer, on the amorphous IZTO layer. The amorphous IZTO layer is converted into a crystalline IZTO layer having hexagonal grains by performing a crystallization heat treatment on the substrate on which the amorphous IZTO layer and the transition metal layer are formed.

[0014] When the sum of the atomic amounts of indium, zinc, and tin is 100%, the amorphous IZTO layer may have 21 to 25 atomic % of indium (In), 54 to 57 atomic % of zinc (Zn), and 19 to 22 atomic % of tin (Sn). Specifically, when the sum of the atomic amounts of indium, zinc, and tin is 100%, the amorphous IZTO layer may have 22.5 to 23.5 atomic % of In, 54.7 to 55.5 atomic % of Zn, and 20.5 to 21.3 atomic % of Sn.

[0015] The heat treatment temperature may be 270° C. to 350° C. The transition metal layer may be a Ta layer. The hexagonal grains may be (ZnO) k Grains of In2O3 (k is 5) phase.

[0016] Another aspect of the present invention provides a method for preparing a thin film transistor. The thin film transistor may include a gate on a substrate; a channel layer overlapping the upper or lower portion of the gate; a gate insulating layer provided between the gate and the channel layer; and a source and a drain connected to both ends of the channel layer, respectively. Here, the channel layer is a crystalline IZTO layer, and the crystalline IZTO layer can be obtained by forming an amorphous In-Zn-Sn oxide (IZTO) layer, forming a transition metal layer containing a transition metal having a greater oxidation tendency than In, Zn, and Sn under the amorphous IZTO layer before forming the amorphous IZTO layer or on the amorphous IZTO layer after forming the amorphous IZTO layer, and changing the amorphous IZTO layer into a crystalline IZTO layer having hexagonal grains by performing a crystallization heat treatment on the substrate on which the amorphous IZTO layer and the transition metal layer are formed.

[0017] Beneficial effects

[0018] According to an embodiment of the present invention, a thin film transistor having a crystalline oxide semiconductor thin film exhibiting high field-effect mobility can be provided.

[0019] However, the effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.

[0021] Figure 2 is a cross-sectional view illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention.

[0022] Figure 3A and 3B is a cross-sectional view illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention.

[0023] Figure 4 is a graph showing XRD patterns of IZTO semiconductor patterns included in TFTs prepared in TFT Preparation Examples 1 to 4 and TFT Comparative Examples 1 to 3.

[0024] Figure 5 is a graph showing XRD patterns of IZTO semiconductor patterns included in TFTs manufactured in TFT Preparation Examples 5 to 8 and TFT Comparative Examples 4 to 6.

[0025] Figure 6A 、 6B 6C and 6D are graphs showing transfer characteristics of TFTs according to TFT Preparation Examples 1 to 4, respectively.

[0026] Figure 7A 、 7B 7C and 7D are graphs showing transfer characteristics of TFTs according to TFT Preparation Examples 5 to 8, respectively. DETAILED DESCRIPTION

[0027] Hereinafter, in order to describe the present invention in more detail, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and can be implemented in other forms. In the accompanying drawings, when a layer is referred to as being "on" another layer or substrate, it can be directly formed on the other layer or substrate, or a third layer can be interposed therebetween.

[0028] Thin-film transistors

[0029] Figure 1 is a cross-sectional view showing a thin film transistor according to an embodiment of the present invention.

[0030] refer to Figure 1 , a substrate (10) may be provided. The substrate (10) may be a semiconductor, metal, glass, or polymer substrate. In one example, the substrate (10) may be a semiconductor or metal substrate. An insulating barrier layer (not shown) may be formed on the substrate (10). In one example, the substrate (10) may be a silicon substrate, and the insulating barrier layer may be a silicon oxide layer.

[0031] A gate electrode (20) extending in one direction may be formed on a substrate (10). The gate electrode (20) may be formed of Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy thereof. A gate insulating layer (30) may be formed on the gate electrode (20). The gate insulating layer (30) may be a silicon oxide film, such as a SiO2 film; a silicon oxynitride film (SiON); an aluminum oxynitride film; a high-k insulating film having a higher dielectric constant than the silicon oxide film; or a composite film thereof. Examples of high-k insulating films having a higher dielectric constant than the silicon oxide film may include Al2O3, HfO2, or ZrO2.

[0032] An indium-zinc-tin oxide layer (In-Zn-Sn oxide, hereinafter referred to as IZTO) provided on the gate insulating layer (30) and overlapping with the gate electrode (20) may be formed as a channel layer (45).

[0033] The IZTO channel layer (45) can be a metal oxide layer containing indium, zinc and tin, and can be an electronic conductive layer, i.e., an N-type semiconductor layer. The IZTO channel layer (45) can be in an amorphous state in a deposited state (when deposited). The IZTO channel layer (45) can be formed using various methods used in the art, specifically, a physical vapor deposition method such as sputtering or a chemical deposition method such as chemical vapor deposition, atomic layer deposition can be used. In one embodiment, the IZTO channel layer (45) can be formed using an IZTO target using a sputtering method in an inert gas atmosphere. In addition, the IZTO channel layer (45) can be patterned using various methods used in the art. The IZTO channel layer (45) can be formed to have a thickness of several to tens of nanometers, for example, 10 to 50 nm, for example, 10 to 30 nm, which can be fully crystallized in the heat treatment described later.

[0034] When the sum of the atomic amounts of indium, zinc, and tin is 100%, the IZTO channel layer (45) may contain 21 to 25 atomic % of indium (In), 54 to 57 atomic % of zinc (Zn), and 19 to 22 atomic % of tin (Sn). In other words, the IZTO channel layer (45) may contain 21 to 25 mol % of indium oxide (InO 1.5 ), 54 to 57 mol % of zinc oxide (ZnO) and 19 to 22 mol % of tin oxide (SnO2). Specifically, when the sum of the atomic amounts of In, Zn and Sn is 100%, the IZTO channel layer (45) may include 22 to 24 atomic % of In, 54.5 to 56 atomic % of Zn and 20 to 21.5 atomic % of Sn, more specifically, 22.5 to 23.5 atomic % of In, 54.7 to 55.5 atomic % of Zn and 20.5 to 21.3 atomic % of Zn. In other words, the IZTO channel layer (45) may contain 22 to 24 mol % of InO 1.5 , 54.5 to 56 mol % of ZnO and 20 to 21.5 mol % of SnO2, more specifically, 22.5 to 23.5 mol % of InO 1.5 , 54.7 to 55.5 mol % ZnO and 20.5 to 21.3 mol % SnO2.

[0035] A source electrode (50S) and a drain electrode (50D) may be formed on both ends of the IZTO channel layer (45), and a portion of the surface of the IZTO channel layer (45) may be exposed between the source electrode (50S) and the drain electrode (50D). The source electrode (50S) and the drain electrode (50D) may be formed using at least one metal selected from aluminum (Al), neodymium (Nd), silver (Ag), chromium (Cr), titanium (Ti), tantalum (Ta), and molybdenum (Mo), or an alloy containing at least one of these, or a metal oxide conductive film such as indium tin oxide (ITO).

[0036] The substrate on which the source / drain (50S, 50D) is formed may be subjected to post-deposition annealing. The post-deposition annealing may be performed in an oxygen atmosphere, specifically in an air atmosphere, at a temperature of about 300 to 500° C., for example, about 250 to 450° C., more specifically about 270 to 430° C. In this case, an ohmic junction may be formed between the source / drain (50S, 50D) and the IZTO channel layer (45).

[0037] A patterned transition metal layer (60) can be formed on a portion of the IZTO channel layer (45) exposed between the source electrode (50S) and the drain electrode (50D). The transition metal layer (60) can be a layer containing a transition metal, and the transition metal contained therein can be a transition metal having a greater oxidation tendency than one or more metals (i.e., In, Zn, and Sn) contained in the IZTO channel layer (45). As an example, the transition metal layer can be a Ta layer, a Ti layer, or a Mo layer. As another example, the transition metal layer can be a transition metal nitride film containing a small amount of nitrogen, for example, the transition metal nitride film has a nitrogen content of 5 to 35 atomic percent, i.e., a transition metal-rich transition metal nitride film, such as a Ti-rich TiN layer, a Ta-rich TaN layer, or a Mo-rich MoN layer.

[0038] Specifically, when the transition metal contained in the transition metal layer (60) is Ta, the Gibbs free energy (ΔGf) for forming Ta2O5 as an example of Ta oxide may be lower than the Gibbs free energy for forming the oxide of each metal contained in the IZTO channel layer (45). For example, the Gibbs free energy (ΔGf) for forming Ta2O5 as an example of Ta oxide may be lower than the Gibbs free energy for forming SnO2 as an example of Sn oxide, the Gibbs free energy for forming ZnO as an example of Zn oxide, or the Gibbs free energy for forming In2O3 as an example of In oxide. In other words, Ta may have a greater oxidation tendency than In, Zn, and Sn.

[0039] The transition metal layer (60) may have a thickness of 3 to 30 nm, for example, the transition metal layer (60) may be formed to have a thickness of 5 to 20 nm, specifically, 7 to 15 nm. The ratio of the thickness of the IZTO channel layer (45) to the thickness of the transition metal layer (60) is 3:1 to 1:2, for example, 2:1 to 1:1, for uniform crystallization of the IZTO channel layer to be performed later.

[0040] In addition, the transition metal layer (60) can be formed to overlap with the gate electrode (20) located below the IZTO channel layer (45), specifically, can be formed to overlap with the central portion of the gate electrode (20) or the central portion of the TFT channel region. However, in this embodiment, the transition metal layer (60) can have a shorter length than the channel length of the TFT (i.e., the distance between the source electrode and the drain electrode (50S, 50D)), so that the transition metal layer (60) cannot contact the source electrode and the drain electrode (50S, 50D). The transition metal layer (60) can also have a width equal to or wider than the channel width of the TFT, so that crystallization, which will be described later, occurs over the entire channel width of the IZTO channel layer (45).

[0041] After forming the transition metal layer (60), the resultant may be subjected to a crystallization heat treatment. The crystallization heat treatment may be performed in an oxygen atmosphere, specifically in an air atmosphere, and within a temperature range of about 150°C to 500°C, specifically greater than about 250°C and less than 400°C, more specifically about 270°C to 350°C or about 290°C to 310°C.

[0042] During the crystallization heat treatment process, in the IZTO channel layer (45) near the interface between the transition metal layer (60) and the IZTO channel layer (45), a transition metal oxide (M) may be formed by reacting with the metal in the transition metal layer (60). a O x , M a The metal in the transition metal layer) is used to remove or consume oxygen species (e.g., interstitial oxygen and hydroxyl groups) loosely bound to metal atoms, and when a transition metal oxide is formed in the transition metal layer (60), electrons can be emitted into the IZTO channel layer (45). The electrons provided to the IZTO channel layer (45) at the interface in contact with the transition metal layer (60) can be transferred to the antibonding orbital of the metal-oxygen bond in the IZTO channel layer (45), thereby weakening the metal-oxygen bond at the interface. In addition, the metal-oxygen bond at the interface weakened during the crystallization heat treatment process may break and rearrange from the interface, and when this rearrangement propagates to the interior of the IZTO channel layer (45), the entire IZTO channel layer (45) can be transformed into a crystal, particularly a polycrystalline, at a relatively low temperature. Therefore, the metal-oxygen lattice fraction in the IZTO channel layer (45) increases compared to the fraction before the heat treatment, and the crystallinity also increases. At the same time, the crystallinity in the IZTO channel layer (45) can decrease from the side in contact with the transition metal layer (60) toward the side opposite thereto, that is, toward the gate insulating layer (30). In other words, the crystallinity in the IZTO channel layer (45) can decrease from the surface opposite to the surface in contact with the gate insulating film 30 toward the gate insulating layer (30).

[0043] The crystalline IZTO channel layer (45) can be a polycrystalline layer having a plurality of grains, and the grains can be in a permeated form, that is, the grains can contact each other to form grain boundaries.

[0044] In addition, the crystalline IZTO channel layer (45) can have a (ZnO) k In2O3 (k = integer) phase as the main crystal structure, and this (ZnO) k In2O3 (k = integer) phase is a homologous compound phase. The homogeneous compound phase can have a structure in which InO2 and (InZn k )O k+1 structures are alternately and repeatedly stacked, and can exhibit a hexagonal structure. Such a crystal structure can have a JCPDS card number of 20 - 1440. In the (ZnO) k In2O3 (k = integer) phase, k can be 5. Correspondingly, when 2θ is about 32 degrees, the XRD pattern of the IZTO channel layer (45) can show a diffraction peak corresponding to the (0021) plane. In addition, the full width at half maximum (FWHM) of the diffraction peak can be about 0.3 to 0.5 radians, specifically, about 0.32 to 0.45 radians, and more specifically, about 0.35 to 0.4 radians.

[0045] SnO2 can be mixed in the (ZnO) k In2O3 (k = integer) phase in the form of a solid solution. In addition, in addition to the (ZnO) k In2O3 (k = integer) phase of the main crystal phase, the IZTO channel layer (45) can also have a spinel phase as a sub-solid phase, that is, (x)ZnIn2O4-(1 - x)Zn2SnO4 (0 < x < 0.45), which is a sub-crystalline phase.

[0046] On the other hand, when the crystallization heat treatment is carried out in an oxygen atmosphere, the transition metal layer (60) can not only be oxidized at the interface in contact with the IZTO channel layer (45), but also be oxidized on the surface exposed to the oxygen atmosphere, so that the transition metal layer (60) can be changed into a transition metal oxide layer, which is an insulator, such as a Ta oxide layer, a Ti oxide layer or a Mo oxide layer. However, when the crystallization heat treatment is carried out in a nitrogen atmosphere, the transition metal layer (60) can be oxidized near the interface in contact with the metal oxide channel layer (45), and can be nitrided near the surface exposed to the nitrogen atmosphere, so that the transition metal layer (60) can be integrally oxynitrided and changed into an insulating transition metal oxynitride layer (for example, a Ta oxynitride layer, a Ti oxynitride layer or a Mo oxynitride layer). After the crystallization heat treatment, the transition metal oxide layer or the transition metal oxynitride layer can be removed by etching to expose the surface of the metal oxide channel layer (45). However, the present invention is not limited thereto.

[0047] Figure 2 1 is a cross-sectional view showing a method for manufacturing a thin film transistor according to another embodiment of the present invention. Figure 1 A method for manufacturing a thin film transistor is described.

[0048] refer to Figure 2 A gate electrode (20) extending in one direction may be formed on a substrate (10), and a gate insulating layer (30) may be formed on the gate electrode (20). A source electrode (50S) and a drain electrode (50D) may be formed on the gate insulating layer (30). At least a portion of a portion of the gate insulating layer (30) overlapping with the gate electrode (20) may be exposed between the source electrode (50S) and the drain electrode (50D).

[0049] You can refer to Figure 1 An IZTO channel layer, a source electrode (50S), and a drain electrode (50D) covering the exposed gate insulating layer (30) are formed as described. Specifically, the IZTO channel layer can be formed to have a thickness of several to several tens of nanometers, for example, 10 to 50 nm, for example, 10 to 30 nm, which can be fully crystallized in the heat treatment described later. In addition, when the sum of the atomic amounts of indium, zinc, and tin is 100%, the IZTO channel layer can have 21 to 25 atomic % of indium (In), 54 to 57 atomic % of zinc (Zn), and 19 to 22 atomic % of tin (Sn). Specifically, when the sum of the atomic amounts of In, Zn, and Sn is 100%, the IZTO channel layer may have 22 to 24 atomic % In, 54.5 to 56 atomic % Zn, and 20 to 21.5 atomic % Sn, and more specifically, 22.5 to 23.5 atomic % In, 54.7 to 55.5 atomic % Zn, and 20.5 to 21.3 atomic % Sn.

[0050] The substrate on which the metal oxide channel layer is formed may be as described with reference to Figure 1 Post-deposition annealing was performed as described.

[0051] Thereafter, a transition metal layer may be formed on the IZTO channel layer. Specifically, the transition metal layer may be a Ta layer, a Ti layer, or a Mo layer. As another example, the transition metal layer is a transition metal nitride layer containing a small amount of nitrogen, such as 5 to 35 atomic percent nitrogen. In other words, the transition metal nitride layer may be a transition metal nitride layer rich in transition metal, such as a Ti-rich TiN layer, a Ta-rich TaN layer, or a Mo-rich MoN layer.

[0052] Thereafter, the transition metal layer and the IZTO channel layer may be patterned in sequence to form a patterned IZTO channel layer (45) and a transition metal layer (60) stacked in sequence on the gate insulating layer (30). Thus, the patterned IZTO channel layer (45) and the transition metal layer (60) may have substantially the same width and length. The IZTO channel layer (45) may span the upper portion of the gate (20) and may be connected to the source (50S) and the drain (50D) at both ends, respectively. In other words, the source (50S) and the drain (50D) may be connected to the metal oxide pattern (45) below both ends of the IZTO channel layer (45).

[0053] In a state where the transition metal layer (60) is deposited but not patterned, or in a state where the transition metal layer (60) is deposited and patterned, the transition metal layer (60) may be deposited as described in reference to Figure 1 The resultant is subjected to a crystallization heat treatment as described. Specifically, the crystallization heat treatment can be performed in an oxygen atmosphere, specifically an air atmosphere, and at a temperature range of about 150° C. to 500° C., specifically greater than about 250° C. and less than 400° C., more specifically about 270° C. to 350° C. or about 290° C. to 310° C.

[0054] During the crystallization heat treatment process, the IZTO channel layer (45) can be Figure 1 Specifically, the crystalline IZTO channel layer (45) may have (ZnO) as the main crystal structure. k In2O3 (k=integer) phase, the (ZnO) k In2O3 (k=integer) phase is a homologous compound phase. The homogeneous compound phase can have InO2 and (InZn k )O k+1 The structure is stacked alternately and repeatedly, and can exhibit a hexagonal structure. This crystal structure can have a JCPDS card number of 20-1440. In (ZnO) k In the In2O3 (k=integer) phase, k may be 5. Accordingly, when 2θ is about 32 degrees, the XRD pattern of the IZTO channel layer (45) may show a diffraction peak corresponding to the (0021) plane. In addition, the full width at half maximum (FWHM) of the diffraction peak may be about 0.3 to 0.5 radians, specifically, about 0.32 to 0.45 radians, and more specifically, about 0.35 to 0.4 radians.

[0055] SnO2 can be mixed with (ZnO) k In2O3 (k=integer) exists in the form of solid solution. In addition, the IZTO channel layer (45) has a main crystalline phase (ZnO) kIn addition to the In2O3 (k = integer) phase, a spinel phase as a sub-solid phase, i.e., (x)ZnIn2O4-(1-x)Zn2SnO4 (0 < x < 0.45), which is a sub-crystalline phase, may also be present.

[0056] Figure 3A and 3B is a cross-sectional view illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention. Except as described later, the method of manufacturing a thin film transistor according to this embodiment may be similar to the method of manufacturing a thin film transistor described in reference Figure 1 as described.

[0057] Reference Figure 3A , a buffer layer (15) may be formed on the substrate (10). The buffer layer (15) may be a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a composite layer thereof.

[0058] A transition metal layer and an IZTO channel layer are sequentially formed on the buffer layer (15), and the IZTO channel layer and the transition metal layer are sequentially patterned to form a patterned transition metal layer (60) and an IZTO channel layer (45) stacked on the buffer layer (15) in sequence. Therefore, the patterned IZTO channel layer (45) and the transition metal layer (60) may have substantially the same width and length. Specifically, the IZTO channel layer (45) may be formed to have a thickness of several to dozens of nanometers, for example, 10 to 50 nm, for example, 10 to 30 nm, which may be sufficiently crystallized in the heat treatment described later. In addition, when the total number of atoms of indium, zinc, and tin is 100%, the IZTO channel layer (45) may have 21 to 25 atomic% of indium (In), 54 to 57 atomic% of zinc (Zn), and 19 to 22 atomic% of tin (Sn). Specifically, when the total number of atoms of In, Zn, and Sn is 100%, the IZTO channel layer may have 22 to 24 atomic% of In, 54.5 to 56 atomic% of Zn, and 20 to 21.5 atomic% of Sn, and more specifically, 22.5 to 23.5 atomic% of In, 54.7 to 55.5 atomic% of Zn, and 20.5 to 21.3 atomic% of Sn. The transition metal layer (60) may be a Ta layer, a Ti layer, or a Mo layer. As another example, the transition metal layer (60) is a transition metal nitride layer containing a small amount of nitrogen, for example, 5 to 35 atomic% of nitrogen. In other words, the transition metal nitride layer may be a transition metal nitride layer rich in transition metals, for example, a TiN layer rich in Ti, a TaN layer rich in Ta, or a MoN layer rich in Mo.

[0059] In the state where the transition metal layer is deposited but not patterned, or in the state where the transition metal layer is deposited and patterned, it may be as described in reference Figure 1The obtained product is subjected to crystallization heat treatment as described. Specifically, the crystallization heat treatment can be carried out within a temperature range of about 150 °C to 500 °C, specifically greater than about 250 °C and less than 400 °C, more specifically about 270 °C to 350 °C or about 290 °C to 310 °C. However, referring to Figure 1 The described crystallization heat treatment can be carried out in an oxygen or nitrogen atmosphere, but in this embodiment, the crystallization heat treatment is carried out in an oxygen atmosphere rather than in a nitrogen atmosphere.

[0060] In the crystallization heat treatment process, the IZTO channel layer (45) can be crystallized as described in reference Figure 1 Specifically, the crystallized IZTO channel layer (45) can have, for example, hexagonal grains and mainly have grains that have a (ZnO) k In2O3 (an integer from k = 3 to 11) phase, and this (ZnO) k In2O3 (an integer from k = 3 to 11) phase is a homologous compound phase. In other words, the crystallized IZTO channel layer (45) can have a (ZnO) k In2O3 (an integer from k = 3 to 11) phase as the main crystal structure. The homogeneous compound phase can have a structure in which InO2 and (InZn k )O k+1 structures are alternately and repeatedly stacked, and the JCPDS card number of this crystal structure can be 20 - 1440. In the (ZnO) k In2O3 (k = integer) phase, k can be 5. Therefore, when 2θ is about 30 to 33 degrees, especially 32 degrees, the XRD pattern of the IZTO channel layer (45) can show a diffraction peak corresponding to the (0021) plane. In addition, the full width at half maximum (FWHM) of the diffraction peak can be about 0.3 to 0.5 radians, specifically, about 0.32 to 0.45 radians, more specifically, about 0.35 to 0.4 radians.

[0061] SnO2 can be mixed in the (ZnO) k In2O3 (k = integer) phase in the form of a solid solution. In addition, in addition to the main crystal phase (ZnO) k In2O3 (k = integer) phase, the IZTO channel layer (45) can also have a spinel phase as a sub-solid phase, that is, (x)ZnIn2O4-(1 - x)Zn2SnO4 (0 < x < 0.45), which is a secondary crystallization phase.

[0062] Referring to Figure 3B, a gate insulating layer (30) can be formed on the IZTO channel layer (45). A gate (20) can be formed on the gate insulating layer (30) to pass through the upper portion of the IZTO channel layer (45). Therefore, the IZTO channel layer (45) can be arranged to overlap with the gate (20) below the gate (20). Thereafter, an interlayer insulating layer (35) can be formed on the gate (20) to cover the gate (20). The interlayer insulating layer (35) can be a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a composite layer thereof.

[0063] Contact holes exposing both ends of the IZTO channel layer (45) are formed in the interlayer insulating layer (35) and the gate insulating layer (30) thereunder, respectively, and a source electrode (50S) and a drain electrode (50D) connected to both ends of the IZTO channel layer (45) can be formed in the contact holes. Thereafter, a heat treatment for improving the ohmic connection between the IZTO channel layer (45) and the source / drain electrodes (50S) and (50D), i.e., post-deposition annealing, can be performed. The post-deposition annealing can be performed in an oxygen atmosphere, specifically, in an atmospheric atmosphere, at a temperature of about 300 to 500° C., for example, about 250 to 450° C., more specifically, about 270 to 430° C.

[0064] Figure 1 、 2 The thin film transistors shown in 3B respectively show a bottom gate / top contact structure, a bottom gate / bottom contact structure, and a top gate / top contact structure. However, the present invention is not limited thereto, and a thin film transistor having a top gate / bottom contact structure can also be implemented.

[0065] As described above, an n-type thin film transistor having an IZTO channel layer as an n-type semiconductor, together with a p-type thin film transistor, can constitute an inverter as an example of a complementary TFT circuit. In this case, the p-type thin film transistor may include a p-type oxide semiconductor as a channel layer, and the p-type oxide semiconductor may be SnO, Cu2O, or NiO, but is not limited thereto.

[0066] Furthermore, the n-type thin film transistor can be used as a switching element electrically connected to a pixel electrode of an organic light-emitting diode (OLED) or a liquid crystal display, or can be used as a switching element electrically connected to one electrode of a memory device, such as a resistance change memory (RRAM), a phase change RAM (PRAM), or a magnetic RAM (MRAM). However, the present invention is not limited thereto.

[0067] Hereinafter, preferred experimental examples are provided to help understand the present invention. However, the following experimental examples are only used to help understand the present invention, and the present invention is not limited to the following experimental examples.

[0068] TFT Preparation Examples 1-4

[0069] A 100 nm thick SiO2 layer was grown on a p-type Si wafer (<0.005 Ω·cm) as a gate insulating film by thermal oxidation. A shadow mask was placed on the SiO2 layer, and an amorphous IZTO semiconductor pattern with a thickness of 17 nm was deposited using RF magnetron sputtering at room temperature. The sputtering IZTO target material was composed of indium oxide (InO 1.5 ), a compound of zinc oxide (ZnO) and tin oxide (SnO2) with a molar ratio of 23:55:21 (the cation atomic percentage of In:Zn:Sn is 23:55:21). Under an Ar atmosphere, the RF power and operating pressure during sputtering were fixed at 50 W and 3 mTorr, respectively. A shadow mask was placed on the amorphous IZTO semiconductor pattern, and an ITO pattern was deposited by sputtering under an Ar atmosphere, thereby forming a source / drain at both ends of the IZTO semiconductor pattern. The width of the semiconductor pattern was 1000 μm, and the length of the semiconductor pattern exposed between the source / drain was 300 μm. Thereafter, post-deposition annealing (PDA) was performed at 400°C in an O2 atmosphere for 1 hour. On the semiconductor pattern exposed between the source / drain, a 10 nm Ta layer was formed by sputtering using a shadow mask. At this time, the width of the Ta layer was 2300 μm wider than the width of the semiconductor pattern, while the length of the Ta layer was 150 μm shorter than the length of the semiconductor pattern exposed between the source and drain electrodes. A plurality of these samples were prepared and crystallized and annealed at different temperatures for 1 hour in an atmospheric atmosphere, i.e., an oxygen atmosphere. The crystallization annealing temperatures for these samples are summarized in Table 1 below.

[0070] TFT Preparation Examples 5-8

[0071] In addition to using indium oxide (InO 1.5 ), a compound composed of zinc oxide (ZnO) and tin oxide (SnO2) (the cation atomic percentage of In:Zn:Sn is 18:60:21) as a sputtering IZTO target instead of the sputtering IZTO target used in TFT Preparation Example 1, the same method as in TFT Preparation Example 1 was performed to prepare TFTs, and TFTs were prepared by changing the crystallization annealing temperature summarized in Table 1 below.

[0072] TFT Comparative Examples 1-3

[0073] TFTs were prepared by the same method as in TFT Preparation Example 1 except that no Ta layer was formed on the semiconductor pattern exposed between the source / drain electrodes for crystallization annealing, and TFTs were prepared by changing the crystallization annealing temperatures summarized in Table 1 below.

[0074] TFT Comparative Examples 4-6

[0075] TFTs were prepared by the same method as in TFT Preparation Example 5 except that no Ta layer was formed on the semiconductor pattern exposed between the source / drain electrodes for crystallization annealing, and TFTs were prepared by changing the crystallization annealing temperatures summarized in Table 1 below.

[0076] Table 1

[0077]

[0078] Figure 4 is a graph showing XRD patterns of IZTO semiconductor patterns included in TFTs prepared in TFT Preparation Examples 1 to 4 and TFT Comparative Examples 1 to 3.

[0079] refer to Figure 4 , it can be seen that, compared with Preparation Examples 1, 2 and 4 and Comparative Examples 1 to 3, the IZTO semiconductor pattern included in the TFT according to Preparation Example 3 exhibits a diffraction peak corresponding to the (0021) plane when 2θ is about 32 degrees. This diffraction peak may mean that the IZTO semiconductor pattern included in the TFT according to Preparation Example 3 has (ZnO) k In2O3 (k=5) phase, the (ZnO) k The In2O3 (k=5) phase is a hexagonal homologous compound phase. In addition, it was found that the diffraction peak had a full width at half maximum (FWHM) of about 0.382 radians.

[0080] Figure 5 is a graph showing XRD patterns of IZTO semiconductor patterns included in TFTs manufactured in TFT Preparation Examples 5 to 8 and TFT Comparative Examples 4 to 6.

[0081] refer to Figure 5 , it can be seen that the diffraction peak of the IZTO semiconductor pattern included in the TFT according to Preparation Example 7 also corresponds to the (0021) plane when 2θ is about 32 degrees, compared with Preparation Examples 5, 6 and 8 and Comparative Examples 4 to 6. This diffraction peak is similar to the diffraction peak of the IZTO semiconductor pattern included in the TFT according to Preparation Example 3, and the IZTO semiconductor pattern included in the TFT according to Preparation Example 7 has (ZnO) k In2O3 (k=5) phase, the (ZnO) k The In2O3 (k=5) phase is a hexagonal homologous compound phase. However, the diffraction peak showed a full width at half maximum (FWHM) of about 0.621 radians, indicating that the crystallinity was lower than that of the IZTO semiconductor pattern included in the TFT according to Preparation Example 3.

[0082] Figure 6A 、 6B6C and 6D are graphs showing transfer characteristics of TFTs according to TFT Preparation Examples 1 to 4, respectively. Figure 7A 、 7B 7C and 7D are graphs showing transfer characteristics of TFTs according to TFT Preparation Examples 5 to 8, respectively.

[0083] Table 2 below shows electrical characteristics of TFTs according to TFT Preparation Examples 1 to 4 and TFT Preparation Examples 5 to 8.

[0084] Table 2

[0085]

[0086] Also refer to Figure 6A 、 6B , 6C, 6D, 7A, 7B, 7C, 7D and Table 2, among the TFTs according to Preparation Examples 1 to 4, the TFTs according to Preparation Examples 1 to 3 have a range of 46.51 to 91.73 cm 2 V -1 s -1 The linear region charge mobility and 23.93 to 57.93 cm 2 V -1 s -1 saturation region charge mobility, which indicates better charge mobility than that of TFT Comparative Example 1. In addition, the TFTs according to Preparation Examples 5 to 8 exhibited a charge mobility of 40.17 to 66.48 cm 2 V -1 s -1 The linear region charge mobility of the TFT of Preparation Example 3 is 91.73 cm 2 V - 1 s -1 , which is significantly better than the TFT according to other examples. Figure 5 and 6, it can be seen that, compared with the TFT according to the comparative example, each containing (ZnO) k The TFTs of Preparation Examples 3 and 7 of the IZTO semiconductor pattern of the In2O3 (k=5) phase generally exhibited better charge mobility. The TFT of Preparation Example 3 showed the best charge mobility, and it can be estimated that the reason for the excellent charge mobility is that the representative (ZnO) k The diffraction peak of the In 2 O 3 (k=5) phase has a smaller half-peak width and is sharper, and the atomic percentage of In:Zn:Sn shows a ratio of 23:55:21, wherein the proportion of Zn is 54 to 57 atomic %.

[0087] Although exemplary embodiments of the present invention have been described above, those skilled in the art should understand that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. A thin film transistor, comprising: gate; a crystalline In-Zn-Sn oxide (IZTO) channel layer, the crystalline In-Zn-Sn oxide (IZTO) channel layer overlapping an upper portion or a lower portion of the gate and having hexagonal grains; a gate insulating layer, the gate insulating layer being disposed between the gate and the IZTO channel layer; and A source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively connected to two ends of the IZTO channel layer, The hexagonal grains are (ZnO) k grains of an In2O3 phase, wherein k is an integer from 3 to 11, and The IZTO channel layer further comprises (x)ZnIn2O4-(1-x)Zn2SnO4 as a subsolid phase, wherein (x)ZnIn2O4-(1-x)Zn2SnO4 is a spinel phase. <x<0.45。 2. The thin film transistor according to claim 1, wherein the (ZnO) k In the In2O3 phase, k is 5.

3. The thin film transistor according to claim 1, wherein SnO2 is mixed in the (ZnO) k In2O3 exists in the form of a solid solution, where k is an integer from 3 to 11. The thin film transistor according to claim 1 , wherein the hexagonal grains have a JCPDS card number of 20-1440. The thin film transistor according to claim 1 , wherein an XRD pattern for the IZTO channel layer shows a diffraction peak corresponding to a (0021) plane. The thin film transistor according to claim 5 , wherein a full width at half maximum (FWHM) of the diffraction peak is 0.3 to 0.5 radians. 7 . The thin film transistor according to claim 1 , wherein the IZTO channel layer has 21 to 25 atomic % of indium (In), 54 to 57 atomic % of zinc (Zn), and 19 to 22 atomic % of tin (Sn) when the sum of the atomic amounts of indium, zinc, and tin is 100%. 8 . The thin film transistor according to claim 7 , wherein the IZTO channel layer has 22.5 to 23.5 atomic % of In, 54.7 to 55.5 atomic % of Zn, and 20.5 to 21.3 atomic % of Sn when the sum of the atomic amounts of indium, zinc, and tin is 100%.

9. A method for preparing crystalline IZTO, comprising: forming an amorphous In-Zn-Sn oxide (IZTO) layer on a substrate; forming a transition metal layer containing a transition metal having a greater oxidation tendency than In, Zn, and Sn under the amorphous IZTO layer before forming the amorphous IZTO layer or on the amorphous IZTO layer after forming the amorphous IZTO layer; and by performing a crystallization heat treatment on the substrate on which the amorphous IZTO layer and the transition metal layer are formed, thereby changing the amorphous IZTO layer into a crystalline IZTO layer having hexagonal grains, The hexagonal grains are (ZnO) k grains of an In2O3 phase, wherein k is an integer from 3 to 11, and The crystalline IZTO layer further comprises (x)ZnIn2O4-(1-x)Zn2SnO4 as a subsolid phase, (x)ZnIn2O4-(1-x)Zn2SnO4 being a spinel phase, wherein 0 <x<0.45。 10 . The preparation method according to claim 9 , wherein the amorphous IZTO layer has 21 to 25 atomic % of indium (In), 54 to 57 atomic % of zinc (Zn), and 19 to 22 atomic % of tin (Sn) when the sum of the atomic amounts of indium, zinc, and tin is 100%. 11 . The preparation method according to claim 10 , wherein the amorphous IZTO layer has 22.5 to 23.5 atomic % of In, 54.7 to 55.5 atomic % of Zn, and 20.5 to 21.3 atomic % of Sn when the sum of the atomic amounts of indium, zinc, and tin is 100%. 12 . The preparation method according to claim 9 , wherein the heat treatment temperature is 270° C. to 350° C. The preparation method according to claim 9 , wherein the transition metal layer is a Ta layer.

14. The preparation method according to claim 9, wherein the hexagonal grains are (ZnO) k Grains of In2O3 phase, where k is 5.

15. A method for preparing a thin film transistor, the thin film transistor comprising a gate electrode on a substrate; and a channel layer overlapping an upper portion or a lower portion of the gate electrode. a gate insulating layer disposed between the gate and the channel layer; and a source electrode and a drain electrode respectively connected to both ends of the channel layer, the method comprising: forming an amorphous In-Zn-Sn oxide (IZTO) layer; forming a transition metal layer containing a transition metal having a greater oxidation tendency than In, Zn, and Sn under the amorphous IZTO layer before forming the amorphous IZTO layer or on the amorphous IZTO layer after forming the amorphous IZTO layer; and by performing a crystallization heat treatment on the substrate on which the amorphous IZTO layer and the transition metal layer are formed, thereby changing the amorphous IZTO layer into a crystalline IZTO layer having hexagonal grains, wherein the crystalline IZTO layer is the channel layer, The hexagonal grains are (ZnO) k grains of an In2O3 phase, wherein k is an integer from 3 to 11, and The channel layer further comprises (x)ZnIn2O4-(1-x)Zn2SnO4 as a subsolid phase, (x)ZnIn2O4-(1-x)Zn2SnO4 is a spinel phase, wherein 0 <x<0.45。 16 . The preparation method according to claim 15 , wherein the amorphous IZTO layer has 21 to 25 atomic % of indium (In), 54 to 57 atomic % of zinc (Zn), and 19 to 22 atomic % of tin (Sn) when the sum of the atomic amounts of indium, zinc, and tin is 100%. The preparation method according to claim 15 , wherein the transition metal layer is a Ta layer.

18. The preparation method according to claim 15, wherein the hexagonal grains are (ZnO) k Grains of In2O3 phase, where k is 5.

Images