Test structure and wafer for semiconductor high voltage devices

Abstract

This invention relates to the field of semiconductor testing, and provides a test structure and wafer for semiconductor high-voltage devices. The test structure is formed on the wafer using photolithography. Gate, source, and substrate terminals are electrically connected to the gate, source, and substrate, respectively. A first drain terminal and a second drain terminal are provided at the drain. A protective resistor is connected in series between the first drain terminal and the drain. During high-voltage testing, the first drain terminal is connected to the test equipment; during low-voltage testing, the second drain terminal is connected to the test equipment. Separating the terminals for high-voltage and low-voltage testing allows for accurate completion of all test items. Furthermore, during high-voltage testing, the protective resistor limits sudden current surges to protect the test equipment without increasing testing costs or complexity.

Description

Technical Field

[0001] This specification relates to the field of semiconductor testing, specifically to a test structure and wafer for a semiconductor high-voltage device. Background Technology

[0002] High-voltage operating conditions place stringent demands on the quality and reliability of semiconductor high-voltage devices. To ensure device quality, a series of electrical performance and reliability tests are required before shipment to evaluate and screen the devices, guaranteeing product quality.

[0003] For high-voltage semiconductor devices, high-voltage tests such as breakdown voltage tests and high-temperature reverse bias tests are required to verify the device's high-voltage withstand capability. During high-voltage testing, the semiconductor high-voltage device is connected to testing equipment, such as a test bench via probes. If internal defects exist in the device during the application of high-voltage stress, the reverse PN junction at the drain terminal may break down due to the high electric field, causing a sudden increase in current. This can burn out the probe card and test bench, and even damage the power supply, resulting in significant economic losses. Replacing the testing equipment also reduces testing efficiency. Existing testing methods include connecting protection devices to the testing equipment, but these devices need to be removed during low-voltage testing, undoubtedly increasing testing costs and operational complexity. Summary of the Invention

[0004] In view of the problems existing in the prior art, the purpose of this invention is to provide a test structure and wafer for semiconductor high-voltage devices. The test structure for semiconductor high-voltage devices can protect external test equipment, without increasing test costs or complexity, and ensures test accuracy and efficiency.

[0005] The embodiments in this specification provide the following technical solutions:

[0006] A test structure for a semiconductor high-voltage device, used for wafer performance testing, wherein the test structure is formed on the wafer using photolithography, comprising:

[0007] The gate and gate terminals are electrically connected to each other;

[0008] The source terminals and source terminals are electrically connected to each other;

[0009] Interconnected substrates and substrate terminals;

[0010] The drain electrode, and a first drain terminal and a second drain terminal electrically connected to the drain electrode respectively, wherein a protective resistor formed by photolithography is connected in series between the first drain terminal and the drain electrode.

[0011] Specifically, when performing high-voltage testing on the semiconductor high-voltage device, the testing equipment is electrically connected to the first drain terminal; when performing low-voltage testing on the semiconductor high-voltage device, the testing equipment is electrically connected to the second drain terminal.

[0012] The test structure of the aforementioned high-voltage semiconductor device has two drain terminals, and a protective resistor is provided between the first drain terminal and the drain. When performing low-voltage tests, connecting the second drain terminal can obtain accurate measurement data. When performing high-voltage tests, the protective resistor can limit the sudden current and protect the test equipment. There is no need to connect an external high-voltage protection device, and the test cost, test steps, or test complexity are not increased.

[0013] This specification also provides an embodiment in which the shape of the test structure is the same as the shape of the transistor in the chip region of the wafer.

[0014] The test structure of the aforementioned semiconductor high-voltage device has the same shape as the transistor in the chip area. During manufacturing, there is no need to use a special mask to manufacture the test structure, which simplifies the manufacturing process and does not increase the number of production steps or production costs.

[0015] This specification also provides an embodiment in which the transistor includes an insulated-gate bipolar transistor, a bipolar transistor, or an insulated-gate field-effect transistor.

[0016] This specification also provides an embodiment in which the test structure is disposed in the dicing groove of the wafer or the chip region.

[0017] This specification also provides an embodiment in which the high voltage test includes at least one of drain breakdown voltage test and high temperature reverse bias test.

[0018] This specification also provides a wafer comprising a test structure for a semiconductor high-voltage device as described in any of the preceding embodiments.

[0019] Compared with the prior art, the beneficial effects that at least one technical solution adopted in the embodiments of this specification can achieve include at least:

[0020] The test structure for semiconductor high-voltage devices provided by this invention has a first drain terminal and a second drain terminal, with a protective resistor connected in series between the first drain terminal and the drain. During high-voltage testing, the gate terminal, source terminal, and substrate terminal are grounded. A high voltage is applied to the drain through the first drain terminal to test for sudden changes in drain current. When a sudden current change occurs, the protective resistor limits the current, preventing damage to the test equipment from the large current during high-voltage testing. This protects the test equipment and ensures the continuity and efficiency of the test process, preventing it from stopping due to equipment failure. Furthermore, by connecting the second drain terminal, low-voltage tests can be performed on other drains. By placing the protective resistor inside the test structure, no external high-voltage protection device is needed during high-voltage testing. This allows for effective and accurate evaluation of the electrical performance of semiconductor high-voltage devices without altering the existing test process. The test process is simple and does not increase test costs. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a MOS transistor test structure;

[0023] Figure 2 This is a schematic diagram of a test structure for a semiconductor high-voltage device equipped with a protective resistor;

[0024] Figure 3 This is a schematic diagram of a test structure for a semiconductor high-voltage device equipped with a protective resistor during low-voltage testing.

[0025] Figure 4 This is a schematic diagram of a test structure for a semiconductor high-voltage device equipped with a protective resistor during high-voltage testing.

[0026] Figure 5 This is a schematic diagram of the test structure of a semiconductor high-voltage device with a protective resistor.

[0027] Wherein, B is the substrate, B1 is the substrate terminal, D is the drain, D1 is the first drain terminal, D2 is the second drain terminal, G is the gate, G1 is the gate terminal, R is the protection resistor, S is the source, and S1 is the source terminal. Detailed Implementation

[0028] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0029] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0031] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] It should be understood that "the connection between component A and component B" means that component A is directly connected to component B, or that component A is indirectly connected to component B through other components. The directional terms such as "upper," "lower," "inner," "outer," and "side" described in the exemplary embodiments of this specification are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this specification.

[0033] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0034] With the widespread application of integrated circuits in daily life, the demand for semiconductors has increased significantly. The high-voltage operating conditions place stringent requirements on the quality and reliability of high-voltage semiconductor devices. To ensure the quality of these devices, a series of electrical performance and reliability tests are conducted before they leave the factory to evaluate and screen them, guaranteeing product quality.

[0035] For high-voltage semiconductor devices, high-voltage tests are required during factory testing, such as breakdown voltage test (one of the WAT and HTRB FT test items) and high temperature reverse bias test (HTRB), to verify the high voltage withstand capability of the high-voltage device.

[0036] Let's take a MOS transistor as an example. For example... Figure 1 The illustrated MOS transistor test structure has its substrate B, gate G, source S, and drain D connected to substrate terminal B1, gate terminal G1, source terminal S1, and drain terminal D2, respectively. During high-voltage testing, the MOS transistor test structure is connected to a testing equipment via probes and probe cards. If internal defects exist in the device during the application of high-voltage stress to the MOS transistor test structure, the reverse PN junction of the drain D will break down due to the high electric field, causing a sudden increase in current. This could burn out the probe card connected to the drain and the testing equipment, and even damage the power supply, resulting in significant economic losses. Furthermore, replacing the probe card and testing equipment reduces testing efficiency and disrupts the continuity of the test. In practice, to avoid accidental damage to the testing equipment, the testing equipment can be connected to a protection device during high-voltage testing and then disconnected during low-voltage testing. However, this process undoubtedly increases the complexity of the testing operation and reduces testing efficiency.

[0037] Through repeated experiments and research, the inventors proposed a test structure and wafer for semiconductor high-voltage devices. The test structure is formed on the wafer using the same photolithography method as that used to manufacture transistors, thus ensuring test accuracy. Like a transistor, the test structure has a substrate, source, gate, and drain, with independent terminals for each of these terminals to connect to external test equipment, such as probe cards and test benches. The drain has two terminals for low-voltage and high-voltage testing, with a resistor on the dedicated high-voltage terminal for protection against voltage surges. Specifically, during high-voltage testing, due to the presence of the PN junction, most of the voltage is applied to the semiconductor high-voltage device itself, allowing the test equipment to accurately measure data such as current. However, when a defect exists in the device, the reverse PN junction of the drain breaks down due to the high electric field, causing a sudden increase in drain current. The protective resistor bears most of the high-voltage stress, thus protecting the test equipment.

[0038] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0039] like Figure 2 and Figure 5 As shown, this invention provides a test structure for a semiconductor high-voltage device, which is configured on a wafer using photolithography. The test structure includes a substrate B, a gate G, a source S, and a drain D, and provides independent terminals for connecting to external test equipment for the substrate B, source S, gate G, and drain D. Specifically, the test structure for the semiconductor high-voltage device includes a substrate B and a substrate terminal B1 electrically connected to the substrate B; a source S and a source terminal S1 electrically connected to the source S; a gate G and a gate terminal G1 electrically connected to the gate G; and a drain D and a first drain terminal D1 and a second drain terminal D2 electrically connected to the drain D. A protective resistor R, formed using photolithography, is also provided at the drain D, and the protective electrode R is connected in series between the drain D and the first drain terminal D1.

[0040] When performing low-voltage testing, the second drain terminal D2 is connected to the test equipment, such as a test bench via probes. Specifically, for example... Figure 3 As shown, when performing tests other than drain breakdown voltage test and high temperature reverse bias test, the gate terminal G1 is connected to the working voltage (VG), the source terminal S1 and the substrate terminal B1 are grounded, and the D2 is connected to the working voltage (LV) to test the drain current (Id). At this time, the first drain terminal D1 is not connected to the test circuit.

[0041] When performing high-voltage tests, such as drain breakdown voltage tests, high-temperature reverse bias tests, or a combination of both, the tests can be performed sequentially. Figure 4 As shown, the gate terminal G1, source terminal S1, and substrate terminal B1 are grounded (0V). The first drain terminal D1 is connected to the test equipment, such as a test bench connected via a probe. The sudden change in drain current (Id) is tested by applying a high voltage (HV, such as 40V or 700V) to the first drain terminal D1. At this time, the second drain terminal D2 is not connected to the test circuit.

[0042] In the above scheme, by setting a first terminal D1 and a second terminal D2 at the drain for high-voltage and low-voltage testing respectively, all electrical parameter tests can be completed without installing a high-voltage protection device on external testing equipment, which is beneficial to improving testing efficiency. Furthermore, the test structure of this semiconductor high-voltage device has a protective resistor R between the first drain terminal D1 and the drain. During high-voltage testing, the gate terminal G1, source terminal S1, and substrate terminal B1 are grounded. High voltage is applied to the drain through the first drain terminal D1 to test the sudden change in drain current (Id). Due to the presence of the PN junction, most of the high voltage is applied to the semiconductor high-voltage device itself, allowing the testing equipment to accurately measure current and other data. When the PN junction is broken down due to a device defect, the drain current (Id) increases instantaneously. The protective resistor R bears most of the high-voltage stress, reducing the drain current (Id) and thus protecting the testing equipment. Because the protective resistor R limits the current, it prevents damage to the probe card and testing equipment from the high current during high-voltage testing, protecting the equipment, avoiding economic losses, and ensuring testing efficiency by preventing the testing process from stopping due to equipment failure. Furthermore, by incorporating the protective resistor R within the testing structure of the semiconductor high-voltage device, there is no need to connect the testing equipment to a protective device during high-voltage testing. Therefore, it does not change the existing testing process and methods, nor does it increase the complexity or cost of the test.

[0043] In some implementations, such as Figure 2 As shown, the test structure for semiconductor high-voltage devices has the same shape as the transistors in the chip region of the same wafer.

[0044] In the above embodiments, since the test structure of the semiconductor high-voltage device has the same shape as the transistor in the chip area, as shown in the layout diagram ( Figure 5 As can be seen, there is no need to make or use special masks during photolithography, simplifying the manufacturing process and saving manufacturing costs. Furthermore, since the test structure has the same shape as the transistor, there is no shape change, and therefore no alteration to existing testing procedures and methods.

[0045] It should be noted that the types of transistors in the chip area include insulated-gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), or insulated-gate field-effect transistors (MOS), and may also include other semiconductor high-voltage devices or power devices constructed using these transistors as the basic structure.

[0046] In some implementations, the MOS transistors in the chip region are PMOS transistors.

[0047] In some implementations, the MOS transistors in the chip region are NMOS transistors.

[0048] In the above scheme, since the protective electrode R has no polarity, it can be applied to the test structure of semiconductor high voltage devices with P-type or N-type MOS transistor structures respectively.

[0049] In some embodiments, the test structure for the semiconductor high-voltage device is disposed in the dicing groove of the wafer.

[0050] In some implementations, the test structure for the semiconductor high-voltage device is located in the chip region of the wafer.

[0051] In the above scheme, the location of the test structure of the semiconductor high voltage device can be flexibly arranged according to design requirements or packaging requirements.

[0052] In some implementations, the high-voltage test includes at least one of the drain breakdown voltage test and the high-temperature reverse bias test.

[0053] In the above scheme, the protective resistor set at the drain can bear most of the high voltage stress when the drain voltage changes suddenly during the drain breakdown voltage test and the high temperature reverse bias test, thereby protecting the test equipment.

[0054] Based on the same inventive concept, embodiments of this specification also provide a wafer, the wafer including a test structure for a semiconductor high-voltage device as described in any of the preceding claims.

[0055] The technical effects that the wafers provided in the above embodiments can bring can be referred to the technical effects provided in the various embodiments of the aforementioned test structure of semiconductor high voltage devices, which will not be repeated here.

[0056] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments described later are relatively simple in description because they correspond to the system; relevant parts can be referred to the descriptions in the system embodiments.

[0057] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A test structure for semiconductor high-voltage devices, used for wafer performance testing, characterized in that, The test structure is formed on the wafer using photolithography, and includes: The gate and gate terminals are electrically connected to each other; The source terminals and source terminals are electrically connected to each other; Interconnected substrates and substrate terminals; The drain electrode, and a first drain terminal and a second drain terminal electrically connected to the drain electrode respectively, wherein a protective resistor formed by photolithography is connected in series between the first drain terminal and the drain electrode. Specifically, when performing high-voltage testing on the semiconductor high-voltage device, the testing equipment is electrically connected to the first drain terminal; when performing low-voltage testing on the semiconductor high-voltage device, the testing equipment is electrically connected to the second drain terminal. The shape of the test structure is the same as the shape of the transistors in the chip region of the wafer; The test structure is set in the dicing groove of the wafer or in the chip area.

2. The test structure according to claim 1, characterized in that, The transistor includes an insulated-gate bipolar transistor, a bipolar transistor, or an insulated-gate field-effect transistor.

3. The test structure according to claim 1, characterized in that, The high-voltage test includes at least one of the drain breakdown voltage test and the high-temperature reverse bias test.

4. A wafer, characterized in that, The wafer includes a test structure for a semiconductor high-voltage device as described in any one of claims 1 to 3.

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