A DFT reset circuit, reset device and reset method

Abstract

The application discloses a DFT reset circuit, a reset device and a reset method, and relates to the technical field of digital circuits, and aims to reduce the occupation of functional pins on a chip when a to-be-tested logic unit is managed in a DFT test. The DFT reset circuit comprises a scan signal providing unit and a reset signal providing unit. The output end of the scan signal providing unit is electrically connected with the scan input end of the to-be-tested logic unit through the reset signal providing unit, and the output end of the reset signal providing unit is electrically connected with the reset end of the to-be-tested logic unit. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the to-be-tested logic unit and a first reset signal to the reset end of the to-be-tested logic unit according to the first scan output signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital circuit, in particular to a DFT reset circuit, a reset device and a reset method. BACKGROUND

[0002] At present, with the rapid development of integrated circuits, the integration of chips is getting higher and higher, resulting in more and more complex logic scale and working mode, and the DFT (Design for test) based on chip level is becoming more and more important.

[0003] In the existing DFT test scheme, SCAN scan is one of the most important means. When doing SCAN scan test, multiple functional pins on the chip need to be reused to apply corresponding excitation to the logic unit under test. However, the functional pins on the chip are limited, and when the required test channels are more, the functional pins on the chip will not be enough. SUMMARY

[0004] The purpose of the present application is to provide a DFT reset circuit, a reset device and a reset method, which are used in DFT test and reduce the occupation of functional pins on the chip when resetting the logic unit under test.

[0005] In a first aspect, the present application provides a DFT reset circuit for resetting the logic unit under test of a chip, comprising a scan signal providing unit and a reset signal providing unit. The output end of the scan signal providing unit is electrically connected to the scan input end of the logic unit under test through the reset signal providing unit, and the output end of the reset signal providing unit is electrically connected to the reset end of the logic unit under test. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used to provide a first scan output signal to the reset signal providing unit according to the scan input signal provided by the scan pin. The reset signal providing unit is used to provide a second scan output signal to the scan input end of the logic unit under test and a first reset signal to the reset end of the logic unit under test according to the first scan output signal.

[0006] Compared with the prior art, in the DFT reset circuit provided by the application, the output end of the scan signal providing unit is electrically connected with the scan input end of the logic unit to be tested through the reset signal providing unit, and the output end of the reset signal providing unit is electrically connected with the reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin. Based on this, in the DFT reset circuit provided by the application, the scan signal providing unit can provide the first scan output signal to the reset signal providing unit only according to the scan input signal provided by the scan pin, and then under the action of the first scan output signal, the reset signal providing unit can not only provide the second scan output signal to the scan input end of the logic unit to be tested according to the first scan output signal to complete the logic function test of the logic unit to be tested, but also provide the first reset signal to the reset end of the logic unit to be tested to complete the management of the reset test of the logic unit to be tested. In the prior art, the scan input signal provided by the scan pin is needed to be used to perform the function logic test of the logic unit to be tested, and the reset signal provided by the reset pin is needed to be used to perform the management of the reset test of the logic unit to be tested, and in the DFT test of the application, the reset signal providing unit is used to replace the function of the reset pin of the chip, so that when the chip is tested, a chip function pin is not needed to be specially occupied as the providing pin of the reset signal, thereby saving the pin resources of the chip. Based on this, the providing pin position of the reset signal in the prior art can be provided with other chip function pins, and the problem of insufficient function pins on the chip can be solved to a certain extent.

[0007] In a second aspect, the application further provides a reset device comprising the DFT reset circuit provided in the first aspect.

[0008] Compared with the prior art, the reset device provided by the application has the same beneficial effects as the DFT reset circuit described in the above technical solution, which will not be repeated here.

[0009] In a third aspect, the application further provides a reset method applied to the DFT reset circuit provided in the first aspect, and the reset method comprises the following steps.

[0010] The scan signal providing unit provides the first scan output signal to the reset signal providing unit according to the scan input signal provided by the scan pin.

[0011] In response to the first scan output signal, the reset signal providing unit provides the second scan output signal to the scan input end of the logic unit to be tested, and provides the first reset signal to the reset end of the logic unit to be tested.

[0012] Compared with the prior art, the reset method provided by the application has the same beneficial effects as the DFT reset circuit described in the above technical solution, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0014] Figure 1 Prior art DFT reset circuit diagram;

[0015] Figure 2 DFT reset circuit diagram in the embodiment of the application.

[0016] Reference signs:

[0017] 11 - scan signal terminal, 12 - external function logic signal terminal,

[0018] 13 - reset signal terminal, 14 - external test signal terminal,

[0019] 15 - scan enable signal terminal, 16 - scan signal output terminal,

[0020] 2 - logic unit to be tested, 31 - scan signal providing unit,

[0021] 32 - reset signal providing unit, 321 - serial chain register,

[0022] 3221 - OR gate, 3231 - data selector,

[0023] 33 - scan signal output unit. DETAILED DESCRIPTION

[0024] In order to clearly describe the technical solutions of the embodiments of the application, in the embodiments of the application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", etc. For example, the first threshold value and the second threshold value are only used to distinguish different threshold values, and the order is not limited. Those skilled in the art can understand that "first", "second", etc. do not limit the quantity and execution order, and "first", "second", etc. also do not necessarily mean different.

[0025] It should be noted that in the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present related concepts in a specific way.

[0026] In the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it. "At least one of the following" or similar expressions means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b or c can represent a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b and c can be single or multiple.

[0027] Figure 1 A DFT reset circuit diagram in the prior art is shown as follows: Figure 1 As shown, at least three chip function pins are occupied in the prior DFT reset circuit. The first chip function pin, i.e. the scan pin PIN0 in the diagram, is electrically connected to the scan input end SI of the logic unit 2 under test through the first silicon chip pin PAD0 and the scan signal end 11 in turn, so as to provide a scan input signal to the logic unit 2 under test. The second chip function pin, i.e. the output pin PIN1 in the diagram, is used to move the scan signal input into the logic unit 2 under test, so as to test the function logic of the logic unit 2 under test. The third chip function pin, i.e. the reset pin PIN2 in the diagram, is directly electrically connected to the reset signal end 13 through the third silicon chip pin PAD2, and provides different reset signal levels to the reset signal end 13 through the third chip function pin, that is, the input signal of the reset signal end 13 is provided by the third chip function pin, and finally the reset signal logic "0" or the reset signal logic "1" is provided to the reset end CDN of the logic unit 2 under test through the reset signal end 13.

[0028] When this scheme is used to perform reset test on the logic unit 2 under test in DFT test, at least three chip function pins are occupied, which will result in insufficient chip function pins under the premise that the number of chip function pins is limited.

[0029] In order to solve the above problems, the present application provides a DFT reset circuit for reset management of a chip to-be-tested logic unit 2, comprising a scan signal providing unit 31 and a reset signal providing unit 32. The output end of the scan signal providing unit 31 is electrically connected with the scan input end SI of the to-be-tested logic unit 2 through the reset signal providing unit 32, and the output end of the reset signal providing unit 32 is electrically connected with the reset end CDN of the to-be-tested logic unit 2. The scan signal providing unit 31 comprises a scan pin PIN0, and is used for providing a first scan output signal to the reset signal providing unit 32 according to a scan input signal provided by the scan pin PIN0. The reset signal providing unit 32 is used for providing a second scan output signal to the scan input end SI of the to-be-tested logic unit 2 and a first reset signal to the reset end CDN of the to-be-tested logic unit 2 according to the first scan output signal.

[0030] In specific implementation: the scan signal providing unit 31 provides a first scan output signal to the reset signal providing unit 32 according to a scan input signal provided by the scan pin PIN0. The reset signal providing unit 32 generates a second scan output signal according to the first scan output signal and transmits the second scan output signal to the scan input end SI of the to-be-tested logic unit 2. The reset signal providing unit 32 also generates a first reset signal according to the first scan output signal and transmits the first reset signal to the reset end CDN of the to-be-tested logic unit 2.

[0031] It can be known from the structure and specific implementation of the DFT reset circuit that the output end of the scan signal providing unit 31 is electrically connected to the scan input end SI of the logic unit 2 under test through the reset signal providing unit 32, the output end of the reset signal providing unit 32 is electrically connected to the reset end CDN of the logic unit 2 under test, and the scan signal providing unit 31 includes a scan pin PIN0. Based on this, in the DFT reset circuit provided by the embodiment of the present application, the scan signal providing unit 31 can provide the first scan output signal to the reset signal providing unit 32 only according to the scan input signal provided by the scan pin PIN0, and then under the action of the first scan output signal, the reset signal providing unit 32 can not only provide the second scan output signal to the scan input end SI of the logic unit 2 under test according to the first scan output signal to complete the logic function test of the logic unit 2 under test, but also provide the first reset signal to the reset end CDN of the logic unit 2 under test to complete the management of the reset test of the logic unit 2 under test. In the prior art, not only is it necessary to use the scan pin to provide the scan input signal to perform the function logic test of the logic unit under test, but also it is necessary to use the reset pin to provide the reset signal to perform the management of the reset test of the logic unit under test. However, in the DFT reset circuit provided by the embodiment of the present application, the reset signal providing unit 32 is used to replace the function of the reset pin PIN2 of the chip in the DFT test, so that when the logic test of the chip is performed, it is not necessary to specially occupy a chip function pin as a providing pin of the reset signal, thereby saving the pin resources of the chip. Based on this, the providing pin position of the reset signal in the prior art can be provided with other chip function pins, which can solve the problem of insufficient function pins on the chip to a certain extent.

[0032] In a possible implementation, the reset signal providing unit 32 includes a reset signal generating module, a selection module and a reset signal output module. The output end of the scan signal providing unit 31 is electrically connected to the scan input end SI of the reset signal generating module, for providing the first scan output signal to the reset signal generating module, the output end of the reset signal generating module is electrically connected to the scan input end SI of the logic unit 2 under test, for providing the second scan output signal to the scan input end SI of the logic unit 2 under test according to the first scan output signal. The output end of the reset signal generating module is also electrically connected to the input end of the selection module, the output end of the selection module is electrically connected to the input end of the reset signal output module, and the selection module is used to provide the second reset signal to the reset signal output module under the action of the second scan output signal. The reset signal output module is electrically connected to the reset end CDN of the logic unit 2 under test, for providing the first reset signal to the reset end CDN of the logic unit 2 under test according to the second reset signal.

[0033] In implementation, the first scan output signal provided by the scan signal providing unit 31 is transmitted to the reset signal generating module. The reset signal generating module generates a second scan output signal according to the scan input signal and directly transmits the second scan output signal to the scan input end SI of the logic unit under test 2. Meanwhile, the reset signal generating module can also transmit the second scan output signal to the selection module. The selection module generates a second reset signal according to the second scan output signal and transmits the second reset signal to the reset signal output module. The reset signal output module generates a first reset signal according to the second reset signal and transmits the first reset signal to the reset end CDN of the logic unit under test 2, so as to complete the reset management of the logic unit under test 2.

[0034] In some embodiments, the reset signal generating module comprises a chain register 321. The output end of the scan signal providing unit 31 is electrically connected with the scan input end SI of the chain register 321. The output end of the chain register 321 is electrically connected with the scan input end SI of the logic unit under test 2 and the input end of the selection module, respectively, for providing the second scan output signal to the scan input end SI of the logic unit under test 2 and the selection module according to the first scan output signal. The output end of the chain register 321 is also electrically connected with the data input end D of the chain register 321.

[0035] Based on this, after the scan input end SI of the chain register 321 receives the first scan output signal, the first scan output signal is transmitted to the output end Q of the chain register 321 and to the data input end D of the chain register 321. Then, according to actual conditions, the signal received by the data input end D of the chain register 321 can be transmitted to the output end Q, or the signal received by the scan input end SI of the chain register 321 can be transmitted to the output end Q, so as to provide the second scan output signal to the scan input end SI of the logic unit under test 2 and the selection module.

[0036] In some embodiments, the selection module comprises an OR gate 3221 and a scan enable signal end 15. The output end of the reset signal generating module is electrically connected with the first input end of the OR gate 3221, for providing the second scan output signal to the OR gate 3221. The scan enable signal end 15 is electrically connected with the second input end of the OR gate 3221, for providing the scan enable signal to the OR gate 3221. The output end of the OR gate 3221 is electrically connected with the input end of the reset signal output module. The OR gate 3221 is used for providing the second reset signal to the reset signal output module according to the second scan output signal and the scan enable signal. The scan enable signal end 15 is also electrically connected with the scan enable end SE of the logic unit under test 2, for providing the scan enable signal to the scan enable end SE of the logic unit under test 2.

[0037] In actual application, the scan enable signal end 15 is also electrically connected with a scan enable end SE of the chain register 321, for providing a scan enable signal to the chain register 321. In the shift stage, the scan enable signal is signal "1", and under the action of the signal "1", the chain register 321 transmits the first scan output signal received by the scan input end SI to the OR gate 3221 and the logic unit 2 under test, and based on the logic of the OR gate 3221, the second reset signal provided by the OR gate 3221 to the reset signal output module is signal "1", and under the condition that the scan enable signal is signal "1", the logic unit 2 under test selects to store the second scan output signal received by the scan input end SI into the register. In the capture stage, the scan enable signal is signal "0", and under the action of the signal "0", the chain register 321 transmits the signal received by the data input end D to the OR gate 3221 and the logic unit 2 under test, and at this time, the second reset signal provided by the OR gate 3221 to the reset signal output module depends on the output signal of the chain register 321, when the output signal of the chain register 321 is signal "0", the second reset signal is signal "0", and when the output signal of the chain register 321 is signal "1", the second reset signal is signal "1".

[0038] In some embodiments, the reset signal output module includes a data selector 3231 and a reset signal end 13. The first input end I0 of the data selector 3231 is electrically connected with the external function logic signal end 12, the second input end I1 of the data selector 3231 is electrically connected with the output end of the selection module through the reset signal end 13, the selection end S of the data selector 3231 is electrically connected with the external test signal end 14, and the output end Z of the data selector 3231 is electrically connected with the reset end CDN of the logic unit 2 under test, for providing the first reset signal to the reset end CDN of the logic unit 2 under test.

[0039] In actual application, in the DFT test mode, the output signal of the external test signal end 14 is signal "1", and under the selection of the signal, the data selector 3231 selects to output the signal received by the second input end I1, that is, the second reset signal output by the OR gate 3221.

[0040] As can be seen from the above, in the shift stage, the second reset signal provided by the OR gate 3221 to the data selector 3231 is signal "1", and the first reset signal output by the data selector 3231 is also signal "1", which meets that the logic unit 2 under test will not be reset in the shift stage, and ensures the accuracy of the shift.

[0041] In the capture stage, the second reset signal provided by the OR gate 3221 to the data selector 3231 can be signal "1" or signal "0", depending on the output signal of the serial chain register 321. If the reset condition needs to be tested, signal "0" is shifted to the serial chain register 321, and finally signal "0" is captured from the data input end D to the output end Q of the serial chain register 321. If the non-reset condition needs to be tested, signal "1" is shifted to the serial chain register 321, and finally signal "0" is captured from the data input end D to the output end Q of the serial chain register 321.

[0042] In a possible implementation, the scan signal providing unit 31 further includes a first silicon chip pin PAD0 and a scan signal end 11. The scan pin PIN0, the first silicon chip pin PAD0 and the scan signal end 11 are electrically connected in sequence, and an output end of the scan signal end 11 is electrically connected to the reset signal providing unit 32.

[0043] Based on this, when the scan input signal provided by the scan pin PIN0 is signal "1", the first scan output signal output by the scan signal providing unit 31 according to signal "1" is also signal "1"; when the scan input signal provided by the scan pin PIN0 is signal "0", the first scan output signal output by the scan signal providing unit 31 according to signal "0" is also signal "0".

[0044] In practice, the first silicon chip pin PAD0 has three input and output ends, namely a PAD end, a C end and an I end, and an output enable OEN end for controlling the first silicon chip pin PAD0 to be in an output mode or an input mode. When the output enable OEN end is electrically connected to signal "1", the first silicon chip pin PAD0 is in the input mode, that is, signal is received from the PAD end and signal is output from the C end; when the output enable OEN end is electrically connected to signal "0", the first silicon chip pin PAD0 is in the output mode, that is, signal is received from the I end and signal is output from the PAD end.

[0045] Further, the DFT reset circuit further includes a scan signal output unit 33 electrically connected to the output end Q of the logic unit under test 2, for outputting the third scan output signal of the logic unit under test 2, wherein the third scan output signal is generated after the second scan output signal passes through the logic unit under test 2. The scan signal output unit 33 includes an output pin PIN1, a second silicon chip pin PAD1 and a scan signal output end 16. The output end of the logic unit under test 2, the scan signal output end 16, the second silicon chip pin PAD1 and the output pin PIN1 are electrically connected in sequence.

[0046] Based on this, in the shift stage, the scan enable signal is signal "1", the scan input signal provided by the scan pin PIN0 is consistent with the first scan output signal, under the action of signal "1", the chain register 321 selects to store the first scan output signal received by the scan input end SI in the chain register 321, and finally the first scan output signal is transmitted to the output end Q of the chain register 321, and then transmitted to the scan input end SI of the logic unit 2 to be tested, after the logic unit 2 to be tested receives the second scan output signal, the third scan output signal is output to the scan signal output unit 33, so as to complete the shift test of the logic unit 2 to be tested.

[0047] In the above embodiment, the DFT reset circuit further comprises a clock signal end. The clock signal end is electrically connected with the clock input end CP of the reset signal providing unit 32 and the clock input end CP of the logic unit 2 to be tested respectively, and is used for providing the clock signal to the reset signal providing unit 32 and the logic unit 2 to be tested. Specifically, the clock signal end is electrically connected with the clock input end CP of the chain register 321 and the clock input end CP of the register in the logic unit 2 to be tested, and is used for providing the clock signal to the chain register 321 and the logic unit 2 to be tested. When the above register is a rising edge register, only when the rising edge of the clock signal comes, the signal received by the scan input end SI will be transmitted to the output end. When the above register is a falling edge register, only when the falling edge of the clock signal comes, the signal received by the scan input end SI will be transmitted to the output end Q, that is, the second scan output signal will be transformed with the period of the clock signal, and will be captured from the scan input end SI of the logic unit 2 to be tested to the output end of the logic unit 2 to be tested, and finally will be removed through the scan signal output unit 33, and the third scan output signal will be observed through the output pin PIN1 of the scan signal output unit 33, so as to complete the logic test of the logic unit 2 to be tested.

[0048] The embodiment of the present application further provides a reset device comprising the DFT reset circuit provided in the above embodiment.

[0049] Compared with the prior art, the reset device provided by the embodiment of the present application has the same beneficial effects as the DFT reset circuit provided in the above embodiment, which will not be repeated here.

[0050] The embodiment of the present application further provides a reset method applied to the DFT reset circuit provided in the above embodiment, and the reset method comprises the following steps of:

[0051] The scan signal providing unit provides the first scan output signal to the reset signal providing unit according to the scan input signal provided by the scan pin.

[0052] In response to the first scan output signal, the reset signal providing unit provides the second scan output signal to the scan input end of the logic unit under test and provides the first reset signal to the reset end of the logic unit under test.

[0053] Compared with the prior art, the reset method provided by the embodiments of the present application has the same beneficial effects as the DFT reset circuit provided in the above embodiments, which will not be repeated here.

[0054] Although the present application has been described in connection with certain embodiments, persons skilled in the art will understand and appreciate that many modifications, changes, alternatives, and substitutions are possible, without departing from the scope and spirit of the present application as disclosed in the accompanying claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single processor or other unit can fulfil the functions of several items recited in the claims. Means-plus-function or step-plus-function clauses are used where for procedural or logical operations, and the means-plus-function clauses recite a means for accomplishing a function. Means-plus-function clauses are considered a form of functional claiming under 35 U.S.C. § 112, under the Federal Circuit's decisions in Diamond v. Diehr, 450 U.S. 175, 185 (1981) and Anderson's Black Rock, Inc. v. Pavco, Inc., 812 F.2d 541, 544-45 (Fed. Cir. 1987). The means may-comprise one or more of the specified functions.

[0055] Although the present application has been described in connection with specific features and embodiments thereof, it will be evident to those skilled in the art that various modifications and combinations are possible without departing from the spirit and scope of the application. Accordingly, the description and drawings are to be regarded as illustrative in nature and are not to be taken as limiting the scope of the application as defined by the appended claims. Obviously, many modifications and variations of the present application are possible in light of its teachings. It is, therefore, to be understood that within the scope of the appended claims and their equivalents, the application can be practiced otherwise than as specifically described.

Claims

1. A DFT reset circuit for reset management of a logic unit under test of a chip, characterized in that, The application relates to a scan signal providing unit and a reset signal providing unit. An output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested.

2. The DFT reset circuit of claim 1, wherein, The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal.

3. The DFT reset circuit of claim 1, wherein, The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and the scan signal providing unit is used for providing a first scan output signal to the reset signal providing unit according to a scan input signal provided by the scan pin. The reset signal providing unit is used for providing a second scan output signal to the scan input end of the logic unit to be tested and a first reset signal to the reset end of the logic unit to be tested according to the first scan output signal. The output end of the scan signal providing unit is electrically connected with a scan input end of the logic unit to be tested through the reset signal providing unit, and an output end of the reset signal providing unit is electrically connected with a reset end of the logic unit to be tested. The scan signal providing unit comprises a scan pin, and The scan enable signal end is also electrically connected with a scan enable end of the logic unit under test, and is used for providing a scan enable signal to the scan enable end of the logic unit under test.

4. The DFT reset circuit of claim 1, wherein, The reset signal output module comprises a data selector and a reset signal end, wherein: The first input end of the data selector is electrically connected with an external function logic signal end, the second input end of the data selector is electrically connected with the output end of the selection module through the reset signal end, the selection end of the data selector is electrically connected with an external test signal end, and the output end of the data selector is electrically connected with a reset end of the logic unit under test, and is used for providing the first reset signal to the reset end of the logic unit under test.

5. The DFT reset circuit of claim 1, wherein, The scan signal providing unit further comprises a first silicon chip pin and a scan signal end; The scan pin, the first silicon chip pin and the scan signal end are electrically connected in sequence, and the output end of the scan signal end is electrically connected with the reset signal providing unit.

6. The DFT reset circuit of claim 1, wherein, The DFT reset circuit further comprises a scan signal output unit, which is electrically connected with an output end of the logic unit under test, and is used for outputting a third scan output signal of the logic unit under test, wherein the third scan output signal is generated after the second scan output signal passes through the logic unit under test. The scan signal output unit comprises an output pin, a second silicon chip pin and a scan signal output end, wherein: The output end of the logic unit under test, the scan signal output end, the second silicon chip pin and the output pin are electrically connected in sequence.

7. The DFT reset circuit of claim 1, wherein, The DFT reset circuit further comprises a clock signal end, which is electrically connected with a clock input end of the reset signal providing unit and a clock input end of the logic unit under test respectively, and is used for providing a clock signal to the reset signal providing unit and the logic unit under test.

8. A reset device, characterized by The DFT reset circuit comprises the DFT reset circuit according to any one of claims 1-7.

9. A reset method, comprising: The reset method is applied to the DFT reset circuit according to any one of claims 1-7, and the reset method comprises: The scan signal providing unit provides a first scan output signal to the reset signal providing unit according to a scan input signal provided by a scan pin; In response to the first scan output signal, the reset signal providing unit provides a second scan output signal to a scan input end of the logic unit under test, and provides a first reset signal to a reset end of the logic unit under test.

Images