Circuit generation method, device, electronic device and storage medium

Abstract

The present application provides a circuit generation method, device, electronic device and storage medium, including: obtaining circuit design parameters, the circuit design parameters include the desired circuit characteristics, the upper limit of the number of devices and the number of device ports; establishing a data set based on the desired circuit characteristics; constructing multiple candidate circuits based on a neural network model; for each candidate circuit, based on fixed device design parameters and data sets, obtaining the device port parameters of the candidate circuit through feasible analysis training; performing incremental analysis on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; obtaining the device design parameters of the candidate circuit through quantitative analysis training according to the data set and the simulation output of the candidate circuit; and obtaining the final circuit. The above scheme constructs the circuit through the neural network model and obtains the final circuit through analysis and screening, thereby automatically generating the circuit, reducing manual operations and improving efficiency.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a circuit generation method, device, electronic device, and storage medium. Background Art

[0002] At present, for complex circuit functions and various types of circuit devices, the circuit design mainly relies on the experience of R&D personnel, and the feasibility of the circuit is verified through simulation.

[0003] However, as analog circuits advance to the nanometer scale, integrated circuits are becoming increasingly complex and integrated. Relying on R&D personnel's experience to design circuits is inefficient. Therefore, the challenge is to efficiently generate circuits. Summary of the Invention

[0004] The present application provides a circuit generation method, device, electronic device and storage medium for efficiently generating circuits.

[0005] In a first aspect, the present application provides a circuit generation method including: obtaining circuit design parameters, wherein the circuit design parameters include desired circuit characteristics, an upper limit on the number of devices, and the number of device ports; establishing a data set based on the desired circuit characteristics; constructing multiple candidate circuits based on a neural network model according to the number of device ports, the upper limit on the number of devices, and the types of candidate devices; for each candidate circuit, obtaining the device port parameters of the candidate circuit through feasibility analysis training based on fixed device design parameters and a data set; if the feasibility analysis passes, performing an incremental analysis on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the incremental analysis passes, obtaining the device design parameters of the candidate circuit through quantitative analysis training according to the data set and the simulation output of the candidate circuit; wherein the device port parameters include electrical signal parameters of each device port, and the data set includes multiple sets of standard inputs and corresponding standard outputs; and obtaining a final circuit based on the candidate circuit that passes the quantitative analysis.

[0006] In one possible implementation, for each candidate circuit, based on fixed device design parameters, the device port parameters of the candidate circuit are obtained by performing feasibility analysis training, including: based on a first objective function as the optimization target of the optimizer, performing iterative training of the feasibility analysis until the first objective function is met, wherein the first objective function characterizes that the voltage input to each port and the voltage output of the port are equal and the sum of the currents is equal to 0; if the number of iterations of the feasibility analysis exceeds a preset first threshold, the candidate circuit is screened out; if the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit has passed the feasibility analysis.

[0007] In one possible implementation, if the feasibility analysis passes, then an additive and subtractive analysis is performed on the candidate circuit based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set, including: if the feasibility analysis passes, then each standard input in the data set is used as the actual input of the candidate circuit, and iterative training of the additive and subtractive analysis is performed until the second objective function is satisfied, wherein the second objective function characterizes that the error between the current actual output and the standard output does not exceed a preset second threshold; wherein, if the number of iterations of this additive and subtractive analysis exceeds a preset third threshold, this training is recorded as 0; if the number of iterations of this additive and subtractive analysis does not exceed the preset third threshold, the current actual output of the candidate circuit is recorded; and correlation analysis is performed on all records of the additive and subtractive analysis training with the standard output in the data set, and if the correlation analysis result is greater than a preset fourth threshold, it is determined that the candidate circuit has passed the additive and subtractive analysis.

[0008] In one possible embodiment, if the incremental analysis passes, the device design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit, including: using the standard input in the data set as the simulation input of the candidate circuit, simulating the candidate circuit based on a circuit simulator, and obtaining the simulation output of the candidate circuit; and randomly generating current training design parameters based on the initial values ​​of the device design parameters and a predetermined standard deviation range; training a prediction model for predicting device design parameters based on the simulation output based on a probability algorithm based on the current training design parameters and the corresponding simulation output; using the simulation output of the candidate circuit as input to obtain the device design parameters output by the prediction model and the standard deviation range of the output; randomly generating current training design parameters based on the output device design parameters and the standard deviation range of the output; and, again executing the step of training the prediction model for predicting device design parameters based on the simulation output based on the probability algorithm based on the current training design parameters and the corresponding simulation output until the number of model training times exceeds a preset fifth threshold, then using the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and determining that the candidate circuit passes the quantitative analysis.

[0009] In a possible implementation, obtaining the final circuit based on the candidate circuits that pass the quantitative analysis includes: screening the candidate circuits that pass the quantitative analysis and pushing the screened candidate circuits to the user; and using the candidate circuit selected by the user as the final circuit.

[0010] In a second aspect, the present application provides a circuit generation device, comprising: an acquisition module for acquiring circuit design parameters, wherein the circuit design parameters include desired circuit characteristics, an upper limit on the number of devices, and the number of device ports; establishing a data set based on the desired circuit characteristics; a construction module for constructing multiple candidate circuits based on a neural network model according to the number of device ports, the upper limit on the number of devices, and the types of candidate devices; a training module for obtaining the device port parameters of the candidate circuit through feasibility analysis training based on fixed device design parameters and a data set for each candidate circuit; if the feasibility analysis passes, performing an incremental analysis on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the incremental analysis passes, obtaining the device design parameters of the candidate circuit through quantitative analysis training according to the data set and the simulation output of the candidate circuit; wherein the device port parameters include electrical signal parameters of each device port, and the data set includes multiple sets of standard inputs and corresponding standard outputs; a screening module for obtaining the final circuit based on the candidate circuit that passes the quantitative analysis.

[0011] In one possible implementation, the training module is specifically used to perform iterative training of the feasibility analysis based on a first objective function as the optimization target of the optimizer until the first objective function is satisfied, wherein the first objective function characterizes that the voltage input to each port and the voltage output of the port are equal and the sum of the currents is equal to 0; the training module is also specifically used to screen out the candidate circuit if the number of iterations of the feasibility analysis exceeds a preset first threshold; if the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit has passed the feasibility analysis.

[0012] In one possible embodiment, the training module is specifically used to, if the feasibility analysis passes, use each standard input in the data set as the actual input of the candidate circuit, and perform iterative training of the incremental analysis until the second objective function is met, wherein the second objective function characterizes that the error between the current actual output and the standard output does not exceed the preset second threshold; wherein, if the number of iterations of this incremental analysis exceeds the preset third threshold, this training will be recorded as 0; if the number of iterations of this incremental analysis does not exceed the preset third threshold, the current actual output of the candidate circuit is recorded; the training module is also specifically used to perform correlation analysis on all records of incremental analysis training with the standard output in the data set, and if the correlation analysis result is greater than the preset fourth threshold, it is determined that the candidate circuit has passed the incremental analysis.

[0013] In one possible embodiment, if the increase / decrease analysis passes, the device design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit, including: the training module is specifically used to use the standard input in the data set as the simulation input of the candidate circuit, simulate the candidate circuit based on a circuit simulator, and obtain the simulation output of the candidate circuit; and randomly generate the current training design parameters based on the initial value of the device design parameter and a predetermined standard deviation range; the training module is also specifically used to train the device design parameters for prediction based on the simulation output based on the current training design parameters and the corresponding simulation output based on a probability-based algorithm. A prediction model for device design parameters; taking the simulation output of the candidate circuit as input to obtain the device design parameters output by the prediction model and the standard deviation range of the output; the training module is specifically used to randomly generate current training design parameters based on the output device design parameters and the standard deviation range of the output; and again executing the step of training the prediction model for predicting device design parameters based on the simulation output based on the current training design parameters and the corresponding simulation output based on a probability-based algorithm until the number of model training times exceeds a preset fifth threshold, then using the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and determining that the candidate circuit passes the quantitative analysis.

[0014] In a possible implementation, the screening module is specifically configured to screen candidate circuits that have passed the quantitative analysis and push the screened candidate circuits to the user; the screening module is also specifically configured to use the candidate circuit selected by the user as the final circuit.

[0015] In a third aspect, the present application provides an electronic device comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement any of the methods described in the first aspect.

[0016] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by a processor as described in any one of the methods in the first aspect.

[0017] The circuit generation method, device, electronic device and storage medium provided in the present application obtain circuit design parameters, wherein the circuit design parameters include the desired circuit characteristics, the upper limit of the number of devices and the number of device ports; a data set is established based on the desired circuit characteristics; multiple candidate circuits are constructed based on the number of device ports, the upper limit of the number of devices and the types of candidate devices based on a neural network model; for each candidate circuit, the device port parameters of the candidate circuit are obtained through feasibility analysis training based on fixed device design parameters and a data set; if the feasibility analysis passes, the candidate circuit is subjected to an increase-decrease analysis based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the increase-decrease analysis passes, the device design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit; wherein the device port parameters include the electrical signal parameters of each device port, and the data set includes multiple sets of standard inputs and corresponding standard outputs; and the final circuit is obtained based on the candidate circuit that passes the quantitative analysis. The above scheme constructs the circuit through a neural network model and obtains the final circuit through analysis and screening, thereby automatically generating the circuit, reducing manual operations and improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an application scenario of a circuit generation method provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a flow chart of a circuit generation method provided in Example 1 of the present application;

[0021] Figure 3 An example of circuit feasibility analysis provided for the embodiments of this application;

[0022] Figure 4 This is a structural example diagram of a circuit generating device provided in Example 2 of the present application;

[0023] Figure 5 This is a device block diagram of a circuit generating device provided in Example 3 of the present application;

[0024] Figure 6 This is a structural diagram of an electronic device provided in Example 4 of the present application.

[0025] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0026] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0027] First, let’s explain the nouns involved:

[0028] Spice model (Simulation program with integrated circuit emphasis, referred to as Spice): an analog circuit simulator used for circuit analysis of integrated circuits.

[0029] Figure 1 This diagram illustrates an application scenario for a circuit generation method provided in an embodiment of the present application. For example, the illustrated scenario: a neural network model obtains the user's circuit design parameters and constructs multiple candidate circuits. The candidate circuits undergo qualitative and quantitative analysis, eliminating those that fail the analysis to obtain the final circuit. The final circuit is then presented to the user for selection.

[0030] The solutions of the embodiments of the present application are described below with reference to the following embodiments.

[0031] Example 1

[0032] Figure 2 This is a flow chart of a circuit generation method provided in Example 1 of the present application, the method comprising the following steps:

[0033] S101, obtaining circuit design parameters, wherein the circuit design parameters include desired circuit characteristics, an upper limit on the number of components, and a number of component ports; and establishing a data set based on the desired circuit characteristics;

[0034] S102, constructing multiple candidate circuits based on a neural network model according to the number of device ports, the upper limit of the number of devices, and the types of candidate devices;

[0035] S103. For each candidate circuit, based on fixed device design parameters and a data set, obtain device port parameters of the candidate circuit through feasibility analysis training; if the feasibility analysis passes, perform an additive and subtractive analysis on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the additive and subtractive analysis passes, obtain device design parameters of the candidate circuit through quantitative analysis training according to the data set and the simulated output of the candidate circuit; wherein the device port parameters include electrical signal parameters of each device port, and the data set includes multiple sets of standard inputs and corresponding standard outputs;

[0036] S104: Obtain a final circuit based on the candidate circuits that pass the quantitative analysis.

[0037] As an example, the execution subject of this embodiment may be a circuit generation device, which can be implemented in various ways. For example, it may be program software, or a medium storing the relevant computer program, such as a USB flash drive. Alternatively, the device may be a physical device integrated or installed with the relevant computer program, such as a chip, smart terminal, computer, server, etc.

[0038] In one example, S101 includes: obtaining the upper limit of the number of devices in the device library; obtaining the number of device ports defined by the user; obtaining the circuit characteristics expected by the user;

[0039] As one possible implementation, a series of input and output voltage or current results are constructed based on the user-designed circuit characteristics to create a data set. For example, if the user-designed circuit characteristic is voltage amplification, a series of voltages are constructed as inputs, and a series of voltages multiplied by the amplification factor are constructed as outputs.

[0040] For example, the upper limit on the number of components is obtained directly from the component library. The number of device ports is set based on user requirements. All components are standardized to the user-defined number of device ports. For example, if the user sets the number of device ports to 3, all components are standardized to 3-port devices. Each port of each device contains two variables: current and voltage. For components such as resistors that are smaller than a 3-port device, the excess ports can be equivalent to ports with constant current and voltage of 0. Similarly, open circuits, short circuits, and power supplies can be equivalent to 3-port devices. Similarly, combinations of multiple components can be equivalent to 3-port devices.

[0041] Optionally, port design is performed based on a neural network simulation Spice model.

[0042] Based on the above implementation, circuit design parameters are obtained, and then a circuit that meets the conditions is automatically generated according to the circuit design parameters.

[0043] Next, based on the obtained circuit design parameters, the circuit is automatically generated and circuit analysis is performed.

[0044] In one example, S102 includes: calculating and obtaining a maximum number of generated circuits; and sequentially constructing a plurality of candidate circuits according to the maximum number of circuits.

[0045] Optionally, the maximum number of generated circuits is calculated based on the maximum circuit number calculation formula:

[0046] ((M*N)^N)*C)^M

[0047] Where M is the upper limit of the number of devices, N is the number of device ports, and C is the type of candidate devices.

[0048] According to the maximum number of circuits, a plurality of candidate circuits are constructed based on a neural network model.

[0049] Based on the above implementation, all circuits that meet the circuit design parameters are generated by enumeration to avoid circuit omission.

[0050] The above solution generates multiple circuits that meet the circuit design parameters. Circuit analysis is then required to verify the circuit's reliability. This circuit analysis includes qualitative and quantitative analysis. Qualitative analysis includes feasibility analysis and incremental analysis, while quantitative analysis is used to determine the circuit's device design parameters. The following example illustrates the circuit analysis process.

[0051] In one example, S103 includes: performing iterative training of feasibility analysis based on a first objective function as the optimization target of the optimizer until the first objective function is satisfied, wherein the first objective function characterizes that the voltage input to each port and the voltage output of the port are equal and the sum of the currents is equal to 0; if the number of iterations of the feasibility analysis exceeds a preset first threshold, the candidate circuit is screened out; if the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit has passed the feasibility analysis.

[0052] In combination with the scenario example, qualitative analysis includes feasibility analysis and increase / decrease analysis. Feasibility analysis is represented by the first objective function. If the first objective function is satisfied, that is, the voltage input to each port of the circuit is equal to the voltage output from the port and the sum of the currents is equal to 0, it means that each port of the circuit can flow normally. If there is a port short circuit, the current cannot pass through the port, and the voltage input to the port and the voltage output from the port are equal and the sum of the currents is equal to 0 is not satisfied. Iterative optimization is performed using the first objective function as the optimization target of the optimizer. If the number of iterations exceeds the preset first threshold and the first objective function is not reached, it is determined that the circuit has failed the feasibility analysis. The number of iterations is limited by the first threshold to prevent infinite loop iterations.

[0053] For ease of understanding, Figure 3 For example, circuit feasibility analysis Figure 3 As shown in the figure, the ports of multiple devices in a circuit are connected. If the circuit can flow normally, the voltages flowing through the ports are equal and the sum of the currents is equal to 0. The current meter at the input port is positive, the current meter at the output port is negative, and the absolute value of the sum of the currents at the input port is equal to the absolute value of the sum of the currents at the output port.

[0054] Based on the above implementation, the candidate circuit is iteratively optimized using the first objective function to obtain the device port parameters of the circuit to ensure normal circuit flow. The number of iterations is constrained by the first threshold to prevent infinite loop iterations.

[0055] In one example, S103 also includes: if the feasibility analysis passes, each standard input in the data set is used as the actual input of the candidate circuit, and iterative training of the incremental analysis is performed until the second objective function is met, wherein the second objective function represents that the error between the current actual output and the standard output does not exceed the preset second threshold; wherein, if the number of iterations of this incremental analysis exceeds the preset third threshold, this training is recorded as 0; if the number of iterations of this incremental analysis does not exceed the preset third threshold, the current actual output of the candidate circuit is recorded; all records of the incremental analysis training are correlated with the standard output in the data set, and if the correlation analysis result is greater than the preset fourth threshold, it is determined that the candidate circuit has passed the incremental analysis.

[0056] Using a scenario example, incremental / subtractive analysis is used to determine whether a circuit's functionality meets user requirements. The data set is constructed based on user requirements. The candidate circuit is trained using the secondary objective function by sequentially acquiring input from the data set. If the candidate circuit's output is within the error range of the data set's output, the candidate circuit's functionality meets user requirements.

[0057] Based on the above implementation, the second objective function is used to verify whether the candidate circuit can achieve the circuit characteristics designed by the user.

[0058] The above solution performs a qualitative analysis on candidate circuits, screening out those that can function normally and meet the circuit characteristics designed by the user. The following is an example of the quantitative analysis process.

[0059] In one example, S103 also includes: using the standard input in the data set as the simulation input of the candidate circuit, simulating the candidate circuit based on a circuit simulator, and obtaining the simulation output of the candidate circuit; and randomly generating the current training design parameters based on the initial value of the device design parameters and the predetermined standard deviation range; training a prediction model for predicting the device design parameters based on the simulation output based on the current training design parameters and the corresponding simulation output based on a probability algorithm; using the simulation output of the candidate circuit as input to obtain the device design parameters output by the prediction model and the standard deviation range of the output; randomly generating the current training design parameters based on the output device design parameters and the standard deviation range of the output; and, again executing the step of training the prediction model for predicting the device design parameters based on the simulation output based on the probability algorithm based on the current training design parameters and the corresponding simulation output until the number of model training times exceeds the preset fifth threshold, then using the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and determining whether the candidate circuit passes the quantitative analysis.

[0060] For example, quantitative analysis is used to determine the device design parameters of a circuit. Device design parameters are the property parameters of the device itself, such as the resistance value of a resistor. Based on the initial values ​​of the device design parameters set by the user, a series of device design parameters are generated within a predetermined standard deviation range. Simulation output is generated by simulating the input data in the candidate circuit input dataset. Iterative training is then used to optimize the device design parameters by predicting the series of device design parameters using the simulation outputs.

[0061] Optionally, a hash table is constructed using simulation outputs as keys and corresponding circuits as values.

[0062] Based on the above implementation methods, the final device design parameters are optimized by training the simulation output to predict the device design parameter model.

[0063] In the above scheme, the candidate circuits are analyzed to obtain the optimized circuits, and then the optimized circuit selection stage is carried out to obtain the final circuit.

[0064] In one example, S104 includes: screening candidate circuits that pass the quantitative analysis, and pushing the screened candidate circuits to the user; and using the candidate circuit selected by the user as the final circuit.

[0065] Optionally, plot each key of the hash table as a radar chart. If radar chart a is included in radar chart b, remove radar chart a.

[0066] Taking the scenario example as an example, the candidate circuits that pass the quantitative analysis are screened and pushed to the user, and the user can select the circuit that meets the needs.

[0067] Based on the above implementations, the final circuit is determined by user selection, so that the final circuit meets user needs.

[0068] In the circuit generation method provided in this embodiment, circuit design parameters are obtained, wherein the circuit design parameters include the desired circuit characteristics, the upper limit of the number of devices, and the number of device ports; a data set is established based on the desired circuit characteristics; multiple candidate circuits are constructed based on the number of device ports, the upper limit of the number of devices, and the types of candidate devices based on a neural network model; for each candidate circuit, the device port parameters of the candidate circuit are obtained through feasibility analysis training based on fixed device design parameters and the data set; if the feasibility analysis passes, the candidate circuit is subjected to an incremental analysis based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the incremental analysis passes, the device design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit; wherein the device port parameters include the electrical signal parameters of each device port, and the data set includes multiple sets of standard inputs and corresponding standard outputs; and the final circuit is obtained based on the candidate circuits that pass the quantitative analysis. The above scheme constructs the circuit through the neural network model and obtains the final circuit through analysis and screening, thereby automatically generating the circuit, reducing manual operations and improving efficiency.

[0069] Example 2

[0070] Figure 4 This is a schematic diagram of the structure of a circuit generating device provided in Example 2 of the present application, such as Figure 4 As shown, the device includes:

[0071] An acquisition module 61 is configured to acquire circuit design parameters, including desired circuit characteristics, an upper limit on the number of components, and a number of component ports; and to establish a data set based on the desired circuit characteristics.

[0072] A construction module 62 is configured to construct a plurality of candidate circuits based on a neural network model according to the number of device ports, the upper limit of the number of devices, and the types of candidate devices;

[0073] A training module 63 is configured to, for each candidate circuit, obtain device port parameters of the candidate circuit through feasibility analysis training based on fixed device design parameters and a data set; if the feasibility analysis passes, perform an incremental analysis on the candidate circuit based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the incremental analysis passes, obtain device design parameters of the candidate circuit through quantitative analysis training based on the data set and the simulated output of the candidate circuit; wherein the device port parameters include electrical signal parameters of each device port, and the data set includes multiple sets of standard inputs and corresponding standard outputs;

[0074] The screening module 64 is configured to obtain a final circuit based on candidate circuits that pass the quantitative analysis.

[0075] In one example, the acquisition module 61 is specifically used to obtain the upper limit of the number of devices in the device library; the acquisition module 61 is also specifically used to obtain the number of device ports defined by the user; the acquisition module 61 is also specifically used to obtain the circuit characteristics expected by the user.

[0076] In one embodiment, acquisition module 61 constructs a series of input and output voltage or current results based on the user-designed circuit characteristics to create a data set. For example, if the user-designed circuit characteristic is voltage amplification, a series of voltages are constructed as inputs, and a series of voltages are multiplied by amplification factors as output data sets.

[0077] For example, the upper limit on the number of components is obtained directly from the component library. The number of device ports is set based on user requirements. All components are standardized to the user-defined number of device ports. For example, if the user sets the number of device ports to 3, all components are standardized to 3-port devices. Each port of each device contains two variables: current and voltage. For components such as resistors that are smaller than a 3-port device, the excess ports can be equivalent to ports with constant current and voltage of 0. Similarly, open circuits, short circuits, and power supplies can be equivalent to 3-port devices. Similarly, combinations of multiple components can be equivalent to 3-port devices.

[0078] Optionally, port design is performed based on a neural network simulation Spice model.

[0079] Based on the above implementation, circuit design parameters are obtained, and then a circuit that meets the conditions is automatically generated according to the circuit design parameters.

[0080] Next, based on the obtained circuit design parameters, the circuit is automatically generated and circuit analysis is performed.

[0081] In one example, the construction module 62 is specifically configured to calculate a maximum number of generated circuits; the construction module 62 is further specifically configured to sequentially construct a plurality of candidate circuits according to the maximum number of circuits.

[0082] Optionally, the maximum number of generated circuits is calculated based on the maximum circuit number calculation formula:

[0083] ((M*N)^N)*C)^M

[0084] Where M is the upper limit of the number of devices, N is the number of device ports, and C is the type of candidate devices.

[0085] According to the maximum number of circuits, a plurality of candidate circuits are constructed based on a neural network model.

[0086] Based on the above implementation, all circuits that meet the circuit design parameters are generated by enumeration to avoid circuit omission.

[0087] The above solution generates multiple circuits that meet the circuit design parameters. Circuit analysis is then performed to verify the circuit's reliability. This circuit analysis includes both qualitative and quantitative analysis. Quantitative analysis includes feasibility analysis and incremental analysis. Quantitative analysis allows the user to obtain the device design parameters for the circuit. The following example illustrates the circuit analysis process.

[0088] In one example, the training module 63 is specifically used to perform iterative training of the feasibility analysis based on the first objective function as the optimization target of the optimizer until the first objective function is met, wherein the first objective function characterizes that the voltage input to each port and the voltage output of the port are equal and the sum of the currents is equal to 0; the training module 63 is also specifically used to screen out the candidate circuit if the number of iterations of the feasibility analysis exceeds a preset first threshold; if the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit has passed the feasibility analysis.

[0089] In one embodiment, training module 63 constructs a series of input and output voltage or current results based on the user-designed circuit characteristics to create a data set. For example, if the user-designed circuit characteristic is voltage amplification, a series of voltages are used as inputs, and a series of voltages multiplied by amplification factors are used as output data sets.

[0090] In conjunction with the scenario example, qualitative analysis includes feasibility analysis and increase / decrease analysis. Feasibility analysis is represented by the first objective function. If the first objective function is satisfied, that is, the voltage of each port of the circuit and the output of the port are equal and the sum of the currents is equal to 0, it means that each port of the circuit can flow normally. If there is a port open circuit, the current cannot pass through the port, then the voltage of the input port and the output port are equal and the sum of the currents is equal to 0. The training module 63 performs iterative optimization with the first objective function as the optimization target of the optimizer. If the number of iterations exceeds the preset first threshold and the first objective function is not reached, it is determined that the circuit does not pass the feasibility analysis. The number of iterations is limited by the first threshold to prevent infinite loop iterations.

[0091] Based on the above embodiment, the training module 63 iteratively optimizes the candidate circuit using the first objective function to obtain the device port parameters of the circuit to ensure normal circuit operation. The first threshold is used to constrain the number of iterations to prevent infinite loop iterations.

[0092] In one example, the training module 63 is specifically used to, if the feasibility analysis passes, use each standard input in the data set as the actual input of the candidate circuit to perform iterative training of the incremental analysis until the second objective function is met, wherein the second objective function characterizes that the error between the current actual output and the standard output does not exceed the preset second threshold; wherein, if the number of iterations of this incremental analysis exceeds the preset third threshold, this training will be recorded as 0; if the number of iterations of this incremental analysis does not exceed the preset third threshold, the current actual output of the candidate circuit is recorded; the training module 63 is also specifically used to perform correlation analysis on all records of the incremental analysis training and the standard output in the data set, and if the correlation analysis result is greater than the preset fourth threshold, it is determined that the candidate circuit has passed the incremental analysis.

[0093] In this scenario example, incremental analysis is used to determine whether a circuit's functionality meets user requirements. The data in the dataset is constructed based on user requirements. Training module 63 sequentially obtains input from the dataset and trains candidate circuits using the second objective function. If the candidate circuit's output and the dataset's output are within the error range, the candidate circuit's functionality meets user requirements.

[0094] Based on the above implementation, the second objective function is used to verify whether the candidate circuit can achieve the circuit characteristics designed by the user.

[0095] The above solution performs a qualitative analysis on candidate circuits, screening out those that can function normally and meet the circuit characteristics designed by the user. The following is an example of the quantitative analysis process.

[0096] In one example, the training module 63 is specifically used to use the standard input in the data set as the simulation input of the candidate circuit, simulate the candidate circuit based on a circuit simulator, and obtain the simulation output of the candidate circuit; and randomly generate the current training design parameters based on the initial value of the device design parameter and the predetermined standard deviation range; the training module 63 is also specifically used to train a prediction model for predicting the device design parameters based on the simulation output based on the current training design parameters and the corresponding simulation output based on a probability algorithm; use the simulation output of the candidate circuit as input to obtain the device design parameters output by the prediction model and the standard deviation range of the output; the training module 63 is also specifically used to randomly generate the current training design parameters based on the output device design parameters and the standard deviation range of the output; and, again execute the step of training the prediction model for predicting the device design parameters based on the simulation output based on the probability algorithm based on the current training design parameters and the corresponding simulation output until the number of model training times exceeds the preset fifth threshold, then use the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and determine whether the candidate circuit passes the quantitative analysis.

[0097] In this scenario example, quantitative analysis is used to obtain device design parameters for a circuit. Device design parameters are property parameters of the device itself, such as the device design parameters of a resistor, i.e., the resistance value. Training module 63 generates a series of device design parameters within a predetermined standard deviation range based on the initial values ​​of the device design parameters set by the user. Simulation output is generated by simulating the input data in the candidate circuit input dataset. Iterative training is performed to optimize the device design parameters by using a model that predicts a series of device design parameters using the simulation outputs.

[0098] Optionally, a hash table is constructed using simulation outputs as keys and corresponding circuits as values.

[0099] Based on the above implementation, the training module 63 optimizes and obtains the final device design parameters by outputting a prediction device design parameter model through training simulation.

[0100] In the above scheme, the candidate circuits are analyzed to obtain the optimized circuits, and then the optimized circuit selection stage is carried out to obtain the final circuit.

[0101] In one example, the screening module 64 is specifically configured to screen candidate circuits that have passed the quantitative analysis and push the screened candidate circuits to the user; the screening module 64 is also specifically configured to use the candidate circuit selected by the user as the final circuit.

[0102] Optionally, plot each key of the hash table as a radar chart. If radar chart a is included in radar chart b, remove radar chart a.

[0103] In combination with the scenario example, the screening module 64 pushes the candidate circuits obtained through quantitative analysis to the user after screening, and the user can select the circuit that meets the requirements.

[0104] Based on the above implementations, the final circuit is determined by user selection, so that the final circuit meets user needs.

[0105] In the circuit generation device provided in this embodiment, an acquisition module is used to acquire circuit design parameters, wherein the circuit design parameters include desired circuit characteristics, an upper limit on the number of components, and the number of component ports; a data set is established based on the desired circuit characteristics; a construction module is used to construct multiple candidate circuits based on the number of component ports, the upper limit on the number of components, and the types of candidate components based on a neural network model; a training module is used to obtain the component port parameters of each candidate circuit through feasibility analysis training based on fixed component design parameters and a data set; if the feasibility analysis passes, the candidate circuit is subjected to an incremental analysis based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; if the incremental analysis passes, the component design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit; wherein the component port parameters include electrical signal parameters of each component port, and the data set includes multiple sets of standard inputs and corresponding standard outputs; and a screening module is used to obtain a final circuit based on the candidate circuits that pass the quantitative analysis. In the above scheme, a circuit is constructed through a neural network model, and the final circuit is obtained through analysis and screening, thereby generating a circuit, reducing manual operations and improving efficiency.

[0106] Example 3

[0107] Figure 5 This is a device block diagram of a circuit generating device according to an exemplary embodiment. The device may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0108] Apparatus 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output interface 812 , a sensor component 814 , and a communication component 816 .

[0109] The processing component 802 generally controls the overall operation of the device 800, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 802 may include one or more modules to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

[0110] The memory 804 is configured to store various types of data to support the operations of the device 800. Examples of such data include instructions for any application or method operating on the device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0111] The power supply component 806 provides power to the various components of the device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device 800.

[0112] The multimedia component 808 includes a screen that provides an output interface between the device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0113] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC), which is configured to receive external audio signals when the device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0114] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0115] The sensor assembly 814 includes one or more sensors for providing various aspects of the status assessment of the device 800. For example, the sensor assembly 814 can detect the open / closed state of the device 800, the relative positioning of components, such as the display and keypad of the device 800. The sensor assembly 814 can also detect changes in the position of the device 800 or a component of the device 800, the presence or absence of user contact with the device 800, the orientation or acceleration / deceleration of the device 800, and temperature changes of the device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0116] The communication component 816 is configured to facilitate wired or wireless communication between the device 800 and other devices. The device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0117] In an exemplary embodiment, the apparatus 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described method.

[0118] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the instructions can be executed by the processor 820 of the apparatus 800 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0119] Example 4

[0120] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Figure 6 As shown, the electronic device includes:

[0121] The electronic device includes a processor 291 and a memory 292; a communication interface 293, and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via bus 294. Communication interface 293 can be used for information transmission. The processor 291 can invoke logic instructions in memory 292 to execute the methods of the above embodiments.

[0122] In addition, the logic instructions in the memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0123] Memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present application. Processor 291 executes the software programs, instructions, and modules stored in memory 292 to perform functional applications and data processing, thereby implementing the methods in the above-mentioned method embodiments.

[0124] Memory 292 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Memory 292 may also include high-speed random access memory and non-volatile memory.

[0125] An embodiment of the present application provides a non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions. When the computer-executable instructions are executed by a processor, they are used to implement the method described in the above embodiment.

[0126] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0127] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A circuit generation method, characterized in that: include: Obtaining circuit design parameters, wherein the circuit design parameters include desired circuit characteristics, an upper limit on the number of components, and a number of component ports; Establishing a data set according to the desired circuit characteristics; Constructing a plurality of candidate circuits based on a neural network model according to the number of device ports, the upper limit of the number of devices, and the types of candidate devices; For each candidate circuit, based on fixed device design parameters and a data set, device port parameters of the candidate circuit are obtained through feasible analysis training; If the feasibility analysis passes, performing an incremental analysis on the candidate circuit based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; If the increase / decrease analysis passes, then the device design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit; wherein the device port parameters include electrical signal parameters of each port of the device, and the data set includes multiple sets of standard inputs and corresponding standard outputs; Obtaining the final circuit based on the candidate circuits that pass the quantitative analysis; If the incremental analysis passes, the device design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit, including: using the standard input in the data set as the simulation input of the candidate circuit, simulating the candidate circuit based on a circuit simulator, and obtaining the simulation output of the candidate circuit; and randomly generating current training design parameters based on the initial values ​​of the device design parameters and a predetermined standard deviation range; training a prediction model for predicting device design parameters based on the simulation output based on a probability algorithm based on the current training design parameters and the corresponding simulation output; using the simulation output of the candidate circuit as input to obtain the device design parameters output by the prediction model and the standard deviation range of the output; randomly generating current training design parameters based on the output device design parameters and the standard deviation range of the output; and, again executing the step of training the prediction model for predicting device design parameters based on the simulation output based on the probability algorithm based on the current training design parameters and the corresponding simulation output until the number of model training times exceeds a preset fifth threshold, then using the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and determining that the candidate circuit passes the quantitative analysis.

2. The method according to claim 1, characterized in that For each candidate circuit, obtaining the device port parameters of the candidate circuit by performing feasible analysis training based on fixed device design parameters includes: Based on a first objective function as an optimization target of the optimizer, iterative training of the feasibility analysis is performed until the first objective function is satisfied, wherein the first objective function represents that the voltage input to each port and the voltage output from the port are equal and the sum of the currents is equal to 0; If the number of iterations of the feasibility analysis exceeds a preset first threshold, the candidate circuit is screened out; if the number of iterations of the feasibility analysis does not exceed the first threshold, it is determined that the candidate circuit passes the feasibility analysis.

3. The method according to claim 1, characterized in that If the feasibility analysis passes, performing an incremental analysis on the candidate circuit according to the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set, including: If the feasibility analysis passes, each standard input in the data set is used as the actual input of the candidate circuit, and iterative training of the incremental and subtractive analysis is performed until a second objective function is satisfied, wherein the second objective function indicates that the error between the current actual output and the standard output does not exceed a preset second threshold; If the number of iterations of this increase / decrease analysis exceeds a preset third threshold, the training is recorded as 0; if the number of iterations of this increase / decrease analysis does not exceed the preset third threshold, the current actual output of the candidate circuit is recorded; A correlation analysis is performed on all records of the incremental analysis training and the standard output in the data set. If the correlation analysis result is greater than a preset fourth threshold, it is determined that the candidate circuit has passed the incremental analysis.

4. The method according to any one of claims 1 to 3, characterized in that The method of obtaining a final circuit based on the candidate circuits obtained through quantitative analysis includes: Screen candidate circuits that pass quantitative analysis and push the screened candidate circuits to users; The candidate circuit selected by the user is used as the final circuit.

5. A circuit generating device, characterized in that: include: An acquisition module, configured to acquire circuit design parameters, wherein the circuit design parameters include desired circuit characteristics, an upper limit on the number of components, and a number of component ports; Create a data set based on the expected circuit characteristics; A construction module, configured to construct a plurality of candidate circuits based on a neural network model according to the number of device ports, the upper limit of the number of devices, and the types of candidate devices; A training module, configured to obtain device port parameters of each candidate circuit through feasible analysis training based on fixed device design parameters and a data set; If the feasibility analysis passes, performing an incremental analysis on the candidate circuit based on the data set and the actual output of the candidate circuit until the actual output of the candidate circuit matches the data set; If the increase / decrease analysis passes, then the device design parameters of the candidate circuit are obtained through quantitative analysis training based on the data set and the simulation output of the candidate circuit; wherein the device port parameters include electrical signal parameters of each port of the device, and the data set includes multiple sets of standard inputs and corresponding standard outputs; A screening module is used to obtain a final circuit based on candidate circuits that pass quantitative analysis; The training module is specifically used to use the standard input in the data set as the simulation input of the candidate circuit, simulate the candidate circuit based on the circuit simulator, and obtain the simulation output of the candidate circuit; and randomly generate the current training design parameters based on the initial value of the device design parameters and the predetermined standard deviation range; the training module is also specifically used to train the prediction model for predicting the device design parameters based on the simulation output based on the current training design parameters and the corresponding simulation output based on a probability algorithm; use the simulation output of the candidate circuit as input to obtain the device design parameters output by the prediction model and the standard deviation range of the output; the training module is also specifically used to randomly generate the current training design parameters based on the output device design parameters and the standard deviation range of the output; and, again execute the step of training the prediction model for predicting the device design parameters based on the simulation output based on the probability algorithm based on the current training design parameters and the corresponding simulation output until the number of model training times exceeds the preset fifth threshold, then use the device design parameters currently output by the prediction model as the device design parameters of the candidate circuit, and determine that the candidate circuit passes the quantitative analysis.

6. The device according to claim 5, characterized in that The training module is specifically configured to perform iterative training of the feasibility analysis based on a first objective function as an optimization target of the optimizer until the first objective function is satisfied, wherein the first objective function represents that the voltage input to each port and the voltage output from the port are equal and the sum of the currents is equal to 0; The training module is further configured to screen out the candidate circuit if the number of iterations of the feasibility analysis exceeds a preset first threshold; and to determine that the candidate circuit has passed the feasibility analysis if the number of iterations of the feasibility analysis does not exceed the first threshold.

7. The device according to claim 5, characterized in that The training module is specifically configured to, if the feasibility analysis passes, use each standard input in the data set as the actual input of the candidate circuit and perform iterative training of the incremental and subtractive analysis until a second objective function is satisfied, wherein the second objective function indicates that the error between the current actual output and the standard output does not exceed a preset second threshold; If the number of iterations of this increase / decrease analysis exceeds a preset third threshold, the training is recorded as 0; if the number of iterations of this increase / decrease analysis does not exceed the preset third threshold, the current actual output of the candidate circuit is recorded; The training module is further configured to perform a correlation analysis on all records of the incremental analysis training and the standard output in the data set. If the correlation analysis result is greater than a preset fourth threshold, it is determined that the candidate circuit has passed the incremental analysis.

8. The device according to any one of claims 5 to 7, characterized in that: The screening module is specifically used to screen candidate circuits that have passed the quantitative analysis and push the screened candidate circuits to the user; The screening module is further configured to select the candidate circuit selected by the user as the final circuit.

9. An electronic device, characterized in that: include: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 4 when executed by a processor.

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