Method and system for timing optimization of fpga

Abstract

The application relates to the field of integrated circuits, and discloses a timing optimization method and system of an FPGA. The method comprises the following steps: performing timing update based on the physical positions of the lookup tables allocated after layout and wiring; determining a target timing violation path based on the timing update result, and traversing the lookup tables on the target timing violation path to select a lookup table pair, wherein the selected lookup table pair is any two lookup tables connected in sequence, which satisfy the following conditions: i) each lookup table has an input line net with a positive time margin, ii) the line net between the two lookup tables is not a high fan-out line net, and iii) the number of input line nets of the latter lookup table is less than N; performing a logic reconstruction operation capable of realizing timing improvement on the selected lookup table pair respectively, and allocating corresponding physical positions to the new lookup tables after reconstruction. The embodiments of the application can effectively reduce the number of logic units passed by the timing path, and more greatly reduce the data signal delay of the timing violation path.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to timing optimization technology of FPGA. BACKGROUND

[0002] Logic synthesis and placement and routing are the two most important stages in the FPGA design process. The logic synthesis stage converts the RTL netlist into a gate-level netlist based on lookup table combinatorial logic cells through circuit conversion, optimization and mapping, etc. The placement and routing stage places and routes the logic cells in the circuit and optimizes the timing to complete the physical-level implementation of the circuit that meets the timing requirements. Current FPGA integrated circuit automation design software basically only optimizes the circuit of the lookup table combinatorial logic cell in the logic synthesis stage before the placement and routing stage, and rarely optimizes the circuit logic of the lookup table in the placement and routing stage. One of the reasons is that circuit logic optimization is only performed in the logic synthesis stage in the traditional integrated circuit automation design process concept. The second reason is that it is difficult to effectively improve the circuit performance by optimizing the circuit logic after the placement, i.e. the physical position of the circuit logic cell, for the FPGA integrated circuit.

[0003] The existing timing optimization process in the placement and routing stage mainly adjusts the physical position of the logic cell on the timing violation path to reduce the delay on the timing violation path. For large-scale and high-complexity FPGA integrated circuits, it is difficult to effectively solve the timing problem of the timing violation path by relying only on the physical position adjustment of the logic cell. Therefore, other timing optimization methods are gradually adopted, including logic cell duplication optimization on the timing violation path, logic cell connection pin optimization on the violation path, and lookup table input connection exchange method on the violation path. These optimization methods help improve the efficiency of timing optimization to some extent, but basically do not involve circuit logic optimization operations. The timing optimization methods in the placement and routing stage of the current FPGA integrated circuit automation design software mainly include logic cell position adjustment optimization, logic cell duplication optimization on the timing violation path, logic cell connection pin optimization on the violation path, and lookup table input connection exchange method on the violation path. The purpose of these optimization methods is basically to reduce the data signal delay of the timing violation path by reducing the delay of a certain segment of the line network or the delay of a certain logic cell. Because it basically does not involve circuit logic optimization operations, it is difficult to reduce the number of logic cells in the path, so for high-complexity and large-scale FPGA integrated circuits, sometimes it cannot effectively solve the timing problem of the timing violation path. SUMMARY

[0004] The purpose of this application is to provide a timing optimization method and system for FPGAs, which can effectively reduce the number of logic unit stages traversed by the timing path and further reduce the data signal delay of timing violation paths.

[0005] This application discloses a timing optimization method for FPGAs, including:

[0006] Timing updates are performed based on the physical location of the lookup table assigned after placement and routing;

[0007] Based on the timing update results, the target timing violation path is determined. The lookup tables on the target timing violation path are traversed to select lookup table pairs. The selected lookup table pairs are any two consecutive lookup tables that satisfy the following conditions: i) each lookup table has an input net with a positive time margin; ii) the net between the two lookup tables is not a high fan-out net; and iii) the number of input nets of the latter lookup table is less than N. N is configured according to the maximum number of input signals of the lookup table in the FPGA.

[0008] Perform logical refactoring operations that enable timing improvements on the selected lookup table pairs, and assign corresponding physical locations to the refactored new lookup tables.

[0009] In a preferred embodiment, before performing the logic refactoring operation that enables timing improvement on the selected lookup table pairs, the method further includes:

[0010] The logical refactoring optimization cost of the lookup table pair is calculated based on the number of lookup table input nets, the time margin of the lookup table input nets, and the fan-out number of the lookup table connected nets.

[0011] All lookup table pairs are sorted based on the time margin of the lookup table pairs, the net length between lookup tables, and the logic refactoring optimization cost to obtain the sorting result.

[0012] In a preferred embodiment, when performing logical reconstruction operations that can achieve timing improvement on the selected lookup table pairs, the method further includes: if it is determined that any lookup table in the current lookup table pair in the sorting result has previously undergone a logical reconstruction operation, then the logical reconstruction operation on the current lookup table pair is abandoned.

[0013] In a preferred embodiment, the method further includes: according to Calculate the logic refactoring optimization cost of the lookup table pair, where n1 and m1 represent the number of input nets and the number of input nets with positive time margin in the first lookup table of the lookup table pair, respectively; n2 and m2 represent the number of input nets and the number of input nets with positive time margin in the second lookup table of the lookup table pair, respectively; and i represents the fan-out number of the nets connecting the two lookup tables in the lookup table pair.

[0014] In a preferred embodiment, the method further comprises: selecting a preset percentage of the timing violation paths with the smallest time margin as the target timing violation paths.

[0015] In a preferred embodiment, the method further comprises: selecting a preset percentage of the timing violation paths with the smallest time margin as the target timing violation paths.

[0016] The application also discloses a timing optimization system of FPGA, which comprises:

[0017] a timing update module, configured to perform timing update based on the physical positions of the allocated look-up tables after layout and wiring;

[0018] a look-up table pair selection module, configured to determine target timing violation paths based on the timing update result, and traverse the look-up tables on the target timing violation paths to select look-up table pairs, wherein the selected look-up table pairs are any two look-up tables connected in sequence and meet the conditions that i) each look-up table has input net with positive time margin, ii) the net between the two look-up tables is not high fan-out net, and iii) the number of input nets of the latter look-up table is less than N, wherein N is configured according to the maximum number of input signals of the look-up tables in the FPGA;

[0019] a logic reconstruction module, configured to perform logic reconstruction operation on the selected look-up table pairs respectively to realize timing improvement, and allocate corresponding physical positions to the reconstructed new look-up tables.

[0020] In a preferred embodiment, the system further comprises a calculation and sorting module, configured to calculate the logic reconstruction optimization cost of the look-up table pairs according to the number of input nets of the look-up tables, the time margin of the input nets of the look-up tables and the fan-out number of the connection nets of the look-up tables, and sort all the look-up table pairs according to the time margin of the look-up table pairs, the length of the net between the look-up tables and the logic reconstruction optimization cost, to obtain a sorting result.

[0021] The logic reconstruction module is further configured to determine that any look-up table in the current look-up table pair in the sorting result has been subjected to logic reconstruction operation, and then abandon the logic reconstruction operation on the current look-up table pair.

[0022] In a preferred embodiment, the calculation and sorting module is further configured to calculate the logic reconstruction optimization cost according to the number of input nets of the look-up tables, the time margin of the input nets of the look-up tables and the fan-out number of the connection nets of the look-up tables. The logic reconfiguration optimization cost of the lookup table pair is calculated, wherein n1 and m1 respectively represent the number of input wire nets and the number of input wire net time margins that are positive of a former lookup table in the lookup table pair, n2 and m2 respectively represent the number of input wire nets and the number of input wire net time margins that are positive of a latter lookup table in the lookup table pair, and i represents the fan-out number of the wire net connecting the two lookup tables in the lookup table pair.

[0023] In a preferred example, the calculation and sorting module is further configured to sort, for all the lookup table pairs, according to the time margin from low to high, and for the lookup table pairs with the same time margin, according to the quotient of the wire net length between the lookup tables and the logic reconfiguration optimization cost from high to low, to obtain a sorting result.

[0024] The system further comprises a target timing violation path selection module configured to select a preset percentage of timing violation paths with the smallest time margin as the target timing violation paths.

[0025] In the embodiments of the present application, at least the following advantages and beneficial technical effects are achieved: the lookup table pair is defined, and the logic reconfiguration optimization is performed in units of the lookup table pair, and then the number of lookup table stages passed by the timing violation path is reduced through the logic reconfiguration optimization, thereby the path delay optimization timing is reduced. Further, the logic reconfiguration cost of the lookup table pair and the calculation method thereof are proposed, and the selected lookup table pairs are sorted based on the time margin and the logic reconfiguration cost, and the logic reconfiguration optimization operation is sequentially performed on the lookup table pairs based on the sorting result, which helps to preferentially select the candidate with the maximum return rate for operation, and can more effectively improve the optimization efficiency.

[0026] A large number of technical features are described in the specification of the present application, which are distributed in various technical solutions. If all possible combinations (i.e. technical solutions) of technical features of the present application are listed, the specification will be too long. In order to avoid this problem, each technical feature disclosed in the above summary of the application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (which are considered to have been described in the specification), unless such combination of technical features is technically infeasible. For example, features A+B+C are disclosed in one example, features A+B+D+E are disclosed in another example, features C and D are equivalent technical means that play the same role, and only one of them can be used technically, and feature E can be combined with feature C technically. Therefore, the solution of A+B+C+D should not be considered to have been described because it is technically infeasible, and the solution of A+B+C+E should be considered to have been described. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 is a timing path diagram of an example.

[0028] Figure 2 is a timing optimization method flowchart of an FPGA according to a first embodiment of the present application.

[0029] Figure 3(a) is a lookup table pair diagram of an example 1 that meets the condition.

[0030] Figure 3(b) is a two lookup table pair diagram of an example 2 that does not meet the condition.

[0031] Figure 4 is a process diagram of logic reconfiguration of an example lookup table pair according to the present application.

[0032] Figure 5 is a process diagram of logic reconfiguration of another example lookup table pair according to the present application.

[0033] Figure 6 is a timing optimization method flowchart of an FPGA according to an embodiment of the present application.

[0034] Figure 7 is a timing optimization system structure diagram of an FPGA according to a second embodiment of the present application. DETAILED DESCRIPTION

[0035] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one ordinarily skilled in the art that the present application can be practiced without these specific details and that numerous implementation variations and modifications can be possible.

[0036] Explanation of some concepts:

[0037] Field-Programmable Gate Array, FPGA for short, is a product further developed on the basis of programmable devices such as PAL, GAL, CPLD, etc. FPGA adopts a concept of Logic Cell Array (LCA), which internally includes three parts of Configurable Logic Block (CLB), Input Output Block (IOB) and Interconnect. FPGA is a programmable device, which has a different structure compared with traditional integrated circuits and gate arrays (such as PAL, GAL, CPLD). FPGA uses small lookup tables (16x1 RAM) to realize combinational logic, each lookup table is connected to the input end of a D flip-flop, and the flip-flop drives other integrated circuits or I / O, thereby forming a basic logic cell module that can realize both combinational logic function and sequential logic function, and these modules are connected to each other or to I / O modules by metal interconnections.

[0038] Logic Synthesis: the process of converting RTL (Register Transfer Level) netlist into gate-level netlist, including three steps of circuit conversion, circuit optimization and circuit mapping.

[0039] Place and Route: the process of physically implementing the gate-level netlist after logic synthesis, including allocating physical locations to logic cells, performing physical wiring and timing optimization.

[0040] Circuit Optimization: the optimization process in logic synthesis, including but not limited to the following aspects: removing useless logic, merging equivalent logic, timing optimization, etc.

[0041] Look Up Table, LUT for short, is a circuit structure that quickly looks up the result through input coding, and all combinational logic in FPGA is realized by looking up the truth table in the lookup memory. The number after LUT generally represents the number of input signals of the lookup table, LUT4 is a 4-input lookup table, LUT5 is a 5-input lookup table, and LUT6 is a 6-input lookup table.

[0042] Truth Table: a table representing all possible states between input and output of a logic event, usually represented by 1 for true and 0 for false, which can be used to describe the behavior of combinational logic circuits.

[0043] Timing Path: a path that needs to be constrained and optimized in sequential circuit design, including four types of non-clock signal paths: from input to register, register to register, register to output, and input to output.

[0044] Time slack: The difference between the actual arrival time of a data signal of a timing path and the required arrival time of the data signal is called time slack. A timing path has a negative time slack, which means that the actual arrival time of a data signal of the timing path is later than the required arrival time of the data signal, and the timing path has a timing violation.

[0045] Timing violation path: A timing path has a negative time slack, which means that the actual arrival time of a data signal of the timing path is later than the required arrival time of the data signal, and the timing path has a timing violation. The smaller the negative time slack is, the more serious the timing violation of the timing path is. To solve the timing violation, the actual arrival time of the data signal can be reduced, i.e., the path delay of the data signal can be reduced.

[0046] Timing critical path: The timing path with the worst time slack in timing violation paths. The timing critical path directly affects the operating frequency of a circuit. The smaller the time slack of the timing critical path is, the lower the highest frequency of the circuit is.

[0047] Path delay of a timing path: The path delay of a data signal of a timing path is the sum of the delays of all logic cells and all nets through which the data signal passes. The higher the number of logic cells through which the data signal passes, the more likely the path delay is longer. To solve the timing violation of a timing path, reducing the path delay is the most direct means. The most commonly used methods for reducing the path delay include reducing the number of logic cells, reducing the delay of a logic cell with a long delay, and reducing the delay of a net with a long delay.

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0049] Generally, a timing path passes through a plurality of lookup tables (LUTs) from a start timing device to an end timing device. For example, a timing path passes through n LUTs and n+1 nets from a start timing device Reg_start to an end timing device Reg_end. Figure 1 For example, a timing path passes through n LUTs and n+1 nets from a start timing device Reg_start to an end timing device Reg_end. One of the main reasons for a timing violation of a timing path is that the path delay of a data signal is too long. The path delay path_delay of the data signal is the sum of the delays of the n LUTs and the n+1 nets, i.e., a total of 2n+1 delays. The main timing optimization method in the layout and routing stage is to reduce the path delay of the data signal by reducing the delays of some LUTs or nets. The number of LUTs through which the data signal passes is basically unchanged, and the path delay path_delay is still composed of 2n+1 delays, only the values of some of the delays are reduced.

[0050] To solve at least the above problems, the first embodiment of the present application provides a timing optimization method of FPGA, which has the opportunity to reduce the number of lookup table stages from n stages to several stages, thereby reducing the number of path delay periods and reducing the path delay optimization timing to a greater extent.

[0051] The flow of the timing optimization method of the FPGA is shown in Figure 2 The method comprises the following steps:

[0052] In step 201, timing update is performed based on the physical location of the lookup table allocated after layout and routing.

[0053] Then, in step 202, the target timing violation path is determined based on the timing update result, and the lookup tables on the target timing violation path are traversed to select a lookup table pair. The selected lookup table pair is any two lookup tables connected in sequence, which satisfy the conditions that i) each lookup table has a positive time margin for the input line net, ii) the line net between the two lookup tables is not a high fan-out line net, and iii) the number of input line nets of the latter lookup table is less than N, which is configured according to the maximum number of input signals of a single lookup table supported in the FPGA.

[0054] N can be configured according to the maximum number of input signals of a single lookup table supported in the FPGA. For example, the current mainstream FPGA chip supports up to six-input lookup tables, so N can be configured as 6. If the latter lookup table is a six-input lookup table, i.e. the number of input line nets is N = 6, the chance of timing improvement after reconstruction is very small. Moreover, with the update of technology, when the FPGA chip supports up to M-input (M > 6) lookup tables in the future, N can be configured as M.

[0055] The selection conditions of the lookup table pair are a comprehensive consideration of the following: the more input line nets with negative time margins, the lower the probability of timing improvement after lookup table reconstruction; the larger the number of connection line nets, the greater the impact on timing after reconstruction, the lower the probability of timing improvement; if the latter lookup table is the maximum number of input signals of a single lookup table supported by the FPGA, the chance of timing improvement after reconstruction is very small, etc. For example, as shown in FIG. 3(a), an example 1 lookup table pair is shown, which has positive time margins for input line nets a, c, d, e, g, h and negative time margins for b, f, which satisfies the conditions and should be selected for subsequent logic reconstruction optimization. As shown in FIG. 3(b), two lookup tables of example 2 are shown, which have negative time margins for input line nets a, b, c, d, which do not satisfy conditions i) and iii), and should not be selected for subsequent logic reconstruction optimization.

[0056] The selection method of the target timing violation path is various. For example, the timing violation path with the smallest time margin in a preset percentage can be selected as the target timing violation path. For example, all timing violation paths can also be selected as the target timing violation path. Without being limited thereto.

[0057] After that, step 203 is entered, and logic restructuring operations capable of achieving timing improvement are performed on the selected lookup table pairs respectively, and corresponding physical locations are allocated to the restructured new lookup tables.

[0058] Optionally, before the step 203, the following steps ① and ② are further included: ① calculating the logic restructuring optimization cost of the lookup table pair according to the number of lookup table input line nets, the time margin of the lookup table input line nets and the fan-out number of the lookup table connection line nets; ② sorting all the lookup table pairs according to the time margin of the lookup table pair, the length of the line net between the lookup tables and the logic restructuring optimization cost, and obtaining the sorting result.

[0059] The implementation of the above step ① is various. In an embodiment, the logic restructuring optimization cost Cost of the lookup table pair can be calculated according to the formula wherein n1 and m1 represent the number of input line nets and the number of input line nets with positive time margin of the former lookup table in the lookup table pair respectively, n2 and m2 represent the number of input line nets and the number of input line nets with positive time margin of the latter lookup table in the lookup table pair respectively, and i represents the fan-out number of the connection line nets between the two lookup tables in the lookup table pair. Taking the lookup table pair of example 1 in FIG. 3(a) as an example, the logic optimization cost is If the fan-out number of the connection line nets between the two lookup tables is 5, the logic optimization cost is In other embodiments, the logic restructuring optimization cost of the lookup table pair can be calculated according to any transformation of the formula of the above embodiment.

[0060] The implementation of the above step ② is various. For example, in an embodiment, for all the lookup table pairs, sorting is performed from low to high according to the time margin (i.e., the lower the time margin s is, the earlier the sorting is), and for the lookup table pairs with the same time margin, sorting is performed from high to low according to the quotient of the length of the line net between the lookup tables and the logic restructuring optimization cost (i.e., for the same time margin s, the quotient of the length of the line net l and the optimization cost c is calculated, i.e., l / c, the larger the quotient l / c is, the earlier the sorting is), and the sorting result is obtained. In other embodiments, for the lookup table pairs with the same time margin, sorting can be performed from high to low according to the difference between the length of the line net between the lookup tables and the logic restructuring optimization cost, and the sorting result is obtained. And it is not limited thereto.

[0061] Optionally, the step 203 can further include the following steps: sequentially performing logic reconstruction on the lookup table pairs in the sorting result according to the sorting, if any of the lookup tables in the current lookup table pair in the sorting result has been subjected to logic reconstruction, abandoning the logic reconstruction on the current lookup table pair, until all the candidate lookup table pairs in the sorting result queue are optimized, and the whole optimization process ends. The purpose of the logic reconstruction is to reduce the number of lookup table stages through which the current timing violation path passes, and the input and logic expression of the reconstructed lookup table need to be updated to ensure logic correctness.

[0062] The following illustrates the logic reconstruction process of the lookup table pair: Figure 4 The process of logic reconstruction of an example lookup table pair is shown, in which the worst timing violation path passes through LUT3 from wire net a, and outputs to wire net o via LUT4 from wire net f. In order to reduce the delay of the timing violation path, LUT3 and LUT4 can be reconstructed into a LUT6. The original worst timing violation path passes through LUT6 from wire net a directly to wire net o, and the number of lookup table stages through which the path passes decreases by 1, and the path delay can be reduced, so that the timing of the timing violation path is improved. Figure 5 The process of logic reconstruction of another example lookup table pair is shown, in which the worst timing violation path passes through LUT4_1 from wire net b, and outputs to wire net o via LUT4_2 from wire net f. LUT4_1 and LUT4_2 are reconstructed into a LUT3 and a LUT5. The original timing violation path passes through LUT5 from wire net b directly to wire net o, and the path delay is reduced, so that the timing of the timing violation path is improved.

[0063] As Figure 6 A flowchart of a timing optimization method of an FPGA according to an embodiment of the present application is shown. The embodiment is for a post-layout design based on physical location timing update, and the timing violation paths are sorted according to the time margin from small to large, and the top 5% of the timing violation paths are selected for traversal. The lookup table pairs that meet the conditions are selected as logic reconstruction candidates, and the logic reconstruction optimization cost of each pair of candidate lookup table pairs is calculated. Each pair of candidate lookup table pairs is sorted according to the time margin, the wire length, and the calculated reconstruction optimization cost, and the logic reconstruction operation is attempted on each pair of candidate lookup table pairs in the order of the sorting. The logic reconstruction operation that can improve the timing is performed (i.e. after the logic reconstruction, the timing is checked to see if the timing is improved, if it is improved, the current logic reconstruction operation is accepted, otherwise the original lookup table logic is maintained), and the physical location of the new lookup table is allocated, until the logic reconstruction operation attempt on all the candidate lookup table pairs in the sorting result is completed. The details listed in this embodiment are mainly for easy understanding, and do not limit the scope of protection of the present application.

[0064] The second embodiment of the present application provides a timing optimization system of FPGA, which has a structure as shown in the figure Figure 7 The timing optimization system of FPGA includes a timing update module, a lookup table pair selection module and a logic reconfiguration module. The timing update module is configured to perform timing update based on the physical positions of the assigned lookup tables after layout and routing. The lookup table pair selection module is configured to determine a target timing violation path based on the timing update result, and traverse the lookup tables on the target timing violation path to select a lookup table pair. The selected lookup table pair is any two lookup tables connected in sequence, which satisfy the following conditions: i) each lookup table has an input net with positive slack; ii) the net between the two lookup tables is not a high fan-out net; and iii) the number of input nets of the latter lookup table is less than N, where N is configured according to the maximum number of input signals of the lookup tables in the FPGA. The logic reconfiguration module is configured to perform logic reconfiguration operation on the selected lookup table pair to achieve timing improvement, and assign corresponding physical positions to the reconfigured new lookup tables.

[0065] Optionally, the system further includes a calculation and sorting module configured to calculate the logic reconfiguration optimization cost of the lookup table pair according to the number of input nets of the lookup table, the slack of the input net of the lookup table and the fan-out number of the net connected between the lookup tables, and sort all the lookup table pairs according to the slack of the lookup table pair, the length of the net between the lookup tables and the logic reconfiguration optimization cost to obtain a sorting result. The logic reconfiguration module is further configured to determine whether any lookup table in the current lookup table pair in the sorting result has performed logic reconfiguration operation, and if so, abandon the logic reconfiguration operation on the current lookup table pair.

[0066] In one embodiment, the calculation and sorting module calculates the logic reconfiguration optimization cost of the lookup table pair according to the formula: wherein n1 and m1 represent the number of input nets and the number of input nets with positive slack of the former lookup table in the lookup table pair, respectively, n2 and m2 represent the number of input nets and the number of input nets with positive slack of the latter lookup table in the lookup table pair, respectively, and i represents the fan-out number of the net connected between the two lookup tables in the lookup table pair. In other embodiments, the calculation and sorting module calculates the logic reconfiguration optimization cost of the lookup table pair according to any modification of the above formula.

[0067] In one embodiment, the calculation and sorting module sorts all the lookup table pairs according to the slack from low to high, and sorts the lookup table pairs with the same slack according to the quotient of the length of the net between the lookup tables and the logic reconfiguration optimization cost from high to low to obtain a sorting result. In other embodiments, the calculation and sorting module sorts the lookup table pairs with the same slack according to the difference of the length of the net between the lookup tables and the logic reconfiguration optimization cost from high to low to obtain a sorting result. Without being limited thereto.

[0068] Optionally, the system further comprises a target timing violation path selection module configured to select, as the target timing violation path, a preset percentage of timing violation paths with the smallest time margin.

[0069] The first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.

[0070] It should be noted that the implementation functions of each module shown in the embodiments of the FPGA timing optimization system described above can be understood with reference to the related description of the FPGA timing optimization method described above. The functions of each module shown in the embodiments of the FPGA timing optimization system described above can be implemented by a program (executable instructions) running on a processor, or by a specific logic circuit. The FPGA timing optimization system described above in the embodiments of the present application, if implemented in the form of a software function module and sold or used as an independent product, can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read Only Memory), a magnetic disk or an optical disk, and various program code storage media. Thus, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0071] It is to be noted that, in the application file of the present patent, the terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover the non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including one" does not exclude the existence of other identical elements in the process, method, article or equipment including the element. In the application file of the present patent, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, including two cases: the action is performed only according to the element, and the action is performed according to the element and other elements. The expressions of multiple, multiple times, multiple kinds, etc. include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0072] All the documents mentioned in the present application are considered to be included in the disclosure of the present application as a whole, so as to be used as a modification if necessary. In addition, it should be understood that the above description is only the preferred embodiment of the present specification, and is not intended to limit the protection scope of the present specification. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of one or more embodiments of the present specification shall be included in the protection scope of one or more embodiments of the present specification.

Claims

1. A method for timing optimization of an FPGA, the method comprising: The method comprises the following steps: performing timing update based on the physical positions of the lookup tables allocated after layout and routing; determining a target timing violation path based on the timing update result, and traversing the lookup tables on the target timing violation path to select a lookup table pair, wherein the selected lookup table pair is any two lookup tables connected in sequence, and each lookup table has a positive timing slack for the input wire net, the wire net between the two lookup tables is not a high fan-out wire net, and the number of input wire nets of the latter lookup table is less than N, wherein N is configured according to the maximum number of input signals of the lookup tables in the FPGA; respectively performing a logic restructuring operation capable of achieving timing improvement on the selected lookup table pair, and allocating corresponding physical positions for the new lookup tables after restructuring; wherein, before the step of respectively performing a logic restructuring operation capable of achieving timing improvement on the selected lookup table pair, the method further comprises the following steps: calculating the logic restructuring optimization cost of the lookup table pair according to the number of lookup table input wire nets, the timing slack of the lookup table input wire net and the fan-out number of the lookup table connection wire net; sorting all the lookup table pairs according to the timing slack, the wire net length between the lookup tables and the logic restructuring optimization cost to obtain a sorting result.

2. The method for timing optimization of an FPGA according to claim 1, wherein, In the step of respectively performing a logic restructuring operation capable of achieving timing improvement on the selected lookup table pair, the method further comprises the following steps: if it is determined that any one of the lookup tables in the current lookup table pair in the sorting result has been subjected to a logic restructuring operation, the logic restructuring operation on the current lookup table pair is abandoned.

3. The method for timing optimization of an FPGA according to claim 1, wherein, The method further comprises: calculating a logical restructuring optimization cost of the pair of lookup tables according to , , respectively represent the number of input wire nets of the former lookup table in the pair of lookup tables, the number of input wire net time margins being positive, , respectively represent the number of input wire nets of the latter lookup table in the pair of lookup tables, the number of input wire net time margins being positive, represent the fan-out number of the connection wire net of the two lookup tables in the pair of lookup tables.

4. The method of timing optimization of an FPGA according to claim 1, wherein, In the step of sorting all the lookup table pairs according to the timing slack, the wire net length between the lookup tables and the logic restructuring optimization cost to obtain a sorting result, the method further comprises the following steps: for all the lookup table pairs, sorting according to the timing slack from low to high, and for the lookup table pairs with the same timing slack, sorting according to the quotient of the wire net length between the lookup tables and the logic restructuring optimization cost from high to low to obtain a sorting result.

5. The method for timing optimization of an FPGA according to any of claims 1-4, characterized in that, The method further comprises the following step:

6. A timing optimization system of an FPGA, characterized by, selecting a preset percentage of timing violation paths with the smallest timing slack as the target timing violation path. The method comprises the following steps: a timing update module configured to perform timing update based on the physical positions of the lookup tables allocated after layout and routing; a lookup table pair selection module configured to determine a target timing violation path based on the timing update result, and traverse the lookup tables on the target timing violation path to select a lookup table pair, wherein the selected lookup table pair is any two lookup tables connected in sequence, and each lookup table has a positive timing slack for the input wire net, the wire net between the two lookup tables is not a high fan-out wire net, and the number of input wire nets of the latter lookup table is less than N, wherein N is configured according to the maximum number of input signals of the lookup tables in the FPGA; a logic restructuring module configured to respectively perform a logic restructuring operation capable of achieving timing improvement on the selected lookup table pair, and allocate corresponding physical positions for the new lookup tables after restructuring; The system further comprises a calculation and sorting module, configured to calculate a logic reconfiguration optimization cost of the lookup table pair according to a number of input line nets of the lookup table, a time margin of the lookup table input line net and a fan-out number of the lookup table connection line net, and sort all the lookup table pairs according to a time margin of the lookup table pair, a length of the line net between the lookup tables and the logic reconfiguration optimization cost, to obtain a sorting result. The logic reconfiguration module is further configured to determine whether a logic reconfiguration operation has been performed before any of the lookup tables in a current lookup table pair in the sorting result, and if so, abandon the logic reconfiguration operation on the current lookup table pair.

7. The timing optimization system of an FPGA according to claim 6, wherein, The computing and ordering module is further configured to compute a logical restructuring optimization cost of the pair of lookup tables according to , , respectively represent the number of input wire nets, the number of input wire net time slack being positive, of the former lookup table in the pair of lookup tables, , respectively represent the number of input wire nets, the number of input wire net time slack being positive, of the latter lookup table in the pair of lookup tables, represent the number of fanouts of the connection wire net of the two lookup tables in the pair of lookup tables.

8. The system for timing optimization of an FPGA according to any of claims 6-7, characterized in that, The calculation and sorting module is further configured to sort all the lookup table pairs according to the time margin from low to high, and sort the lookup table pairs with the same time margin according to a quotient of the length of the line net between the lookup tables and the logic reconfiguration optimization cost from high to low, to obtain the sorting result. The system further comprises a target timing violation path selection module, configured to select a preset percentage of timing violation paths with the smallest time margin as the target timing violation path.

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