Chip verification method, device, electronic device and storage medium

Abstract

The present disclosure proposes a chip verification method, device, electronic device and storage medium, wherein the method includes: obtaining a transmission period of performance data of a chip to be verified; determining at least one first sub-period and a second sub-period in each first sub-period according to the transmission period; determining the expected target performance indicator of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance indicator; running the chip to be verified according to each set target performance indicator and each expected target performance indicator to obtain the monitoring target performance indicator of the chip to be verified in each of the first sub-periods, thereby, through the set target performance indicator of the first sub-period and the expected target performance of the second sub-period, the monitoring target performance indicator of the chip to be verified in each first sub-period can be made to meet the actual periodic transmission performance.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a chip verification method, device, electronic device and storage medium. Background Art

[0002] SOC (System-on-a-Chip) is an integrated circuit chip that can effectively reduce the development cost of electronic / information system products, shorten the development cycle, and improve product competitiveness. It is the most important product development method that the industry will adopt in the future. In the design process of SOC chips, whether the performance indicators meet the design requirements is a very critical design task. How to quickly and accurately model and simulate the performance characteristics of the chip is a very important design challenge.

[0003] Related technology usually verifies the performance of the SOC chip through EDA (Electronic Design Automation) after the integration of the subsystems and the top-level system of the SOC chip is completed. However, since EDA verification simulation can only fit the transmission characteristics of the system from the average transmission aspect, and the actual transmission characteristics of the chip are often not this average transmission, this average transmission verification method cannot accurately simulate the transmission performance of the chip. Summary of the invention

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to some extent.

[0005] The present disclosure provides a chip verification method to solve the problem in the related art that the transmission performance of the chip cannot be accurately simulated.

[0006] According to a first aspect of the present disclosure, a chip verification method is provided, including: obtaining a transmission period of performance data of a chip to be verified; determining, based on the transmission period, at least one first sub-period and a second sub-period in each first sub-period; determining, based on the duration corresponding to each of the first sub-periods and set target performance indicators, an expected target performance indicator of the second sub-period in the corresponding first sub-period; and running the chip to be verified according to each of the set target performance indicators and each of the expected target performance indicators to obtain a monitoring target performance indicator of the chip to be verified in each of the first sub-periods.

[0007] As a possible implementation method of the embodiment of the present disclosure, the expected target performance indicator of the second sub-period in the corresponding first sub-period is determined according to the duration corresponding to each of the first sub-periods and the set target performance indicator, including: for each of the first sub-periods, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; and multiplying each of the duration ratios by the set target performance indicator of the corresponding first sub-period as the expected target performance indicator of the second sub-period in the corresponding first sub-period.

[0008] As a possible implementation method of an embodiment of the present disclosure, determining at least one first sub-period and a second sub-period in each first sub-period based on the transmission period includes: dividing the transmission period to obtain multiple first sub-periods; for any first sub-period in the multiple first sub-periods, setting a second sub-period in any first sub-period, wherein the duration of the second sub-period is less than the duration of any first sub-period.

[0009] As a possible implementation method of the embodiment of the present disclosure, the chip to be verified is run according to each of the set target performance indicators and each of the expected target performance indicators to obtain the monitoring target performance indicators of the chip to be verified in each of the first sub-time periods, including: setting parameters in the verification instance of the chip to be verified according to each of the set target performance indicators and each of the expected target performance indicators; running the chip to be verified according to the verification instance after parameter setting to obtain the transmission behavior information of the chip to be verified in each of the first sub-time periods; determining the monitoring target performance indicators of the chip to be verified in each of the first sub-time periods according to the transmission behavior information of each of the first sub-time periods.

[0010] As a possible implementation method of the embodiment of the present disclosure, the transmission period of the performance data of the chip to be verified is obtained, including: obtaining a historical transmission log of the performance data of the chip to be verified; and determining the transmission period of the performance data of the chip to be verified based on the historical transmission log.

[0011] According to the second aspect of an embodiment of the present disclosure, a chip verification device is provided, comprising: an acquisition module for acquiring a transmission period of performance data of a chip to be verified; a first determination module for determining, based on the transmission period, at least one first sub-period and a second sub-period in each first sub-period; a second determination module for determining, based on the duration corresponding to each of the first sub-periods and set target performance indicators, an expected target performance indicator of a second sub-period in the corresponding first sub-period; and an operation module for operating the chip to be verified according to each of the set target performance indicators and each of the expected target performance indicators, so as to obtain a monitoring target performance indicator of the chip to be verified in each of the first sub-periods.

[0012] As a possible implementation method of the embodiment of the present disclosure, the second determination module is also used to: for each of the first sub-periods, compare the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; and multiply the product of each of the duration ratios and the set target performance indicator of the corresponding first sub-period as the expected target performance indicator of the second sub-period in the corresponding first sub-period.

[0013] As a possible implementation method of an embodiment of the present disclosure, the first determination module is also used to: divide the transmission period into multiple first sub-periods; for any first sub-period among the multiple first sub-periods, set a second sub-period in any of the multiple first sub-periods, wherein the duration of the second sub-period is less than the duration of any of the first sub-periods.

[0014] As a possible implementation method of the embodiment of the present disclosure, the operation module is also used to: set parameters in the verification instance of the chip to be verified according to each of the set target performance indicators and each of the expected target performance indicators; run the chip to be verified according to the verification instance after the parameter setting to obtain the transmission behavior information of the chip to be verified in each of the first sub-time periods; determine the monitoring target performance indicator of the chip to be verified in each of the first sub-time periods according to the transmission behavior information of each of the first sub-time periods.

[0015] As a possible implementation manner of the embodiment of the present disclosure, the acquisition module is further used to: acquire a historical transmission log of the performance data of the chip to be verified; and determine a transmission period of the performance data of the chip to be verified according to the historical transmission log.

[0016] According to the third aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the chip verification method proposed in the embodiment of the first aspect of the present disclosure.

[0017] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided. When instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device can execute the chip verification method proposed in the embodiment of the first aspect of the present disclosure.

[0018] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program. When the computer program is executed by a processor of an electronic device, the electronic device is enabled to execute the chip verification method proposed in the embodiment of the first aspect.

[0019] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description or learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and / or additional aspects and advantages of the present disclosure will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0021] Figure 1 is a flow chart of a chip verification method according to an exemplary embodiment;

[0022] Figure 2 is a flow chart of another chip verification method according to an exemplary embodiment;

[0023] Figure 3 is a flow chart of another chip verification method according to an exemplary embodiment;

[0024] Figure 4 is a flow chart of another chip verification method according to an exemplary embodiment;

[0025] Figure 5 is a schematic structural diagram of a chip verification device according to an exemplary embodiment;

[0026] Figure 6 The invention is a block diagram of an electronic device showing a chip verification method according to an exemplary embodiment. DETAILED DESCRIPTION

[0027] Embodiments of the present disclosure are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0028] Related technology usually verifies the performance of the SOC chip through EDA (Electronic Design Automation) after the integration of the subsystems and the top-level system of the SOC chip is completed. However, since EDA verification simulation can only fit the transmission characteristics of the system from the average transmission aspect, for example, the read and write bandwidth characteristics of the specified system are verified and simulated by limiting the traffic, the actual transmission characteristics of the chip are often not this average transmission, but random burst characteristics with peaks and troughs. Therefore, this average transmission verification method cannot accurately simulate the transmission performance of the chip.

[0029] The chip verification method, device, electronic device and storage medium provided by the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0030] Figure 1 It is a flowchart of a chip verification method according to an exemplary embodiment. It should be noted that the chip verification method can be applied to a chip verification device. The chip verification device can be, for example, a hardware device that can be connected to the chip through a bus, or a controller in the hardware device, or control software in the hardware device, etc., which can be set according to actual needs, and the present disclosure does not limit this.

[0031] like Figure 1 As shown, the chip verification method includes the following steps:

[0032] Step 101, obtaining a transmission period of performance data of a chip to be verified.

[0033] Among them, the chip to be verified may be a SOC chip or other chip that can be verified using the chip verification method provided in the embodiment of the present disclosure. The present disclosure does not limit this. The embodiment of the present disclosure is described by taking the chip as a SOC chip as an example.

[0034] In the embodiment of the present disclosure, the transmission period may be the time period of the entire transmission process of the performance data of the chip to be verified. As an example, the transmission period of the performance data of the chip to be verified may be determined based on the historical transmission period of the chip to be verified.

[0035] Step 102: Determine at least one first sub-period and a second sub-period in each first sub-period according to the transmission period.

[0036] In order to make the simulated transmission performance of the chip conform to the actual periodic transmission performance, in the embodiment of the present disclosure, the transmission period can be divided into at least one first sub-period, and a second sub-period is set in each first sub-period.

[0037] Step 103: Determine the expected target performance index of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index.

[0038] Furthermore, a target performance indicator may be set for each first sub-period respectively. That is to say, the target performance indicator may be set as a constraint condition for the first sub-period, which requires that the transmission performance of the control node of the chip to be verified within the first sub-period is less than or equal to the set target performance indicator. For example, taking the target performance indicator as the target bandwidth as an example, the transmission bandwidth of the control node of the SOC chip within the first sub-period is less than or equal to the target bandwidth.

[0039] Furthermore, in order to make the transmission performance of the control node of the chip to be verified within the first sub-period less than or equal to the set target performance indicator, the expected target performance indicator of the second sub-period in the corresponding first sub-period can be determined according to the duration corresponding to each first sub-period and the set target performance indicator.

[0040] Step 104 , operating the chip to be verified according to each set target performance indicator and each expected target performance indicator, so as to obtain the monitoring target performance indicator of the chip to be verified in each first sub-period.

[0041] As an example, according to each set target performance indicator and each expected target performance indicator, parameters are set in the verification instance of the chip to be verified, and according to the verification instance after the parameter setting, the chip to be verified is run to obtain the transmission behavior information of the chip to be verified in each first sub-time period; according to the transmission behavior information of each first sub-time period, the monitoring target performance indicator of the chip to be verified in each first sub-time period is determined.

[0042] That is to say, in the chip verification environment, according to each set target performance indicator and each expected target performance indicator, the corresponding parameters are set in the verification instance of the chip to be verified, and then, according to the verification instance after the parameter setting, the operation of the chip to be verified is controlled so that the chip to be verified performs a transmission process simulation according to each set target performance indicator and each expected target performance indicator, so as to obtain the transmission behavior information of the chip to be verified in each first sub-period, and then, the transmission behavior information is analyzed to obtain the monitoring target performance indicator of the chip to be verified in each first sub-period. Among them, the transmission behavior information is any information required for chip verification, such as the transmission time point, the total amount of data transmission, etc.

[0043] In summary, the transmission period of the performance data of the chip to be verified is obtained; according to the transmission period, at least one first sub-period and the second sub-period in each first sub-period are determined; according to the duration corresponding to each of the first sub-periods and the set target performance indicators, the expected target performance indicators of the second sub-period in the corresponding first sub-period are determined; according to the set target performance indicators and the expected target performance indicators, the chip to be verified is run to obtain the monitoring target performance indicators of the chip to be verified in each first sub-period, thereby, through the set target performance indicators of the first sub-period and the expected target performance of the second sub-period, the monitoring target performance indicators of the chip to be verified in each first sub-period can be made to meet the actual periodic transmission performance.

[0044] In order to clearly explain how to determine the expected target performance indicator of the second sub-period in the corresponding first sub-period, the present disclosure proposes another chip verification method, such as Figure 2 As shown, Figure 2is a flow chart of another chip verification method according to an exemplary embodiment. In the embodiment of the present disclosure, for each first sub-period, the ratio of the duration of the first sub-period to the duration of the corresponding second sub-period is determined, and the expected target performance index of the corresponding second sub-period is determined according to the duration ratio and the set target performance index of the first sub-period. Figure 2 The illustrated embodiment may include the following steps:

[0045] Step 201, obtaining a transmission period of performance data of a chip to be verified.

[0046] Step 202: Determine at least one first sub-period and a second sub-period in each first sub-period according to the transmission period.

[0047] Step 203: for each first sub-period, compare the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio.

[0048] In an embodiment of the present disclosure, each first sub-period may correspond to a duration, and the second sub-period in each first sub-period may also correspond to a duration. The duration corresponding to the second sub-period is less than the duration corresponding to the corresponding first sub-period. The durations corresponding to the first sub-periods may be the same or different, and the durations corresponding to the second sub-periods may be the same or different. The present disclosure does not make specific limitations.

[0049] In the embodiment of the present disclosure, the duration of each first sub-period may be compared with the duration of the corresponding second sub-period to obtain a corresponding duration ratio.

[0050] Step 204: The product of each time length ratio and the set target performance index of the corresponding first sub-period is used as the expected target performance index of the second sub-period in the corresponding first sub-period.

[0051] For example, the length of a first sub-period is Ta, the set target performance indicator of the first sub-period is freq_A, the length of the second sub-period in the first sub-period is Tb, the ratio of the length of the first sub-period to the length of the corresponding second sub-period is Ta / Tb, and the expected target performance of the second sub-period in the first sub-period is freq_B=freq_A*(Ta / Tb).

[0052] Step 205 : running the chip to be verified according to each set target performance indicator and each expected target performance indicator to obtain the monitoring target performance indicator of the chip to be verified in each first sub-period.

[0053] It should be noted that the execution process of steps 201 to 202 and step 205 can be implemented in any way in the embodiments of the present disclosure, and the embodiments of the present disclosure do not limit this and will not be described in detail.

[0054] In summary, for each first sub-period, the duration of the first sub-period is compared with the duration of the corresponding second sub-period to obtain a duration ratio; the product of each duration ratio and the set target performance indicator of the corresponding first sub-period is used as the expected target performance indicator of the second sub-period in the corresponding first sub-period. Thus, according to the duration corresponding to each first sub-period and the set target performance indicator, the expected target performance indicator of the second sub-period in the corresponding first sub-period is determined, so that the monitoring target performance indicator of the chip to be verified in each first sub-period has a sudden change in peaks and troughs, while meeting the requirements of the set target performance indicator.

[0055] In order to clearly explain how to determine at least one first sub-period and a second sub-period in each first sub-period according to the transmission period, the present disclosure proposes another chip verification method, such as Figure 3 As shown, Figure 3 is a flow chart of another chip verification method according to an exemplary embodiment. In the embodiment of the present disclosure, multiple transmission periods can be divided into multiple first sub-periods, and a second sub-period is set in each first sub-period. Figure 3 The illustrated embodiment may include the following steps:

[0056] Step 301, obtaining a transmission period of performance data of a chip to be verified.

[0057] Step 302: divide the transmission period into multiple first sub-periods.

[0058] In the embodiment of the present disclosure, the transmission period may be divided into equal parts or unequal parts to obtain a plurality of first sub-periods. For example, the duration of the first sub-period may be between 1 microsecond and 5 microseconds.

[0059] Step 303: for any first sub-period in the plurality of first sub-periods, set a second sub-period in any first sub-period.

[0060] The duration of the second sub-period is shorter than the duration of any first sub-period.

[0061] Furthermore, for each first sub-period in the plurality of first sub-periods, a second sub-period is set in each first sub-period, wherein the duration of the second sub-period is shorter than the duration of any first sub-period.

[0062] Step 304: Determine the expected target performance index of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index.

[0063] Step 305 : running the chip to be verified according to each set target performance indicator and each expected target performance indicator to obtain the monitoring target performance indicator of the chip to be verified in each first sub-period.

[0064] It should be noted that the execution process of step 301 and step 304 to step 305 can be implemented in any way in the embodiments of the present disclosure, and the embodiments of the present disclosure do not limit this and will not be described in detail.

[0065] In summary, by dividing the transmission period to obtain multiple first sub-periods, a second sub-period is set in any first sub-period among the multiple first sub-periods. Thus, the transmission period can be decomposed into multiple sub-periods, so that corresponding target performance indicators can be set on multiple sub-periods, thereby achieving performance verification with greater freedom.

[0066] In order to clearly explain how to obtain the transmission period of the performance data of the chip to be verified, the present disclosure proposes another chip verification method, such as Figure 4 As shown, Figure 4 is a flow chart of another chip verification method according to an exemplary embodiment. In the embodiment of the present disclosure, the transmission period of the performance data of the chip to be verified can be determined according to the historical transmission log of the performance data of the chip to be verified. Figure 4 The illustrated embodiment may include the following steps:

[0067] Step 401: Obtain the historical transmission log of the performance data of the chip to be verified.

[0068] In the embodiment of the present disclosure, the transmission log may include the performance data transmission information of the chip to be verified, for example, it may include the transmission period and transmission process of the performance data.

[0069] As an example, the transmission period and transmission process of the historical performance data of the chip to be verified can be written into a log file to obtain the historical transmission log to be verified. The historical transmission log of the performance data of the chip to be verified can be extracted to obtain the historical transmission log of the performance data of the chip to be verified.

[0070] Step 402: Determine the transmission period of the performance data of the chip to be verified according to the historical transmission log.

[0071] Furthermore, by parsing the historical transmission log, the transmission period of the historical performance data of the chip to be verified in the historical transmission log can be extracted, and the transmission period of the historical performance data of the chip to be verified is used as the transmission period of the performance data of the heart rate to be verified. In order to improve the accuracy of the transmission period of the performance data of the chip to be verified, the transmission period of the historical performance data can be obtained multiple times, and the average value of the corresponding transmission period can be determined based on the transmission period of the historical performance data obtained multiple times, and the average value of the transmission period of the historical performance data can be used as the transmission period of the performance data of the chip to be verified.

[0072] Step 403: Determine at least one first sub-period and a second sub-period in each first sub-period according to the transmission period.

[0073] Step 404: Determine the expected target performance index of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index.

[0074] Step 405 , operating the chip to be verified according to each set target performance indicator and each expected target performance indicator, so as to obtain the monitoring target performance indicator of the chip to be verified in each first sub-period.

[0075] It should be noted that the execution process of step 403 to step 405 can be implemented in any way in the embodiments of the present disclosure, and the embodiments of the present disclosure do not limit this and will not be described in detail.

[0076] In summary, according to the historical transmission log of the performance data of the chip to be verified, the transmission period of the performance data of the chip to be verified can be determined.

[0077] The chip verification method of the embodiment of the present disclosure obtains the transmission period of the performance data of the chip to be verified; according to the transmission period, determines at least one first sub-period and the second sub-period in each first sub-period; according to the duration corresponding to each first sub-period and the set target performance index, determines the expected target performance index of the second sub-period in the corresponding first sub-period; according to each set target performance index and each expected target performance index, runs the chip to be verified to obtain the monitoring target performance index of the chip to be verified in each first sub-period. Thus, through the set target performance index of the first sub-period and the expected target performance of the second sub-period, the monitoring target performance index of the chip to be verified in each first sub-period can be made to meet the real periodic transmission performance.

[0078] In order to implement the above embodiments, the present disclosure also proposes a chip verification device.

[0079] Figure 5 It is a schematic structural diagram of a chip verification device according to an exemplary embodiment.

[0080] like Figure 5 As shown, the chip verification device 500 includes: an acquisition module 510 , a first determination module 520 , a second determination module 530 and an operation module 540 .

[0081] Among them, the acquisition module 510 is used to obtain the transmission period of the performance data of the chip to be verified; the first determination module 520 is used to determine at least one first sub-period and the second sub-period in each first sub-period according to the transmission period; the second determination module 530 is used to determine the expected target performance indicator of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance indicator; the operation module 540 is used to operate the chip to be verified according to each set target performance indicator and each expected target performance indicator to obtain the monitoring target performance indicator of the chip to be verified in each first sub-period.

[0082] As a possible implementation method of the embodiment of the present disclosure, the second determination module 530 is also used to: for each first sub-period, compare the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; and multiply each of the duration ratios by the set target performance indicator of the corresponding first sub-period as the expected target performance indicator of the second sub-period in the corresponding first sub-period.

[0083] As a possible implementation method of an embodiment of the present disclosure, the first determination module 520 is also used to: divide the transmission period into multiple first sub-periods; for any first sub-period in the multiple first sub-periods, set a second sub-period in any first sub-period, wherein the duration of the second sub-period is less than the duration of any first sub-period.

[0084] As a possible implementation method of the embodiment of the present disclosure, the operation module 540 is also used to: set parameters in the verification instance of the chip to be verified according to each set target performance indicator and each expected target performance indicator; run the chip to be verified according to the verification instance after the parameter setting to obtain the transmission behavior information of the chip to be verified in each first sub-time period; determine the monitoring target performance indicator of the chip to be verified in each first sub-time period according to the transmission behavior information of each first sub-time period.

[0085] The chip verification device of the embodiment of the present disclosure obtains the transmission period of the performance data of the chip to be verified; determines at least one first sub-period and the second sub-period in each first sub-period according to the transmission period; determines the expected target performance index of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index; runs the chip to be verified according to each set target performance index and each expected target performance index to obtain the monitoring target performance index of the chip to be verified in each first sub-period. Thus, through the set target performance index of the first sub-period and the expected target performance of the second sub-period, the monitoring target performance index of the chip to be verified in each first sub-period can be made to meet the real periodic transmission performance.

[0086] In order to implement the above embodiments, the present disclosure also provides an electronic device, such as Figure 6 As shown, Figure 6 FIG. 1 is a block diagram of an electronic device for a chip verification method according to an exemplary embodiment. Figure 6 As shown, the electronic device 600 may include:

[0087] The memory 610 and the processor 620, and the bus 630 connecting different components (including the memory 610 and the processor 620), the memory 610 stores a computer program, and when the processor 620 executes the program, the chip verification method described in the embodiment of the present disclosure is implemented.

[0088] Bus 630 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor or a local bus using any of a variety of bus architectures. By way of example, these architectures include, but are not limited to, an Industry Standard Architecture (ISA) bus, a Micro Channel Architecture (MAC) bus, an Enhanced ISA bus, a Video Electronics Standards Association (VESA) local bus, and a Peripheral Component Interconnect (PCI) bus.

[0089] The electronic device 600 typically includes a variety of computer-readable media. These media can be any available media that can be accessed by the electronic device 600, including volatile and non-volatile media, removable and non-removable media.

[0090] The memory 610 may also include computer system readable media in the form of volatile memory, such as random access memory (RAM) 640 and / or cache memory 650. The electronic device 600 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, the storage system 660 may be used to read and write non-removable, non-volatile magnetic media ( Figure 6 not shown, usually called a "hard drive"). Although Figure 6 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk"), and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to the bus 630 via one or more data medium interfaces. The memory 610 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of the various embodiments of the present disclosure.

[0091] A program / utility 680 having a set (at least one) of program modules 670 may be stored, for example, in the memory 610, such program modules 670 including, but not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. The program modules 670 generally perform the functions and / or methods of the embodiments described in the present disclosure.

[0092] The electronic device 600 may also communicate with one or more external devices 690 (e.g., keyboard, pointing device, display 691, etc.), one or more devices that enable a user to interact with the electronic device 600, and / or any device that enables the electronic device 600 to communicate with one or more other computing devices (e.g., network card, modem, etc.). Such communication may be performed through an input / output (I / O) interface 692. Furthermore, the electronic device 600 may also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public network, such as the Internet) through a network adapter 693. Figure 6 As shown, the network adapter 693 communicates with other modules of the electronic device 600 via the bus 630. It should be understood that although Figure 6 Not shown, other hardware and / or software modules may be used in conjunction with electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0093] The processor 620 executes various functional applications and data processing by running the programs stored in the memory 610 .

[0094] It should be noted that the implementation process and technical principles of the electronic device of this embodiment refer to the aforementioned explanation of the chip verification method of the embodiment of the present disclosure, and will not be repeated here.

[0095] The electronic device provided by the embodiment of the present disclosure obtains the transmission period of the performance data of the chip to be verified; determines at least one first sub-period and the second sub-period in each first sub-period according to the transmission period; determines the expected target performance index of the second sub-period in the corresponding first sub-period according to the duration corresponding to each first sub-period and the set target performance index; runs the chip to be verified according to each set target performance index and each expected target performance index to obtain the monitoring target performance index of the chip to be verified in each first sub-period. Thus, through the set target performance index of the first sub-period and the expected target performance of the second sub-period, the monitoring target performance index of the chip to be verified in each first sub-period can be made to meet the real periodic transmission performance.

[0096] In order to implement the above embodiments, the embodiments of the present disclosure also provide a computer-readable storage medium.

[0097] When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the chip verification method as described above.

[0098] In order to implement the above embodiments, the present disclosure also provides a computer program product. When the computer program is executed by a processor of an electronic device, the electronic device can execute the chip verification method as described above.

[0099] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0100] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A chip verification method, characterized in that: include: Obtaining the transmission period of the performance data of the chip to be verified; Determine, according to the transmission period, at least one first sub-period and a second sub-period in each first sub-period; For each of the first sub-periods, comparing the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; The product of each of the time length ratios and the set target performance index of the corresponding first sub-period is used as the expected target performance index of the second sub-period in the corresponding first sub-period; According to each of the set target performance indicators and each of the expected target performance indicators, the chip to be verified is operated to obtain a monitoring target performance indicator of the chip to be verified in each of the first sub-periods.

2. The method according to claim 1, characterized in that The determining, according to the transmission period, at least one first sub-period and a second sub-period in each first sub-period comprises: Dividing the transmission period into multiple first sub-periods; For any first sub-period among the multiple first sub-periods, a second sub-period is set in the any first sub-period, wherein the duration of the second sub-period is shorter than the duration of the any first sub-period.

3. The method according to any one of claims 1 to 2, characterized in that: The step of operating the chip to be verified according to each of the set target performance indicators and each of the expected target performance indicators to obtain a monitoring target performance indicator of the chip to be verified in each of the first sub-periods includes: According to each of the set target performance indicators and each of the expected target performance indicators, parameter setting is performed in the verification instance of the chip to be verified; According to the verification instance after parameter setting, the chip to be verified is run to obtain transmission behavior information of the chip to be verified in each of the first sub-periods; According to the transmission behavior information of each of the first sub-periods, a monitoring target performance indicator of the chip to be verified in each of the first sub-periods is determined.

4. The method according to any one of claims 1 to 2, characterized in that The transmission period for obtaining the performance data of the chip to be verified includes: Obtaining a historical transmission log of performance data of the chip to be verified; A transmission period of the performance data of the chip to be verified is determined according to the historical transmission log.

5. A chip verification device, characterized in that: include: An acquisition module, used for acquiring a transmission period of performance data of a chip to be verified; A first determining module, configured to determine, according to the transmission period, at least one first sub-period and a second sub-period in each first sub-period; a second determining module, configured to compare, for each of the first sub-periods, the duration of the first sub-period with the duration of the corresponding second sub-period to obtain a duration ratio; The product of each of the time length ratios and the set target performance index of the corresponding first sub-period is used as the expected target performance index of the second sub-period in the corresponding first sub-period; An operation module is used to operate the chip to be verified according to each of the set target performance indicators and each of the expected target performance indicators to obtain a monitoring target performance indicator of the chip to be verified in each of the first sub-time periods.

6. The device according to claim 5, characterized in that The first determining module is further used for: Dividing the transmission period into multiple first sub-periods; For any first sub-period among the multiple first sub-periods, a second sub-period is set in the any first sub-period, wherein the duration of the second sub-period is shorter than the duration of the any first sub-period.

7. The device according to any one of claims 5-6, characterized in that The operation module is also used for: According to each of the set target performance indicators and each of the expected target performance indicators, parameter setting is performed in the verification instance of the chip to be verified; According to the verification instance after parameter setting, the chip to be verified is run to obtain transmission behavior information of the chip to be verified in each of the first sub-periods; According to the transmission behavior information of each of the first sub-periods, a monitoring target performance indicator of the chip to be verified in each of the first sub-periods is determined.

8. The device according to any one of claims 5-6, characterized in that The acquisition module is further used for: Obtaining a historical transmission log of performance data of the chip to be verified; A transmission period of the performance data of the chip to be verified is determined according to the historical transmission log.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the chip verification method according to any one of claims 1 to 4.

10. A computer-readable storage medium, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the chip verification method according to any one of claims 1 to 4.

11. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor of an electronic device, the electronic device is enabled to execute the chip authentication method according to any one of claims 1 to 4.

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