Display panel, driving method thereof, and display device

Abstract

This invention provides a display panel, its driving method, and a display device. The display panel includes a pixel circuit and a light-emitting element; the pixel circuit includes a data writing module and a driving module; the data writing module provides a data signal and an adjustment voltage; the driving module provides a driving current to the light-emitting element, and the driving module includes a driving transistor; wherein the adjustment voltage is used to adjust the bias state of the driving transistor, the adjustment voltage is VJ, and the maximum value of the voltage of the data signal is VD, where VJ ≥ VD. This invention can improve the flickering problem of the display panel.

Description

[0001] This application is a divisional application based on the patent application filed on March 1, 2021, with application number 202110226111.4 and entitled "Display Panel and Driving Method Thereof and Display Device Thereof". Technical Field

[0002] This invention relates to the field of display technology, and more particularly to a display panel, its driving method, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) possess advantages such as low power consumption, low cost, self-emissiveness, wide viewing angle, and fast response speed, making them a current research hotspot in the display field. Electronic products employ different refresh rates for display in different application scenarios. For example, higher refresh rates are used to drive dynamic images (such as sports events or games) to ensure smooth visuals; lower refresh rates are used to drive slow-motion images or static images to reduce power consumption. However, electronic products using organic self-emissive technology exhibit screen flickering when displaying slow-motion or static images, affecting the visual experience. Summary of the Invention

[0004] This invention provides a display panel, its driving method, and a display device to solve the technical problem of image flickering in the prior art.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including pixel circuitry and light-emitting elements;

[0006] The pixel circuit includes a data writing module and a driving module;

[0007] The data writing module is used to provide data signals and regulate voltage;

[0008] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor; wherein...

[0009] The adjustment voltage is used to adjust the bias state of the driving transistor. The adjustment voltage is VJ, and the maximum value of the voltage of the data signal is VD, where VJ ≥ VD.

[0010] Secondly, embodiments of the present invention provide a driving method for a display panel.

[0011] The display panel includes:

[0012] Pixel circuits and light-emitting elements;

[0013] The pixel circuit includes a data writing module and a driving module;

[0014] The data writing module is used to provide data signals and regulate voltage;

[0015] The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor; wherein...

[0016] The adjustment voltage is used to adjust the bias state of the driving transistor. The adjustment voltage is VJ, and the maximum value of the voltage of the data signal is VD, where VJ ≥ VD.

[0017] The operation of the display panel includes a data writing stage and a reset and adjustment stage.

[0018] The driving method includes:

[0019] During the data writing phase, the data writing module writes data signals;

[0020] During the reset adjustment phase, the data writing module writes the adjustment voltage.

[0021] Thirdly, embodiments of the present invention also provide a display device, including a display panel provided in any embodiment of the present invention.

[0022] The display panel, driving method, and display device provided in this embodiment of the invention have the following beneficial effects: by setting the adjustment voltage to be greater than or equal to the maximum value of the data signal voltage, the bias degree of the driving transistor can be made sufficiently large, thereby improving the flickering phenomenon when displaying images. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present invention;

[0026] Figure 3 This is a timing diagram of a pixel circuit in a display panel provided in an embodiment of the present invention;

[0027] Figure 4This is a timing diagram of a pixel circuit in a display panel of the prior art.

[0028] Figure 5 This illustrates a brightness curve of a display panel in the prior art during operation;

[0029] Figure 6 A schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of another pixel circuit in a display panel provided in an embodiment of the present invention;

[0031] Figure 8 for Figure 7 A timing diagram of a display panel provided in the embodiment;

[0032] Figure 9 A schematic diagram of the circuit structure of a display panel provided in an embodiment of the present invention;

[0033] Figure 10 This is a schematic diagram of another pixel circuit in a display panel provided in an embodiment of the present invention;

[0034] Figure 11 for Figure 10 A timing diagram of a display panel provided in the embodiment;

[0035] Figure 12 This is a timing diagram of another display panel provided in an embodiment of the present invention;

[0036] Figure 13 A flowchart of the driving method provided in an embodiment of the present invention;

[0037] Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0040] This invention provides a display panel, its driving method, and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit is electrically connected to the light-emitting element to drive the light-emitting element to emit light, thereby enabling the display panel to display images. During the display of one frame, the pixel circuit provides a driving current to the light-emitting element under the control of a light-emitting control signal to control the light-emitting element to emit light. In the initial stage of light emission, there is a process of increasing brightness, and the bias state of the driving transistor affects the rate of brightness increase. In the prior art, due to the large difference in the bias state of the driving transistor between adjacent frames, the brightness increase rate differs significantly, resulting in flickering when displaying images. In this invention, the operation of driving the display panel includes a data writing frame and a holding frame. During the data writing phase of the data writing frame, a data signal is written to the gate of the driving transistor, and during the light emission phase, the driving transistor is controlled to be in a bias state to generate a driving current. During the reset adjustment phase of the holding frame, an adjustment voltage is written to the first terminal (source) of the driving transistor to adjust the bias state of the driving transistor. By setting a reset adjustment phase in the hold frame, the difference in the bias state of the driving transistors in the hold frame and the data write frame is reduced, thereby reducing the difference in the rate of brightness increase of the light-emitting element in the initial stage of light emission in the hold frame and the rate of brightness increase of the light-emitting element in the initial stage of light emission in the data write frame, and improving the flickering phenomenon when displaying images. The above is the central idea of ​​the present invention, and the present invention will be described in detail below with specific embodiments.

[0041] Figure 1 This is a cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel circuit in a display panel provided in an embodiment of the present invention. Figure 3 This is a timing diagram of a pixel circuit in a display panel provided in an embodiment of the present invention.

[0042] like Figure 1 As shown, the display panel includes a substrate 10, an array layer 20, and a display layer 30 located on the substrate 10. The display layer 30 includes multiple light-emitting elements 31, which may include organic light-emitting diodes (OLEDs) or inorganic light-emitting diodes (LEDs). The array layer 20 includes pixel circuits 21 electrically connected to the light-emitting elements 31. Specifically, the light-emitting element 31 includes a first electrode, a light-emitting layer, and a second electrode stacked together. In one embodiment, the first electrode is a reflective anode, and the second electrode is a transparent cathode. Additionally, an encapsulation structure 40 is provided on the side of the display layer 30 away from the array layer 20. The encapsulation structure 40 is used to encapsulate and protect the light-emitting elements 31 to ensure their lifespan.

[0043] The structure of pixel circuit 21 can be referenced. Figure 2The pixel circuit, as illustrated in the diagram, includes a data writing module 211, a driving module 212, and a compensation module 213. The data writing module 211 provides data signals and adjusts the voltage; the driving module 212 provides driving current to the light-emitting element 31 and includes a driving transistor Mn; the compensation module 213 compensates for the threshold voltage of the driving transistor Mn.

[0044] like Figure 2 As illustrated, the gate of the driving transistor Mn is connected to the first node N1 in the pixel circuit, the source of the driving transistor Mn is connected to the second node N2, and the drain of the driving transistor Mn is connected to the third node N3. The data writing module 211 is connected to the source of the driving transistor Mn; the compensation module 213 is connected between the gate and drain of the driving transistor Mn. The pixel circuit also includes a light-emitting control module 214 and a reset module 215. The light-emitting control module 214 controls the driving transistor Mn to provide driving current to the light-emitting element 31, thereby controlling the light-emitting element 31 to perform the light-emitting phase; the reset module 215 provides a reset signal to the gate of the driving transistor Mn.

[0045] Specifically, the control terminal of the data writing module 211 is electrically connected to the first control signal terminal S1, the first terminal of the data writing module 211 is connected to the data signal input terminal Data, and the second terminal of the data writing module 211 is connected to the source of the driving transistor Mn. The control terminal of the compensation module 213 is electrically connected to the second control signal terminal S2, the first terminal of the compensation module 213 is electrically connected to the source of the driving transistor Mn, and the second terminal of the compensation module 213 is electrically connected to the drain of the driving transistor Mn. The light-emitting control module 214 is connected in series with the driving transistor Mn and the light-emitting element 31, respectively. The control terminal of the light-emitting control module 214 is electrically connected to the light-emitting control signal terminal E, and one terminal of the light-emitting control module 214 is electrically connected to the first power supply terminal PV. The control terminal of the reset module 215 is electrically connected to the reset control signal terminal Sr, the first terminal of the reset module 215 is electrically connected to the reset signal terminal Ref, and the second terminal of the reset module 215 is electrically connected to the gate of the driving transistor Mn.

[0046] Combination Figure 3 The timing diagram illustrates the operation of the display panel, which includes data writing frame Z1 and holding frame Z2.

[0047] In data writing frame Z1, the pixel circuit executes reset phase T1, data writing phase T2, and light emission phase T3. Reset phase T1 precedes data writing phase T2. In reset phase T1, reset module 215 is activated to reset the gate of driving transistor Mn. Specifically, reset module 215 is activated under the control of the reset control signal terminal Sr, providing the reset signal terminal Ref to the gate of driving transistor Mn to reset the gate of driving transistor Mn, ensuring that the display panel can write accurate data voltage to the gate of the driving transistor when executing data writing frame Z1. In data writing phase T2, data writing module 211 and compensation module 213 are activated, writing data signals to the gate of driving transistor Mn. Compensation module 213 compensates for the threshold voltage of driving transistor Mn. Specifically, the data writing module 211 is activated under the control of the first control signal terminal S1, writing the signal provided by the data signal input terminal Data to the source of the driving transistor Mn. The compensation module 213 is activated under the control of the second control signal terminal S2, providing the voltage of the drain of the driving transistor Mn to the gate of the driving transistor Mn. During the light emission stage T3, the light emission control module 214 is activated under the control of the light emission control signal terminal E, providing the driving current generated by the driving transistor Mn to the light emission element 31.

[0048] In hold frame Z2, the pixel circuit executes reset adjustment phase T4 and emission phase T3. In reset adjustment phase T4, data writing module 211 is turned on, compensation module 213 is turned off, and data writing module 211 writes an adjustment voltage to adjust the bias state of driving transistor Mn. Specifically, data writing module 211 is turned on under the control of the first control signal terminal S1, and writes the adjustment voltage through the data signal input terminal Data to the source of driving transistor Mn to adjust its bias state. The operation of the pixel circuit in emission phase T3 in hold frame Z2 is the same as its operation in emission phase T3 in data writing frame Z1.

[0049] The display panel includes data lines that are electrically connected to multiple pixel circuits; these data lines are the data signal writing terminals. Figure 3As shown in the timing diagram, the data signal input terminal Data provides a data signal in data write frame Z1. Even before the light emission phase T3 of data write frame Z1 ends, the data signal input terminal Data begins to provide the adjustment voltage VJ. That is, after each data write phase in the data write frame ends, the data line can begin to provide the adjustment voltage VJ. Furthermore, the portion of the signal after the adjustment voltage is provided on the data line (i.e., the data signal input terminal Data) can still be a data signal. In hold frame Z2, the reset module 215 remains off. Therefore, the pixel circuit does not execute the reset phase T1 in this frame, and the gate of the driving transistor Mn can maintain the potential of the previous light emission phase, generating a driving current under the control of the potential of the previous light emission phase. This ensures that the brightness of the light-emitting element driven by the pixel circuit in hold frame Z2 is the same as the brightness of the light-emitting element in data write frame Z1.

[0050] When the light-emitting control module 214 is off, it cannot provide driving current to the light-emitting element 31, so the light-emitting element 31 does not emit light. When a valid level signal is provided at the light-emitting control signal terminal E, the light-emitting control module 214 is turned on, and it can provide the driving current generated by the driving transistor Mn to the light-emitting element 31, so the light-emitting element 31 emits light. In the initial stage of light emission from the light-emitting element 31, there is a brightness increase process, and the rate of brightness increase is related to the bias state of the driving transistor Mn.

[0051] In the data writing frame Z1, which includes the stage of resetting the gate of the driving transistor Mn, the voltage VR of the reset signal terminal Ref is provided to the gate of the driving transistor Mn, thus affecting the bias state of the driving transistor Mn. At the beginning of the data writing stage T2, the gate voltage of the driving transistor Mn is VR; the source voltage of the driving transistor Mn maintains the voltage during the previous stage of light emission, which is close to the voltage VP provided by the first power supply terminal PV; therefore, at this time, the gate voltage relative to the source of the driving transistor Mn is Vgs1 = VR - VP.

[0052] Figure 4 This is a timing diagram of a pixel circuit in a prior art display panel. In the prior art, the control terminal of the data writing module 211 and the control terminal of the compensation module 213 are connected to the same scan signal terminal S'. In the prior art, the display panel executes a hold frame Z2' after the data writing frame Z1. The data writing frame Z1 and the hold frame Z2' take the same amount of time, but in the hold frame Z2', both the data writing module 211 and the compensation module 213 are turned off, and there is no process of resetting the gate of the driving transistor Mn. The gate of the driving transistor Mn maintains the potential of the previous light-emitting stage to control the generation of the driving current. The gate potential of the driving transistor Mn in the previous light-emitting stage is the value at which the data signal V is generated. Data The potential after writing to the gate is V.Data +Vth, where Vth is the threshold voltage of the driving transistor Mn. At time T2' in hold frame Z2', corresponding to the data write phase T2 in data write frame Z1, the source of the driving transistor Mn maintains the potential from the previous light-emitting phase, which is close to VP. Therefore, at this time, the voltage Vgs1' relative to the source of the driving transistor Mn is V... Data +Vth-VP. With V Ref Taking -3V and -2V as an example, and using the formula for driving current Id = K * (VP - V) as an example... Data ) 2 V Data The larger the value, the smaller the drive current Id, and therefore, when performing low grayscale display, V... Data Relatively large. And V Data The larger the value, the greater the difference between Vgs1' and Vgs1. This means that the bias state of the driving transistor Mn differs significantly between the two cases, resulting in a large difference in the rate of brightness increase of the light-emitting element 31 between the data write frame Z1 and the hold frame Z2'. Specifically, |Vgs1| > |Vgs1'|. Therefore, in the data write frame Z1, after the light-emitting control module 214 is turned on, the rate of brightness increase of the light-emitting element 31 is slower; while in the hold frame Z2', after the light-emitting control module 214 is turned on, the rate of brightness increase of the light-emitting element 31 is faster.

[0053] Figure 5 This diagram illustrates a brightness curve of a display panel in the prior art, with the horizontal axis representing time and the vertical axis representing brightness. Figure 5 The diagram illustrates one operating mode of the display panel, in which one data write frame Z1 and three hold frames Z2' are executed within one cycle ZT. Position W1 represents the brightness increase process of the light-emitting element in data write frame Z1, and position W2 represents the brightness increase process of the light-emitting element in hold frame Z2'. It can also be seen from the diagram that the brightness increase rate of the light-emitting element in data write frame Z1 is slower than that in hold frame Z2'. This results in a relatively serious flickering problem in the existing display technology.

[0054] Continue to refer to the above. Figure 3 The schematic timing diagram shows that during the operation of the display panel provided by this invention, a holding frame Z2 is included. Holding frame Z2 includes a reset adjustment phase T4. During the reset adjustment phase T4, the data writing module 211 writes an adjustment voltage VJ to the source of the driving transistor Mn. In this phase, the voltage at the source of the driving transistor Mn is close to VJ, while the gate of the driving transistor Mn maintains the potential of the previous light-emitting phase, thus the gate voltage of the driving transistor Mn is close to VJ. Data +Vth. Then, at this time, the gate-to-source voltage of the driving transistor Mn is Vgs2 = V. Data+Vth-VJ. In this invention, by controlling the adjustment voltage VJ to adjust the bias state of the driving transistor Mn, the difference between Vgs2 and Vgs1 can be reduced, making Vgs2 and Vgs1 closer. This is equivalent to writing the adjustment voltage VJ to the source of the driving transistor Mn during the reset adjustment phase T4 to simulate the bias state of the driving transistor Mn in the data write frame Z1, thereby reducing the brightness rise rate of the light-emitting element 31 in the hold frame Z2. This makes the brightness rise rate of the light-emitting element in the hold frame Z2 more consistent with the brightness rise rate of the light-emitting element in the data write frame Z1, improving the display flicker problem.

[0055] Specifically, such as Figure 2 As shown, the data writing module 211 includes a first transistor M1a. The first terminal of the first transistor M1a is connected to the data signal input terminal Data, the second terminal of the first transistor M1a is connected to the source of the driving transistor Mn, and the gate of the first transistor M1a is connected to the first control signal terminal S1. Specifically, during the data writing phase T2, under the control of the signal at the first control signal terminal S1, the first transistor M1a writes a voltage signal to the source of the driving transistor Mn; during the reset adjustment phase T4, under the control of the signal at the first control signal terminal S1, the first transistor M1a writes an adjustment voltage to the source of the driving transistor Mn. In this embodiment, the first transistor M1a is used as a data writing transistor during the data writing phase T2 and as a voltage regulating transistor during the reset adjustment phase T4. Therefore, adding a reset adjustment phase in the holding frame only requires changing the driving timing of the pixel circuit, without changing the structure of the pixel circuit.

[0056] Continue to refer to Figure 2 As illustrated, the compensation module 213 includes a compensation transistor M2. The first terminal of the compensation transistor M2 is connected to the drain of the driving transistor Mn, and the second terminal of the compensation transistor M2 is connected to the gate of the driving transistor Mn. The gate of the compensation transistor M2 is connected to the second control signal terminal S2. That is, the gate of the compensation transistor M2 and the gate of the first transistor M1a are respectively connected to different control signal terminals, thereby enabling separate control of the on / off states of the compensation module 213 and the data writing module 211. This ensures that during the reset adjustment phase T4, the data writing module 211 can be turned on while the compensation module 213 is turned off.

[0057] Continue to refer to Figure 2 As shown, the light-emitting control module 214 includes a first light-emitting control module 214a and a second light-emitting control module 214b. The first light-emitting control module 214a is connected between the first power supply terminal PV and the source of the driving transistor Mn, and the second light-emitting control module 214b is connected between the drain of the driving transistor Mn and the light-emitting element 31. Figure 2The diagram illustrates that the control terminals of both the first light-emitting control module 214a and the second light-emitting control module 214b are connected to the light-emitting control signal terminal E. In another embodiment, the first light-emitting control module 214a and the second light-emitting control module 214b are controlled by different control signals, thus their on / off states can be different. In this embodiment, during the reset adjustment phase T4, at least the first light-emitting control module 214a remains off to ensure that the bias state of the driving transistor is adjusted by writing an adjustment voltage to the source of the driving transistor during this phase. This prevents the first light-emitting control module 214a from providing a voltage signal to the source of the driving transistor during this phase, which would affect the adjustment of the driving transistor's bias state.

[0058] Specifically, the first light-emitting control module 214a includes a first light-emitting transistor M3, and the second light-emitting control module 214b includes a second light-emitting transistor M4. The gates of both the first and second light-emitting transistors M3 and M4 are connected to the light-emitting control signal terminal E. The first terminal of the first light-emitting transistor M3 is connected to the first power supply terminal PV, and the second terminal of the first light-emitting transistor M3 is connected to the source of the driving transistor Mn. The first terminal of the second light-emitting transistor M4 is connected to the drain of the driving transistor Mn, and the second terminal of the second light-emitting transistor M4 is connected to the light-emitting element 31.

[0059] Specifically, such as Figure 2 As illustrated, the reset module 215 includes a reset transistor M5, the control terminal of the reset transistor M5 is connected to the reset control signal terminal Sr, the first terminal of the reset transistor M5 is connected to the reset signal terminal Ref, and the second terminal of the reset transistor M5 is connected to the gate of the driving transistor Mn.

[0060] In one embodiment, during the reset phase T1, the gate voltage of the driving transistor Mn is Vg1, and the source voltage of the driving transistor Mn is Vs1. Therefore, during this phase, the voltage Vgs of the gate relative to the source of the driving transistor Mn is Vg1 - Vs1. Specifically, Vg1 is close to the reset signal VR written by the reset module 215 to the gate of the driving transistor Mn, the source voltage of the driving transistor Mn maintains the voltage during the previous light-emitting phase, and Vs1 is close to the voltage VP provided by the first power supply terminal PV.

[0061] During the reset adjustment phase T4, the gate voltage of driving transistor Mn is Vg2, and the source voltage is Vs2. Therefore, during this phase, the gate voltage Vgs1 relative to the source of driving transistor Mn is Vg2 - Vs2. Specifically, if the gate of driving transistor Mn maintains the potential from the previous light-emitting phase, then Vg2 is close to Vs2. Data +Vth;Vs2 is close to the regulated voltage VJ written to the source of the driving transistor Mn.

[0062] For the driving transistor Mn, when the voltage of its gate relative to the source is less than Vth, the driving transistor will turn on, and the greater the voltage of the gate relative to the source, the greater the biasing degree of the driving transistor. In this embodiment, -3V ≤ Vg1 - Vs1 - (Vg2 - Vs2) ≤ 3V, that is, -3V ≤ Vgs - Vgs1 ≤ 3V. Then, the difference in the biasing states of the driving transistor Mn in both the holding frame Z2 and the data writing frame Z1 is relatively small, which can reduce the brightness rising speed of the light-emitting element 31 in the holding frame Z2, making the brightness rising speed of the light-emitting element in the holding frame Z2 and the brightness rising speed of the light-emitting element in the data writing frame Z1 tend to be consistent, and improving the problem of display screen flicker.

[0063] Furthermore, in some embodiments, -2V ≤ Vg1 - Vs1 - (Vg2 - Vs2) ≤ 2V. In other embodiments, -1V ≤ Vg1 - Vs1 - (Vg2 - Vs2) ≤ 1V. This can further narrow the difference in the biasing states of the driving transistor Mn in both the holding frame Z2 and the data writing frame Z1, further improve the display screen flicker, and enhance the display effect.

[0064] In the embodiment of the present invention, an adjustment voltage is written to the source of the driving transistor Mn during the reset adjustment stage T4 to adjust the biasing state of the driving transistor Mn, and the influence of the following factors can be considered for the value of the adjustment voltage VJ.

[0065] Specifically, at the initial moment of the reset adjustment stage T4, the voltage of the source of the driving transistor Mn is Vs1; where VJ > Vs1. During the reset adjustment stage T4, an adjustment voltage VJ is written to the source of the driving transistor Mn, then the source voltage of the driving transistor Mn is increased during the reset adjustment stage T4, thereby increasing the biasing degree of the driving transistor Mn to reduce the difference in the biasing states of the driving transistor Mn in the holding frame Z2 and the driving transistor Mn in the data writing frame Z1. Optionally, 0V < VJ - Vs1 ≤ 3.5V. Furthermore, 1V < VJ - Vs1 ≤ 3.5V is set. Setting VJ > Vs1 to adjust the biasing state of the driving transistor Mn in the holding frame, while improving the problem of display screen flicker, there is no need to set VJ too large to reduce power consumption.

[0066] Specifically, when the holding frame Z2 has neither a reset stage T1 nor a data writing stage T2, at the initial moment of the reset adjustment stage T4, the source of the driving transistor Mn maintains the voltage in the previous light-emitting stage. Then Vs1 is close to the power supply voltage VP written by the light-emitting control module 214 to the source of the driving transistor Mn by turning on the first power supply terminal PV in the previous light-emitting stage. In the embodiment of the present invention, VJ≥VP is set to adjust the bias state of the driving transistor Mn in the holding frame, which is equivalent to writing an adjustment voltage VJ to the source of the driving transistor Mn in the reset adjustment stage T4 to simulate the bias state of the driving transistor Mn in the data writing frame Z1, so as to reduce the brightness rising speed of the light-emitting element 31 in the holding frame Z2, making the brightness rising speed of the light-emitting element in the holding frame Z2 and the brightness rising speed of the light-emitting element in the data writing frame Z1 tend to be consistent and improving the display screen flickering problem.

[0067] In one embodiment, VP = 4.6V, 6V≤VJ≤8V. Setting VP is greater than VP and VJ is not too large to avoid excessive power consumption.

[0068] In one embodiment, the maximum value of the voltage of the preset data signal is VD, and VJ≥VD. Here, the voltage of the preset data signal is the data voltage required to display different gray levels preset in the display panel. Among them, the lower the displayed gray level, the greater the corresponding voltage of the preset data signal. VJ≥VD, that is, VJ is not less than the preset dark state voltage in the display panel. According to the description in the above embodiment, after resetting the gate of the driving transistor Mn in the data writing frame Z1, the voltage Vgs1 of the gate of the driving transistor Mn relative to the source is Vgs1 = VR - VP; in the reset adjustment stage T4, the voltage Vgs2 of the gate of the driving transistor Mn relative to the source is Vgs2 = V Data +Vth - VJ. And VJ≥VD≥V Data , then V Data -VJ≤0, so that Vgs2≤Vth, and only when V Data = VD, Vgs2 = Vth. That is to say, when the holding frame displays a non-dark state, it can be ensured that after writing an adjustment voltage to the driving transistor in the reset adjustment stage, the driving transistor is in a bias state, thereby adjusting the bias of the driving transistor. In the embodiment of the present invention, the power supply voltage VP provided by the first power supply terminal PV is <VD. Specifically, VP = 4.6V and VD = 5.5V. Based on the above Figure 2As explained in the embodiment, when VJ is greater than VP, the bias state of the driving transistor can be adjusted. In this embodiment, VJ is set to be greater than VD, where VD is greater than VP. This ensures that the bias degree of the driving transistor in the hold frame is sufficiently large, making the bias state of the driving transistor in the hold frame close to that in the data write frame, thereby improving the problem of screen flicker.

[0069] In one embodiment, the voltage of the reset signal is VR, and VJ ≥ VR. Since the voltage VR of the reset signal in the display panel is relatively small, by setting VJ to be no less than VR, it is possible to avoid writing too small a voltage to the source of the driving transistor when adjusting the bias state of the driving transistor in the hold frame, thus preventing the bias adjustment from being ineffective.

[0070] Specifically, the regulating voltage VJ is a constant voltage.

[0071] correspond Figure 2 and the following Figure 10 The pixel circuit structure illustrated in the embodiment provides a data signal at the data writing phase and an adjustment voltage VJ at the reset adjustment phase, meaning the data signal input is multiplexed in both phases. Normally, in a display module, the data signal input is connected to the driving circuit (i.e., the driving chip) via data lines in the display panel. By setting the adjustment voltage VJ to a constant voltage, when the display panel operates in hold frame mode, the driving circuit provides a constant voltage to the data signal input, simplifying the driving circuit's operation.

[0072] Corresponding to the following Figure 7 The illustrated pixel circuit structure includes a data signal input terminal (Data) and an adjustment signal input terminal (V). H These are two different signal terminals. The process of writing the adjustment voltage to the source of the driving transistor during the reset adjustment phase does not affect the control of the data writing process. In this embodiment, setting the adjustment voltage VJ to a constant voltage enables the adjustment signal input terminal V in multiple pixel circuits of the display panel to... H Connecting to the same adjustment signal line can reduce the number of voltage regulation signal lines in the display panel, and can provide adjustment signals to multiple adjustment signal lines from one output port of the drive circuit, which can reduce the number of additional ports in the drive circuit, and also reduce the power consumption of the adjustment signal line in transmitting the adjustment signal.

[0073] In one embodiment, during the reset adjustment phase T4, the gate voltage of the driving transistor Mn is Vg2, and the source voltage of the driving transistor Mn is Vs2. The gate-to-source voltage of the driving transistor Mn during this phase is set to Vgs2 = Vg2 - Vs2 ≤ -2V. The value of Vgs2 is set within a certain range to ensure that the driving transistor Mn is in a biased state, and that the bias state in this phase is close to the bias state of the driving transistor Mn in the data write frame Z1. This makes the brightness rise rate of the light-emitting element in frame Z2 and the brightness rise rate of the light-emitting element in data write frame Z1 more consistent, improving the display flicker problem.

[0074] In one embodiment, Figure 6 This is a schematic diagram of the circuit structure of another display panel provided in an embodiment of the present invention, as shown below. Figure 6 The diagram illustrates a portion of the display panel's structure, which includes a display area AA and a non-display area BA. The pixel circuitry 21 within the display panel is as described above. Figure 2 The circuit structure shown in the figure is simplified, only illustrating the data writing module 211 within the pixel circuit 21. The display panel also includes a driving circuit 22 and a data line 23. Specifically, the driving circuit 22 is a driving chip, and the driving circuit 22 is connected to the data writing module 211 via the data line 23.

[0075] When the display panel is operating, during the data writing phase T2, the driving circuit 22 provides a data signal to the data writing module 211 via the data line 23; during the reset adjustment phase T4, the driving circuit 22 provides an adjustment voltage VJ to the data writing module 211 via the data line 23. Specifically, after the data writing frame Z1, the display panel executes at least one hold frame Z2. One data line 23 is electrically connected to multiple pixel circuits in a column of pixels. Optionally, after all the multiple pixel circuits connected to one data line 23 in the data writing frame Z1 have completed the data writing phase T2, the driving circuit 22 controls the supply of an adjustment voltage VJ to the data line 23, so that the pixel circuits adjacent to that data line 23 execute the reset adjustment phase T4 in the hold frame Z2. Specifically, the adjustment voltage VJ is not less than the maximum preset data voltage that the driving circuit 22 can output. This implementation provides different voltage signals to the data line at different operating stages through the driving circuit, so that the data writing module can be reused in the data writing stage and the reset adjustment stage. While adjusting the bias state of the driving transistor in the holding frame to improve the screen flicker problem, it does not require any changes to the structure of the pixel circuit or the connection method between the pixel circuit and the driving circuit.

[0076] In another implementation, Figure 7 This is a schematic diagram of another pixel circuit in a display panel provided in an embodiment of the present invention. Figure 8 for Figure 7 A timing diagram of a display panel provided in the embodiment.

[0077] like Figure 7 As shown, the data writing module 211 includes a second transistor M1b and a third transistor M1c. The first terminal of the second transistor M1b is connected to the data signal input terminal Data, the second terminal of the second transistor M1b is connected to the source of the driving transistor Mn, and the gate of the second transistor M1b is connected to the second control signal terminal S2; the first terminal of the third transistor M1c is connected to the adjustment signal input terminal V. H The second terminal of the third transistor M1c is connected to the source of the driving transistor Mn, and the gate of the third transistor M1c is connected to the third control signal terminal S3. The pixel circuit includes a compensation module 213, which includes a compensation transistor M2, whose first terminal is connected to the gate of the driving transistor Mn, whose second terminal is connected to the drain of the driving transistor Mn, and whose gate is connected to the second control signal terminal S2. As illustrated in the figure, the pixel circuit also includes a driving module 212, a light emission control module 214, and a reset module 215. The connection relationships between these modules and the various control terminals can be referred to the above. Figure 2 The descriptions of the corresponding embodiments will not be repeated here.

[0078] The operation of the display panel includes data writing frame Z1 and holding frame Z2. Specifically...

[0079] In data writing frame Z1, the pixel circuit executes reset phase T1, data writing phase T2, and light emission phase T3. In reset phase T1, reset module 215 is activated under the control of the reset control signal terminal Sr, providing the reset signal terminal Ref to the gate of driving transistor Mn to reset the gate of driving transistor Mn. In data writing phase T2, under the control of the second control signal terminal S2, second transistor M1b writes the data signal to the source of driving transistor Mn; simultaneously, under the control of the second control signal terminal S2, compensation transistor M2 is activated, providing the voltage at the drain terminal of driving transistor Mn to the gate of driving transistor Mn. In this phase, the data signal is written to the gate of driving transistor Mn, compensating for the threshold voltage of driving transistor Mn. In light emission phase T3, light emission control module 214 is activated under the control of the light emission control signal terminal E, providing the driving current generated by driving transistor Mn to light-emitting element 31.

[0080] During hold frame Z2, the pixel circuit executes reset adjustment phase T4 and light emission phase T3. During reset adjustment phase T4, under the control of the third control signal terminal S3, the third transistor M1c writes the adjustment voltage VJ to the source of the driving transistor Mn. During light emission phase T3, the light emission control module 214 is turned on under the control of the light emission control signal terminal E. The gate of the driving transistor Mn maintains the potential from the previous light emission phase and, under the control of the gate potential, generates a driving current. This driving current generated by the driving transistor Mn is provided to the light-emitting element 31 during this phase. During hold frame Z2, the compensation module 213 and the reset module 215 are turned off.

[0081] In this embodiment, a reset adjustment stage T4 is set in the holding frame Z2. During the reset adjustment stage T4, an adjustment voltage VJ is written to the source of the driving transistor Mn to simulate the bias state of the driving transistor Mn in the data writing frame Z1. This reduces the brightness rise rate of the light-emitting element 31 in the holding frame Z2, making the brightness rise rate of the light-emitting element in the holding frame Z2 and the brightness rise rate of the light-emitting element in the data writing frame Z1 more consistent, thus improving the flickering problem of the display screen. The data writing module 211 includes a second transistor M1b and a third transistor M1c. The second transistor M1b is a data writing transistor, and the third transistor M1c is a voltage regulating transistor. The input terminals (i.e., the first terminals) of the two transistors are connected to different signal input terminals, and the two transistors are controlled by different control signal terminals, enabling separate control of the data writing stage and the reset adjustment stage. Furthermore, the gate of the data writing transistor and the gate of the compensation transistor are connected to the same control signal terminal (the second control signal terminal), ensuring that the compensation transistor and the data writing transistor can be turned on simultaneously during the data writing stage without requiring additional control of the compensation transistor.

[0082] Furthermore, the adjustment signal input terminals corresponding to at least two third transistors are connected to the same voltage regulation signal line. Figure 9 This is a schematic diagram of the circuit structure of a display panel provided in an embodiment of the present invention. Figure 9 The diagram illustrates two pixel circuits located in the same pixel column, where the adjustment signal input terminal V corresponds to the third transistor M1c in both pixel circuits. H Connected to the same voltage regulation signal line X H The diagram also illustrates data line 23 and power signal line 24. The data signal terminals (Data) of the two pixel circuits are connected to the same data line 23, and the power signal terminals (PV) are connected to the same power signal line 24. One pixel circuit is located in the nth pixel row, and the other pixel circuit is located in the (n+1)th pixel row. The second control signal terminal in the pixel circuit of the nth pixel row is labeled S2n, and the second control signal terminal in the pixel circuit of the (n+1)th pixel row is labeled S2. n+1 , Figure 9 Other reference numerals in the accompanying drawings can be understood by referring to them, and will not be explained one by one here.

[0083] In another embodiment, the adjustment signal input terminal of the third transistor in multiple pixel circuits located in the same pixel row is connected to the same voltage regulation signal line. (This is not illustrated in the accompanying drawings.)

[0084] By connecting the adjustment signal input terminals of the third transistors in multiple pixel circuits to the same voltage regulation signal line, the number of voltage regulation signal lines in the display panel can be reduced, saving wiring space. Furthermore, connecting the input terminals of each voltage regulation signal line in the display panel to the same output port of the driver circuit (i.e., the driver chip) can save on the number of ports and also reduce the voltage drop when transmitting the voltage regulation signal, thus reducing power consumption.

[0085] In another implementation, Figure 10 This is a schematic diagram of another pixel circuit in a display panel provided in an embodiment of the present invention. Figure 11 for Figure 10 A timing diagram of a display panel provided in the embodiment.

[0086] like Figure 10 As shown, the data writing module 211 includes a second transistor M1b and a fourth transistor M1d. The first terminal of the second transistor M1b is connected to the data signal input terminal Data, the second terminal of the second transistor M1b is connected to the source of the driving transistor Mn, and the gate of the second transistor M1b is connected to the second control signal terminal S2. The first terminal of the fourth transistor M1d is connected to the data signal input terminal Data, the second terminal of the fourth transistor M1d is connected to the source of the driving transistor Mn, and the gate of the fourth transistor M1d is connected to the fourth control signal terminal S4. The pixel circuit includes a compensation module 213, which includes a compensation transistor M2. Its first terminal is connected to the gate of the driving transistor Mn, its second terminal is connected to the drain of the driving transistor Mn, and its gate is connected to the second control signal terminal S2. As illustrated in the figure, the pixel circuit also includes a driving module 212, a light-emitting control module 214, and a reset module 215. The connection relationships between these modules and the various control terminals can be referred to the above. Figure 2 The descriptions of the corresponding embodiments will not be repeated here.

[0087] The operation of the display panel includes data writing frame Z1 and holding frame Z2. Specifically...

[0088] In data writing frame Z1, the pixel circuit executes reset phase T1, data writing phase T2, and light emission phase T3. In reset phase T1, reset module 215 is activated under the control of the reset control signal terminal Sr, providing the reset signal terminal Ref to the gate of driving transistor Mn to reset the gate of driving transistor Mn. In data writing phase T2, under the control of the second control signal terminal S2, second transistor M1b writes the data signal to the source of driving transistor Mn; simultaneously, under the control of the second control signal terminal S2, compensation transistor M2 is activated, providing the voltage at the drain terminal of driving transistor Mn to the gate of driving transistor Mn. In this phase, the data signal is written to the gate of driving transistor Mn, compensating for the threshold voltage of driving transistor Mn. In light emission phase T3, light emission control module 214 is activated under the control of the light emission control signal terminal E, providing the driving current generated by driving transistor Mn to light-emitting element 31.

[0089] During hold frame Z2, the pixel circuit executes reset adjustment phase T4 and light emission phase T3. During reset adjustment phase T4, under the control of the signal at the fourth control signal terminal S4, the fourth transistor M1d writes the adjustment voltage VJ to the source of the driving transistor Mn. During light emission phase T3, the light emission control module 214 is turned on under the control of the light emission control signal terminal E. The gate of the driving transistor Mn maintains the potential from the previous light emission phase and, under the control of the gate potential, generates a driving current. This driving current generated by the driving transistor Mn is provided to the light-emitting element 31 during this phase. During hold frame Z2, the compensation module 213 and the reset module 215 are turned off.

[0090] This implementation sets a reset adjustment stage T4 in the hold frame Z2. During the reset adjustment stage T4, an adjustment voltage VJ is written to the source of the driving transistor Mn to simulate the bias state of the driving transistor Mn in the data write frame Z1. This reduces the brightness rise rate of the light-emitting element 31 in the hold frame Z2, making the brightness rise rate of the light-emitting element in the hold frame Z2 and the brightness rise rate of the light-emitting element in the data write frame Z1 more consistent, thus improving the display flicker problem. The data write module 211 includes a second transistor M1b and a fourth transistor M1d. The second transistor M1b is a data write transistor, and the fourth transistor M1d is a voltage regulating transistor. The input terminals (i.e., the first terminals) of the two transistors are connected to the same signal input terminal, and the two transistors are controlled by different control signal terminals. Therefore, the gate of the data write transistor and the gate of the compensation transistor can be connected to the same control signal terminal (the second control signal terminal), ensuring that the compensation transistor and the data write transistor can be turned on simultaneously during the data write stage. Furthermore, in the data write frame and the hold frame, the data write module writes voltage signals to the source of the driving transistor through different transistors.

[0091] In one embodiment, the operating mode of the display panel includes a first mode, the first mode including a repeated first cycle, the first cycle including a data write frame and at least one hold frame. Figure 12 This is a timing diagram of another display panel provided in an embodiment of the present invention. Figure 12 As shown, the first cycle ZT1 includes one data write frame Z1 and four hold frames Z2. The timing of hold frame Z2 in the figure is as described above. Figure 3 The timing diagram in the embodiment is illustrated. In the first cycle ZT1, a data signal is written to the pixel circuit in the data write frame Z1, and a driving current is generated under the control of the data signal to control the light-emitting element to emit light. In the holding frame Z2, there is no reset phase T1 and data write phase T2. In the holding frame Z2, the gate of the driving transistor maintains the potential of the previous light-emitting phase, and a driving current is generated under the control of this potential. That is, the brightness of the light-emitting element in the holding frame Z2 maintains the brightness of the light-emitting element in the data write frame Z1. In this embodiment of the invention, a reset adjustment phase T4 is set in the holding frame Z2 to adjust the bias state of the driving transistor Mn, so that the brightness rise rate of the light-emitting element in the holding frame Z2 is consistent with the brightness rise rate of the light-emitting element in the data write frame Z1, thereby improving the flickering problem of the display screen.

[0092] In one embodiment, when the display breadboard is driven to operate in the first mode, the display panel displays slow-motion video footage. In another embodiment, when the display breadboard is driven to operate in the first mode, the display panel displays static images.

[0093] Furthermore, the display panel's operating mode also includes a second mode, which includes repeated data writing frames Z1. In this second mode, the image refresh rate of the display panel is higher than that in the first mode. The second mode is a high-frequency operating mode compared to the first mode, while the first mode is a low-frequency operating mode. In applications, the first mode is used in scenarios where the display panel is driven to display dynamic images. The display panel provided in this embodiment includes different operating modes, and the display panel switches between the first and second modes according to the different refresh rate requirements of the displayed image. For example, driving the display panel to operate in the first mode to display static images or slow-motion videos can reduce the power consumption of the display panel; driving the display panel to operate in the second mode to display dynamic images can improve the smoothness of the image display.

[0094] In one embodiment, the driving transistor Mn is a P-type transistor. Specifically, the active layer of the driving transistor Mn is made of silicon; optionally, the driving transistor Mn is a low-temperature polycrystalline silicon (LTPS) transistor. LTPS transistors have high electron mobility and stability. Furthermore, the transistors in each module of the pixel circuit are also P-type transistors. The pixel circuit incorporating LTPS transistors can occupy a smaller area while meeting the driving performance requirements of the light-emitting elements.

[0095] Furthermore, in this embodiment of the invention, the pixel circuit further includes a light-emitting element reset module, which is electrically connected to the light-emitting element and used to reset the electrodes of the light-emitting element. A first terminal of the light-emitting element reset module is electrically connected to a reset signal terminal, and a second terminal of the light-emitting element reset module is electrically connected to the light-emitting element.

[0096] In one embodiment, the control terminal of the light-emitting element reset module is connected to the control terminal of the reset module, so that during the reset phase, the light-emitting element reset module resets the electrodes of the light-emitting element.

[0097] In another embodiment, the control terminal of the light-emitting element reset module and the control terminal of the compensation module are connected to the same control terminal. Then, during the data writing stage, the light-emitting element reset module resets the electrodes of the light-emitting element.

[0098] Furthermore, this embodiment of the invention also provides a driving method for a display panel, which can be used to drive the display panel provided in this embodiment of the invention. The display panel includes: pixel circuits and light-emitting elements; the structure of the pixel circuits can be referred to the above. Figure 2 , Figure 7 or Figure 10 The diagram illustrates the process. The pixel circuit includes a data writing module 211, a driving module 212, and a compensation module 213. The data writing module 211 provides data signals and adjusts the voltage. The driving module 212 provides driving current to the light-emitting element 31 and includes a driving transistor Mn. The compensation module 213 compensates for the threshold voltage of the driving transistor Mn. The operation of the display panel includes a data writing frame Z1 and a holding frame Z2. The driving method can be understood in conjunction with the operation of the display panel in the above-described display panel embodiment. Figure 13 A flowchart of the driving method provided in the embodiments of the present invention is shown below. Figure 13 As shown, the driving method includes:

[0099] In data writing frame Z1, pixel circuit 21 performs data writing stage T2 and light emission stage T3. In data writing stage T2, data writing module 211 and compensation module 213 are turned on, and data writing module 211 writes data signal.

[0100] While holding frame Z2, pixel circuit 21 executes reset adjustment phase T4 and light emission phase T3. During reset adjustment phase T4, data writing module 211 is turned on and compensation module 213 is turned off. Data writing module 211 writes adjustment voltage to adjust the bias state of driving transistor Mn.

[0101] The driving method provided in this embodiment of the invention controls the pixel circuit to perform a reset adjustment stage when the display panel is working in the hold frame, so as to adjust the bias state of the driving transistor in the hold frame, thereby reducing the difference in the bias state of the driving transistor between the hold frame and the data write frame, thereby reducing the difference between the initial brightness rise rate of the light-emitting element in the hold frame and the initial brightness rise rate of the light-emitting element in the data write frame, and improving the flickering phenomenon when displaying images.

[0102] Further details can be found in the above. Figure 2 , Figure 7 or Figure 10 As shown, the pixel circuit also includes a reset module 215 and a light-emitting control module 214; the data writing module 211 is connected between the data signal input terminal Data and the source of the driving transistor Mn; the compensation module 213 is connected between the gate and the drain of the driving transistor Mn; the reset module 215 is connected between the reset voltage input terminal Ref and the gate of the driving transistor Mn; the light-emitting control module 214 includes a first light-emitting control module 214a and a second light-emitting control module 214b, the first light-emitting control module 214a is connected between the first power supply terminal PV and the source of the driving transistor Mn, and the second light-emitting control module 214b is connected between the drain of the driving transistor Mn and the light-emitting element 31.

[0103] Specifically, embodiments of the present invention provide a driving method that can be applied to driving. Figure 2 The display panel provided in the embodiment corresponds to Figure 2 The schematic pixel circuit shows that the reset control signal terminal Sr provides the first scan signal, the first control signal terminal S1 provides the second scan signal, the second control signal terminal S2 provides the third scan signal, and the light emission control signal terminal E provides the fourth scan signal. Combined with... Figure 3 The timing diagram illustrates the driving method, which includes: in data write frame Z1, the pixel circuit sequentially executes reset phase T1, data write phase T2, and light emission phase T3; wherein,

[0104] During the reset phase T1, the first scan signal controls the reset module 215 to turn on, the second scan signal controls the data writing module 211 to turn off, the third scan signal controls the compensation module 213 to turn off, and the fourth scan signal controls the light emission control module 214 to turn off. In this phase, the gate of the driving transistor Mn is reset via the reset module 215.

[0105] During the data writing phase T2, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the data writing module 211 to turn on, the third scan signal controls the compensation module 213 to turn on, and the fourth scan signal controls the light emission control module 214 to turn off. In this phase, data signals are written to the gate of the driving transistor Mn, and the offset of the threshold voltage of the driving transistor Mn is compensated.

[0106] During the light-emitting stage T3, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the data writing module 211 to turn off, the third scan signal controls the compensation module 213 to turn off, and the fourth scan signal controls the light-emitting control module 214 to turn on. During this stage, the driving transistor Mn generates a driving current, and the light-emitting control module 214 controls the supply of driving current to the light-emitting element.

[0107] While holding frame Z2, the pixel circuit sequentially executes the reset adjustment phase T4 and the emission phase T3; wherein...

[0108] During the reset adjustment phase T4, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the data writing module 211 to turn on, the third scan signal controls the compensation module 213 to turn off, and the fourth scan signal controls the light emission control module 214 to turn off. During this phase, the data writing module 211 turns on and writes an adjustment voltage to the source of the driving transistor Mn to adjust the bias state of the driving transistor Mn.

[0109] During the light-emitting stage, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the data writing module 211 to turn off, the third scan signal controls the compensation module 213 to turn off, and the fourth scan signal controls the light-emitting control module 214 to turn on. In this stage, the gate of the driving transistor Mn maintains the potential of the previous light-emitting stage and generates a driving current under the control of this potential. The light-emitting control module 214 controls the supply of driving current to the light-emitting element.

[0110] In the driving method provided by this embodiment, during the data writing phase, the data writing module is controlled to write a voltage signal to the source of the driving transistor, and during the reset adjustment phase, the data writing module is controlled to write an adjustment voltage to the source of the driving transistor to adjust the bias state of the driving transistor. That is, the data writing module is multiplexed between the data writing phase and the reset adjustment phase. The flickering problem of the display screen can be improved simply by changing the driving timing of the pixel circuit, without changing the structure of the pixel circuit.

[0111] This invention also provides another driving method that can be applied to drivers. Figure 7 and Figure 10 The display panel provided in the embodiment.

[0112] correspond Figure 7 The schematic pixel circuit includes a data writing module comprising a first submodule and a second submodule. The first submodule is connected between the data signal input terminal Data and the source of the driving transistor Mn. The first submodule includes a second transistor M1b, the gate of which is connected to the second control signal terminal S2. The first terminal of the second transistor M1b is connected to the data signal input terminal Data, and the second terminal of the second transistor M1b is connected to the source of the driving transistor Mn. The second submodule is connected to the adjustment signal input terminal V. H Between the source of the driving transistor Mn and the second submodule, a third transistor M1c is included. The gate of the third transistor M1c is connected to the third control signal terminal S3, and the first terminal of the third transistor M1c is connected to the adjustment signal input terminal V. H The second terminal of the third transistor M1c is connected to the source of the driving transistor Mn. Figure 7 In the illustrated pixel circuit, the reset control signal terminal Sr provides the first scan signal, the second control signal terminal S2 provides the second scan signal, the third control signal terminal S3 provides the third scan signal, and the light emission control signal terminal E provides the fourth scan signal.

[0113] correspond Figure 10 The schematic pixel circuit includes a data writing module comprising a first submodule and a second submodule. The first submodule is connected between the data signal input terminal Data and the source of the driving transistor Mn. The first submodule includes a second transistor M1b, whose gate is connected to a second control signal terminal S2, a first terminal of which is connected to the data signal input terminal Data, and a second terminal of which is connected to the source of the driving transistor Mn. The second submodule is also connected between the data signal input terminal Data and the source of the driving transistor Mn. The second submodule includes a fourth transistor M1d, whose gate is connected to a fourth control signal terminal S4, a first terminal of which is connected to the data signal input terminal Data, and a second terminal of which is connected to the source of the driving transistor Mn. Figure 10 In the illustrated pixel circuit, the reset control signal terminal Sr provides the first scan signal, the second control signal terminal S2 provides the second scan signal, the fourth control signal terminal S4 provides the third scan signal, and the light emission control signal terminal E provides the fourth scan signal.

[0114] The driving method provided in this embodiment of the invention includes:

[0115] In data writing frame Z1, the pixel circuit sequentially executes reset phase T1, data writing phase T2, and light emission phase T3.

[0116] During the reset phase T1, the first scan signal controls the reset module 215 to turn on, the second scan signal controls the first sub-module (i.e., the second transistor M1b) to turn off, and the third scan signal controls the second sub-module (corresponding to...) to turn off. Figure 7 In this embodiment, the third transistor M1c corresponds to... Figure 10 In this embodiment, the fourth transistor M1d is turned off, the second scan signal controls the compensation module 213 to turn off, and the fourth scan signal controls the light emission control module 214 to turn off; during this stage, the gate of the driving transistor Mn is reset by the reset module 215.

[0117] During the data writing phase T2, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the first sub-module and the compensation module 213 to turn on, the third scan signal controls the second sub-module to turn off, and the fourth scan signal controls the light emission control module 214 to turn off. During this phase, the first sub-module and the compensation module are turned on simultaneously, writing the data signal to the gate of the driving transistor Mn and compensating for the offset of the threshold voltage of the driving transistor Mn.

[0118] During the light-emitting stage T3, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the first sub-module and the compensation module 213 to turn off, the third scan signal controls the second sub-module to turn off, and the fourth scan signal controls the light-emitting control module 214 to turn on. During this stage, the driving transistor Mn generates a driving current, and the light-emitting control module 214 controls the supply of driving current to the light-emitting element.

[0119] While holding frame Z2, the pixel circuit sequentially executes the reset adjustment phase T4 and the emission phase T3; wherein...

[0120] During the reset adjustment phase T4, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the first sub-module and the compensation module 213 to turn off, the third scan signal controls the second sub-module to turn on, and the fourth scan signal controls the light emission control module 214 to turn off. During this phase, the second sub-module turns on and writes an adjustment voltage to the source of the driving transistor Mn to adjust the bias state of the driving transistor Mn.

[0121] During the light-emitting stage T3, the first scan signal controls the reset module 215 to turn off, the second scan signal controls the first sub-module and the compensation module 213 to turn off, the third scan signal controls the second sub-module to turn off, and the fourth scan signal controls the light-emitting control module 214 to turn on. During this stage, the gate of the driving transistor Mn maintains the potential of the previous light-emitting stage and generates a driving current under the control of this potential. The light-emitting control module 214 controls the supply of driving current to the light-emitting element.

[0122] In the driving method provided by this embodiment, the first submodule in the control data writing module writes a voltage signal to the source of the driving transistor during the data writing phase, and the second submodule in the control data writing module writes an adjustment voltage to the source of the driving transistor during the reset adjustment phase to adjust the bias state of the driving transistor. Since the first and second submodules are controlled by different control signals, the compensation module can be controlled by the same control signal as the first submodule, allowing the compensation module and the first submodule to be turned on and off simultaneously.

[0123] When applied to a display panel, the first, second, third, and fourth scan signals are provided by different shift drive circuits. Therefore, when applying the driving method provided in this embodiment of the invention, four different shift drive circuits need to be set in the display panel. Each shift drive circuit includes multiple cascaded shift registers.

[0124] This invention also provides a display device. Figure 14 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 14 As shown, this includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 has been described in the above-described display panel embodiments and will not be repeated here. In the embodiments of the present invention, the display device can be any device with display functionality, such as a mobile phone, tablet computer, laptop computer, e-reader, television set, smart wearable product, etc.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: Pixel circuits and light-emitting elements; The pixel circuit includes a data writing module and a driving module; The data writing module is used to provide data signals and regulate voltage; The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor; wherein... The regulating voltage is used to adjust the bias state of the driving transistor; The pixel circuit further includes a light-emitting control module, one end of which is electrically connected to a first power supply terminal. The operation of the display panel includes a data write frame and a hold frame. The operation mode of the display panel includes a first mode, which includes a repeated first cycle. The first cycle includes one data write frame and at least one hold frame. Within at least one first cycle: VJ≥VP, and VJ≥VD; Wherein, the regulating voltage is VJ, the maximum value of the voltage of the data signal is VD, and the power supply voltage provided by the first power supply terminal is VP.

2. The display panel according to claim 1, characterized in that, The adjustment voltage is greater than or equal to the dark state voltage in the data signal voltage.

3. The display panel according to claim 1, characterized in that, The data writing module is connected to the source of the driving transistor; The pixel circuit further includes a compensation module, which is used to compensate the threshold voltage of the driving transistor. The compensation module is connected between the gate and the drain of the driving transistor.

4. The display panel according to claim 3, characterized in that, The data writing module includes a first transistor, whose first end is connected to the data signal input terminal, whose second end is connected to the source of the driving transistor, and whose gate is connected to the first control signal terminal. The first transistor is used to provide the data signal and the regulating voltage.

5. The display panel according to claim 3, characterized in that, The data writing module includes: The second transistor has a first terminal connected to the data signal input terminal, a second terminal connected to the source of the driving transistor, and a gate connected to the second control signal terminal. The third transistor has its first terminal connected to the adjustment signal input terminal, its second terminal connected to the source of the driving transistor, and its gate connected to the third control signal terminal. The second transistor is used to write the data signal into the source of the driving transistor; The third transistor is used to write the regulated voltage to the source of the driving transistor.

6. The display panel according to claim 3, characterized in that, The data writing module includes: The second transistor has a first terminal connected to the data signal input terminal, a second terminal connected to the source of the driving transistor, and a gate connected to the second control signal terminal. The fourth transistor has its first terminal connected to the data signal input terminal, its second terminal connected to the source of the driving transistor, and its gate connected to the fourth control signal terminal. The second transistor is used to write the data signal into the source of the driving transistor; The fourth transistor is used to write the regulated voltage to the source of the driving transistor.

7. The display panel according to claim 5 or 6, characterized in that, The compensation module includes a compensation transistor, the first end of which is connected to the drain of the driving transistor, the second end of which is connected to the gate of the driving transistor, and the gate of which is connected to the second control signal terminal.

8. The display panel according to claim 1, characterized in that, The operation of the display panel includes a data writing stage, a reset and adjustment stage, and a light emission stage. During the data writing phase, the data writing module writes data signals; During the reset adjustment phase, the data writing module writes the adjustment voltage. The light-emitting control module is used to control the light-emitting element to enter the light-emitting stage; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between a first power supply terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. During the reset adjustment phase, at least the first light-emitting control module remains off.

9. The display panel according to claim 1, characterized in that, During the data writing frame, the pixel circuit performs a data writing phase and a light emission phase. During the data writing phase, the data writing module writes data signals. During the holding frame, the pixel circuit performs a reset adjustment phase and an emission phase, during which the data writing module writes an adjustment voltage. The pixel circuit also includes a reset module for providing a reset signal to the gate of the driving transistor; The data write frame also includes a reset phase, which is located before the data write phase, during which the reset module is activated.

10. The display panel according to claim 9, characterized in that, During the hold frame, the reset module remains off.

11. The display panel according to claim 1, characterized in that, The regulating voltage is a constant voltage.

12. The display panel according to claim 1, characterized in that, During the data writing frame, the pixel circuit performs a data writing phase and a light emission phase. During the data writing phase, the data writing module writes data signals. During the holding frame, the pixel circuit performs a reset adjustment phase and an emission phase, during which the data writing module writes an adjustment voltage. During the holding frame, the adjusted voltage is a constant voltage.

13. The display panel according to claim 1, characterized in that, It also includes driver circuitry and data lines; The driving circuit is connected to the data writing module via a data line; The operation of the display panel includes a data writing stage and a reset and adjustment stage. During the data writing phase, the driving circuit provides the data signal to the data writing module through the data line; During the reset adjustment phase, the drive circuit provides the adjustment voltage to the data writing module via the data line.

14. The display panel according to claim 1, characterized in that, During the data writing frame, the pixel circuit performs a data writing phase and a light emission phase. During the data writing phase, the data writing module writes data signals. During the holding frame, the pixel circuit performs a reset adjustment phase and an emission phase, during which the data writing module writes an adjustment voltage.

15. The display panel according to claim 14, characterized in that, The operating mode of the display panel also includes a second mode, which includes repeated data writing frames; The image refresh rate of the display panel in the second mode is greater than that in the first mode.

16. The display panel according to claim 1, characterized in that, The driving transistor is a P-type transistor.

17. A driving method for a display panel, characterized in that, The display panel includes: Pixel circuits and light-emitting elements; The pixel circuit includes a data writing module and a driving module; The data writing module is used to provide data signals and regulate voltage; The driving module is used to provide driving current to the light-emitting element, and the driving module includes a driving transistor; wherein... The regulating voltage is used to adjust the bias state of the driving transistor; The pixel circuit further includes a light-emitting control module, one end of which is electrically connected to a first power supply terminal. The operation of the display panel includes a data write frame and a hold frame. The operation mode of the display panel includes a first mode, which includes a repeated first cycle. The first cycle includes one data write frame and at least one hold frame. Within at least one first cycle: VJ≥VP, and VJ≥VD; Wherein, the regulating voltage is VJ, the maximum value of the voltage of the data signal is VD, and the power supply voltage provided by the first power supply terminal is VP; The operation of the display panel includes a data writing stage and a reset and adjustment stage. The driving method includes: During the data writing phase, the data writing module writes the data signal; During the reset adjustment phase, the data writing module writes the adjustment voltage.

18. The driving method according to claim 17, characterized in that, The pixel circuit also includes a compensation module and a reset module; The compensation module is used to compensate the threshold voltage of the driving transistor; The data writing module is connected between the data signal input terminal and the source of the driving transistor; The compensation module is connected between the gate and the drain of the driving transistor. The reset module is connected between the reset voltage input terminal and the gate of the driving transistor; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power supply terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. The driving method includes: During the data write frame, the pixel circuit sequentially executes a reset phase, a data write phase, and a light emission phase; wherein... During the reset phase, the first scan signal controls the reset module to turn on, the second scan signal controls the data writing module to turn off, the third scan signal controls the compensation module to turn off, and the fourth scan signal controls the light emission control module to turn off. During the data writing phase, the first scan signal controls the reset module to turn off, the second scan signal controls the data writing module to turn on, the third scan signal controls the compensation module to turn on, and the fourth scan signal controls the light emission control module to turn off. During the light emission stage, the first scan signal controls the reset module to turn off, the second scan signal controls the data writing module to turn off, the third scan signal controls the compensation module to turn off, and the fourth scan signal controls the light emission control module to turn on. In the holding frame, the pixel circuit sequentially executes the reset adjustment phase and the light emission phase; wherein... During the reset adjustment phase, the first scan signal controls the reset module to turn off, the second scan signal controls the data writing module to turn on, the third scan signal controls the compensation module to turn off, and the fourth scan signal controls the light emission control module to turn off. During the light emission phase, the first scan signal controls the reset module to turn off, the second scan signal controls the data writing module to turn off, the third scan signal controls the compensation module to turn off, and the fourth scan signal controls the light emission control module to turn on.

19. The driving method according to claim 17, characterized in that, The pixel circuit also includes a compensation module and a reset module; The data writing module includes a first submodule and a second submodule, wherein the first submodule is connected between the data signal input terminal and the source of the driving transistor; The second submodule is connected between the adjustment signal input terminal and the source of the driving transistor, or the second submodule is connected between the data signal input terminal and the source of the driving transistor; The compensation module is used to compensate for the threshold voltage of the driving transistor. The compensation module is connected between the gate and the drain of the driving transistor. The reset module is connected between the reset voltage input terminal and the gate of the driving transistor; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module. The first light-emitting control module is connected between the first power supply terminal and the source of the driving transistor, and the second light-emitting control module is connected between the drain of the driving transistor and the light-emitting element. The driving method includes: During the data write frame, the pixel circuit sequentially executes a reset phase, a data write phase, and a light emission phase; wherein... During the reset phase, a first scan signal controls the reset module to turn on, a second scan signal controls the first sub-module to turn off, a third scan signal controls the second sub-module to turn off, the second scan signal controls the compensation module to turn off, and a fourth scan signal controls the light emission control module to turn off. During the data writing phase, the first scan signal controls the reset module to turn off, the second scan signal controls the first sub-module and the compensation module to turn on, the third scan signal controls the second sub-module to turn off, and the fourth scan signal controls the light emission control module to turn off. During the light emission stage, the first scan signal controls the reset module to turn off, the second scan signal controls the first sub-module and the compensation module to turn off, the third scan signal controls the second sub-module to turn off, and the fourth scan signal controls the light emission control module to turn on. In the holding frame, the pixel circuit sequentially executes the reset adjustment phase and the light emission phase; wherein... During the reset adjustment phase, the first scan signal controls the reset module to turn off, the second scan signal controls the first sub-module and the compensation module to turn off, the third scan signal controls the second sub-module to turn on, and the fourth scan signal controls the light emission control module to turn off. During the light emission phase, the first scan signal controls the reset module to turn off, the second scan signal controls the first sub-module and the compensation module to turn off, the third scan signal controls the second sub-module to turn off, and the fourth scan signal controls the light emission control module to turn on.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1-16.

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