Wafer level chip scale packaging method

Abstract

The application relates to the chip technical field, and discloses a wafer-level chip packaging method.The packaging method provided by the application comprises the following steps: preparing a to-be-electroplated wafer; preparing a buffer film on a first surface of the to-be-electroplated wafer; the first surface is a surface far from an electroplating seed layer of the to-be-electroplated wafer; and the to-be-electroplated wafer is clamped with an electroplating fixture, and the buffer film can be attached to the electroplating fixture; electroplating treatment is conducted on the to-be-electroplated wafer to form a wiring layer on the to-be-electroplated wafer; the buffer film is removed; ball mounting treatment is conducted on the electroplated wafer to obtain a packaged wafer; and subsequent segmentation and other treatments are conducted on the packaged wafer, so that single wafers are obtained.The packaging method can effectively improve the electroplating quality of the wafer in the electroplating process, and ensures the quality of subsequent packaging steps.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly relates to a wafer-level chip packaging method. BACKGROUND

[0002] Wafer-level packaging has the characteristics of small size and high efficiency, and becomes the preferred packaging scheme. Based on wafer-level chips, the whole is packaged, and then the chips are separated after packaging to form single chips. Although this method improves the processing efficiency of the chips, the wafer-level packaging technology is generally used for thick wafers due to its complex process and high requirement for the machine.

[0003] Generally, the wafer thickness is generally 625 microns to 750 microns, and the wafer is packaged based on the thickness, and then thinned. However, after the wafer is thinned, the thinned wafer needs to be further packaged, but due to the large warping of the thinned wafer, the machine cannot automatically work, and the thinned wafer is brittle and prone to cracking during operation. SUMMARY

[0004] The present application improves the technical problems of low packaging efficiency and low yield of wafer-level packaging of thin wafer in the prior art.

[0005] To solve the above technical problems, the present application discloses a wafer-level chip packaging method, which comprises:

[0006] Preparation of a wafer to be electroplated;

[0007] A buffer film is prepared on the first surface of the wafer to be electroplated; the first surface is the surface away from the electroplating seed layer of the wafer to be electroplated;

[0008] The wafer to be electroplated is clamped with an electroplating jig, and the buffer film can be attached to the electroplating jig;

[0009] The wafer to be electroplated is electroplated to form a wiring layer on the wafer to be electroplated;

[0010] The buffer film is removed;

[0011] The electroplated wafer is ball-mounted to obtain a packaged wafer.

[0012] Optionally, the buffer film comprises a UV film.

[0013] Optionally, the preparation of the wafer to be electroplated comprises:

[0014] Preparation of a sputtering wafer;

[0015] The first surface of the sputtering wafer is connected with a support; the radial size of the support is the same as that of the sputtering wafer;

[0016] The sputtering seed layer is processed on the sputtering-preparation wafer, and the support is removed to obtain the wafer to be plated.

[0017] Optionally, the thickness of the support ranges from 550 to 850 microns.

[0018] Optionally, the material of the support includes silicon.

[0019] Optionally, the material of the seed layer includes titanium-copper composite material.

[0020] Optionally, the sputtering-preparation wafer is prepared by the following steps:

[0021] An initial wafer is provided; the second surface opposite to the first surface of the initial wafer is provided with an electrode;

[0022] A first dielectric layer is prepared on the second surface;

[0023] A barrier layer is coated on the first dielectric layer to obtain a wafer to be exposed;

[0024] The first surface of the wafer to be exposed is adhered to the placement platform of the exposure equipment;

[0025] The wafer to be exposed is sequentially subjected to exposure, development and etching to form a first dielectric hole for exposing the electrode on the first dielectric layer to obtain a sputtering-preparation wafer.

[0026] Optionally, the thickness of the first dielectric layer ranges from 3 to 10 microns.

[0027] Optionally, the wafer after plating is subjected to ball planting to obtain a wafer after packaging, including:

[0028] A second dielectric layer is prepared on the second surface of the wafer after plating; the second dielectric layer includes a second dielectric hole; the second dielectric hole is used for exposing the connecting electrode of the wiring layer;

[0029] Sputtering seed layer and plating solder column processing are sequentially performed on the second dielectric layer; the solder column includes a first solder column and a second solder column; the first solder column is located on the second dielectric hole; the second solder column can form a uniform distribution of solder column array with the first solder column;

[0030] The solder column is subjected to reflow soldering to obtain a wafer after packaging.

[0031] Optionally, the thickness of the initial wafer ranges from 150 to 300 microns.

[0032] By adopting the technical scheme, the wafer-level chip packaging method provided by the present application has the following beneficial effects:

[0033] The packaging method provided in this application involves first preparing a wafer to be electroplated; then preparing a buffer film on a first surface of the wafer, the first surface being the surface away from the electroplating seed layer; attaching the wafer to an electroplating fixture, with the buffer film adhering to the fixture; performing electroplating on the wafer to form a wiring layer; removing the buffer film; and performing ball-mounting on the electroplated wafer to obtain a packaged wafer; subsequently, further processing such as dicing the packaged wafer yields individual wafers. This packaging method effectively reduces the leakage of electroplating solution from the first surface during the electroplating process of thin wafers due to large warpage, thus affecting the electroplating quality. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart illustrating an optional wafer-level chip packaging method according to this application.

[0036] Figure 2 This is a schematic cross-sectional view of a wafer after an optional sputtering seed layer according to this application;

[0037] Figure 3 This is a schematic diagram of an optional packaged wafer according to this application.

[0038] The following is supplementary explanation of the attached figures:

[0039] 1-Electrode; 2-Passivation layer; 3-First dielectric layer; 4-Seed layer; 5-Groove; 6-First dielectric hole; 7-Second dielectric hole; 8-Bond post; 81-First bond post; 82-Second bond post; 9-Wiring layer. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] The terms "one embodiment" or "an embodiment" as may be used herein as referring to a particular feature, structure, or characteristic, can be understood as referring to an implementation or implementations that can include the particular feature, structure, or characteristic. In this description, the terms "top," "bottom," "front," "back," and the like as can be referenced herein can be used to describe one implementation of an article or element as oriented in the drawing under discussion. Such terms are not used to denote or imply that a particular orientation of the article or element is required or is necessary for purposes of the application. Moreover, the terms "first," "second," and the like, as can be used herein do not denote any inherent degree or amount of importance, but can be used to designate the nature or manner of the acts or features being described. As used herein, the terms "first," "second," and the like can be used interchangeably to distinguish between two or more different elements or steps in a process. Thus, these terms are used herein to designate different ordinal numbers, and are not used to designate a particular order or sequence unless specifically stated otherwise. It is to be understood that the use of the terms "first," "second," and the like do not limit the scope of the application to only two such elements or steps, but rather these terms are used to distinguish between two or more elements or steps in a process. Thus, these terms are used herein to designate different ordinal numbers, and are not used to designate a particular order or sequence unless specifically stated otherwise.

[0042] For the purposes of the detailed description below, it is to be understood that the application can assume various alternative variations and step sequences, except where expressly specified to the contrary. Moreover, other than in any operating examples, or where otherwise indicated, all numbers expressing, for example, quantities of ingredients used in the specification and claims are to be understood as being modified in all instances by the term "about." Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present application. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques.

[0043] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0044] When a range of values is disclosed, the disclosure is to be construed to cover each and every sub-range, as well as the minimum and maximum values, of the range. Further, the disclosure as to a range of values should be considered to include each and every integer value within the range, unless the context clearly dictates otherwise. Additionally, the disclosure as to a range of values should be considered to include any and all sub-ranges within the range, unless the context clearly dictates otherwise. For example, a range of "1 to 10" should be considered to include any and all sub-ranges between (and including) the minimum value of 1 and the maximum value of 10; that is, all sub-ranges beginning with a minimum value of 1 or more and ending with a maximum value of 10 or less, as well as every number between 1 and 10. Exemplary sub-ranges include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, and the like.

[0045] The prior art is mostly directed to packaging of a wafer-level chip with a relatively thick thickness, and then performing a thinning process. However, in actual production, after the wafer is thinned, the wafer-level chip also needs to be re-routed and packaged to improve production efficiency and meet the preparation requirements. However, the thinned wafer, for example, with a thickness of less than 300 microns, is prone to warping, which causes the subsequent packaging process to fail or the product quality to be poor. Therefore, see Figure 1 , Figure 1 An optional wafer-level chip packaging flowchart is provided in the present application. The present application provides a wafer-level chip packaging method, which comprises the following steps:

[0046] S101: preparing a wafer to be electroplated.

[0047] In a feasible embodiment, see Figure 2 , Figure 2 An optional cross-sectional view of the wafer after sputtering a seed layer 4 is provided in the present application. Step S101 can be specifically described as: preparing a wafer before sputtering; connecting the first surface of the wafer before sputtering to a support; the radial dimension of the support is the same as that of the wafer before sputtering; performing a sputtering seed layer 4 process on the wafer before sputtering, and removing the support to obtain the wafer to be electroplated. The provision of the support not only reduces the warping of the wafer and improves the sputtering uniformity, but also ensures that the wafer can be adsorbed on the adsorption platform of the sputtering device.

[0048] In a feasible embodiment, the thickness of the support ranges from 550 to 850 microns.

[0049] In a feasible embodiment, the material of the support includes silicon.

[0050] Optionally, the resistivity of the support is 1-100 ohm-cm, and the warping of the support is less than 50 microns.

[0051] In one possible embodiment, the seed layer 4 is made of titanium-copper composite material, i.e. the first layer is made of titanium and the second layer is made of copper.

[0052] Optionally, referring to Figure 2 The seed layer 4 can form a groove 5 in the first dielectric hole 6, so that a structure connected with the wiring layer 9 can be formed in the subsequent electroplating process.

[0053] In one possible embodiment, the preparation of the wafer before sputtering specifically includes: providing an initial wafer; the second surface opposite to the first surface of the initial wafer is provided with an electrode 1; a first dielectric layer 3 is prepared on the second surface; a barrier layer is coated on the first dielectric layer 3 to obtain a wafer to be exposed; the first surface of the wafer to be exposed is bonded and connected with a placement platform of an exposure device; the wafer to be exposed is sequentially subjected to exposure, development and etching treatment to form a first dielectric hole 6 for exposing the electrode 1 on the first dielectric layer 3, thereby obtaining a wafer before sputtering. Thus, the warping of the wafer with a certain warping can be reduced, and the exposure accuracy and uniformity can be ensured.

[0054] Optionally, the first surface of the wafer to be exposed can be bonded with the placement platform by using an anti-static tape.

[0055] Optionally, as shown in Figure 2 the surface of the initial wafer is further provided with a passivation layer 2; the passivation layer 2 is provided with an opening for exposing the electrode 1, and the passivation layer 2 is used for protecting the chip circuit.

[0056] Optionally, the passivation layer 2 can be a local passivation structure as shown in Figure 2 or can be full-surface passivation, i.e. the passivation layer 22 is provided on the entire surface of the wafer.

[0057] It should be noted that the initial wafer can be ready-made or can be formed and processed according to the general chip processing technology.

[0058] In one possible embodiment, the thickness of the first dielectric layer 3 ranges from 3 to 10 microns.

[0059] The first dielectric layer 3 and the second dielectric layer below can serve as a buffer protection layer of the wafer, and have a protection function and a stress buffering function, which greatly improves the product structure reliability, protects the chip surface from stress damage, and makes the chip surface more flat, which is beneficial to improve the uniformity and bonding force of the subsequent electroplating process.

[0060] Optionally, the material of the dielectric layer includes low-temperature cured high molecular material or high-temperature cured high molecular material.

[0061] S102: preparing a buffer film on a first surface of the wafer to be plated; the first surface is a surface away from the electroplating seed layer 4 of the wafer to be plated.

[0062] In a feasible embodiment, the buffer film comprises a UV film.

[0063] Optionally, a film matching the thickness of the wafer can be selected, which can be a UV film or a non-UV film.

[0064] Optionally, the thickness of the UV film is 450-700 microns, and the overall thickness of the wafer to be plated with the attached buffer film is 700-1000 microns.

[0065] Optionally, step S102 can be specifically described as: placing the second surface of the wafer to be plated downward and attaching the buffer film on the second surface.

[0066] It should be noted that the above-mentioned vacuum platform needs to be cleaned before attaching the film to keep it clean, and a hundred-level dust-free cloth can be attached to ensure the attachment yield of the film, and then the film is repaired to completely attach the film and the wafer edge.

[0067] S103: connecting the wafer to be plated with an electroplating jig, and the buffer film can be attached to the electroplating jig.

[0068] In the embodiment, the buffer film is provided, so that the leakage of the electroplating solution from the first surface due to the large warping degree of the wafer during electroplating is effectively reduced, and the electroplating quality is affected.

[0069] S104: electroplating the wafer to be plated to form a wiring layer 9 on the wafer to be plated, referring to Figure 3 .

[0070] S105: removing the buffer film.

[0071] S106: ball mounting the wafer after electroplating to obtain a packaged wafer.

[0072] In a feasible embodiment, step S106 can be specifically described as: preparing a second dielectric layer on the second surface of the wafer after electroplating; the second dielectric layer comprises a second dielectric hole 7; the second dielectric hole 7 is used to expose a connecting electrode of the wiring layer 9; sequentially performing sputtering seed layer 4 and electroplating solder column 8 treatment on the second dielectric layer; the solder column 8 comprises a first solder column 81 and a second solder column 82; the first solder column 81 is located on the second dielectric hole 7; the second solder column 82 can form a uniformly distributed solder column 8 array with the first solder column 81; reflow soldering the solder column 8 to obtain a packaged wafer.

[0073] In a feasible embodiment, the thickness of the initial wafer ranges from 150 to 300 microns.

[0074] In the present embodiment, the first electrode 1 corresponding to the first dielectric layer 3 of the lower layer is connected with the first solder column 81 of the second dielectric hole 7 of the upper layer through the wiring layer 9, thereby forming a conduction circuit. Figure 3 As can be seen, the electrode 1 corresponding to the first dielectric layer 3 of the lower layer is connected with the first solder column 81 of the second dielectric hole 7 of the upper layer through the wiring layer 9, thereby forming a conduction circuit.

[0075] In the process of electroplating the above-mentioned solder column 8, such uniform array of solder column 8 can effectively improve the uniformity of electroplating current, thereby improving the uniformity of electroplating, and the formed solder column 8 has good uniformity, such as height and width, etc. The formed second solder column 82 can effectively balance the distribution of the first solder column 81, ensure the uniformity of stress during subsequent flip-chip welding of the chip, and improve the welding quality.

[0076] The above only describes optional embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A wafer-level chip packaging method, characterized in that, The application relates to a method for manufacturing a wafer for packaging a semiconductor device. The method comprises the following steps: preparing a sputtering wafer; connecting a first surface of the sputtering wafer with a support; the radial size of the support is the same as that of the sputtering wafer; the resistivity of the support is 1 ohm*cm to 100 ohm*cm, and the warping of the support is less than 50 microns; performing sputtering seed layer treatment on the sputtering wafer and removing the support to obtain a wafer to be electroplated; preparing a buffer film on a first surface of the wafer to be electroplated; the first surface is a surface away from an electroplating seed layer of the wafer to be electroplated; the buffer film comprises a UV film; the thickness of the buffer film is 450 microns to 700 microns; the thickness of the wafer to be electroplated and the thickness of the buffer film are 700 microns to 1000 microns; connecting the wafer to be electroplated with an electroplating fixture, and the buffer film can be attached to the electroplating fixture; performing electroplating treatment on the wafer to be electroplated to form a wiring layer (9) on the wafer to be electroplated; removing the buffer film; 2. The packaging method according to claim 1, characterized in that, performing ball planting treatment on the wafer after electroplating to obtain a wafer after packaging.

3. The packaging method of claim 1, wherein, The thickness of the support ranges from 550 microns to 850 microns.

4. The packaging method of claim 1, wherein, The material of the support comprises silicon.

5. The packaging method of claim 1, wherein, The material of the seed layer (4) comprises titanium-copper composite material. The method for preparing the sputtering wafer comprises the following steps: providing an initial wafer; an electrode (1) is arranged on a second surface of the initial wafer, which is opposite to the first surface; preparing a first dielectric layer (3) on the second surface; coating a barrier layer on the first dielectric layer (3) to obtain a wafer to be exposed; adhesively connecting a first surface of the wafer to be exposed with a placement platform of an exposure device; 6. The packaging method according to claim 5, wherein, sequentially performing exposure, development and etching treatment on the wafer to be exposed to form a first dielectric hole (6) for exposing the electrode (1) on the first dielectric layer (3), thereby obtaining a sputtering wafer.

7. The packaging method according to claim 5, wherein, The thickness of the first dielectric layer (3) ranges from 3 microns to 10 microns. The method for performing ball planting treatment on the wafer after electroplating to obtain a wafer after packaging comprises the following steps: preparing a second dielectric layer on a second surface of the wafer after electroplating; the second dielectric layer comprises a second dielectric hole (7); the second dielectric hole (7) is used for exposing a connecting electrode (1) of the wiring layer (9); sequentially performing sputtering seed layer (4) and electroplating solder column (8) treatment on the second dielectric layer; the solder column (8) comprises a first solder column (81) and a second solder column (82); the first solder column (81) is located on the second dielectric hole (7); the second solder column (82) can form a uniformly distributed solder column (8) array with the first solder column (81); 8. The packaging method according to claim 5, wherein, performing reflow soldering on the solder column (8) to obtain a wafer after packaging. The thickness of the initial wafer ranges from 150 microns to 300 microns.

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