Sensing device and manufacturing method thereof

Abstract

The present invention provides a sensing device and a method for manufacturing the same. The sensing device includes a substrate, a switching element, a sensing element, and a common electrode. The switching element is located on the substrate and includes a source electrode. The sensing element is located on one side of the switching element and includes a lower electrode, a photoelectric conversion layer, and an upper electrode. The lower electrode is electrically connected to the source electrode. The photoelectric conversion layer is located on the lower electrode. The upper electrode is located on the photoelectric conversion layer. The common electrode is electrically connected to the upper electrode and is formed from the same film layer as the source electrode. A method for manufacturing the sensing device is also provided.

Description

Technical Field

[0001] The present invention relates to a sensing device and a manufacturing method thereof. Background Art

[0002] Due to their outstanding performance, optical sensors have been widely used in security inspections, industrial testing, and medical diagnosis. For example, in medical diagnosis, X-ray sensors can be used to capture images of the human chest, blood vessels, teeth, and other areas. Generally speaking, these sensors mainly consist of thin-film transistors (TFTs) and PIN diodes. PIN diodes convert light energy into electrical signals, while TFTs are used to read the electrical signals measured by the PIN diodes.

[0003] Traditionally, the manufacturing process for these sensors involves fabricating thin-film transistors (TFTs) followed by PIN diodes. This separate fabrication of TFTs and PIN diodes results in numerous photomasks, complex process steps, and a lengthy production process. Therefore, integrating the TFT and PIN diode manufacturing processes is currently a challenging R&D challenge. Summary of the Invention

[0004] One of the objectives of the present invention is to provide a sensing device having a structure integrating a switch element and a sensing element.

[0005] Another object of the present invention is to provide a sensing device with good reliability.

[0006] The present invention provides a manufacturing method of a sensing device, which can integrate the manufacturing processes of a switch element and a sensing element, simplify the process steps of the sensing device, and provide a sensing device with good reliability.

[0007] One embodiment of the present invention provides a sensing device, comprising: a substrate; a switching element, located on the substrate and including a source; a sensing element, located on one side of the switching element and including: a lower electrode, electrically connected to the source; a photoelectric conversion layer, located on the lower electrode; and an upper electrode, located on the photoelectric conversion layer; and a common electrode, electrically connected to the upper electrode and belonging to the same film layer as the source.

[0008] One embodiment of the present invention provides a sensing device, comprising: a substrate; a switching element, located on the substrate and comprising: a semiconductor layer; and a gate, surrounding the semiconductor layer; and a sensing element, located on the substrate and comprising: a lower electrode; an upper electrode, overlapping the lower electrode; and a photoelectric conversion layer, located between the upper electrode and the lower electrode.

[0009] One embodiment of the present invention provides a method for manufacturing a sensing device, comprising: forming a semiconductor layer on a substrate; forming a first insulating layer on the semiconductor layer; forming a blanket conductive layer on the first insulating layer and the substrate; forming a blanket semiconductor stack on the conductive layer; forming a blanket transparent electrode layer on the semiconductor stack; patterning the transparent electrode layer to form a top electrode; patterning the semiconductor stack to form a photoelectric conversion layer; and patterning the conductive layer to form a bottom electrode and a top gate.

[0010] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1A to 1G 1 is a partial cross-sectional schematic diagram and a partial top view schematic diagram of the steps of a manufacturing method of a sensing device according to an embodiment of the present invention, wherein: Figure 1G FIG. 1 is a partial cross-sectional diagram of a sensing device according to an embodiment of the present invention.

[0012] Figure 2A FIG. 1 is a partial top view of a sensing device according to an embodiment of the present invention.

[0013] Figure 2B It is along Figure 2A Schematic cross-sectional view taken along section line AA'.

[0014] Figure 2C It is along Figure 2A Schematic cross-sectional view taken along section line BB'.

[0015] The reference numerals are as follows:

[0016] 10,20: Sensing device

[0017] 110:Substrate

[0018] 111: Surface

[0019] 120,121,131,170: Insulation layer

[0020] 140: Conductor layer

[0021] 150:Semiconductor stack

[0022] 160: transparent electrode layer

[0023] 180,280:Switching element

[0024] 190: Sensing element

[0025] A-A', B-B': hatching line

[0026] B1, B2, T1, T2: End

[0027] BE: Bottom electrode

[0028] BG: bottom gate

[0029] C1: drain region

[0030] C2: Source region

[0031] Cc: channel area

[0032] CH: semiconductor layer

[0033] CM: Common Electrode

[0034] DE: drain

[0035] DL: data line

[0036] Dx, Dy, Dz: direction

[0037] GE: Gate

[0038] Lb, Lc, Lt: length

[0039] PN: Photoelectric conversion layer

[0040] S1, S2, S3, S4: Spacing

[0041] S5: Minimum spacing

[0042] SE: Source

[0043] SL: Scan Line

[0044] TE: Upper electrode

[0045] TG: Top Gate

[0046] V1, V2, V3, V4: through hole

[0047] V11, V21, V31, V41: through hole

[0048] W21, W22, W31, W32: side walls

[0049] Wg, Wc: width

[0050] Wp, Wt: size DETAILED DESCRIPTION

[0051] In the accompanying drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. is magnified. Throughout the specification, the same reference numerals represent the same elements. It should be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to another element, or an intermediate element can also exist. On the contrary, when an element is referred to as being "directly on" or "directly connected to" another element, there is no intermediate element. As used herein, "connection" can refer to physical and / or electrical connection. Furthermore, "electrical connection" or "coupling" can be the presence of other elements between two elements.

[0052] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, a first "element," "component," "region," "layer," or "portion" discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0053] The terms used herein are for the purpose of describing specific embodiments only and are not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms, including "at least one" or to represent "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. It should also be understood that when used in this specification, the terms "comprising" and / or "including" specify the presence of the features, regions, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, wholes, steps, operations, elements, parts and / or combinations thereof.

[0054] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element, as shown in the figures. It should be understood that relative terms are intended to include different orientations of the device in addition to the orientation shown in the figures. For example, if the device in one figure is turned over, the element described as being on the "lower" side of the other elements will be oriented on the "upper" side of the other elements. Thus, the exemplary term "lower" can include both "lower" and "upper" orientations, depending on the particular orientation of the figure. Similarly, if the device in one figure is turned over, the element described as being "lower" or "below" the other elements will be oriented as being "above" the other elements. Thus, the exemplary terms "lower" or "below" can include both "lower" and "upper" orientations.

[0055] As used herein, "about," "approximately," or "substantially" includes the stated value and an average value within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the particular amount of error associated with the measurement (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5%. Furthermore, as used herein, "about," "approximately," or "substantially" can be used to select a more acceptable range of deviations or standard deviations depending on the optical property, etching property, or other property, rather than using a single standard deviation for all properties.

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present invention, and will not be interpreted as idealized or overly formal unless explicitly defined as such herein.

[0057] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments. Thus, variations in the shapes of the illustrations as a result of, for example, manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions as shown herein, but rather include deviations in shape that result, for example, from manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. Furthermore, sharp angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions and are not intended to limit the scope of the claims.

[0058] Figures 1A to 1G The following is a partial cross-sectional diagram and a partial top view diagram of the steps of the manufacturing method of the sensing device 10 according to one embodiment of the present invention. Figures 1A to 1G A method for manufacturing the sensing device 10 will be described.

[0059] Please refer to Figure 1A In some embodiments, the bottom gate BG and the scan line SL can be formed on the substrate 110 first. The substrate 110 can be a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon substrate, but is not limited thereto. In other embodiments, the substrate 110 can be a flexible substrate, such as a polymer substrate or a plastic substrate. In this context, the normal direction of the substrate 110 can be a direction Dz perpendicular to the surface 111 of the substrate 110, and the direction Dz can be perpendicular to the direction Dx and the direction Dy.

[0060] For example, the method for forming the bottom gate BG and the scan line SL may include the following steps. First, a conductive layer (not shown) is formed on the substrate 110. Subsequently, a patterned photoresist (not shown) is formed on the conductive layer using a photolithography process. Next, the conductive layer is etched using the patterned photoresist as a mask to form the bottom gate BG and the scan line SL. Thereafter, the patterned photoresist is removed.

[0061] For example, the material of the bottom gate BG and the scan line SL may include a metal such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but is not limited thereto. The bottom gate BG and the scan line SL may also be made of other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials having conductive properties.

[0062] Referring to FIG. 1B(a), in this embodiment, a blanket insulating layer 120 may be formed on the substrate 110. The insulating layer 120 may be formed using chemical vapor deposition or other suitable methods to block impurities in the substrate 110. In some embodiments, the insulating layer 120 may cover the bottom gate BG and the scan line SL to prevent unnecessary electrical connection. The insulating layer 120 may be made of a transparent insulating material such as silicon oxide, silicon nitride, silicon oxynitride, an organic polymer, or a stack of these materials, but the present invention is not limited thereto.

[0063] Next, referring to FIG. 1B(a) and FIG. 1B(b), a semiconductor layer CH is formed on the substrate 110 and the insulating layer 120. In some embodiments, the semiconductor layer CH may partially overlap the bottom gate BG, and the orthographic projections of the semiconductor layer CH and the bottom gate BG on the substrate 110 may form a cross pattern. For example, the length Lc of the semiconductor layer CH in the direction Dx may be greater than the width Wg of the bottom gate BG in the direction Dx, and the width Wc of the semiconductor layer CH in the direction Dy may be less than the length Lb of the bottom gate BG in the direction Dy. The direction Dx is substantially perpendicular to the direction Dy, such that the orthographic projections of the two end portions B1 and B2 of the bottom gate BG in the direction Dy on the substrate 110 are outside the orthographic projection of the semiconductor layer CH on the substrate 110.

[0064] The method for forming the semiconductor layer CH may include the following steps: first, forming a blanket semiconductor material layer (not shown) on the insulating layer 120; then, using a photolithography process, forming a patterned photoresist (not shown) on the semiconductor material layer; subsequently, using the patterned photoresist as a mask to perform an etching process on the semiconductor material layer to form the semiconductor layer CH; thereafter, removing the patterned photoresist.

[0065] The material of the semiconductor layer CH may include a metal oxide semiconductor material, such as: at least one of indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO, IZO), indium gallium oxide (InGaO, IGO), indium tin oxide (InSnO, ITO), indium gallium zinc tin oxide (InGaZnSnO, IGZTO), gallium zinc tin oxide (GaZnSnO, GZTO), gallium zinc oxide (GaZnO, GZO), zinc tin oxide (ZnSnO, ZTO) and indium tin zinc oxide (InSnZnO, ITZO), but is not limited thereto.

[0066] Referring to FIG. 1C(a), insulating layers 121 and 131 are then formed on the substrate 110, wherein the insulating layer 121 may cover the bottom gate BG and the scan line SL, the insulating layer 131 may cover the semiconductor layer CH, and the insulating layer 131 may overlap the insulating layer 121 on the scan line SL. The method for forming the insulating layers 121 and 131 may include the following steps. First, a blanket insulating layer (not shown) is formed on the insulating layer 120 and the semiconductor layer CH. Subsequently, a patterned photoresist (not shown) is formed on the blanket insulating layer using a photolithography process. Next, the patterned photoresist is used as a mask to perform an etching process on the blanket insulating layer and the insulating layer 120 to form the insulating layers 121 and 131. Thereafter, the patterned photoresist is removed. The blanket insulating layer may be formed using chemical vapor deposition or other suitable methods, and the material of the blanket insulating layer may include a transparent insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, an organic polymer, or a stack of the above materials, but the present invention is not limited thereto. In some embodiments, the insulating layers 121 and 131 may be formed in the same etching process, but are not limited thereto.

[0067] 1C(b), in some embodiments, the orthographic projections of the two end portions B1 and B2 of the bottom gate BG in the direction Dy on the substrate 110 may be outside the orthographic projections of the insulating layers 121 and 131 on the substrate 110. In other words, the insulating layers 121 and 131 may not overlap and expose the two end portions B1 and B2 of the bottom gate BG.

[0068] Please refer to Figure 1DNext, a blanket conductive layer 140 is formed on the insulating layer 131 and the substrate 110, a blanket semiconductor stack 150 is formed on the conductive layer 140, and a blanket transparent electrode layer 160 is formed on the semiconductor stack 150. The conductive layer 140, the semiconductor stack 150, and the transparent electrode layer 160 can be formed using chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0069] For example, the material of the conductive layer 140 may include a metal such as chromium (Cr), gold (Au), silver (Ag), copper (Cu), tin (Sn), lead (Pb), hafnium (Hf), tungsten (W), molybdenum (Mo), neodymium (Nd), titanium (Ti), tantalum (Ta), aluminum (Al), zinc (Zn), or alloys of any combination of the above metals, or stacks of the above metals and / or alloys, but is not limited thereto. The conductive layer 140 may also include other conductive materials, such as metal nitrides, metal oxides, metal oxynitrides, stacks of metals and other conductive materials, or other materials having conductive properties.

[0070] In some embodiments, the semiconductor stack 150 may include an N-type semiconductor material layer, an intrinsic semiconductor material layer, and a P-type semiconductor material layer sequentially formed on the conductive layer 140. For example, the intrinsic semiconductor material layer is intrinsic amorphous silicon deposited by a plasma-enhanced chemical vapor deposition (PECVD) process using silane (SiH4) and hydrogen (H2) as reactant gases. The N-type semiconductor material layer is, for example, phosphorus (P)-doped amorphous silicon formed by using phosphine (PH3), hydrogen (H2), and silane (SiH4) as reactant gases. The P-type semiconductor material layer is, for example, boron (B)-doped amorphous silicon formed by using trimethyl borate, hydrogen (H2), and silane (SiH4) as reactant gases, but the present invention is not limited thereto.

[0071] The material of the transparent electrode layer 160 may include indium tin oxide, indium zinc oxide, aluminum zinc oxide (AlZO), aluminum indium oxide (AlInO), indium oxide (InO), gallium oxide (GaO), carbon nanotubes, silver nanoparticles, metals or alloys with a thickness of less than 60 nanometers (nm), organic transparent conductive materials, or other suitable transparent conductive materials.

[0072] Please refer to Figure 1E, then, the transparent electrode layer 160 is patterned to form an upper electrode TE on the semiconductor stack 150. Specifically, patterning the transparent electrode layer 160 may include the following steps. First, a patterned photoresist (not shown) is formed on the transparent electrode layer 160 using a photolithography process. Next, the transparent electrode layer 160 is wet-etched using the patterned photoresist as a mask to form the upper electrode TE. The wet etching process uses an etchant such as, but not limited to, oxalic acid or aluminic acid. Thereafter, the patterned photoresist is removed.

[0073] Next, the semiconductor stack 150 is patterned to form the photoelectric conversion layer PN. For example, patterning the semiconductor stack 150 may include the following steps. First, a patterned photoresist (not shown) is formed on the upper electrode TE and the semiconductor stack 150 using a photolithography process. Next, the semiconductor stack 150 is dry-etched using the patterned photoresist as a mask to form the photoelectric conversion layer PN. The etching gas used in the dry etching process includes, but is not limited to, sulfur hexafluoride (SF6) and chlorine (Cl2). Thereafter, the patterned photoresist is removed.

[0074] In some embodiments, the patterned transparent electrode layer 160 and the patterned semiconductor stack 150 can use the same photomask. Because the patterned transparent electrode layer 160 is etched using a wet etching process, the etching solution also removes the portion of the transparent electrode layer 160 below the edge of the patterned photoresist during the wet etching process, resulting in the size Wt of the top electrode TE formed after the wet etching process being smaller than the size of the patterned photoresist. In addition, because the patterned semiconductor stack 150 is etched using a dry etching process, the size Wp of the photoelectric conversion layer PN formed after the dry etching process is similar to or equal to the size of the patterned photoresist, resulting in the size Wt of the top electrode TE being smaller than the size Wp of the photoelectric conversion layer PN.

[0075] It is worth noting that during the process of forming and patterning the semiconductor stack 150, the semiconductor layer CH is completely covered under the blanket conductive layer 140. In this way, the blanket conductive layer 140 can effectively block the hydrogen ions (H+) in the reaction gas and the semiconductor layer CH, thereby preventing the hydrogen ions from entering the semiconductor layer CH and affecting the properties of the semiconductor layer CH, thereby avoiding affecting the reliability of the sensing device 10.

[0076] Referring to Figure 1F(a), the conductive layer 140 is then patterned to form the bottom electrode BE and the top gate TG. Patterning the conductive layer 140 may include the following steps. First, a patterned photoresist (not shown) is formed on the conductive layer 140 using a photolithography process. Next, the conductive layer 140 is etched using the patterned photoresist as a mask to form the bottom electrode BE and the top gate TG. In other words, the bottom electrode BE and the top gate TG belong to the same film layer. The patterned photoresist is then removed.

[0077] Referring to FIG. 1F(b), in some embodiments, the top gate TG may further extend downward along the two opposing sidewalls W31 and W32 of the insulating layer 131 and the two opposing sidewalls W21 and W22 of the insulating layer 121 to the two end portions B1 and B2 of the bottom gate BG, such that the two end portions T1 and T2 of the top gate TG may be physically connected to the two end portions B1 and B2 of the bottom gate BG, respectively, to form a ring-shaped gate GE. The gate GE may surround the semiconductor layer CH, and the central axis of the gate GE may extend along the extension direction of the length Lc of the semiconductor layer CH (i.e., direction Dx). In some embodiments, the central axis of the gate GE may fall within the semiconductor layer CH. In certain embodiments, the central axis of the gate GE may overlap the central axis of the semiconductor layer CH in direction Dx.

[0078] In some embodiments, after forming the top gate TG, a doping process may be performed. The doping process may use the top gate TG as a mask to dope the semiconductor layer CH. After the doping process, the region of the semiconductor layer CH that overlaps the top gate TG may become the channel region Cc, and the region of the semiconductor layer CH that does not overlap the top gate TG may become the drain region C1 and the source region C2, and the drain region C1 and the source region C2 may have a lower resistance than the channel region Cc. For example, the doping process may inject hydrogen elements into the drain region C1 and the source region C2 of the semiconductor layer CH, thereby increasing the carrier mobility of the drain region C1 and the source region C2 of the semiconductor layer CH. In some embodiments, the doping process may be a hydrogen plasma treatment. In some embodiments, the drain region C1 and the source region C2 of the semiconductor layer CH may form ohmic contacts with the drain and source regions formed subsequently, respectively.

[0079] Please refer to Figure 1G, then, an insulating layer 170 is formed on the substrate 110. The method for forming the insulating layer 170 may include the following steps. First, a dielectric material layer (not shown) is formed on the substrate 110 using chemical vapor deposition or other suitable methods. Then, a patterned photoresist (not shown) is formed on the dielectric material layer using a photolithography process. Subsequently, the patterned photoresist is used as a mask to perform an etching process on the dielectric material layer to form an insulating layer 170 having through holes V1, V2, V3, and V4. Thereafter, the patterned photoresist is removed. In this embodiment, the through holes V1 and V2 can further penetrate the insulating layer 131 to expose the drain region C1 and the source region C2 of the semiconductor layer CH, respectively, and the through hole V3 can expose the lower electrode BE, and the through hole V4 can expose the upper electrode TE.

[0080] Next, a drain electrode DE, a source electrode SE, a common electrode CM, and a data line DL are formed on the insulating layer 170. The drain electrode DE is electrically connected to the drain region C1 of the semiconductor layer CH via a via V1. The source electrode SE is electrically connected to the source region C2 of the semiconductor layer CH via a via V2. The source electrode SE is also electrically connected to the bottom electrode BE via a via V3. The common electrode CM is located on the top electrode TE and is electrically connected to the top electrode TE via a via V4. Since the common electrode CM, the drain electrode DE, the source electrode SE, and the data line DL can be formed in the same process, the number of process photomasks can be reduced, thereby simplifying the process steps.

[0081] Figure 1G Figure 1 is a partial cross-sectional diagram of a sensing device 10 according to an embodiment of the present invention. In this embodiment, sensing device 10 may include a substrate 110, a switching element 180, a sensing element 190, and a common electrode CM. The switching element 180, sensing element 190, and common electrode CM are all disposed on substrate 110. Sensing element 190, for example, is a PIN diode, which converts light energy into an electronic signal. Switching element 180, for example, is a thin-film transistor, which reads the signal measured by sensing element 190.

[0082] The switch element 180 includes at least a source electrode SE. For example, in this embodiment, the switch element 180 may include a semiconductor layer CH, a source electrode SE, a drain electrode DE, and a top gate electrode TG. The insulating layer 121 is located between the semiconductor layer CH and the substrate 110, the insulating layer 131 is located between the semiconductor layer CH and the top gate electrode TG, the insulating layer 170 is located between the source electrode SE and the drain electrode DE and the top gate electrode TG, and the insulating layers 131 and 170 are located between the source electrode SE and the drain electrode DE and the semiconductor layer CH. The drain electrode DE is electrically connected to the drain region C1 of the semiconductor layer CH, and the source electrode SE is electrically connected to the source region C2 of the semiconductor layer CH. Therefore, the switch element 180 may be a top-gate thin film transistor.

[0083] In some embodiments, the switching element 180 may include a semiconductor layer CH, a source electrode SE, a drain electrode DE, a top gate electrode TG, and a bottom gate electrode BG. The semiconductor layer CH is located between the bottom gate electrode BG and the top gate electrode TG. The insulating layer 121 is located between the bottom gate electrode BG and the semiconductor layer CH. The insulating layer 131 is located between the semiconductor layer CH and the top gate electrode TG. The insulating layer 170 is located between the source electrode SE and the drain electrode DE and the top gate electrode TG. The insulating layers 131 and 170 are located between the source electrode SE and the drain electrode DE and the semiconductor layer CH. The semiconductor layer CH is located between the bottom gate electrode BG and the top gate electrode TG. The drain electrode DE is electrically connected to the drain region C1 of the semiconductor layer CH, and the source electrode SE is electrically connected to the source region C2 of the semiconductor layer CH. Therefore, the switching element 180 may be a dual-gate thin film transistor.

[0084] In some embodiments, the switch element 180 may include a semiconductor layer CH, a source electrode SE, a drain electrode DE, and a bottom gate electrode BG. The insulating layer 121 is located between the bottom gate electrode BG and the semiconductor layer CH, and the insulating layers 131 and 170 are located between the source electrode SE and the drain electrode DE and the semiconductor layer CH. The drain electrode DE is electrically connected to the drain region C1 of the semiconductor layer CH, and the source electrode SE is electrically connected to the source region C2 of the semiconductor layer CH. Therefore, the switch element 180 may be a bottom-gate thin-film transistor.

[0085] In this embodiment, the sensing element 190 can be located on one side of the switching element 180 and can include an upper electrode TE, a lower electrode BE, and a photoelectric conversion layer PN. The upper electrode TE overlaps the lower electrode BE, the upper electrode TE and the lower electrode BE are electrically independent of each other, and the photoelectric conversion layer PN is located between the upper electrode TE and the lower electrode BE. The lower electrode BE is electrically connected to the source electrode SE, and the lower electrode BE and the top gate TG are formed from the same film layer. The upper electrode TE is electrically connected to the common electrode CM, and the common electrode CM and the source electrode SE are formed from the same film layer. In this way, the sensing device 10 can have a structure that integrates the switching element 180 and the sensing element 190.

[0086] In some embodiments, the photoelectric conversion layer PN is disposed on the bottom electrode BE, and the photoelectric conversion layer PN may completely overlap the bottom electrode BE. In other words, the orthographic projection of the photoelectric conversion layer PN on the substrate 110 may completely fall within the orthographic projection of the bottom electrode BE on the substrate 110. In some embodiments, the spacing S1 between the sidewalls of the photoelectric conversion layer PN and the sidewalls of the bottom electrode BE may be 2 μm to 5 μm, for example, approximately 3 μm or approximately 4 μm. In some embodiments, the top electrode TE may completely overlap the photoelectric conversion layer PN. In other words, the orthographic projection of the top electrode TE on the substrate 110 may completely fall within the orthographic projection of the photoelectric conversion layer PN on the substrate 110. In certain embodiments, the spacing S2 between the sidewalls of the top electrode TE and the sidewalls of the photoelectric conversion layer PN may be 0.5 μm to 3 μm, for example, approximately 1 μm or approximately 2 μm.

[0087] In some embodiments, the sensing device 10 may further include a scan line SL, which may be electrically connected to the bottom gate BG, and the scan line SL may belong to the same film layer as the bottom gate BG. In addition, the sensing device 10 may further include a data line DL, which may be electrically connected to the drain DE, and the data line DL may belong to the same film layer as the source SE and the drain DE. In this way, there are at least insulating layers 121, 131, and 170 between the scan line SL and the data line DL, thereby increasing the spacing between the scan line SL and the data line DL at the intersection, thereby reducing the parasitic capacitance of the scan line SL and the data line DL, and thus improving the problem of electrostatic discharge (ESD). In some embodiments, in the normal direction Dz of the substrate 110, the spacing S3 between the scan line SL and the data line DL is Preferably For example, about or However, the present invention is not limited thereto.

[0088] Below, use Figures 2A to 2C Continue to describe other embodiments of the present invention, and continue to use Figures 1A to 1G The component numbers and related contents of the embodiments are the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the above embodiments and will not be repeated here.

[0089] Figure 2A FIG. 2 is a partial top view of a sensing device 20 according to an embodiment of the present invention. Figure 2B It is along Figure 2A Schematic cross-sectional view taken along section line AA'. Figure 2C It is along Figure 2A In order to make the expression of the accompanying drawings more concise, Figure 2A The substrate 110 and the insulating layers 121 , 131 , and 170 are omitted.

[0090] In this embodiment, the sensing device 20 may include a substrate 110, a switching element 280, a sensing element 190, and a common electrode CM. The switching element 280, the sensing element 190, and the common electrode CM are all disposed on the substrate 110. The sensing element 190 includes an upper electrode TE, a lower electrode BE, and a photoelectric conversion layer PN. The upper electrode TE overlaps the lower electrode BE, and the photoelectric conversion layer PN is located between the upper electrode TE and the lower electrode BE. The lower electrode BE can be electrically connected to the source electrode SE of the switching element 280 via, for example, a via V31. The common electrode CM is located on the upper electrode TE and is electrically connected to the common electrode CM via, for example, a via V41.

[0091] Figures 2A to 2C The sensing device 20 shown is similar to the Figure 1G The main difference between the sensing device 10 shown is that the switch element 280 of the sensing device 20 at least includes a semiconductor layer CH and a gate GE, and the gate GE surrounds the semiconductor layer CH.

[0092] For example, in this embodiment, the switching element 280 may include a semiconductor layer CH, a source electrode SE, a drain electrode DE, and a gate electrode GE. The gate electrode GE may include a top gate electrode TG and a bottom gate electrode BG. Insulating layers 121 and 131 encapsulate the semiconductor layer CH, with the insulating layer 121 located between the bottom gate electrode BG and the semiconductor layer CH, and the insulating layer 131 located between the semiconductor layer CH and the top gate electrode TG. An insulating layer 170 is located between the source electrode SE and the drain electrode DE and the top gate electrode TG, and the insulating layers 131 and 170 are located between the source electrode SE and the semiconductor layer CH, and between the drain electrode DE and the semiconductor layer CH. The region of the semiconductor layer CH that overlaps the top gate electrode TG is the channel region Cc, and the region of the semiconductor layer CH that does not overlap the top gate electrode TG is the drain region C1 and the source region C2. The channel region Cc connects the drain region C1 and the source region C2, and the drain region C1 and the source region C2 may have a lower resistance than the channel region Cc. The drain electrode DE may be electrically connected to the drain region C1 through a via V11 , and the source electrode SE may be electrically connected to the source region C2 through a via V21 .

[0093] Specifically, the semiconductor layer CH may have a length Lc along direction Dx and a width Wc along direction Dy, with direction Dx being substantially perpendicular to direction Dy. A top gate TG is located on the insulating layer 131. The length Lt of the top gate TG in direction Dy and the length Lb of the bottom gate BG in direction Dy are both greater than the width Wc of the semiconductor layer CH, and the length Lb of the bottom gate BG is greater than the length Lt of the top gate TG. Therefore, the top gate TG may extend along direction Dy across both sides of the semiconductor layer CH. The top gate TG may also extend downward along the sidewalls of the insulating layers 121 and 131 to the bottom gate BG, such that the top gate TG is physically connected to the bottom gate BG to form a ring-shaped gate GE. The top gate TG and the bottom gate BG surround the semiconductor layer CH. In this way, the gate GE can help prevent hydrogen ions in the reactant gas from entering the semiconductor layer CH during the formation of the photoelectric conversion layer PN, thereby ensuring good reliability of the sensing device 20. Furthermore, the ring-shaped gate GE can also enhance the carrier mobility of the semiconductor layer CH, for example, by doubling the carrier mobility of the semiconductor layer CH. Thus, the sensing device 20 can provide a higher frame rate, for example, a high-frequency dynamic sensing image higher than 7 Hz.

[0094] In some embodiments, in the direction Dy, a spacing S4 between the sidewalls of the bottom gate BG and the top gate TG may be 0 to 3 μm, for example, about 1 μm or about 2 μm. In some embodiments, the central axis of the ring gate GE may be located in the semiconductor layer CH.

[0095] In some embodiments, the top gate TG and the bottom gate BG have a width Wg in the direction Dx, and the width Wg may be 2 μm to 10 μm, for example, 4 μm, 6 μm, or 8 μm. In some embodiments, the minimum spacing S5 between the orthographic projection of the top gate TG on the substrate 110 and the orthographic projection of the source SE on the substrate 110 may be 0 to 5 μm, preferably 1 μm to 3 μm, for example, approximately 1.5 μm, 2 μm, or 2.5 μm.

[0096] In summary, the manufacturing method of the sensing device of the present invention forms the common electrode and the source electrode with the same film layer, and forms the lower electrode and the top gate with the same film layer, thereby integrating the manufacturing process of the switching element and the sensing element, so that the sensing device has a structure that integrates the switching element and the sensing element, and can reduce the number of process photomasks and simplify the process steps. Furthermore, the manufacturing method of the sensing device of the present invention uses a blanket conductor layer to block hydrogen ions, which can effectively prevent hydrogen ions from entering the semiconductor layer, so as not to affect the reliability of the sensing device. In addition, the sensing device of the present invention has reduced parasitic capacitance of the scan line and the data line, and thus can also improve ESD. In addition, the sensing device of the present invention also uses a ring gate to prevent hydrogen ions from entering the semiconductor layer, so that the sensing device can have good reliability.

[0097] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Those skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A sensing device comprising: substrate; a switching element, located on the substrate and comprising a source electrode, a drain electrode and a bottom gate electrode; A sensing element is located on one side of the switching element and includes: a lower electrode electrically connected to the source electrode; a photoelectric conversion layer, located on the lower electrode; and an upper electrode, located on the photoelectric conversion layer; and a common electrode electrically connected to the upper electrode and belonging to the same film layer as the source electrode; a scan line electrically connected to the bottom gate and belonging to the same film layer as the bottom gate; a data line electrically connected to the drain electrode and belonging to the same film layer as the source electrode and the drain electrode; The distance between the sidewall of the upper electrode and the sidewall of the photoelectric conversion layer is 0.5 μm to 3 μm; There is an insulating layer between the scan line and the data line; The switching element further includes a semiconductor layer and a top gate, the insulating layer is located between the source and drain and the semiconductor layer, the semiconductor layer is located between the bottom gate and the top gate, and the drain is electrically connected to the drain region of the semiconductor layer, and the source is electrically connected to the source region of the semiconductor layer. 2 . The sensing device as claimed in claim 1 , wherein the top gate and the bottom electrode belong to the same film layer. 3 . The sensing device as claimed in claim 1 , wherein the bottom gate and the top gate surround the semiconductor layer.

4. The sensing device according to claim 1, wherein the spacing between the scan line and the data line in the normal direction of the substrate is 5 . The sensing device as claimed in claim 1 , wherein the photoelectric conversion layer completely overlaps the lower electrode, and the upper electrode completely overlaps the photoelectric conversion layer; and a distance between a sidewall of the photoelectric conversion layer and a sidewall of the lower electrode is 2 μm to 5 μm.

6. A sensing device comprising: substrate; A switching element is located on the substrate and includes: semiconductor layer; a gate surrounding the semiconductor layer; the gate including a bottom gate, and source and drain, and A sensing element is located on the substrate and includes: lower electrode; an upper electrode overlapping the lower electrode; and a photoelectric conversion layer, located between the upper electrode and the lower electrode; a scan line electrically connected to the bottom gate and belonging to the same film layer as the bottom gate; a data line electrically connected to the drain electrode and belonging to the same film layer as the source electrode and the drain electrode; There is an insulating layer between the scan line and the data line; The gate includes a top gate, an insulating layer is located between the source and drain and the semiconductor layer, the semiconductor layer is located between the bottom gate and the top gate, and the drain is electrically connected to the drain region of the semiconductor layer, and the source is electrically connected to the source region of the semiconductor layer. The sensing device as claimed in claim 6 , wherein the top gate and the bottom electrode belong to the same film layer. 8 . The sensing device as claimed in claim 6 , wherein the source is electrically connected to the semiconductor layer and the bottom electrode. 9 . The sensing device as claimed in claim 8 , wherein a minimum distance between an orthographic projection of the gate and an orthographic projection of the source on the substrate is 0 to 5 μm. 10 . The sensing device as claimed in claim 8 , further comprising a common electrode electrically connected to the upper electrode and formed in the same film layer as the source electrode.

11. A method for manufacturing a sensing device, comprising: forming a semiconductor layer on a substrate; forming a first insulating layer on the semiconductor layer; forming a blanket conductor layer on the first insulating layer and the substrate; forming a blanket semiconductor stack on the conductor layer; forming a blanket transparent electrode layer on the semiconductor stack; patterning the transparent electrode layer to form an upper electrode; patterning the semiconductor stack to form a photoelectric conversion layer; as well as patterning the conductive layer to form a bottom electrode and a top gate; The distance between the sidewall of the upper electrode and the sidewall of the photoelectric conversion layer is 0.5 μm to 3 μm; forming a bottom gate and a scan line on the substrate before forming the semiconductor layer; After patterning the conductive layer, a second insulating layer is formed on the substrate, and after forming the second insulating layer, a source electrode, a drain electrode, and a data line are formed on the second insulating layer; The scan line is electrically connected to the bottom gate and belongs to the same film layer as the bottom gate; The data line is electrically connected to the drain electrode and belongs to the same film layer as the source electrode and the drain electrode; There is an insulating layer between the scan line and the data line; The insulating layer is located between the source and drain and the semiconductor layer. The semiconductor layer is located between the bottom gate and the top gate. The drain is electrically connected to the drain region of the semiconductor layer, and the source is electrically connected to the source region of the semiconductor layer. 12 . The method for manufacturing a sensing device as claimed in claim 11 , wherein the top gate is physically connected to the bottom gate. 13 . The method for manufacturing a sensing device as claimed in claim 11 , wherein the top gate and the bottom gate surround the semiconductor layer. 14 . The method for manufacturing a sensing device according to claim 11 , further comprising a plurality of through holes in the second insulating layer respectively exposing both ends of the semiconductor layer, the lower electrode, and the upper electrode.

15. The method for manufacturing a sensing device according to claim 14, further comprising forming a common electrode on the second insulating layer after forming the second insulating layer, wherein the source is electrically connected to one end of the semiconductor layer and the lower electrode, the drain is electrically connected to the other end of the semiconductor layer, and the common electrode is electrically connected to the upper electrode.

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