A low EMI noise IGBT device with N-type charge layer

Abstract

The application discloses a low-EMI noise IGBT device with an N-type charge layer, which comprises, from bottom to top, a collector metal electrode, a P+ collector region, an N buffer layer and an N drift region which are sequentially stacked. On the surface of the N drift region, the N drift region is divided into a MOS region and a hole path region; the MOS region comprises a gate and a P well which are sequentially arranged left and right; the hole path region comprises a first floating P region, a first dummy gate, a spacing P-type region, a second dummy gate and a second floating P region which are sequentially arranged left and right; an N D + layer is arranged below the second floating P region. D The N D + layer and the N drift region form an N D + high-low junction, which can block the accumulation of holes near the gate oxide in the device opening stage, reduce the negative capacitance charging of the gate, and inhibit the EMI noise of the device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and relates to a low-EMI noise IGBT (Insulated Gate Bipolar Transistor) device with an N-type charge layer. BACKGROUND

[0002] The floating P region IGBT device is widely used in the fields of switching power supply, inverter, uninterruptible power supply and motor variable frequency speed regulation, because it realizes injection enhancement (IE) through the action of the floating P region, enhances the hole accumulation near the emitter side of the drift region, reduces the conduction power consumption, and has good short-circuit bearing capacity. However, in the opening stage of the device, the floating P region stores holes and raises its potential, so that the displacement current at the floating P region charges the gate, and then causes the device to have a large and uncontrollable overshoot current, generating serious electromagnetic interference (EMI) noise.

[0003] Especially when the small current is opened, the phenomenon is particularly serious, because compared with the rated current opening, when the small current is opened, the collector current generated by the negative capacitance and the floating P region charging the gate occupies a larger proportion of the total collector current; at the same time, compared with the rated current opening, when the small current is opened, the time for the collector to reach the small current opening is shorter. Therefore, when the small current is opened, the collector current I C The overshoot is more obvious and dIc / dt is not controlled by the gate resistance, generating serious electromagnetic interference noise.

[0004] In order to solve the influence of the floating P region on the gate, the predecessors proposed a new structure of hole path IGBT which can extract holes at the floating P region in the opening stage, as shown in Figure 3 The hole path IGBT device, when opened, has a reverse bias voltage between the emitter and the N drift region, so that the dummy gate accumulates a large number of holes to form a reverse P-type layer. Therefore, the holes in the floating P region can enter the emitter through the P reverse layer to form a hole flow path, as shown by the arrows in Figure 3 The existence of the hole path reduces the holes stored in the floating P region, and weakens the displacement current at the floating P region charging the gate, so that the hole path IGBT can suppress the EMI noise of the device.

[0005] Although the proposed hole path IGBT structure can extract holes at the floating P region in the opening stage, it does not consider the phenomenon of accumulated holes near the gate oxide in the opening stage, which will be equivalent to a negative capacitor superimposed on the gate, which will charge the gate in the opening stage, causing the gate to overshoot, and thus causing the device to have a large and uncontrollable overshoot current. SUMMARY

[0006] The purpose of the present application is to overcome the negative capacitance effect of the hole path IGBT, and to provide a low EMI noise IGBT device with an N-type charge layer, which can suppress the negative capacitance effect and effectively solve the EMI noise problem of the device in the small current opening stage.

[0007] To solve the above technical problems, the present application adopts the following technical solutions.

[0008] A low EMI noise IGBT device with an N-type charge layer, comprising a collector metal electrode, a P+ collector region, an N buffer layer and an N drift region stacked from bottom to top; on the surface of the N drift region, it is divided into a MOS region and a hole path region; the MOS region comprises a gate and a P well arranged from left to right; the surface of the P well is two adjacent N+ emitter regions and an ohmic contact P+ layer, one N+ emitter region is located on the left side of the ohmic contact P+ layer; the hole path region comprises a first floating P region, a first dummy gate, a spacer P-type region, a second dummy gate and a second floating P region arranged from left to right; an N-type charge layer, i.e. N+ layer, is arranged below the second floating P region and adjacent to the second floating P region, and is located on the left side of the gate oxide. The gate is covered with a gate oxide around it. D

[0009] The N D + layer and the second floating P region form a P / N D + PN junction, which can prevent holes in the N drift region from entering the second floating P region along the gate oxide in the opening stage of the device. The N D + layer and the N drift region form a high-low junction N D + / N D , which can prevent holes from accumulating near the gate oxide in the opening stage of the device.

[0010] The N D + layer has a transverse width of at least the width of the second floating P region, a junction depth of at least the position of the bottom of the gate oxide, and a doping concentration greater than that of the N drift region and less than the maximum value of the device manufacturing process.

[0011] The first dummy gate and the second dummy gate are directly connected together, and the first dummy gate and the second dummy gate are respectively covered with a first dummy gate oxide layer and a second dummy gate oxide layer.

[0012] ​The second floating P region, the second dummy gate, the oxide layer of the second dummy gate, the N drift region and the interval P type region form a hole path, which can lead the holes at the floating P region out during the opening process.

[0013] Compared with the prior art, the present application has the following advantages and beneficial effects:

[0014] 1. The N D + layer and the N drift region form a high-low junction N D + / N D , which blocks the accumulation of the holes injected into the N drift region near the gate oxide, thereby inhibiting the negative capacitance effect of the device and reducing the EMI noise of the device.

[0015] 2. The N D + layer and the floating P region form a P / N D + PN junction, which blocks the holes from entering the floating P region near the gate oxide, thereby reducing the accumulation of the holes at the junction of the floating P region and the gate oxide, and thus inhibiting the charging of the gate by the displacement current at the floating P region, and reducing the EMI noise of the device.

[0016] 3. The N D + layer occupies a very small area of the entire N drift region, so it has little effect on the Miller capacitance of the new device, and the turn-off characteristics, turn-on voltage drop and hole path IGBT structure of the new device are almost the same.

[0017] 4. The present application reduces the EMI noise of the device by changing the bulk structure, which is beneficial to reducing the complexity of the peripheral circuit, improving the circuit integration and reducing the circuit size. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural schematic diagram of an embodiment of the present application.

[0019] Figure 2 is a hole accumulation diagram near the gate oxide of an embodiment of the present application.

[0020] Figure 3 is a structural schematic diagram of a hole path IGBT device of the prior art.

[0021] Wherein, 101, collector metal electrode; 102, P+ collector region; 103, N buffer layer; 104, N drift region; 105, first floating P region; 106, first dummy gate; 107, oxide layer of the first dummy gate; 108, interval P type region; 109, second dummy gate; 110, oxide layer of the second dummy gate; 111, second floating P region; 112, N D113, P-well; 114, P+ layer with ohmic contact; 115, N+ emitter region; 116, field oxide; 117, emitter metal layer; 118, gate; 119, gate oxide. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings.

[0023] This invention relates to a low-EMI noise IGBT device with an N-type charge layer, such as... Figure 1 As shown, the structure includes a collector metal electrode 101, a P+ collector region 102, an N buffer layer 103, and an N drift region 104, which are stacked sequentially from bottom to top. The surface of the N drift region 104 is divided into a MOS region and a hole path region.

[0024] The MOS region is configured from left to right as a gate 118 and a P-well 113. The gate 118 is surrounded by gate oxide 119; the surface of the P-well 113 consists of two adjacent N+ emitter regions 115 and an ohmic contact P+ layer 114, with the N+ emitter regions 115 located to the left of the ohmic contact P+ layer 114.

[0025] The hole path regions, from left to right, are defined as follows: first floating P-region 105, first dummy gate 106, spaced P-type region 108, second dummy gate 109, and second floating P-region 111. It should be noted that the first dummy gate 106 and the second dummy gate 109 are directly connected to the emitter, and the first dummy gate 106 and the second dummy gate 109 are respectively covered by an oxide layer 107 for the first dummy gate and an oxide layer 110 for the second dummy gate.

[0026] In the hole path region, the second floating P region 111, the second dummy gate 109, the oxide layer 110 of the second dummy gate, the N drift region 104, and the spaced P-type region 108 constitute a hole path, which can discharge the holes at the second floating P region 111 during the turn-on process, reduce the rise rate of the potential of the second floating P region 111, and thus suppress the EMI noise generated by the second floating P region 111.

[0027] In addition, there is an N-type charge layer in the hole path region called N D +Layer 112, N D + Layer 112 is located below and adjacent to the second floating P area 111; N D Layer 112 is located to the left of gate oxide 119 and is adjacent to gate oxide 119.

[0028] N D + Layer 112 and the second floating P region 111 form P / N DA PN junction. This PN junction forms a P / N configuration relative to the second floating P-region 111 and N-drift region 104. D The PN junction has a larger built-in potential, therefore during the turn-on phase, the P / N junction... D The junction prevents holes in the N-drift region 104 from entering the second floating P-region 111 along the gate oxide 119, allowing more holes to enter the second floating P-region 111 from the N-drift region 104. This reduces hole accumulation at the interface between the second floating P-region 111 and the gate oxide 119, thus suppressing the charging of the gate 118 by the displacement current at the second floating P-region 111, thereby reducing the device's EMI noise.

[0029] N D + Layer 112 and N drift region 104 form a high-low junction N D + / N D Before the device is turned on, the N in the high-low junction... D + Layer 112 diffuses electrons into the N drift region 104, therefore in N D There is a high potential region at layer 112. When the device is turned on, the potential of the N-drift region 104 is higher than that of the gate 118, causing holes to accumulate near the gate oxide 119. However, due to the N-drift region... D The + layer 112 is a high potential region, which can prevent holes from accumulating near the gate oxide 119, such as Figure 2 As shown, the reduction in hole accumulation at gate oxide 119 can suppress Figure 2 Medium negative capacitor C Gpch Charging the gate reduces the overshoot of the gate 118 and suppresses the EMI noise of the device.

[0030] The top layer of the device consists of a field oxide layer 116 and an emitter metal layer 117. The field oxide layer 116 is located above the first floating P-region 105, the oxide layer 107 of the first dummy gate, the oxide layer 110 of the second dummy gate, the second floating P-region 111, and the gate oxide layer 119. The emitter metal layer 117 is located above the field oxide layer 116, the spacer P-type region 108, the N+ emitter region 115, and the ohmic contact P+ layer 114.

[0031] N D The + layer 112 occupies a very small proportion of the entire N-drift region 104, therefore the Miller capacitance of the device changes little, and it has almost no effect on the conductance modulation effect of the N-drift region 104. This indicates that the newly introduced N... D + Layer 112 has little impact on other electrical characteristics of the device.

[0032] N D The lateral width of layer 112 shall not exceed the width of the second floating P zone 111, i.e., N D+ The maximum lateral width of the layer 112 is less than the width of the second floating P region 111. D + The junction depth of the layer 112 is at least not exceeding the bottom of the gate oxide 119, i.e. N D + The deepest junction depth of the layer 112 is below the bottom of the gate oxide 119. D + The doping concentration of the layer 112 is greater than that of the N drift region 104 and less than the maximum value of the device manufacturing process. D + The lateral width, doping concentration and junction depth of the layer 112 all affect the EMI noise, thus the above parameters can be adjusted to obtain an IGBT device with optimal electrical characteristics.

[0033] In summary, the present application provides a low EMI noise IGBT device with N-type charge layer, which introduces an N D + layer on the trench gate side of the hole path IGBT, so that the N D + layer and the N drift region form an N D + N D high-low junction. In the initial stage of device opening, the N D + N D high-low junction can block the accumulation of holes near the gate oxide, reduce the negative capacitance of the gate, so that the device can effectively reduce the dI / dt and collector current overshoot of the device under the same opening power consumption, and further suppress the EMI noise of the device.

Claims

1. A low EMI noise IGBT device having an N-type charge layer, characterized by, It comprises, from bottom to top, a current collector metal electrode (101), a P+ collector region (102), an N buffer layer (103) and an N drift region (104) arranged in sequence; on the surface of the N drift region (104), it is divided into a MOS region and a hole path region; The MOS region comprises, from left to right, a gate (118) and a P well (113); the surface in the P well (113) is two adjacent N+ emitter regions (115) and an ohmic contact P+ layer (114), and one N+ emitter region (115) is located on the left side of the ohmic contact P+ layer (114); The hole path region comprises a first floating P region (105), a first dummy gate (106), a spaced P type region (108), a second dummy gate (109), a second floating P region (111) arranged in sequence from left to right; an N type charge layer (112) arranged below and adjacent to the second floating P region (111), located on the left side of the gate oxide (119) adjacent to the second floating P region (111). D + layer (112), located on the left side of the gate oxide (119) adjacent to the second floating P region (111). The N D + layer (112) and the second floating P region (111) form a P / N D + junction, which can prevent the holes in the N drift region (104) from entering the second floating P region (111) along the gate oxide (119) in the device on phase. The N D + layer (112) has a doping concentration greater than a doping concentration of the N- drift region (104); and D + layer (112) has a doping concentration less than a maximum value of a device manufacturing process. The first dummy gate (106) and the second dummy gate (109) are directly connected together, and the first dummy gate (106) and the second dummy gate (109) are respectively covered with a first dummy gate oxide layer (107) and a second dummy gate oxide layer (110); The second floating P region (111), the second dummy gate (109), the second dummy gate oxide layer (110), the N drift region (104) and the interval P type region (108) constitute a hole path, which can lead the holes at the floating P region out during the opening process of the device; The gate (118) is covered with a gate oxide (119).

2. The low EMI noise IGBT device with N-type charge layer according to claim 1, characterized in that, The N D + layer (112) and the N drift region form a high-low junction N D + / N D , which can prevent the accumulation of holes near the gate oxide (119) during the device on phase.

3. The low EMI noise IGBT device with N-type charge layer according to claim 1, characterized in that, The N D The lateral width of the + layer (112) is at least no more than the width of the second floating P region (111).

4. The low EMI noise IGBT device with N-type charge layer of claim 1, wherein, The N D + layer (112) is at least not deeper than the location of the bottom of the gate oxide (119).

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