Switching power supply control circuit and method

Abstract

Embodiments of the present application disclose a switching power supply control circuit and method. The switching power supply control circuit is used for controlling conduction of a power switch, comprising a power supply unit and a driving unit, wherein: the power supply unit is configured to supply power to the driving unit; the driving unit comprises a driving control circuit, a first driving switch and a second driving switch, wherein a width-length ratio of the first driving switch is less than a width-length ratio of the second driving switch, and the driving control circuit is configured to: during a first time period, provide a first driving signal for controlling the power switch to be in a conduction state by controlling the first driving switch to be in a conduction state and the second driving switch to be in an off state; and during a second time period, provide a second driving signal for controlling the power switch to be in the conduction state by controlling the first driving switch and the second driving switch to be in the conduction state, wherein the second time period is later in time than the first time period.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the field of integrated circuits, and particularly to a switching power supply control circuit and method. Background Technology

[0002] In traditional switching power supply systems, in order to save system costs and reduce the pin resources of the control circuit, a method of powering the control circuit directly using the system bus voltage without power supply capacitors is often adopted.

[0003] For example, in a traditional switching power supply system, there is no capacitor connected to the output terminal of the power supply unit included in the control circuit outside the control circuit. Instead, only a pF (picofarad) level capacitor is connected to the output terminal of the power supply unit inside the power supply unit.

[0004] However, although the above structure can reduce costs, during the operation of the control circuit to drive the power switch, the power supply voltage provided by the power supply unit may be pulled down to a lower level at the moment the drive switch in the drive unit included in the control circuit is turned on. This large fluctuation in the power supply voltage will affect the stability of the internal circuit and signal, and may even trigger the undervoltage protection of the power supply voltage inside the control circuit when the power supply voltage is pulled down to a lower level. Summary of the Invention

[0005] This invention provides a switching power supply control circuit and a method for use in the switching power supply control circuit. By first controlling a drive switch with a smaller width-to-length ratio to be in the conducting state, and then controlling a drive switch with a larger width-to-length ratio to be in the conducting state, the power switch can be driven in segments. This can effectively reduce the fluctuation and pull-down level of the power supply voltage VDD when driving the power switch, thereby reducing the risk of the control circuit triggering undervoltage protection.

[0006] On one hand, embodiments of the present invention provide a switching power supply control circuit for controlling the conduction of a power switch, comprising a power supply unit and a drive unit, wherein: the power supply unit is configured to supply power to the drive unit; the drive unit includes a drive control circuit, a first drive switch, and a second drive switch, wherein the width-to-length ratio of the first drive switch is smaller than that of the second drive switch, and the drive control circuit is configured to: during a first time period, by controlling the first drive switch to be in a conducting state and the second drive switch to be in a turning state, provide a first drive signal for controlling the power switch to be in a conducting state; and during a second time period, by controlling the first drive switch and the second drive switch to be in a conducting state, provide a second drive signal for controlling the power switch to be in a conducting state, wherein the second time period is later than the first time period.

[0007] On the other hand, embodiments of the present invention provide a method for use in a switching power supply control circuit to control the conduction of a power switch. The switching power supply control circuit includes a power supply unit and a drive unit, wherein the drive unit includes a drive control circuit, a first drive switch, and a second drive switch. The width-to-length ratio of the first drive switch is smaller than that of the second drive switch. The method includes: supplying power to the drive unit using the power supply unit; and using the drive control circuit to perform the following operations: during a first time period, by controlling the first drive switch to be in a conducting state and the second drive switch to be in a turning state, providing a first drive signal for controlling the power switch to be in a conducting state; and during a second time period, by controlling the first drive switch and the second drive switch to be in a conducting state, providing a second drive signal for controlling the power switch to be in a conducting state, wherein the second time period is later than the first time period.

[0008] The switching power supply control circuit and the method used in the switching power supply control circuit of the present invention can provide the drive signal for controlling the power switch to be in the on state in a segmented manner. This can effectively reduce the fluctuation and pull-down level of the power supply voltage VDD when driving the power switch, thereby reducing the risk of the control circuit triggering undervoltage protection. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of a switching power supply control circuit provided by the prior art is shown.

[0011] Figure 2 It shows Figure 1 The waveform diagram of the corresponding signal in the switching power supply control circuit is shown below;

[0012] Figure 3 A schematic diagram of the switching power supply control circuit provided in the first embodiment of the present invention is shown;

[0013] Figure 4 It shows Figure 3 The waveform diagram of the corresponding signal in the switching power supply control circuit is shown below;

[0014] Figure 5 A schematic diagram of the switching power supply control circuit provided in the second embodiment of the present invention is shown; and

[0015] Figure 6A flowchart illustrating a method for use in a switching power supply control circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0016] The features and exemplary embodiments of various aspects of the present invention will now be described in detail. To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present invention and are not configured to limit the present invention. For those skilled in the art, the present invention can be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the invention.

[0017] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0018] To address the problems of the prior art, embodiments of the present invention provide a switching power supply control circuit and a method used in the switching power supply control circuit. To better understand the switching power supply control circuit and method provided by the embodiments of the present invention, the switching power supply control circuit provided by the prior art is first described below.

[0019] Figure 1 A schematic diagram of a switching power supply control circuit provided by the prior art is shown. For example... Figure 1 As shown, the control circuit 100 may include a power supply unit 110 and a drive unit 120. Wherein, Figure 1 The power supply unit 110 shown may include a high-voltage junction field-effect transistor (JFET) J1, a low-dropout linear regulator (LDO) unit 1102, and a capacitor C2.

[0020] Specifically, the control circuit U100 can be connected to the system bus voltage VIN through the high voltage pin HV, and VIN can directly power the control circuit U100. Inside the control circuit U100, the HV pin can be connected to the first terminal of JFET J1, the second terminal of JFET J1 can be connected to the reference ground, and the third terminal of JFET J1 can be connected to the first terminal of LDO unit 1102. The second terminal of LDO unit 1102 can be grounded through capacitor C2 and can be used as the output terminal of power supply unit 110. LDO unit 1102 can be used to generate internal power supply VDD.

[0021] As an example, JFET J1 can control a high voltage of hundreds of volts from the HV pin to a level below tens of volts. As mentioned above, LDO unit 1102 can be used to output the internal circuit power supply VDD. For cost reasons, there is no external capacitor connected to VDD in the control circuit U100; only a pF-level capacitor is connected to VDD inside the control circuit U100.

[0022] like Figure 1 As shown, the drive unit 120 may include a drive control circuit 1202, an inverter 1204, a drive circuit 1206, a drive circuit 1208, a drive switch M1, and a drive switch M2.

[0023] The above structure can reduce costs. However, during the operation of the control circuit U100 to drive the power switch M3, there may be an excessive VDD current in the drive unit 120 at the moment the switch is turned on, causing the power supply voltage VDD to be pulled down to a lower level.

[0024] refer to Figure 1 and Figure 2 , Figure 2 It shows Figure 1 The diagram shows the waveforms of the corresponding signals in the switching power supply control circuit. Figure 1 The input signal of the drive unit 120 shown is a pulse width modulation (PWM) control signal, and the output signal is a control signal used to control the power switch M3 to turn on and off.

[0025] The first terminal of the drive control circuit 1202 can be connected to the gate of the drive switch M1 via the inverter 1204 and the drive circuit 1206. The source of the drive switch M1 can be connected to the internal power supply VDD. The drain of the drive switch M1 can be connected to the Gate pin of the control circuit U100. The second terminal of the drive control circuit 1202 can be connected to the gate of the drive switch M2 via the drive circuit 1208. The drain of the drive switch M2 can be connected to the drain of the drive switch M1 and the Gate pin. The source of the drive switch M2 can be grounded.

[0026] Furthermore, since parasitic capacitances Cgs and Cgd exist between the gate, source, and drain of power switch M3, respectively, when power switch M3 is in the on state, the power supply voltage VDD charges the gate capacitance of power switch M3 through drive switch M1, which generates a peak current of hundreds of milliamperes. Since there is no large-value capacitor connected to the output of power supply unit 110 outside the control circuit U100, but the capacitor connected to VDD inside power supply unit 110 is only on the order of pF, the internal power supply voltage VDD will be pulled down to a low level at the moment drive switch M1 is turned on. This large fluctuation of power supply voltage VDD will affect the stability of internal circuits and signals. Even when power supply voltage VDD is pulled down to an even lower level, it will trigger the undervoltage protection of power supply voltage VDD inside the control circuit, which will cause the control circuit to be restarted, and thus cause the power supply system to fail to work properly.

[0027] like Figure 2 As shown, at the instant the drive switch M1 is turned on (corresponding to the moment when the PWM signal changes from low level to high level), the power supply voltage VDD is pulled down to a lower level. As mentioned above, this will affect the stability of the internal circuit and signal. In fact, when the power supply voltage VDD is pulled down to an even lower level, it will trigger the undervoltage protection of the power supply voltage VDD inside the control circuit, which will cause the control circuit to be restarted, and thus cause the power supply system to fail to work properly.

[0028] Therefore, in order to solve one or more of the above problems, embodiments of the present invention provide a switching power supply control circuit and a method used in the switching power supply control circuit, which adopts a segmented approach to provide drive signals for controlling the power switch to be in the on state. This can effectively reduce the fluctuation and pull-down level of the power supply voltage VDD when driving the power switch, thereby reducing the risk of the control circuit triggering undervoltage protection.

[0029] The following is a detailed description of the switching power supply control circuit provided in the embodiments of the present invention, with reference to... Figure 3 , Figure 3 A schematic diagram of the switching power supply control circuit provided in the first embodiment of the present invention is shown.

[0030] For ease of description, Figure 3 and Figure 1 The same components may use the same reference numerals in the accompanying drawings, and their details will not be described again.

[0031] As an example, this embodiment of the invention provides a switching power supply control circuit for controlling the conduction of a power switch. The control circuit may include a power supply unit and a drive unit, wherein: the power supply unit can be configured to supply power to the drive unit; the drive unit may include a drive control circuit, a first drive switch, and a second drive switch, wherein the width-to-length ratio of the first drive switch is smaller than that of the second drive switch, and the drive control circuit can be configured to: during a first time period, by controlling the first drive switch to be in a conducting state and the second drive switch to be in a turning state, provide a first drive signal for controlling the power switch to be in a conducting state; and during a second time period, by controlling the first drive switch and the second drive switch to be in a conducting state, provide a second drive signal for controlling the power switch to be in a conducting state, wherein the second time period is later than the first time period.

[0032] As an example, by first controlling the drive switch with a smaller width-to-length ratio to be in the ON state and the drive switch with a larger width-to-length ratio to be in the OFF state, and then controlling both drive switches with smaller and larger width-to-length ratios to be in the ON state, since the driving capability of the drive switch corresponds to its width-to-length ratio—specifically, the drive switch with a smaller width-to-length ratio has a weaker driving capability and provides a smaller driving current, while the drive switch with a larger width-to-length ratio has a stronger driving capability and provides a larger driving current—that is, first providing a smaller driving current to the power switch, and then providing a larger driving current, the peak VDD current when the drive switch is ON can be effectively reduced through the above technical solution.

[0033] This method of first controlling the drive switch with a smaller width-to-length ratio to be in the ON state and the drive switch with a larger width-to-length ratio to be in the OFF state, and then controlling both the drive switches with smaller and larger width-to-length ratios to be in the ON state, can be achieved through the two technical solutions described below. It is understood that the spirit and scope of the present invention are not limited to the specific embodiments below, which are merely illustrative and not restrictive. Any technical solution that can achieve the sequential ON of the two drive switches is within the spirit and scope of the present invention.

[0034] As an example, one implementation could be to provide a delay circuit in the drive unit 220, which could be configured such that the turn-on time of the drive switch with a larger width-to-length ratio (W / L) (corresponding to the second drive switch) is delayed by a preset period compared to the turn-on time of the drive switch with a smaller width-to-length ratio (corresponding to the first drive switch).

[0035] Specifically, such as Figure 3As shown, the control circuit U200 may include a power supply unit 110 and a drive unit 220. The power supply unit 110 may include a high-voltage junction field-effect transistor (JFET) J1, an LDO unit 1102, and a capacitor C2, etc. The drive unit 220 may include a drive control circuit 2202, an inverter 1204, a drive circuit 1206, a delay circuit 2204, an inverter 2206, a drive circuit 2208, a drive switch M1, a drive switch M2, and a drive switch M4, etc. The inverters 1204 and 2206 constitute the drive unit of the control circuit U200.

[0036] like Figure 3 As shown, drive switches M1 and M2 can be connected between the output terminal of power supply unit 110 and ground. Drive switch M4 is connected in parallel with drive switch M1. Drive control circuit 2202 can receive pulse width modulation (PWM) signals. Its first terminal can be connected to the control terminal (e.g., gate) of drive switch M1 via inverter 1204 and drive circuit 1206. The first terminal of drive control circuit 2202 can also be connected to the control terminal (e.g., gate) of drive switch M4 via delay circuit 2204, inverter 2206 and drive circuit 2208. The second terminal of drive control circuit 2202 can be connected to the control terminal (e.g., gate) of drive switch M2 via drive circuit 1208. The common terminal (drain of drive switches M1 and M2) can be connected to the GATE pin to supply power to power switch M3 (see...). Figure 1 It provides drive signals.

[0037] As an example, control circuit U200 drives power switch M3 (see...) Figure 1 When it is turned on, Figure 3 In the illustrated embodiment, a segmented driving approach is adopted. Specifically, the drive control circuit 2202 can be used to output a control signal (labeled High_ctrl) to control the conduction of the drive switch M1 with a smaller aspect ratio. At this time, the drive switch M4 is in the off state to provide a drive signal for driving the power switch M3 to the on state. Then, the delay circuit 2204 can be used to delay for a period of time (e.g., Td, see [reference]) from the on-time of the drive switch M1. Figure 4 After a certain delay, a control signal (labeled as High_ctrl2) is output to control the conduction of the drive switch M4 with a large aspect ratio. At this time, the drive switch M1 is also in the conducting state to provide a drive signal for driving the power switch M3 to be in the conducting state.

[0038] In addition, the drive control circuit 2202 can be used to output a control signal (labeled as Low_ctrl) for controlling the turn-off of drive switch M2. For example, when drive switch M1 is in the on state, drive switch M2 is controlled to be in the off state; when both drive switches M1 and M4 are in the on state, drive switch M2 is controlled to be in the off state; and when drive switch M4 is in the on state, drive switch M2 is controlled to be in the off state.

[0039] It is understandable that the driving capability of a drive switch corresponds to its width-to-length ratio. For example, a drive switch with a smaller width-to-length ratio has a weaker driving capability and provides a smaller driving current, while a drive switch with a larger width-to-length ratio has a stronger driving capability and provides a larger driving current. By using this segmented driving method, the peak VDD current used to drive the power switch M3 to turn on can be effectively reduced.

[0040] In other words, by using this segmented driving method—first providing a smaller drive current to the power switch and then providing a larger drive current—the peak VDD current used to drive the power switch M3 to turn on can be effectively reduced.

[0041] The following combination Figure 4 right Figure 3 The working principle of the control circuit shown will be introduced. Figure 4 It shows Figure 3 The diagram shows the waveform of the corresponding signal in the switching power supply control circuit.

[0042] like Figure 4 As shown, at time t0, when the PWM signal changes from low to high, the control signal High_ctrl also changes from low to high. Then, using the aforementioned delay circuit 2204, a delay is applied so that at time t1, after a delay period Td from time t0, the control signal High_ctrl2 changes from low to high. The resulting waveform of the power supply voltage VDD is shown in the figure. Figure 4 The solid line in the figure shows the VDD waveform before optimization of the drive unit 220, and the dashed line shows the VDD waveform before optimization. It can be seen from the figure that the above technical solution can effectively reduce the peak VDD current used to drive the power switch M3 to turn on. Figure 4 During the time period t0-t2, the PWM signal and the High_ctrl signal are at a high level, while the High_ctrl2 signal is at a high level during the time period t1-t2.

[0043] In other words, during the time period t0-t1, only drive switch M1 is in the on state, and the magnitude of the drive current supplied to the power switch is equal to the smaller drive current supplied by drive switch M1; and during the time period t0-t2, both drive switches M1 and M4 are in the on state, and the magnitude of the drive current supplied to the power switch is equal to the sum of the smaller drive current supplied by drive switch M1 and the larger drive current supplied by drive switch M4.

[0044] from Figure 3 and Figure 4 As can be seen, by optimizing the drive unit using a segmented drive approach, the negative peak current of VDD when the drive power switch is turned on can be effectively reduced.

[0045] As an example, another implementation could be to provide a detection circuit in the drive unit, which could be configured to perform level detection on the output drive signal generated by the conduction of drive switch M1 when drive switch M1 is in the on state, and control drive switch M5 to be turned on when the output drive signal is detected to be higher than a preset threshold (e.g., Vt).

[0046] Specifically, refer to Figure 5 , Figure 5 A schematic diagram of the switching power supply control circuit provided in the second embodiment of the present invention is shown. The control circuit U300 may include a power supply unit 110 and a drive unit 320. The power supply unit 110 may include a high-voltage junction field-effect transistor (JFET) J1, an LDO unit 1102, and a capacitor C2, etc. The drive unit 320 may include a drive control circuit 3202, an inverter 1204, a drive circuit 1206, a detection circuit 3204, an inverter 3206, a drive circuit 3208, a drive circuit 1208, a drive switch M1, a drive switch M2, and a drive switch M5, etc.

[0047] like Figure 5As shown, drive switches M1 and M2 can be connected between the output terminal of power supply unit 110 and ground. Drive switch M5 is connected in parallel with drive switch M1. Drive control circuit 3202 can receive pulse width modulation (PWM) signals. The first terminal of drive control circuit 3202 can be connected to the control terminal (e.g., gate) of drive switch M1 via inverter 1204 and drive circuit 1206. The first terminal of drive control circuit 3202 can also be connected to the control terminal (e.g., gate) of drive switch M5 via detection circuit 3204, inverter 3206 and drive circuit 3208. The second terminal of drive control circuit 3202 can be connected to the control terminal (e.g., gate) of drive switch M2 via drive circuit 1208. The common terminal of drive switches M1 and M2 (i.e., the drain of drive switches M1 and M2) can be connected to the GATE pin to supply power to power switch M3 (see...). Figure 1 The drive signal is provided and can be connected to one end of the detection circuit 3204 to provide the detection circuit 3204 with the output drive signal generated by the conduction of the drive switch M1, so that it can perform level detection on the output drive signal generated by the conduction of the drive switch M1, and control the conduction of the drive switch M5 when the output drive signal is detected to be higher than a preset threshold (e.g., Vt).

[0048] As an example, when the control circuit U300 is configured to drive the power switch M3 to the on state, it... Figure 5 The circuit shown firstly uses a drive control circuit 3202 to control a drive switch M1 with a smaller width-to-length ratio to be in the ON state, thereby providing a smaller drive signal for driving the power switch M3 to be in the ON state. The detection circuit 3204 can be configured to perform level detection on the first drive signal when the PWM signal or the High_ctrl signal is at a logic high level (i.e., the drive switch M1 is in the ON state), and when the voltage level of the first drive signal is detected to be higher than a preset threshold voltage level Vt, the drive control circuit 3202 controls a drive switch M5 with a larger width-to-length ratio to be in the ON state, thereby providing a larger drive signal for controlling the power switch M3 to be in the ON state.

[0049] Similar to the description above, when drive switch M1 is in the ON state, the magnitude of the drive current supplied to power switch M3 is equal to the smaller drive current supplied by drive switch M1; and when both drive switches M1 and M5 are in the ON state, the magnitude of the drive current supplied to the power switch is equal to the sum of the smaller drive current supplied by drive switch M1 and the larger drive current supplied by drive switch M5.

[0050] As can be seen, both of the above implementation methods can achieve the following: first, control the drive switch with a smaller width-to-length ratio to be in the conducting state, and then control the drive switch with a larger width-to-length ratio to be in the conducting state. This segmented driving method can effectively reduce the peak VDD current used to drive the power switch M3 to be in the conducting state.

[0051] In addition, the drive control circuit 3202 can be used to output a control signal (labeled as Low_ctrl) for controlling the turn-off of drive switch M2. For example, when drive switch M1 is in the on state, drive switch M2 is controlled to be in the off state; when both drive switches M1 and M5 are in the on state, drive switch M2 is controlled to be in the off state; and when drive switch M5 is in the on state, drive switch M2 is controlled to be in the off state.

[0052] Similarly, by adopting, such as Figure 5 The segmented driving method shown can reduce the negative peak current of VDD when the drive power switch M3 is turned on.

[0053] In summary, the switching power supply control circuit provided by the embodiments of the present invention can control the drive signal provided to the power switch by controlling the sequential conduction of the drive switch without the need for an external capacitor, and adopts a segmented drive method. In this way, the peak VDD current when the power switch is turned on can be effectively reduced.

[0054] Furthermore, embodiments of the present invention also provide a method for use in the switching power supply control circuit described above, for controlling the conduction of the power switch, such as... Figure 6 As shown, Figure 6 A flowchart illustrating a method for use in a switching power supply control circuit according to an embodiment of the present invention is shown.

[0055] As described above, the switching power supply control circuit may include a power supply unit and a drive unit. The drive unit may include a drive control circuit, a first drive switch, and a second drive switch. The width-to-length ratio of the first drive switch is smaller than that of the second drive switch. The method may include: S610, supplying power to the drive unit using the power supply unit; S620, using the drive control circuit to perform the following operations: during a first time period, by controlling the first drive switch to be in a conducting state and the second drive switch to be in a turning state, providing a first drive signal for controlling the power switch to be in a conducting state; and during a second time period, by controlling the first drive switch and the second drive switch to be in a conducting state, providing a second drive signal for controlling the power switch to be in a conducting state, wherein the second time period is later than the first time period.

[0056] As an example, the driving unit may also include a delay circuit, and the method may further include: using the delay circuit to delay the turn-on time of the second driving switch by a preset period of time compared with the turn-on time of the first driving switch.

[0057] As an example, the drive unit may also include a third drive switch, wherein the method may further include: controlling the third drive switch to be in an off state during the first time period and the second time period using a drive control circuit.

[0058] In the above embodiments, the driving unit may further include a first inverter, a first driving circuit, a second inverter, a second driving circuit, and a third driving circuit, wherein: the first driving switch and the third driving switch are connected between the output terminal of the power supply unit and ground, and the second driving switch is connected in parallel with the first driving switch; the first terminal of the driving control circuit is connected to the control terminal of the first driving switch via the first inverter and the first driving circuit; the first terminal of the driving control circuit is also connected to the control terminal of the second driving switch via a delay circuit, the second inverter, and the second driving circuit; and the second terminal of the driving control circuit is connected to the control terminal of the third driving switch via the third driving circuit.

[0059] As an example, the driving unit may also include a detection circuit, and the method may further include: using the detection circuit to perform level detection on the first driving signal when the first driving switch is in the on state, and controlling the second driving switch to be turned on when the first driving signal is detected to be higher than a preset threshold.

[0060] As an example, the drive unit may also include a fourth drive switch, wherein the method may further include: controlling the fourth drive switch to be in an off state during the first time period and the second time period using a drive control circuit.

[0061] In the above embodiments, the driving unit may further include a third inverter, a fourth driving circuit, a fifth driving circuit, and a sixth driving circuit, wherein: the first driving switch and the fourth driving switch are connected between the output terminal of the power supply unit and ground, and the second driving switch is connected in parallel with the first driving switch; the first terminal of the driving control circuit is connected to the control terminal of the first driving switch via the third inverter and the fourth driving circuit; the first terminal of the driving control circuit is also connected to the control terminal of the second driving switch via the detection circuit, the fourth inverter, and the fifth driving circuit; and the second terminal of the driving control circuit is connected to the control terminal of the fourth driving switch via the sixth driving circuit, and the common terminal of the first driving switch and the fourth driving switch is further connected to the detection circuit.

[0062] In summary, the method provided by the embodiments of the present invention first controls the conduction of the first drive switch to provide a smaller drive current to the power switch, and then controls the conduction of the second drive switch to provide a larger drive current to the power switch. This segmented driving method can effectively reduce the fluctuation and pull-down level of the power supply voltage VDD when driving the power switch, thereby reducing the risk of the control circuit triggering undervoltage protection.

[0063] It should be noted that, in combination with the above Figures 3 to 5 The technical details of the switching power supply control circuit provided in the embodiments of the present invention have been described in detail, and the details of the method provided in the embodiments of the present invention are similar. Therefore, for the sake of simplicity, the description of the method is omitted here.

[0064] It should be clarified that the present invention is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present invention is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of the present invention.

[0065] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this invention are programs or code segments used to perform the required tasks. The programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0066] It should also be noted that the exemplary embodiments mentioned in this invention describe methods or systems based on a series of steps or apparatus. However, this invention is not limited to the order of the steps described above; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0067] The above description is merely a specific embodiment of the present invention. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the protection scope of the present invention.

Claims

1. A switching power supply control circuit for controlling the conduction of a power switch, characterized in that, The power supply unit is configured to supply power to the drive unit. The drive unit comprises a drive control circuit, a first drive switch and a second drive switch, wherein a width-length ratio of the first drive switch is smaller than a width-length ratio of the second drive switch, and the drive control circuit is configured to: provide, during a first time period, a first drive signal for controlling the power switch to be in a conducting state by controlling the first drive switch to be in a conducting state and the second drive switch to be in a non-conducting state; and provide, during a second time period, a second drive signal for controlling the power switch to be in a conducting state by controlling the first drive switch and the second drive switch to be in a conducting state, wherein the second time period is later in time than the first time period. The drive unit further comprises:

2. The switching power supply control circuit according to claim 1, characterized by a delay circuit configured to cause a conducting time of the second drive switch to be delayed from a conducting time of the first drive switch by a preset time period. The drive unit further comprises a third drive switch, wherein the drive control circuit is further configured to:

3. The switching power supply control circuit according to claim 2, characterized by control the third drive switch to be in a non-conducting state during the first time period and the second time period. The drive unit further comprises a first inverter, a first drive circuit, a second inverter, a second drive circuit and a third drive circuit, wherein:

4. The switching power supply control circuit according to claim 3, characterized by the first drive switch and the third drive switch are connected between an output terminal of the power supply unit and a ground, and the second drive switch is connected in parallel with the first drive switch; a first terminal of the drive control circuit is connected to a control terminal of the first drive switch via the first inverter and the first drive circuit; the first terminal of the drive control circuit is further connected to a control terminal of the second drive switch via the delay circuit, the second inverter and the second drive circuit; and a second terminal of the drive control circuit is connected to a control terminal of the third drive switch via the third drive circuit. The drive unit further comprises:

5. The switching power supply control circuit according to claim 1, wherein a detection circuit configured to perform level detection on the first drive signal when the first drive switch is in a conducting state, and control the second drive switch to be in a conducting state when it is detected that a level of the first drive signal is higher than a preset threshold. The drive unit further comprises a fourth drive switch, wherein the drive control circuit is further configured to:

6. The switching power supply control circuit according to claim 5, wherein control the fourth drive switch to be in a non-conducting state during the first time period and the second time period. The drive unit further comprises a third inverter, a fourth drive circuit, a fourth inverter, a fifth drive circuit and a sixth drive circuit, wherein:

7. The switching power supply control circuit according to claim 6, characterized by the first drive switch and the fourth drive switch are connected between the output terminal of the power supply unit and the ground, and the second drive switch is connected in parallel with the first drive switch; the first terminal of the drive control circuit is connected to the control terminal of the first drive switch via the third inverter and the fourth drive circuit; the first terminal of the drive control circuit is further connected to the control terminal of the second drive switch via the detection circuit, the fourth inverter and the fifth drive circuit; and the second terminal of the drive control circuit is connected to the control terminal of the third drive switch via the sixth drive circuit. A second end of the drive control circuit is connected to a control end of the fourth drive switch via the sixth drive circuit, wherein a common end of the first drive switch and the fourth drive switch is further connected to the detection circuit.

8. A method for use in a switching power supply control circuit for controlling the turn-on of a power switch, characterized by, The switching power supply control circuit comprises a power supply unit and a drive unit, wherein the drive unit comprises a drive control circuit, a first drive switch and a second drive switch, a width-length ratio of the first drive switch is smaller than a width-length ratio of the second drive switch, and the method comprises: powering the drive unit by using the power supply unit; performing the following operations by using the drive control circuit: during a first time period, providing a first drive signal for controlling the power switch to be in a conducting state by controlling the first drive switch to be in a conducting state and the second drive switch to be in an off state; and during a second time period, providing a second drive signal for controlling the power switch to be in a conducting state by controlling the first drive switch and the second drive switch to be in a conducting state, wherein the second time period is later in time than the first time period.

9. The method of claim 8, wherein, The drive unit further comprises a delay circuit, and the method further comprises: delaying, by using the delay circuit, a conducting time of the second drive switch by a preset time period compared with a conducting time of the first drive switch.

10. The method of claim 8, wherein, The drive unit further comprises a detection circuit, and the method further comprises: performing, by using the detection circuit, level detection on the first drive signal when the first drive switch is in a conducting state, and controlling the second drive switch to be in a conducting state when it is detected that a level of the first drive signal is higher than a preset threshold.

11. The method according to any of the preceding claims, characterized in that, The drive unit further comprises a third drive switch, and the method further comprises: controlling, by using the drive control circuit, the third drive switch to be in an off state during the first time period and the second time period.

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