A control method and circuit of a dual-clamp ZVS step-up / down converter

Abstract

The application discloses a control method and circuit of a double-clamp ZVS (Zero Voltage Switching) boost-buck converter, which comprises a double-clamp ZVS boost-buck converter main power circuit and a converter control circuit. The input voltage of the main power circuit, the voltage of a clamping capacitor and the drain-source voltage of a fourth switch tube are input into the converter control circuit. The converter control circuit outputs driving signals of the first switch tube to the fourth switch tube to control the switching of the switch tubes in the converter, so that the output voltage of the converter is stable. On one hand, the opening time of the clamping switch tube of the double-clamp converter is accurately controlled through pre-prepared data, so that the ZVS of the first switch tube and the cycle starting current of the converter are controlled. On the other hand, a clamping protection circuit is introduced to improve the reliability of the converter and avoid the excessive opening of the clamping switch tube under various extreme conditions. In addition, the variable frequency control and the highest frequency limitation are automatically realized through a simple ZVS detection mode, so that the conversion efficiency of the converter is improved.

Description

Technical Field

[0001] This invention belongs to the field of converter technology, specifically relating to a control method and circuit for a dual-clamp ZVS buck-boost converter. Background Technology

[0002] like Figure 1 The aforementioned double-clamped ZVS buck-boost converter k -Boost powercon ver The converter (ter) is a high-efficiency, isolated converter, first proposed by VICOR Corporation in the United States, patent number US9083254B1. Figure 1 The converter mainly consists of first to fifth switching transistors, a transformer, a clamping capacitor, an output filter capacitor, and an output load resistor. The third switching transistor can also be referred to as the clamping switching transistor. The first to fifth switching transistors additionally include parasitic diodes and parasitic capacitances of each switching transistor; the transformer additionally includes its leakage inductance; the fifth switching transistor, filter capacitor, output load resistor, and other components are connected to the secondary side of the transformer; the first to fourth switching transistors and the clamping capacitor are connected to the primary side of the transformer. The first and second switching transistors and the third and fourth switching transistors respectively form two half-bridge arms, and the primary side of the transformer is respectively connected to the midpoint of the two half-bridge arms; the input voltage source and the output capacitor are connected in parallel with the two half-bridge arms respectively.

[0003] Figure 2A The typical waveforms of a dual-clamp ZVS converter are given, where the first and second switches conduct complementaryly, and the third and fourth switches conduct complementaryly. i Lm The excitation current of the transformer is indicated; as shown. i Lr Indicate the total primary current of the transformer; such as Figure 2A As shown, when the first and fourth switches are turned on, the transformer's magnetizing induction energy storage and magnetizing current are... i Lm Linear increase, such as Figure 2A shown t 0 to t 1. During the time period; when the second and third switching transistors are turned on, the fifth switching transistor on the secondary side of the transformer is turned on, energy is transferred from the transformer to the secondary side, the transformer is demagnetized, and the excitation current... i Lm Linear decrease; in t At time 2, the third switch is turned off and the fourth switch is turned on. The transformer current freewheels through the second and third switches, and the transformer current remains essentially constant. i r0 Unchanged, corresponding to the above Figure 2A of t2~ t 3 stage, so that the t 0 to t 3 corresponds to a complete cycle of the double-clamp ZVS buck-boost converter. In addition, Figure 2A the period starting current of the transformer shown in i r0 is a small negative value, and the period starting negative current i r0 plays an important role and is the key to the control algorithm of the double-clamp ZVS converter. On the one hand, appropriate negative current i r0 helps to achieve ZVS zero-voltage turn-on of the first switch, thereby reducing switching loss and improving the conversion efficiency of the converter; on the other hand, if the current i r0 is too large, it will introduce additional conduction loss and affect the conversion efficiency of the converter. Figure 2B Another possible operating waveform of the double-clamp ZVS buck-boost converter under the same load is given, and the turn-on time of the third switch is relatively long, thereby causing the period starting current i r0 to be relatively large, which further causes the turn-on time of the first switch to be long, the switching frequency of the converter to be low, and ultimately causes a series of negative problems such as large conduction loss of the converter and large input ripple current. Further, the Figure 2A and 2B indicate that the period starting current i r0 is determined by the turn-on time of the third switch, and the turn-on time further affects the switching frequency of the converter. Under light load conditions of the converter, the switching frequency of the converter needs to be appropriately controlled, otherwise the switching frequency is too high under light load conditions, which easily causes the converter to fail. In addition, to accurately control the starting current, the double-clamp ZVS buck-boost converter also needs to effectively control the switching frequency of the converter. The U.S. Patent US9083254B1 proposes to indirectly control the clamp switch through the driving mode of the fifth switch, which is relatively complex and not conducive to the realization of primary and secondary side voltage withstand isolation. SUMMARY

[0004] To solve the above technical problems, the present application proposes a simple, reliable and effective solution, which can not only accurately control the size of the negative current, but also adaptively control the switching frequency of the converter, thereby realizing efficient and reliable operation of the converter. The present application adopts the following technical solutions:

[0005] A control method for a dual-clamp ZVS buck-boost converter, based on a first switching transistor. Q 1 to 4 switching transistors Q 4 Clamping capacitors C f The dual-clamp ZVS buck-boost converter main power circuit 300 controls the first switching transistor by executing the following steps. Q 1 to 4 switching transistors Q 4 The switch stabilizes the output voltage of the dual-clamp ZVS buck-boost converter.

[0006] Step 1, based on the input voltage of the main power circuit 300 of the dual-clamp ZVS buck-boost converter. v in Clamping capacitors C f voltage v o Fourth switching transistor Q 4 drain-source voltage v dsQ4 The voltages were obtained respectively. v in Corresponding sampling signal v ins ,Voltage v o Corresponding sampling signal v os ,Voltage v dsQ4 Corresponding sampling signal v dss ;

[0007] Step 2, based on the sampled signal v ins Sampling signal v os The first switching transistor was obtained respectively. Q 1 activation time identifier signal T 1. and the third switching transistor Q 3 Opening time identifier signal T 2;

[0008] Step 3, based on the sampled signal v dss Obtain the fourth switching transistor Q 4 zero-crossing signal of drain-source voltage v st ;

[0009] Step 4, based on the fourth switching transistorQ 4 zero-crossing signal of drain-source voltage v st and counting clock C lk Obtain the fourth switching transistor Q 4 Pulse width ramp signal v ramp ;

[0010] Step 5, based on the first switching transistor Q 1 activation time identifier signal T 1. Third switching transistor Q 3 Opening time identifier signal T 2. and the fourth switching transistor Q 4 Pulse width ramp signal v ramp Obtain the activation time identifier signal T 1 corresponds to high and low pulse width signals S 1 and activation time indicator signal T 2 corresponds to high and low pulse width signals S 2;

[0011] Step 6, based on the activation time identifier signal T 1 corresponds to high and low pulse width signals S 1 and activation time indicator signal T 2 corresponds to high and low pulse width signals S 2. and the fourth switching transistor Q 4 zero-crossing signal of drain-source voltage v st Obtain the first switching transistor Q 1 to 4 switching transistors Q 4 drive signal QS 1~ QS 4.

[0012] A circuit for a dual-clamp ZVS buck-boost converter control method includes a dual-clamp ZVS buck-boost converter main power circuit 300 and a converter control circuit 311. The dual-clamp ZVS buck-boost converter main power circuit 300 includes a first switching transistor on the primary side. Q 1 to 4 switching transistors Q 4 Clamping capacitors C f The fifth switch on the secondary side Q 5. And synchronous rectifier controller 301, first switching transistor Q The source and second switch of 1Q 2's drain connected, first switch Q 1's drain connected input voltage v in 2's anode, second switch Q 2's source connected input voltage v in 2's cathode, third switch Q 3 2's source and fourth switch Q 4 2's drain connected, third switch Q 3 2's drain connected clamping capacitor C f 2's anode, fourth switch Q 4 2's source connected clamping capacitor C f 2's cathode, fifth switch Q 5's drain-source voltage produces fifth switch Q 5's drive signal QS 5, controls fifth switch Q 5's switch; input voltage to the double-clamped ZVS buck-boost converter main power circuit 300 v in , clamping capacitor C f 's voltage v o , and fourth switch Q 4 's drain-source voltage v dsQ4 is input to the converter control circuit 311, which outputs the drive signals for the first switch Q 1 through fourth switch Q 4 's drive signal QS 1 QS 4, controls the first switch Q 1 through fourth switch Q 4 's switch in the double-clamped ZVS buck-boost converter, thereby stabilizing the output voltage of the double-clamped ZVS buck-boost converter.

[0013] As a preferred technical solution of the present application, a capacitor Q4 zvs is connected in parallel across the drain-source of the fourth switch C 4 for controlling the double-clamped ZVS buck-boost converter's period start current.

[0014] As a preferred embodiment of the present invention, the converter control circuit 311 includes a first voltage sampling circuit 303, a feedforward and output voltage closed-loop circuit 304, a pulse width modulation circuit 305, a clamping protection circuit 306, a second voltage sampling circuit 307, a zero-crossing detection circuit 308, a pulse width ramp generation circuit 309, and an oscillator 310. The input voltage of the main power circuit 300 of the dual-clamp ZVS buck-boost converter is... v in Clamping capacitors C f voltage v o The voltage is connected to the first voltage sampling circuit 303 and output through the first voltage sampling circuit 303. v in Corresponding sampling signal v ins and voltage v o Corresponding sampling signal v os ; Sampled signal v ins Sampling signal v os The first switching transistor is connected to the feedforward and output voltage closed-loop circuit 304 and output through the feedforward and output voltage closed-loop circuit 304. Q 1 activation time identifier signal T 1. and the third switching transistor Q 3 Opening time identifier signal T 2; The fourth switching transistor Q 4 drain-source voltage v dsQ4 The voltage is connected to the second voltage sampling circuit 307, and the output voltage is obtained through the second voltage sampling circuit 307. v dsQ4 Corresponding sampling signal v dss ; Sampled signal v dss The signal is connected to the zero-crossing detection circuit 308, and the zero-crossing signal is output by the zero-crossing detection circuit 308. v st Zero-crossing signal v st The pulse width ramp generation circuit 309 is connected, and the pulse width ramp generation circuit 309 outputs a pulse width ramp signal under the action of the oscillator 310. v ramp Identification signal T 1. Identification signal T 2. and pulse width ramp signal v rampThe signal is connected to the pulse width modulation circuit 305, and the pulse width modulation circuit 305 outputs the on-time indicator signal. T 1 corresponds to high and low pulse width signals S 1. and activation time indicator signal T 2 corresponds to high and low pulse width signals S 2; Clamping protection circuit 306 based on high and low pulse width signals S 1. High and low pulse width signals S 2. Zero-crossing signal v st Output first switching transistor Q 1 to 4 switching transistors Q 4 drive signal QS 1~ QS 4.

[0015] As a preferred embodiment of the present invention, the feedforward and output voltage closed-loop circuit 304 includes a subtractor 501, a proportional-integral regulator 502, a feedforward parameter calculation module 504, and a table data module 503, wherein the sampled signal... v os With preset voltage reference v oref The error value output by subtractor 501 E er Error value E er The proportional-integral controller 502 outputs the controller signal. v er The feedforward parameter calculation module 504 is based on the regulator output signal. v er Sampling signal v ins Sampling signal v os And the correction ratio coefficient output by the table data module 503 k and corrected bias coefficient dT Output first switch transistor Q 1 activation time identifier signal T 1. and the third switching transistor Q 3 Opening time identifier signal T 2; Table data module 503 is based on the regulator output signal v er Output the corresponding correction ratio. k and corrected bias coefficient dT .

[0016] As a preferred technical scheme of the present application, the clamping protection circuit 306 comprises a first complementary circuit 701, a dead zone circuit 702, a second complementary circuit 703, a dead zone circuit 704, an inverter device 705, a first AND gate device 706, a second AND gate device 707, the high-low pulse width signal S 1 sequentially passes through the first complementary circuit 701 and the dead zone circuit 702 to output a drive signal of the first switch tube Q 1 QS 1 Q 1 QS 2 S 2 sequentially passes through the second complementary circuit 703 and the dead zone circuit 704 to output a complementary signal with a dead zone S 3S and S 4S , the complementary signal S 4S and the zero-crossing signal v st are logically ANDed by the two-input second AND gate device 707 to output a drive signal of the fourth switch tube Q 4 4 QS 4 v st , the complementary signal S 3S after the inverting operation by the inverter device 705 is logically ANDed by the two-input first AND gate device 706 to output a drive signal of the third switch tube Q 3 3 QS 3

[0017] As a preferred technical scheme of the present application, the zero-crossing detection circuit 308 comprises a comparator Cp 1 R 81 , a resistor R 82 , a preset reference voltage signal v F is connected to the positive input end of the comparator R 81 1, and a sampling signal Cp v dss is connected to the negative input end of the comparator R 82 1, and the output end of the comparator Cp Cp 1 outputs a drain-source voltage zero-crossing signal Q 4 4 of the fourth switch tube v st ​​.

[0018] As a preferred technical solution of the present application, the pulse width ramp generation circuit 309 comprises a third AND gate device 900, a digital counter 901, a maximum frequency limiting module 902, the zero-crossing signal v st The maximum frequency limiting module 902 outputs a maximum frequency limiting signal T st The third AND gate device 900 outputs a cycle setting signal R st The maximum frequency limiting module 902 outputs a maximum frequency limiting signal R st The digital counter 901 outputs a maximum frequency limiting signal C lk The maximum frequency limiting module 902 outputs a maximum frequency limiting signal T st The digital counter 901 outputs a maximum frequency limiting signal C lk The cycle setting signal R st The digital counter 901 outputs a maximum frequency limiting signal v ramp .

[0019] As a preferred technical solution of the present application, the first switch tube Q The on time of the first switch tube T 1 is identified by the following formula: Q 3 The on time of the third switch tube T 2 is identified by the following formula:

[0020] ;

[0021] ;

[0022] In the formula, k in The input voltage v in The resistance sampling voltage corresponding to the input and output voltages in the first voltage sampling circuit; k o The voltage of the clamping capacitor C f The resistance sampling voltage corresponding to the input and output voltages in the first voltage sampling circuit. v o The resistance sampling voltage corresponding to the input and output voltages in the first voltage sampling circuit.

[0023] As a preferred technical solution of the present application, the maximum frequency limiting module 902 comprises a limiting threshold NLm Module 1101, digital comparator 1102, numerical counter 1103, numerical counter 1103 based on the set signal R st With the counting clock C lk Output count value v Trm Value, access the positive input end of the digital comparator 1102; limit threshold N Lm Module 1101 based on the minimum cycle output limit threshold of the double-clamp ZVS buck-boost converter N Lm , access the inverting input end of the digital comparator 1102; the output end of the digital comparator 1102 outputs the highest frequency limit signal T st .

[0024] The beneficial effects of the present application are: the present application provides a control method and circuit of double-clamp ZVS buck-boost converter, including double-clamp ZVS buck-boost converter main power circuit, converter control circuit, based on the input voltage of the main power circuit, the voltage of the clamp capacitor, and the drain-source voltage of the fourth switch tube, access the converter control circuit, the converter control circuit outputs the drive signal of the first switch tube to the fourth switch tube, controls the switching of each switch tube in the converter, and makes the output voltage of the converter stable. On the one hand, the turn-on time of the clamping switch tube of the double-clamp converter is accurately controlled by pre-prepared data, so as to control the converter cycle starting current and the ZVS of the first switch tube, on the other hand, the clamping protection circuit is introduced, the reliability of the converter is improved, and the clamping switch tube is prevented from being excessively turned on in various extreme conditions; in addition, the variable frequency control and the highest frequency limit are automatically realized by a simple ZVS detection method, and the conversion efficiency of the converter is improved. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 The power circuit of the prior art double-clamp ZVS buck-boost converter;

[0026] Figure 2A It is a typical working waveform schematic diagram of the prior art double-clamp ZVS buck-boost converter;

[0027] Figure 2B It is another typical working waveform schematic diagram of the prior art double-clamp ZVS buck-boost converter;

[0028] Figure 3A It is a main power circuit diagram of the double-clamp ZVS buck-boost converter of the present embodiment;

[0029] Figure 3B It is a control device structure diagram of the double-clamp ZVS buck-boost converter of the present embodiment;

[0030] Figure 4 Voltage sampling circuit structure diagram of the embodiment;

[0031] Figure 5 Feedforward and output voltage closed-loop circuit structure diagram of the embodiment;

[0032] Figure 6 Working waveform schematic diagram of the double-clamp ZVS buck-boost converter of the embodiment;

[0033] Figure 7 Clamp protection circuit structure diagram of the embodiment;

[0034] Figure 8 Zero-crossing detection circuit structure diagram of the embodiment;

[0035] Figure 9 Pulse width ramp generation circuit structure diagram of the embodiment;

[0036] Figure 10 Working waveform schematic diagram of the pulse width ramp generation circuit of the embodiment;

[0037] Figure 11 Maximum frequency limiting module structure diagram of the embodiment;

[0038] Figure 12 Working waveform schematic diagram of the maximum frequency limiting module of the embodiment;

[0039] Figure 13 Steady-state waveform schematic diagram of the double-clamp ZVS buck-boost converter of the embodiment. DETAILED DESCRIPTION

[0040] The application will be further described below in conjunction with the drawings. The following embodiments enable a person skilled in the art to have a more comprehensive understanding of the application, but do not limit the application in any way.

[0041] The application designs a control method and circuit of a double-clamp ZVS buck-boost converter. The control method and circuit control the switching of the first switch Q 1 to the fourth switch Q 4 , and thus stabilize the output voltage of the double-clamp ZVS buck-boost converter.

[0042] The control method of the double-clamp ZVS buck-boost converter is based on the first switch Q 1 to the fourth switch Q 4 , the clamp capacitor C fThe dual-clamp ZVS buck-boost converter main power circuit 300, as shown in the figure. Figure 3A As shown, the first switching transistor is controlled by performing the following steps. Q 1 to 4 switching transistors Q 4 The switch stabilizes the output voltage of the dual-clamp ZVS buck-boost converter.

[0043] Step 1, based on the input voltage of the main power circuit 300 of the dual-clamp ZVS buck-boost converter. v in Clamping capacitors C f voltage v o Fourth switching transistor Q 4 drain-source voltage v dsQ4 The voltages are obtained by passing through voltage sampling circuits respectively. v in Corresponding sampling signal v ins ,Voltage v o Corresponding sampling signal v os ,Voltage v dsQ4 Corresponding sampling signal v dss ;

[0044] Step 2, based on the sampled signal v ins Sampling signal v os After passing through the feedforward and output voltage closed-loop circuit 304, the first switching transistor is obtained respectively. Q 1 activation time identifier signal T 1. and the third switching transistor Q 3 Opening time identifier signal T 2;

[0045] Step 3, based on the sampled signal v dss After passing through the zero-crossing detection circuit 308, the fourth switching transistor is obtained. Q 4 zero-crossing signal of drain-source voltage v st ;

[0046] Step 4, based on the fourth switching transistor Q 4 zero-crossing signal of drain-source voltage vst , and a counting clock C lk , through the pulse width ramp generation circuit 309, to obtain the fourth switch tube Q 4 's pulse width ramp signal v ramp ;

[0047] Step 5, based on the first switch tube Q 1's turn-on time identification signal T 1, the third switch tube Q 3 's turn-on time identification signal T 2, and the fourth switch tube Q 4 's pulse width ramp signal v ramp , through the pulse width modulation circuit 305, to obtain the high-low pulse width signal T 1 corresponding to the turn-on time identification signal S 1 and the high-low pulse width signal T 2 corresponding to the turn-on time identification signal S 2;

[0048] Step 6, based on the high-low pulse width signal T 1 corresponding to the turn-on time identification signal S 1 and the high-low pulse width signal T 2 corresponding to the turn-on time identification signal S 2, and the fourth switch tube Q 4 's drain-source voltage zero-crossing signal v st , through the clamping protection circuit 306, to obtain the driving signals Q 1~ Q 4 of the first switch tube QS 1 to the fourth switch tube Figure 3A Based on the above-mentioned double-clamp ZVS buck-boost converter control method circuit, including the double-clamp ZVS buck-boost converter main power circuit 300, the converter control circuit 311, as shown in

[0049] and QS , the double-clamp ZVS buck-boost converter main power circuit 300 includes the first switch tube 3B 1 to the fourth switch tube Q 4 of the primary side, the clamping capacitor Q f , the fifth switch tube C Q of the secondary side​5, and the anode of the synchronous rectifier controller 301, the first switch tube Q 1, and the source of the second switch tube Q 2, the drain of the first switch tube Q 1, the drain of the second switch tube v in 2, the source of the third switch tube Q 2, the source of the fourth switch tube v in 1, the anode of the third switch tube Q 3 1, the source of the fourth switch tube Q 4 2, the drain of the third switch tube Q 3 1, the drain of the fourth switch tube C f 1, the anode of the fourth switch tube Q 4 1, the source of the fourth switch tube C f 1, the cathode of the synchronous rectifier controller 301, the fifth switch tube Q 5, the drain-source voltage of the fifth switch tube Q 5, the driving signal of the fifth switch tube QS 5, the fifth switch tube Q 5, the input voltage of the double-clamped ZVS buck-boost converter main power circuit 300 v in 1, the clamping capacitor C f 1, the voltage of the clamping capacitor v o 1, and the fourth switch tube Q 4 1, the drain-source voltage of the fourth switch tube v dsQ4 1, the input signal of the converter control circuit 311, the converter control circuit 311 outputting the driving signal of the first switch tube Q 1 to the fourth switch tube Q 4 1 QS 1 Czvs 4, the first switch tube Q 1 to the fourth switch tube Q 4 1, the switch of the double-clamped ZVS buck-boost converter, thereby stabilizing the output voltage of the double-clamped ZVS buck-boost converter; and further comprising a capacitor Q4 1, connected in parallel across the drain and the source of the fourth switch tube Figure 3A 1, for controlling the period starting current of the double-clamped ZVS buck-boost converter.

[0050] Figure 3BThe main power circuit 300 of the dual-clamp ZVS buck-boost converter also includes a transformer. T r Output capacitor C Ld Output load R Ld The diode shown in the figure D 1~ D 4 and capacitor C 1~ C 4 are the first to fourth switching transistors respectively. Q 1~ Q 4 Parasitic diodes and parasitic capacitances.

[0051] like QS As shown, the converter control circuit 311 includes a first voltage sampling circuit 303, a feedforward and output voltage closed-loop circuit 304, a pulse width modulation circuit 305, a clamping protection circuit 306, a second voltage sampling circuit 307, a zero-crossing detection circuit 308, a pulse width ramp generation circuit 309, and an oscillator 310. The input voltage of the main power circuit 300 of the dual-clamp ZVS buck-boost converter is... v in Clamping capacitors C f voltage v o The voltage is connected to the first voltage sampling circuit 303 and output through the first voltage sampling circuit 303. v in Corresponding sampling signal v ins and voltage v o Corresponding sampling signal v os ; Sampled signal v ins Sampling signal v os The first switching transistor is connected to the feedforward and output voltage closed-loop circuit 304 and output through the feedforward and output voltage closed-loop circuit 304. Q 1 activation time identifier signal T 1. and the third switching transistor Q 3 Opening time identifier signal T 2; The fourth switching transistor Q 4 drain-source voltage v dsQ4 The voltage is connected to the second voltage sampling circuit 307, and the output voltage is obtained through the second voltage sampling circuit 307. v dsQ4 Corresponding sampling signal vdss ; sampling signal v dss access zero-crossing detection circuit 308, zero-crossing detection circuit 308 outputs zero-crossing signal v st ; zero-crossing signal v st access pulse width ramp generation circuit 309, pulse width ramp generation circuit 309 outputs pulse width ramp signal under the action of oscillator 310 v ramp ; identification signal T 1, identification signal T 2, and pulse width ramp signal v ramp access pulse width modulation circuit 305, through pulse width modulation circuit 305 output on-time identification signal T 1 corresponding high-low pulse width signal S 1, and on-time identification signal T 2 corresponding high-low pulse width signal S 2; clamping protection circuit 306 based on high-low pulse width signal S 1, high-low pulse width signal S 2, zero-crossing signal v st output the driving signal of the first switch tube Q 1 to the fourth switch tube Q 4 QS 1 Figure 4 4.

[0052] As shown in Figure 5 , the first voltage sampling circuit 303 includes resistors R 11 , resistors R 12 , capacitors C 11 , resistors R 21 , resistors R 22 , capacitors C 21 , the input voltage v in in turn through resistors R 11 , resistors R 12 grounded, capacitors C 11 parallel resistors R 12 across, resistors R 11 , resistors R ​12 the connection node of the resistor v ins , filter capacitor C 11 in parallel with the sampling resistor R 12 to filter the input voltage v in via the resistor R 11 , R 12 in series to generate the sampling signal v ins ; the voltage C f of the resistor v o in sequence via the sampling resistor R 21 , the resistor R 22 is grounded C 21 in parallel with the resistor R 22 across the resistor R 21 , the resistor R 22 the connection node of the resistor v os , filter capacitor C 21 in parallel with the voltage R 22 to filter the output voltage v o via the sampling resistor R 21 , R 22 in series to generate the sampling signal v os ;

[0053] The second voltage sampling circuit 307 comprises a resistor R 31 , the resistor R 32 , a depletion MOS tube Q p , a capacitor C 31 , the drain-source voltage of the fourth switch tube Q 4 is connected to the resistor v dsQ4 at one end of the resistor R 31 ​R 31 The other end is connected to a depletion-type MOSFET. Q p The drain of the depletion-type MOSFET Q p The base of the resistor R 32 Connect to preset voltage source v dg Depletion-type MOSFET Q p The source electrode via capacitor C 31 Grounded. The MOSFET Q p The main purpose is to control the switching transistors of the main power circuit 300 of the dual-clamp ZVS buck-boost converter. Q 4 Drain-source high voltage signal v dsQ4 Converted into low voltage signal v dss This facilitates further processing by the control device 311. When the third capacitor... C 31 voltage v dss Voltage lower than voltage source v dg At that time, depletion-type MOSFET Q p High voltage signal activated v dsQ4 Through MOSFET Q p Give capacitor C 31 Charging; and when the capacitor C 31 voltage v dss Higher voltage source v dg At that time, MOSFET Q p At this point, charging is complete, thereby achieving control over the high-voltage signal. v dsQ4 Sampling is performed. The voltage source... v dg Typically, 5V or 3.3V is selected.

[0054] like dT As shown, the feedforward and output voltage closed-loop circuit 304 includes a subtractor 501, a proportional-integral regulator 502, a feedforward parameter calculation module 504, and a table data module 503. The sampled signal v os With preset voltage referencev oref error value outputted by the subtractor 501 E er error value E er regulator output signal outputted by the proportional-integral regulator 502 v er feedforward parameter calculation module 504 based on the regulator output signal v er sampled signal v ins sampled signal v os correction proportional coefficient and correction bias coefficient outputted by the table data module 503 k correction proportional coefficient and correction bias coefficient outputted by the table data module 503 dT turn-on time identification signal of the first switch tube Q 1turn-on time identification signal of the third switch tube T 1 Q 3 turn-on time identification signal of the third switch tube T 2corresponding correction proportional coefficient and correction bias coefficient outputted by the table data module 503 based on the regulator output signal v er corresponding correction proportional coefficient and correction bias coefficient outputted by the table data module 503 based on the regulator output signal k corresponding correction proportional coefficient and correction bias coefficient outputted by the table data module 503 based on the regulator output signal Figure 6 The coefficients are used to further adjust the turn-on time of the third switch tube of the double-clamp ZVS buck-boost converter.

[0055] Based on the feedforward and output voltage closed-loop circuit 304, the calculation formulas of the T 1 and T 2 in the embodiment are as follows:

[0056] ; (1)

[0057] In the formula, R1 and R2 are resistance sampling voltage division coefficients corresponding to the input and output voltages of the first voltage sampling circuit, i.e. k in k o k in is the input voltage v in in the first voltage sampling circuit k o is the voltage of the clamp capacitor C f v o in the first voltage sampling circuit ​

[0058] like Figure 6 As shown, equation (1) T 1 and T The two time periods refer to the first switching transistor of the dual-clamp ZVS buck-boost converter. Q The turn-on time of 1 and the third switching transistor of the converter Q 3 The opening time, that is Figure 5 shown t 0~ t 1. Time period and t 1~ t 1_2 Time period. Furthermore, t 0~ t During time period 1, the first switching transistor of the dual-clamp ZVS buck-boost converter Q 1 and the fourth switching transistor Q 4 Simultaneously activate, input voltage v in When applied to both ends of the transformer's excitation inductance, the transformer's excitation inductance current increases linearly, as shown in equation (2) below.

[0059] (2)

[0060] exist t 0~ t During the time period 1, the clamping capacitor C f voltage v o When applied to both ends of the transformer, the transformer excitation current decreases linearly.

[0061] (3)

[0062] Among them, in equations (2) and (3) i Lm_t0 , i Lm_t1 and i Lm_t2 Each refers to t 0、 t 1 and t The transformer excitation current at time 2. Furthermore, to ensure that the transformer excitation current is reset cycle by cycle, the... t 0~ t 1 time period and t 1~ t The change in transformer excitation current should remain consistent over two time periods, that is...

[0063] (4)

[0064] thereby,

[0065] (5)

[0066] Equation (5) gives the third switching transistor of the dual-clamp ZVS buck-boost converter. Q 3 The theoretical turn-on time. It should be noted that the value shown in equation (5) is a theoretical calculation. In actual converter operation, only equation (5) controls the third switch. The system is prone to divergence and instability, and the theoretical value needs to be corrected and protected. The correction and protection scheme is as described in this application. dT The lookup method shown is implemented as in equation (6).

[0067] (6)

[0068] In the formula k and Figure 6 These are the correction ratio coefficient and the correction bias coefficient, respectively. As can be seen from equation (6), the purpose of the correction and protection scheme of this invention is to avoid the third switching transistor... Q 3 The opening time is too long; such as dT As shown, theoretically, the turn-on time of the third switch is t 1 to t 2 near, however t 2. The time point is difficult to obtain precisely, therefore, the embodiments of this invention will... Q 3 The theoretical breakpoint is "shifted forward" to t 1_2 At the time point, the stated t 1_2 The time point is obtained from equation (6). It should be noted that... Q 3 The theoretical breakpoint is "shifted forward" to t 1_2 This will not affect the normal operation of the dual-clamp ZVS buck-boost converter, because the transformer primary current can continue to flow through it. Q 3 The parasitic diode that is turned on performs freewheeling. Furthermore, the correction coefficient in equation (6)... k and Figure 5 Adjustments need to be made based on the operating state of the dual-clamp ZVS buck-boost converter, i.e., the output load conditions, to avoid overload. Q 3 Insufficient switching time of the transistor affects the converter's efficiency. See also dT The present invention application is based on the output value of regulator 502 v erThe correction coefficient shown in equation (6) is adjusted in real time by looking up in the table data module 503 k and dT The table data in the table data module 503 can be obtained by offline measurement. The value range of the correction coefficient k and Figure 3A is 0.8-0.9 and 0.0-0.1 respectively.

[0069] Therefore, the turn-on time identification signal Q 1 of the first switch tube T 1 and the turn-on time identification signal Q 2 of the third switch tube 3 are calculated by the following equations respectively: T

[0070]

[0071]

[0072] In the equation, V k in is the input voltage v in The resistance sampling voltage division coefficient corresponding to the input and output voltages in the first voltage sampling circuit; k o V C f is the voltage of the clamping capacitor v o The resistance sampling voltage division coefficient corresponding to the input and output voltages in the first voltage sampling circuit.

[0073] Further, referring to Czvs , the application example in the present application is provided with a ZVS capacitor Q 4 connected in parallel across the drain and source of the fourth switch tube Figure 6 in the main power circuit 300 of the dual-clamp ZVS buck-boost converter for controlling the period starting current, referring to Figure 6 i r0 . The ZVS capacitor C zvs has a capacitance value determined according to the input and output operating conditions of the specific dual-clamp ZVS buck-boost converter, which is usually between 1 nF and 100 nF. Referring to Czvs , at the moment t 1_2 , the third switch tube Q 3 of the dual-clamp ZVS buck-boost converter is turned off, and the primary side current i Lr of the transformer​​​Q 3 The body diode freewheeling, in t 1_3 At any given moment, the primary current of the transformer i Lr Zero crossing, followed by transformer excitation inductance, leakage inductance, and the third and fourth switches of the dual-clamp ZVS buck-boost converter. Q 3 , Q 4 parasitic capacitance C 3、 C 4. And externally connected ZVS capacitors Czvs Resonance begins; during resonance, the primary current of the transformer... i Lr The approximate expression is shown in equation (7).

[0074] (7)

[0075] In the formula C oss_34 = C 3+ C 4+ C zvs As can be seen from equation (7), the external ZVS capacitor... Figure 7 The periodic start current of the dual-clamping can be controlled, thereby reliably realizing the first switching transistor of the converter. Q Enabling ZVS in version 1 improves transformation efficiency.

[0076] like Figure 3B As shown, the clamping protection circuit protects the clamping switch transistor in extreme cases. Q3 The clamping protection circuit 306 is protected by control, and includes a first complementary circuit 701, a dead-time circuit 702, a second complementary circuit 703, a dead-time circuit 704, an inverter device 705, a first AND gate device 706, and a second AND gate device 707. The input signal of the clamping protection circuit is... Figure 3B The pulse width output signal of the pulse width modulation circuit 305 shown S 1. S 2 and the zero-crossing signal output of the zero-crossing detection circuit 308. v st The output signal of the clamping protection circuit is QS The first to fourth switching transistors of the dual-clamp main power circuit shown Q 1~ Q 4 drive signal QS 1 to QS 4. The high and low pulse width signals S1 sequentially through the first complementary circuit 701, the dead-time circuit 702, and outputs the first two switching tubes Q 1 of the drive signal QS 1 and the second switching tube Q 1 of the drive signal QS 2; the high-low pulse width signal S 2 sequentially through the second complementary circuit 703, the dead-time circuit 704, and outputs the complementary signal with dead-time S 3S and S 4S , the complementary signal S 4S and the zero-crossing signal v st is logically ANDed by the two-input second AND gate device 707, and outputs the fourth switching tube Q 4 of the drive signal QS 4, the zero-crossing signal v st is logically ANDed by the inverter device 705, and outputs the complementary signal S 3S is logically ANDed by the two-input first AND gate device 706, and outputs the third switching tube Q 3 of the drive signal QS 3. The purpose of the clamp protection circuit is to ensure that the third switching tube, i.e. the clamp switching tube Q 3 of the drive signal Figure 8 3 of the double-clamp ZVS buck-boost converter must be generated only after the zero-crossing signal v st turns low, thereby ensuring that the clamp switching tube Q 3 will not be turned on "excessively" under any problem or transient operating condition, and will not affect the normal operation of the converter.

[0077] As shown in Cp , the zero-crossing detection circuit 308 includes a comparator Cp 1, a resistor R 81 , a resistor R 82 , and a preset reference voltage signal v F The positive input terminal of the comparator R 81 1 is connected through a resistor Cp v dss The sampling signal R 82 is connected through a resistor Cp ​The negative input terminal of 1, comparator Figure 3B The output terminal of 1 outputs the fourth switching transistor. Q 4 zero-crossing signal of drain-source voltage v st The voltage sampling signal v dss Depend on Figure 4 The 307 module generates a voltage signal derived from the drain-source voltage of the fourth switch in the dual-clamp ZVS buck-boost converter, which is converted from a high-voltage signal to a voltage signal via a sampling circuit. The reference voltage signal... v F Usually and Figure 3B The voltage source shown v dg Related, usually v F =(0.1~0.4) v dg .when v st When it is high, it indicates the fourth switching transistor. Q 4 drain-source voltage v dsQ4 Voltage zero crossing. The zero-crossing indicator signal. v st On the one hand, it is used for Figure 3B The clamping protection circuit of the 306 module is used for, on the one hand, Figure 9 The 309 module shown is used to determine the switching frequency of the dual-clamp ZVS buck-boost converter.

[0078] Furthermore, the pulse width ramp generation circuit, such as Figure 10 As shown, the embodiments of this invention are based on zero-crossing indicator signals. v st An automatic frequency conversion mechanism is introduced. The pulse width ramp generation circuit 309 includes a third AND gate device 900, a digital counter 901, and a maximum frequency limiting module 902. The embodiments of this invention are based on zero-crossing indicator signals. v st An automatic frequency conversion mechanism is introduced, the zero-crossing signal v st The highest frequency limit signal output by the highest frequency limit module 902 T st The third AND gate 900, which has two inputs, outputs a periodic set signal. R st The highest frequency limiting module 902 is based on the periodic set signal. R st With the counting clock generated by the oscillator 310 C lkOutput highest frequency limit signal T st , digital counter 901 based on the counting clock generated by the oscillator 310 C lk , cycle set signal R st Output pulse width ramp signal v ramp Each time the counting clock arrives, the counter performs a plus one operation. Cycle set signal R st temporarily, the count value is cleared, and a new round of counting period begins. The clock signal C lk is generated by the oscillator 310. The set signal R st Zero-crossing identification signal v st and the 902 module highest frequency limit signal T st is obtained through a logical AND operation via a two-input AND gate 900. Figure 10 The schematic waveform of the pulse width ramp generation circuit module is given, and the highest frequency limit signal T st is flipped to high level after passing T Lm time; when the zero-crossing identification signal v st is flipped to high level, the cycle set signal R st is flipped to high level, and then the pulse width ramp signal v ramp is immediately cleared, and the next cycle begins. The T Lm time corresponds to the minimum cycle time of the converter, T Lm and the value can be determined according to the specific working condition of the converter, and is usually about 1μs. From the Figure 9 it can be seen that the embodiment of the present application modulates the running frequency of the converter in real time by real-time sampling the drain-source voltage of the fourth switch tube of the double-clamp ZVS buck-boost converter v dsQ4 ; at the same time, Figure 11 the highest frequency limit module 902 limits the highest working frequency of the converter to ensure reliable operation.

[0079] Further, Figure 9 the implementation block diagram of the highest frequency limit module is given Figure 10 , and the highest frequency limit module 902 includes a limit threshold N LmModule 1101, digital comparator 1102, and numerical counter 1103, the numerical counter 1103 being based on the set signal. R st With counting clock C lk Output count value v Trm The value is connected to the non-inverting input of the digital comparator 1102; the threshold value is limited. N Lm Module 1101 Minimum Cycle Output Limit Threshold Based on Dual-Clamp ZVS Buck-Boost Converter N Lm The input is connected to the inverting input of digital comparator 1102; the output of digital comparator 1102 outputs a maximum frequency limit signal. T st The aforementioned N Lm That is Figure 11 As shown T Lm Clocks within time C lk Quantity value. Figure 12 The input signal of the module is a counting clock. C lk Periodic set signal R st The output signal is the highest frequency limiting signal. T st Each count clock C lk Upon arrival, the numerical counter 1103 increments by 1, and the reset signal is received each time. R st When the level is high, the second digital counter's count value is reset to zero and counting restarts. When the second counter outputs a signal... v Trm The count value is counted up to the limit threshold. T Lm At that time, digital comparator 1102 flips, and the frequency limiting signal... T st The signal flips to a high level when the count value is reset. R st When set to zero, the frequency limiting signal T st It also toggles to low. See also Figure 9 Due to frequency limiting signal T st Even if Figure 9 The zero-crossing indicator signal shown v st First, compare with the highest frequency limiting signal shown. T stArrival, Figure 9 The shown AND gate module 900 guarantees the periodic set signal R st The shown zero-crossing and frequency limiting signal T st are high, and then flip, thereby finally limiting Figure 13 The shown ramp signal v clamp The highest frequency of the shown ramp signal, that is, the highest operating frequency of the entire converter is limited to ensure reliable operation.

[0080] The application designs a control method and circuit of a double-clamp ZVS boost-buck converter. On one hand, the application can accurately control the turn-on time of the clamp switch tube of the double-clamp ZVS boost-buck converter, thereby controlling the periodic starting current of the converter and the ZVS of the first switch tube. On the other hand, the application additionally introduces a clamp protection circuit, thereby improving the reliability of the converter and avoiding the “overturn-on” of the clamp switch tube in various extreme situations. In addition, the application automatically realizes frequency control through a simple ZVS detection method, thereby improving the conversion efficiency of the converter.

[0081] Further, according to the embodiment of the application, a double-clamp ZVS boost-buck converter prototype is built, and a steady-state waveform is measured. As shown in the figure, it can be seen that the application can effectively realize reliable control of the converter. ​

[0082] Although the application has been disclosed as above with reference to the preferred embodiments, the application is not intended to be limited thereto. Those skilled in the art, without departing from the spirit and scope of the application, can make various modifications and decorations.

[0083] The above is only the preferred embodiment of the application, but does not limit the patent range of the application. Although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions recorded in the foregoing embodiments, or equivalently replace some technical features. Any equivalent structure made by using the content of the specification and drawings, directly or indirectly applied to other related technical fields, is also within the patent protection range of the application.​

Claims

1. A control method for a dual-clamp ZVS buck-boost converter, characterized in that: Based on the first switch Q1 to the fourth switch Q4, and the clamping capacitor C f The dual-clamp ZVS buck-boost converter main power circuit (300) and converter control circuit (311) execute steps 1 to 6 to control the switching of the first switch Q1 to the fourth switch Q4, thereby stabilizing the output voltage of the dual-clamp ZVS buck-boost converter. The main power circuit (300) of the dual-clamp ZVS buck-boost converter includes the first switch Q1 to the fourth switch Q4 on the primary side and the clamping capacitor C. f The fifth switch Q5 on the secondary side and the synchronous rectifier controller (301) are connected. The source of the first switch Q1 and the drain of the second switch Q2 are connected. The drain of the first switch Q1 is connected to the input voltage V. in The positive terminal of the second switch Q2 is connected to the source of the input voltage V. in The negative terminal of the transistor is connected to the source of the third switch Q3 and the drain of the fourth switch Q4. The drain of the third switch Q3 is connected to the clamping capacitor C. f The anode of the fourth switch Q4 is connected to the clamping capacitor C. f The cathode of the synchronous rectifier controller (301) generates a drive signal QS5 for the fifth switch Q5 based on the drain-source voltage of the fifth switch Q5, and controls the switching of the fifth switch Q5; the input voltage v of the dual-clamp ZVS buck-boost converter main power circuit (300) is... in Clamping capacitor C f voltage v o and the drain-source voltage v of the fourth switch Q4 dsQ4 As an input signal, it is connected to the converter control circuit (311). The converter control circuit (311) outputs the drive signals QS1~QS4 of the first switch Q1 to the fourth switch Q4 to control the switching of the first switch Q1 to the fourth switch Q4 in the dual-clamp ZVS buck-boost converter, thereby stabilizing the output voltage of the dual-clamp ZVS buck-boost converter. Step 1, based on the input voltage v of the main power circuit (300) of the dual-clamp ZVS buck-boost converter in Clamping capacitor C f voltage v o The drain-source voltage v of the fourth switching transistor Q4 dsQ4 The voltage v was obtained respectively. in The corresponding sampled signal v ins Voltage v o The corresponding sampled signal v os Voltage v dsQ4 The corresponding sampled signal v dss ; Step 2, based on the sampled signal v ins Sampling signal v os The on-time indicator signal T1 of the first switch Q1 and the on-time indicator signal T2 of the third switch Q3 are obtained respectively. Step 3, based on the sampled signal v dss The zero-crossing signal v of the drain-source voltage of the fourth switch Q4 is obtained. st ; Step 4, based on the zero-crossing signal v of the drain-source voltage of the fourth switch Q4 st and counting clock C lk The pulse width ramp signal v of the fourth switch Q4 is obtained. ramp ; Step 5, based on the turn-on time indicator signal T1 of the first switch Q1, the turn-on time indicator signal T2 of the third switch Q3, and the pulse width ramp signal v of the fourth switch Q4. ramp , obtain the high and low pulse width signals S1 corresponding to the activation time identifier signal T1 and the high and low pulse width signals S2 corresponding to the activation time identifier signal T2; Step 6, based on the high and low pulse width signals S1 corresponding to the turn-on time indicator signal T1 and S2 corresponding to the turn-on time indicator signal T2, and the zero-crossing signal v of the drain-source voltage of the fourth switch Q4. st The drive signals QS1~QS4 of the first switch Q1 to the fourth switch Q4 are obtained.

2. A circuit for a control method applied to the dual-clamp ZVS buck-boost converter of claim 1, characterized in that: The circuit includes a dual-clamp ZVS buck-boost converter main power circuit (300) and a converter control circuit (311). The dual-clamp ZVS buck-boost converter main power circuit (300) includes the first switch Q1 to the fourth switch Q4 on the primary side and the clamping capacitor C. f The fifth switch Q5 on the secondary side and the synchronous rectifier controller (301) are connected. The source of the first switch Q1 and the drain of the second switch Q2 are connected. The drain of the first switch Q1 is connected to the input voltage V. in The positive terminal of the second switch Q2 is connected to the source of the input voltage V. in The negative terminal of the transistor is connected to the source of the third switch Q3 and the drain of the fourth switch Q4. The drain of the third switch Q3 is connected to the clamping capacitor C. f The anode of the fourth switch Q4 is connected to the clamping capacitor C. f The cathode of the synchronous rectifier controller (301) generates a drive signal QS5 for the fifth switch Q5 based on the drain-source voltage of the fifth switch Q5, and controls the switching of the fifth switch Q5; the input voltage v of the dual-clamp ZVS buck-boost converter main power circuit (300) is... in Clamping capacitor C f voltage v o and the drain-source voltage v of the fourth switch Q4 dsQ4 As an input signal, the converter control circuit (311) outputs drive signals QS1~QS4 from the first switch Q1 to the fourth switch Q4 to control the switching of the first switch Q1 to the fourth switch Q4 in the dual-clamp ZVS buck-boost converter, thereby stabilizing the output voltage of the dual-clamp ZVS buck-boost converter.

3. The circuit according to claim 2, characterized in that: It also includes the capacitor C connected in parallel across the drain and source terminals of the fourth switch Q4. zvs Used to control the periodic start current of a dual-clamp ZVS buck-boost converter.

4. The circuit according to claim 2, characterized in that: The converter control circuit (311) includes a first voltage sampling circuit (303), a feedforward and output voltage closed-loop circuit (304), a pulse width modulation circuit (305), a clamping protection circuit (306), a second voltage sampling circuit (307), a zero-crossing detection circuit (308), a pulse width ramp generation circuit (309), and an oscillator (310). The input voltage v of the dual-clamp ZVS buck-boost converter main power circuit (300) is... in Clamping capacitor C f voltage v o The voltage is connected to the first voltage sampling circuit (303), and the output voltage v is obtained through the first voltage sampling circuit (303). in The corresponding sampled signal v ins and voltage v o The corresponding sampled signal v os ; Sampled signal v ins Sampling signal v os The feedforward and output voltage closed-loop circuit (304) is connected, and the feedforward and output voltage closed-loop circuit (304) outputs the turn-on time indicator signal T1 of the first switch Q1 and the turn-on time indicator signal T2 of the third switch Q3; the drain-source voltage v of the fourth switch Q4 is... dsQ4 The voltage is connected to the second voltage sampling circuit (307), and the output voltage v is obtained through the second voltage sampling circuit (307). dsQ4 The corresponding sampled signal v dss ; Sampled signal v dss The zero-crossing detection circuit (308) is connected, and the zero-crossing signal v is output after passing through the zero-crossing detection circuit (308). st Zero-crossing signal v st The pulse width ramp generation circuit (309) is connected, and the pulse width ramp generation circuit (309) outputs a pulse width ramp signal v under the action of the oscillator (310). ramp ; Identification signal T1, identification signal T2, and pulse width ramp signal v ramp The circuit (305) connects to the pulse width modulation circuit (305), which outputs high and low pulse width signals S1 corresponding to the on-time indicator signal T1 and high and low pulse width signals S2 corresponding to the on-time indicator signal T2. The clamping protection circuit (306) is based on the high and low pulse width signals S1, S2, and zero-crossing signal v. st Output drive signals QS1~QS4 for the first switch Q1 to the fourth switch Q4.

5. The circuit according to claim 4, characterized in that: The feedforward and output voltage closed-loop circuit (304) includes a subtractor (501), a proportional-integral regulator (502), a feedforward parameter calculation module (504), and a table data module (503), wherein the sampled signal v os With preset voltage reference v oref The subtractor (501) outputs the error value E. er Error value E er The proportional-integral controller (502) outputs the controller signal v. er The feedforward parameter calculation module (504) is based on the regulator output signal v er Sampling signal v ins Sampling signal v os The table data module (503) outputs the correction ratio coefficient k and the correction bias coefficient dT, and outputs the turn-on time indicator signal T1 of the first switch Q1 and the turn-on time indicator signal T2 of the third switch Q3; the table data module (503) outputs the regulator output signal v er Output the corresponding correction scaling factor k and correction bias factor dT.

6. The circuit according to claim 4, characterized in that: The clamping protection circuit (306) includes a first complementary circuit (701), a first dead-time circuit (702), a second complementary circuit (703), a second dead-time circuit (704), an inverter device (705), a first AND gate device (706), and a second AND gate device (707). The high and low pulse width signals S1 sequentially pass through the first complementary circuit (701) and the first dead-time circuit (702) to output the driving signal QS1 of the first two switching transistors Q1 and the driving signal QS2 of the second switching transistor Q1. The high and low pulse width signals S2 sequentially pass through the second complementary circuit (703) and the second dead-time circuit (704) to output the complementary signal S with dead time. 3S and S 4S complementary signal S 4S and the zero-crossing signal v st The second AND gate (707) performs a logic AND operation on the second input, outputting the drive signal QS4 for the fourth switch Q4. The zero-crossing signal v st After being inverted by the inverter device (705) and the complementary signal S 3S The first AND gate device (706) performs a logic AND operation on the two inputs to output the drive signal QS3 for the third switch Q3.

7. The circuit according to claim 4, characterized in that: The zero-crossing detection circuit (308) includes a comparator Cp1 and a resistor R. 81 Resistance R 82 Preset reference voltage signal v F Through resistor R 81 Connect the positive input terminal of comparator Cp1 and sample the signal v. dss Through resistor R 82 Connect the negative input terminal of comparator Cp1. The output terminal of comparator Cp1 outputs the zero-crossing signal v of the drain-source voltage of the fourth switching transistor Q4. st .

8. The circuit according to claim 4, characterized in that: The pulse width ramp generation circuit (309) includes a third AND gate device (900), a digital counter (901), and a maximum frequency limiting module (902). The zero-crossing signal v st The highest frequency limit signal T output by the highest frequency limit module (902) st The second input third AND gate device (900) outputs a periodic set signal R. st The highest frequency limiting module (902) is based on the periodic set signal R. st With the counting clock C generated by the oscillator (310) lk Output maximum frequency limit signal T st The digital counter (901) is based on a counting clock C generated by the oscillator (310). lk Periodic set signal R st Output pulse width ramp signal v ramp .

9. The circuit according to claim 5, characterized in that: The turn-on time indicator signal T1 of the first switch Q1 and the turn-on time indicator signal T2 of the third switch Q3 are calculated using the following formulas: ； ； In the formula, k in Input voltage v in In the first voltage sampling circuit, the resistor sampling voltage divider coefficients corresponding to the input and output voltages; k o Clamping capacitor C f voltage v o The voltage division coefficients of the resistors corresponding to the input and output voltages of the first voltage sampling circuit are used for sampling.

10. The circuit according to claim 8, characterized in that: The highest frequency limiting module (902) includes a limiting threshold N. Lm Module (1101), digital comparator (1102), numerical counter (1103), the numerical counter (1103) is based on the set signal R st With counting clock C lk Output count value v Trm The value is connected to the non-inverting input of the digital comparator (1102); the threshold N is limited. Lm Module (1101) is based on the minimum cycle output limit threshold N of a dual-clamp ZVS buck-boost converter. Lm The input is connected to the inverting input of the digital comparator (1102); the output of the digital comparator (1102) outputs a maximum frequency limit signal T. st .

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