Electro-optical device processed using deep ultraviolet radiation

Abstract

An optical device is described. At least a portion of the optical device includes ferroelectric nonlinear optical material(s) and is processed using ultraviolet lithography. In some aspects, the at least a portion of the optical device is processed using deep ultraviolet lithography. In some aspects, a short distance root mean square surface roughness of sidewalls of the at least a portion of the optical device is less than ten nanometers. In some aspects, the at least a portion of the optical device has a loss of no more than 2 dB / cm.

Description

[0001] Cross-reference of related applications This application is a continuation-in-part of co-pending U.S. Patent Application No. 16 / 785,206, filed on February 7, 2020, entitled “LITHIUM NIOBATE DEVICES FABRICATEDUSING DEEP ULTRAVIOLET RADIATION”, which is incorporated herein by reference for all purposes. Background Technology

[0002] Optical devices (such as waveguides) are used in a variety of applications. Lithium niobate devices may be desired for use in waveguides, resonators, and other optical and electro-optical devices. However, lithium niobate is notoriously difficult to fabricate into devices with the desired performance characteristics. Therefore, a mechanism is desired to provide optical devices using lithium niobate that possess sufficient performance characteristics. Attached Figure Description

[0003] Various embodiments of the invention are disclosed in the following detailed description and accompanying drawings.

[0004] Figure 1A-1B An embodiment of an optical device comprising lithium niobate, fabricated using ultraviolet lithography, is depicted.

[0005] Figure 2 An embodiment depicting a measurement of transmission in an optical device comprising lithium niobate and fabricated using ultraviolet lithography.

[0006] Figure 3 This is a flowchart depicting an embodiment of a method for forming an optical device comprising lithium niobate using ultraviolet lithography.

[0007] Figure 4-8 An embodiment of an optical device comprising lithium niobate, formed using ultraviolet lithography during processing, is depicted.

[0008] Figure 9 This is a flowchart depicting an embodiment of a method for forming an optical device comprising lithium niobate using deep ultraviolet lithography.

[0009] Figure 10-15 Another embodiment of an optical device comprising lithium niobate, formed using ultraviolet lithography during processing, is depicted.

[0010] Figure 16-21 Another embodiment of an optical device comprising lithium niobate, formed using ultraviolet lithography during processing, is depicted. Detailed Implementation

[0011] This invention can be implemented in many ways, including as: a process; an apparatus; a system; a composition of matter; a computer program product embodied on a computer-readable storage medium; and / or a processor, such as a processor configured to execute instructions stored in and / or provided by a memory coupled to the processor. In this specification, these implementations or any other form in which the invention may be taken can be referred to as techniques. Generally, the order of steps of the disclosed process can be changed within the scope of this invention.

[0012] The following provides a detailed description of one or more embodiments of the present invention, along with accompanying drawings illustrating the principles of the invention. The invention is described in conjunction with these embodiments, but is not limited to any particular embodiment. The scope of the invention is limited only by the claims, and the invention includes many alternatives, modifications, and equivalents. Many specific details are set forth in the following description to provide a thorough understanding of the invention. These details are provided for illustrative purposes, and the invention may be practiced without some or all of these specific details. For clarity, technical materials known in the art related to the invention have not been described in detail so as not to unnecessarily obscure the invention.

[0013] Lithium niobate (LN) is desired for use in optical devices, particularly in electro-optic devices. As used herein, optical devices can include both optical and electro-optic devices. The desirableness of LN is at least in part due to the variation of its refractive index with an applied external electric field. However, fabricating LN optical devices with the desired performance characteristics is challenging. For example, LN optical devices can have higher losses than desired. Recently, electron beam lithography has been used to fabricate LN optical devices to pattern a mask layer (e.g., via electron beam lithography). The underlying hard mask and LN layer can be etched using other techniques. LN optical devices thus formed can have improved performance. However, electron beam lithography is time-consuming, can be non-uniform, and can have limited reproducibility. Electron beam patterning of the mask using a scanning process is inherently slow. Furthermore, the electron beam is subject to drift during use. Because beam deflection is limited in range, electron beam lithography can only pattern relatively small areas (e.g., about one square millimeter or less). To pattern larger areas, the electron beam platform is moved, and electron beam lithography is repeated. Besides slowing down production, this aspect of electron beam lithography can also cause misalignment at the seams between these areas. These misalignments adversely affect the performance of the device being processed. Therefore, an improved method for processing LN optical devices is desired.

[0014] Other nonlinear optical materials may suffer from similar drawbacks to lithium tantalate (LT). For example, lithium tantalate (e.g., LiTaO3) has similar optical properties to LT. Processing lithium tantalate (LT) can also be challenging. Furthermore, LT may be susceptible to damage during high-temperature processing methods. Other ferroelectric nonlinear (e.g., second-order) optical materials may also be desired for use in optical devices. Such ferroelectric nonlinear optical materials may include, but are not limited to, potassium niobate (e.g., KNbO3), gallium arsenide (GaAs), potassium titanium oxyphosphate (KTP), lead zirconate titanate (PZT), and barium titanate (BaTiO3). The described techniques can also be used for other nonlinear ferroelectric optical materials, particularly those whose processing might otherwise be challenging. For example, such nonlinear ferroelectric optical materials may exhibit inert chemical etching reactions using conventional etching chemicals (such as fluorine, chlorine, or bromine compounds). Therefore, an improved method for processing devices using ferroelectric nonlinear optical materials (such as LT) is desired.

[0015] Methods for fabricating optical devices and optical devices thus formed are described. At least a portion of the optical device comprises an LN layer and is fabricated using photolithography, such as deep ultraviolet (DUV) lithography. Fabricating the optical device may include providing a hard mask layer on the LN layer. A mask is fabricated on the hard mask layer. This mask is formed using DUV photolithography. More specifically, the mask layer is provided, for example, by spin coating onto a DUV photoresist. The mask layer may be heat-treated. Portions of the mask layer may be selectively exposed to electromagnetic radiation in the DUV wavelength range. In some embodiments, the mask layer is heat-treated again after exposure. The mask layer is developed. Consequently, portions of the mask layer are removed to form a pattern exposing apertures of the underlying hard mask layer. A hard mask is formed from the hard mask layer by transferring the pattern of the mask onto the hard mask layer. For example, portions of the hard mask layer exposed by apertures in the mask may be selectively etched. The hard mask may have recesses or apertures in the areas where the hard mask layer is etched. The pattern of the hard mask can be transferred to the LN layer, for example, using physical etching. Multiple exposures can be performed on at least several spliced ​​regions spanning the surface of the substrate. In some cases, each of these spliced ​​regions is at least 10 mm by 10 mm. In some embodiments, the spliced ​​region can be at least 15 mm by 15 mm. In some embodiments, each spliced ​​region is at least 20 mm by 20 mm. Therefore, longer and / or more optical devices including LN can be fabricated using DUV lithography within a single spliced ​​region.

[0016] The lens element (LN) in an optical device fabricated using DUV lithography has improved surface roughness of one or more sidewalls. For example, the short-range root-mean-square (RMS) surface roughness of the sidewalls of the LN in an optical device formed using DUV lithography is less than ten nanometers. In some embodiments, this RMS surface roughness does not exceed five nanometers. In some cases, the short-range RMS surface roughness does not exceed two nanometers. The LN in the optical device can also have improved performance. In some aspects, the LN in the optical device has a loss of no more than 2 dB / cm. In some embodiments, the LN has a loss of less than 1.0 dB / cm. In some cases, this loss does not exceed 0.5 dB / cm. Therefore, the performance of an optical device including an LN can be improved.

[0017] Although described in the context of LN, the apparatus and methods described herein can be applied to one or more other nonlinear (e.g., second-order) optical materials, particularly ferroelectric nonlinear optical materials that may be difficult to process using conventional techniques. Such nonlinear ferroelectric optical materials may have an inert chemical etching reaction against conventional etching using chemicals such as fluorine, chlorine, or bromine compounds. For example, LT, potassium niobate, gallium arsenide, potassium titanate oxyphosphate, lead zirconate titanate, and / or barium titanate may be used instead of LN or in addition to LN. For example, methods for processing optical devices and optical devices thus formed such that at least a portion of the optical device comprises one or more ferroelectric nonlinear optical materials (e.g., LT) and is processed using photolithography (e.g., DUV lithography). Processing the optical device may include providing a hard mask layer on the ferroelectric nonlinear optical layer. A mask is processed on the hard mask layer. This mask is formed using DUV photolithography. More specifically, the mask layer is provided, for example, by spin-coating onto a DUV photoresist. The mask layer may be heat-treated. A portion of the mask layer can be selectively exposed to electromagnetic radiation in the DUV wavelength range. In some embodiments, the mask layer is heat-treated again after exposure. The mask layer is developed. Consequently, a portion of the mask layer is removed to form a pattern of apertures exposing the underlying hard mask layer. A hard mask is formed from the hard mask layer by transferring the mask pattern to the hard mask layer. For example, portions of the hard mask layer exposed by apertures in the mask can be selectively etched. The hard mask may have recesses or apertures in the etched areas of the hard mask layer. The pattern of the hard mask can be transferred to the ferroelectric nonlinear optical layer, for example, using physical etching. Multiple exposures can be performed on at least a plurality of spliced ​​regions spanning the surface of the substrate. In some cases, each of these spliced ​​regions is at least 10 mm by 10 mm. In some embodiments, the spliced ​​region may be at least 15 mm by 15 mm. In some embodiments, each spliced ​​region is at least 20 mm by 20 mm. Thus, longer and / or more optical devices including LNs can be fabricated using DUV lithography within a single spliced ​​region.

[0018] One or more ferroelectric nonlinear optical materials in optical devices fabricated using DUV lithography have improved surface roughness of sidewalls (one or more). For example, the short-range root-mean-square (RMS) surface roughness of the sidewalls of one or more ferroelectric nonlinear optical materials (e.g., LT) in optical devices formed using DUV lithography is less than ten nanometers. In some embodiments, this RMS surface roughness does not exceed five nanometers. In some cases, the short-range RMS surface roughness does not exceed two nanometers. One or more ferroelectric nonlinear optical materials (such as LT) in optical devices can also have improved performance. In some aspects, one or more ferroelectric nonlinear optical materials in optical devices have a loss of no more than 2 dB / cm. In some embodiments, one or more ferroelectric nonlinear optical materials have a loss of less than 1.0 dB / cm. In some cases, this loss does not exceed 0.5 dB / cm. Therefore, the performance of optical devices including one or more ferroelectric nonlinear optical materials can be improved.

[0019] Figure 1A and 1B Embodiments of devices 100A and 100B are depicted respectively, and devices 100A and 100B include LN processing using photolithography (such as DUV lithography). Figure 1A This is a diagram depicting device 100A, which includes an optical device 110A formed on a substrate 101A. Figure 1A Not drawn to scale. Substrate 101A may include a carrier wafer and any underlying layer between the wafer and optical device 110A. Optical device 110A includes an LN region. Although shown as only a portion of optical device 110A, the entire layer may be formed of LN. In some embodiments, optical device 110A may include other components not shown. Optical device 110A includes a flat region 111A, sidewalls 112A and 114A, and a top surface 116A. Thus, optical device 110A includes ridges having sidewalls 112A and 114A and a top surface 116A. Therefore, in the illustrated embodiment, the LN layer is not completely etched through. In another embodiment and / or in other regions, the LN layer may be etched through to expose the underlying layer (such as substrate 101A). In such an embodiment, some or all of the flat region 111A may be omitted.

[0020] Similarly, Figure 1BThis is a micrograph of device 100B, which includes an optical device 110B formed on a substrate (not shown). The substrate may include a carrier wafer and any underlying layer between the wafer and the optical device 110B. The optical device 110B includes an LN layer. In some embodiments, the optical device 110B may include other components not shown. The optical device 110B includes ridges and a flat region 111B, the ridges having sidewalls 112B and 114A and a top surface 116B.

[0021] The LN regions of optical devices 110A and 110B are formed using DUV lithography. As a result, the sidewalls 112A, 114A, 112B, and 114B of optical devices 110A and 110B have improved surface roughness. The short-range root-mean-square (RMS) surface roughness is the RMS surface roughness over a length (e.g., along direction l) not exceeding two hundred nanometers. The short-range RMS surface roughness of the sidewalls 112A and 114A of the LN region in optical device 110A and the short-range RMS surface roughness of the LN region in optical device 110B are each less than ten nanometers. In some embodiments, the short-range RMS surface roughness of the LN regions of both optical devices 110A and 110B does not exceed five nanometers. In some embodiments, the short-range RMS surface roughness of the LN regions of both optical devices 110A and 110B does not exceed two nanometers. Additionally, in some embodiments, the short-range RMS roughness of each of the top surfaces 116A and 116B does not exceed one nanometer. In some embodiments, the long-range (length greater than two hundred nanometers to two hundred micrometers) RMS surface roughness of the sidewalls 112A, 114A, 112B and / or 114B may differ from the short-range RMS surface roughness.

[0022] Because of the improved smoothness, optical devices can have improved performance. (Refer to...) Figure 2 This can be seen. Figure 2Example 200 depicts measurements of transmission in an optical device comprising lithium niobate and fabricated using ultraviolet lithography. Graph 200 indicates transmission through an LN optical device (such as one or more optical devices 110A and / or 110B) operating as a resonator. The drop in graph 200 indicates resonance. In some embodiments, the peak width is approximately picometers and indicates the efficiency of the corresponding optical device. In some embodiments, the LN regions of optical device 110A and LN optical device 110B have a signal loss of no more than 5 dB / cm. In some embodiments, the LN regions of optical device 110A and LN optical device 110B each have a loss of no more than 2 dB / cm. In some such embodiments, the loss of each LN region of optical device 110A and LN optical device 110B is less than 1.0 dB / cm. For example, in some embodiments, this loss may not exceed 0.5 dB / cm.

[0023] Therefore, optical devices 110A and 110B processed using DUV lithography can have reduced surface roughness and improved efficiency. Furthermore, because patterning is performed using DUV lithography, optical devices 110A and 110B can be processed over a larger area of ​​substrates 101A and 101B with higher reproducibility, better uniformity, higher production volume. Therefore, the method for processing optical devices including LN and the optical devices thus formed can be improved.

[0024] Figure 3 This is a flowchart depicting an embodiment of a method 300 for forming an optical device including an LN using ultraviolet lithography (such as DUV lithography). Method 300 is described in the context of a process that may have subprocesses. Although described in a particular order, an alternative order may be used that is inconsistent with the description herein. Method 300 begins after an LN layer has been provided on a substrate. In some embodiments, the LN layer may be thin, for example, no more than ten micrometers in thickness. In some embodiments, the LN layer may be no more than one micrometer in thickness. In some embodiments, the thickness of the LN layer may be no more than seven hundred nanometers. In some such embodiments, the thickness may be no more than four hundred nanometers. Other thicknesses are possible. An underlayer (such as silicon dioxide) may be present between the LN layer and a carrier wafer. In some embodiments, the carrier wafer may include silicon, quartz, silica, LN, sapphire, and / or another material. For example, the LN layer may be located on a silicon dioxide underlayer having a nominal thickness of at least two micrometers and no more than five micrometers. Other thicknesses, additional layers, and / or other layers may be present.

[0025] At 302, a hard mask layer is provided. In some embodiments, the hard mask may include one or more of amorphous silicon, silicon dioxide, silicon nitride, ceramic, metal (e.g., Ti), or other hard mask materials. In some embodiments, at 302, chemical vapor deposition (CVD) or other deposition methods may be used.

[0026] In step 304, a mask is formed on a hard mask layer using UV lithography. In some embodiments, step 304 includes providing a mask layer. For example, the mask layer may be a photoresist layer spin-coated onto the hard mask layer. Using UV lithography, portions of the mask layer are selectively exposed. In some embodiments, the wavelength of the electromagnetic radiation used for UV lithography is no more than 450 nanometers. In some embodiments, DUV lithography is used. For example, the wavelength of the electromagnetic radiation used may be less than 250 nanometers. In some embodiments, other wavelengths of electromagnetic radiation may be used to expose the mask layer. Furthermore, as part of step 304, the mask layer may be heat-treated (e.g., baked) before and / or after exposure. The exposed mask is also developed. In some embodiments, post-development baking is not performed. Thus, portions of the mask layer are removed to form apertures in the mask layer. Thus, a patterned mask is formed.

[0027] At 306, a hard mask is provided from the hard mask layer. To achieve this, a mask formed by DUV lithography is used. Thus, a pattern from the mask can be transferred to the hard mask layer. A hard mask is thus formed. In some embodiments, 306 includes chemically and / or physically removing portions of the hard mask layer that are exposed by the pattern in the mask. In some embodiments, the removal at 306 forms apertures in the hard mask layer to provide the hard mask. In some embodiments, the removal at 306 forms recesses in the hard mask layer to provide the hard mask. The hard mask can be used in method 300 because a mask patterned using DUV lithography may be more easily removed by etching the LN layer in 308, described below, for patterning. Such removal of the mask may result in sidewalls of the optical device having a surface roughness higher than desired. However, in other embodiments, steps 302 and 304 may be omitted, for example, if a higher surface roughness is tolerable.

[0028] At 308, a hard mask is used to etch the LN layer. Therefore, the pattern in the hard mask can be transferred to the LN layer at 308. In some embodiments, physical etching is used at 308. For example, dry etching, reactive ion etching (RIE), plasma etching, and / or other physical etching mechanisms can be used at 308. In some embodiments, chemical etching or other etching can be used at 308. In embodiments where the hard mask includes recesses rather than apertures, the pattern transfer at 308 also removes at least some of the thinned portions of the hard mask. In some embodiments, the LN layer is not completely etched through at 308. Therefore, the formed optical device can be a raised portion or ridge remaining after 308. In some embodiments, portions of the LN layer can be etched through at 308. Furthermore, at 308, any remaining mask and / or hard mask can be removed.

[0029] In step 310, some or all of method 300 may be repeated. For example, in step 304, a mask layer may be provided and baked. After one area has been exposed, the platform may be moved to expose one or more additional areas of the mask layer. Therefore, this portion of step 304 may be repeated. Once all desired areas have been exposed, the mask layer may be developed to provide a mask for the entire substrate. The pattern may then be transferred to the underlying layer in steps 306 and 308. Thus, in some embodiments, at least a portion of step 304 may be repeated once or multiple times. In other embodiments, steps 302, 304, 306, and 308 may be repeated for different areas of the substrate. Thus, multiple areas of the device may be processed. For example, larger optical devices and / or optical devices extending across the edges of the patterned areas may be formed.

[0030] For example, Figure 4-8 An embodiment of an apparatus 400 comprising LN and formed using method 300 during processing is described. Figure 4-8 The drawing is not to scale, and only a portion of device 400 is shown. Furthermore, device 400 is for illustrative purposes and may not represent a specific device. For example, sidewalls are typically shown as vertical and flat, while the top surface is typically shown as horizontal and flat. However, some variations are generally possible.

[0031] Figure 4 The apparatus 400 is depicted after a mask layer has been provided as part of 304. Therefore, it is shown to include a substrate 401 comprising a carrier wafer, a bottom layer 402, an LN layer 410, a hard mask layer 420, and a DUV mask layer 430. The bottom layer 402 may be an insulator, such as silicon dioxide. In this embodiment, the bottom layer 402 is depicted as separate from the substrate 401. In some embodiments, other layers may be present and / or one or more layers shown may be omitted. For example, in some embodiments, the bottom layer 402 may be omitted.

[0032] Figure 5 The apparatus 400 is depicted after step 304 has been completed. A DUV mask layer 430 has been selectively exposed to DUV light and developed. Thus, a DUV mask 430A has been formed. A portion of the hard mask layer 420 is exposed by the DUV mask 430A.

[0033] Figure 6 The device 400 is depicted after step 306 has been completed. Therefore, a hard mask 420A has been formed. In the illustrated embodiment, the pattern of a DUV mask 430A has been transferred onto the hard mask 420A. In the illustrated embodiment, the hard mask 420A has recesses 422 in the areas where the hard mask layer 430 is etched. Therefore, the pattern of the DUV mask 430A has been transferred onto the hard mask 420A.

[0034] Figure 7-8 The device 400 is depicted after 308 has been completed. The DUV mask 430A and the hard mask 420A have also been removed. Figure 7 This is a cross-sectional view of device 400. Figure 8 This is a plan view indicating the splicing (shown by dashed lines) of device 400. Therefore, the LN optical device 410A is shown in... Figure 7 and 8 In addition, Figure 8 The image shows an LN optical device 410B. In some embodiments, LN optical devices 410A and / or LN optical devices 410B include other components. However, for simplicity, only a portion of LN optical devices 410A and a portion of LN optical devices 410B are shown. LN optical devices 410A and 410B can be considered as ridges formed in LN layer 410 by removing portions of the LN layer exposed by hard mask 420A. Therefore, the sidewalls (such as sidewalls 412 and 414) of optical devices 410A and 410B are the sidewalls of the ridges. In some embodiments, LN layer 410 may be etched through at 308. In this embodiment, the underlying layer (such as one or more bottom layers 402) may be exposed after 308 is completed.

[0035] LN optical devices 410A and 410B are located in different stitching areas exposed at different times. Therefore, as Figure 8 As indicated, LN optical devices 410A and 410B may be misaligned. Therefore, LN optical devices 410A and 410B are slightly widened in the spliced ​​area to reduce the effect of this misalignment. Thus, in the illustrated embodiment, LN optical devices 410A and 410B can be considered as part of a single optical device spanning multiple spliced ​​areas. DUV lithography is also used to form LN optical devices 410A and 410B. Therefore, each has sidewalls. The sidewalls 412 and 414 of LN optical device 410A are... Figure 7 and 8 The sidewalls 412 and 414 have improved surface roughness due to the use of DUV lithography. The short-range RMS surface roughness of each of the sidewalls 412 and 414 of the LN optical device 410A is less than ten nanometers. In some embodiments, the short-range RMS surface roughness of each sidewall 412 and 414 of the LN optical device 410A does not exceed five nanometers. In some embodiments, the short-range RMS surface roughness of each sidewall 412 and 414 of the LN optical device 410A does not exceed two nanometers. The LN optical device 410B has a short-range RMS surface roughness similar to or greater than that of the LN optical device 410A.

[0036] Optical devices 410A and 410B can have improved performance. In some embodiments, each LN optical device 410A and 410B has a signal loss of no more than 5 dB / cm. In some embodiments, each LN optical device 410A and 410B has a loss of no more than 2 dB / cm. In some such embodiments, the loss of each LN optical device in LN optical devices 410A and 410B is less than 1.0 dB / cm. For example, in some embodiments, this loss may not exceed 0.5 dB / cm.

[0037] Therefore, LN optical devices 410A and 410B can have improved manufacturability, performance, and reduced sidewall surface roughness. Because of the use of DUV lithography, production volume can be increased and the processing time of the apparatus 400 can be reduced, uniformity can be improved, and reproducibility can be enhanced. DUV lithography also allows for large splicing areas. For example, in some embodiments, a splicing area of ​​at least ten millimeters by ten millimeters can undergo DUV lithography in a single irradiation. In some embodiments, the splicing area can be at least fifteen millimeters by fifteen millimeters. For example, the splicing area can be nominally twenty millimeters by twenty millimeters or larger. Therefore, such as Figure 8 The number of splices shown is reduced. This not only increases production volume and reproducibility, but also reduces misalignment in optical devices (e.g., as shown between LN optical devices 410A and 410B).

[0038] Figure 9This is a flowchart depicting an embodiment of a method 900 for forming an optical device including an LN using DUV lithography. Method 900 is described in the context of a process that may have subprocesses. Although described in a particular order, an alternative order may be used that differs from the description herein. Method 900 begins after an LN layer has been provided on a substrate (such as a carrier wafer). In some embodiments, the LN layer may be thin, for example, no more than ten micrometers in thickness. In some embodiments, the LN layer may be no more than one micrometer thick. In some embodiments, the thickness of the LN layer may be no more than seven hundred nanometers. In some such embodiments, the thickness may be no more than four hundred nanometers. Other thicknesses are possible. One or more insulating underlayers (such as silicon dioxide) may be present between the LN layer and the underlying wafer. For example, the LN layer may be located on a silicon dioxide underlayer having a nominal thickness of at least two micrometers and no more than about five micrometers. Other thicknesses, additional layers, and / or other layers may be present.

[0039] At 902, a stop layer may be provided. The stop layer is insensitive to etches that can be used to form a hard mask. For example, if chemical etching is used to selectively remove portions of the hard mask layer as discussed below, the stop layer provided at 902 is insensitive to the chemicals used in such etching. If multiple etches are used to form the hard mask, it is desirable that the stop layer provided at 902 be insensitive to at least the last(s) etch(s) used to pattern the hard mask. The etch stop layer provided at 902 may also be removed without excessive damage to the underlying LN layer. In some embodiments, 902 may be omitted.

[0040] At 904, a hard mask layer is provided. In some embodiments, the hard mask may comprise one or more of amorphous silicon, silicon dioxide, silicon nitride, aluminum oxide, titanium dioxide, ceramic, another semiconductor, and / or other hard mask materials. In some embodiments, a metallic hard mask may be used. In some embodiments, CVD, plasma-enhanced CVD, or other deposition methods may be used at 904.

[0041] At 906, an anti-reflective coating (ARC) layer is provided on the hard mask layer. In some embodiments, the ARC layer is spin-coated onto the hard mask layer. The ARC layer is configured to reduce reflections of DUV electromagnetic radiation from underlying layers during DUV lithography for the DUV mask. In some embodiments, 906 may be omitted.

[0042] At 908, a DUV mask layer is provided on the ARC layer. In some embodiments, the DUV mask layer is a polymer, such as a DUV photoresist. For example, a DUV photoresist such as UV™ 210 Positive DUV Photoresist can be used. In some embodiments, 908 includes a spin-coated DUV mask layer. However, other deposition methods are possible.

[0043] At 910, the DUV mask layer is heat-treated before exposure. Therefore, 910 can be considered as pre-exposure baking or pre-exposure heat treatment. In some embodiments, the heat treatment at 910 is performed at one or more temperatures greater than 140 degrees Celsius. In some embodiments, the heat treatment is at one or more temperatures greater than 145 degrees Celsius. For example, a temperature of 150 degrees Celsius or near 150 degrees Celsius may be used for the heat treatment at 910. In some embodiments, the heat treatment lasts for more than one minute. In some embodiments, at least 70 seconds are used for the heat treatment. In some embodiments, the heat treatment at 910 lasts for at least 80 seconds. For example, an apparatus may be heat-treated for a nominal time of 90 seconds or more at one or more temperatures of 150 degrees Celsius or near 150 degrees Celsius.

[0044] In some embodiments, 910 includes gradually increasing the temperature to which the apparatus is exposed for pre-exposure heat treatment. In some embodiments, the temperature (e.g., the temperature of the mask layer, the temperature of other parts of the apparatus, or the temperature measured in an oven or on a hot plate) increases at a rate not exceeding 140 degrees Celsius per minute. In some embodiments, the rate of temperature increase does not exceed 125 degrees Celsius per minute. In some embodiments, the temperature increases at a rate not exceeding 100 degrees Celsius per minute.

[0045] At 912, the DUV mask layer is selectively exposed to DUV radiation. For example, a wavelength not exceeding 250 nanometers can be used at 912. In some embodiments, 912 includes exposing multiple stitching regions. For example, stitching regions can be exposed while the platform is moved, and another region is exposed using the same or different crosshairs. Thus, the DUV mask layer is selectively exposed to DUV radiation.

[0046] At 914, the DUV mask layer is heat-treated after exposure. Therefore, 914 can be considered as post-exposure baking or post-exposure heat treatment. In some embodiments, the heat treatment at 914 is performed at one or more temperatures greater than 140 degrees Celsius. In some embodiments, the heat treatment is at one or more temperatures greater than 145 degrees Celsius. For example, a temperature of 150 degrees Celsius or near 150 degrees Celsius may be used for the heat treatment at 914. In some embodiments, the heat treatment lasts for more than one minute. In some embodiments, at least 70 seconds are used for the heat treatment. In some embodiments, the heat treatment at 914 lasts for at least 80 seconds. For example, an apparatus may be heat-treated for a nominal time of 90 seconds or more at one or more temperatures of 150 degrees Celsius or near 150 degrees Celsius.

[0047] In some embodiments, 914 includes gradually increasing the temperature to which the apparatus is exposed for post-exposure heat treatment. In some embodiments, the temperature (e.g., the temperature of the mask layer, the temperature of other parts of the apparatus, or the temperature measured, such as in an oven or on a hot plate) increases at a rate not exceeding 140 degrees Celsius per minute. In some embodiments, the rate of temperature increase does not exceed 125 degrees Celsius per minute. In some embodiments, the temperature increases at a rate not exceeding 100 degrees Celsius per minute.

[0048] At step 916, the exposed DUV mask layer is further developed. In some embodiments, post-development baking is not performed. Therefore, portions of the DUV mask layer are removed to form one or more apertures in the DUV mask layer. Thus, a patterned DUV mask is formed.

[0049] At 918, the portion of the ARC layer exposed by the aperture in the DUV mask is removed. For example, the ARC layer may be etched at 918. In some embodiments, 918 may be omitted. In such an embodiment, the ARC layer may be removed using the same process as at 920.

[0050] At 920, the pattern of the DUV mask is transferred to the hard mask layer. In some embodiments, the pattern in the DUV mask is also transferred to the ARC layer. Thus, a hard mask is formed. In some embodiments, 920 includes chemically and / or physically removing portions of the hard mask layer exposed by the pattern in the mask. For example, if the hard mask layer is a silicon dioxide layer, a fluorine-based chemical may be used at 920. In other embodiments, dry etching, RIE, or other etching mechanisms may be used. In some embodiments, the removal at 920 forms apertures in the hard mask layer to provide the hard mask. In this embodiment, the stop layer formed at 902 can prevent damage to the underlying LN layer. In some embodiments, the removal at 920 forms recesses in the hard mask layer to provide the hard mask. Therefore, damage to the LN layer can still be avoided.

[0051] At 922, the pattern of the hard mask can be transferred to the stop layer. This can occur via chemical or physical etching. The etching used to remove the stop layer at 922 is different from one or more of the etching used to pattern the hard mask at 920. In some embodiments, 922 can be omitted.

[0052] At 924, the pattern in the hard mask is transferred to the LN layer. In some embodiments, physical etching is used at 924. For example, dry etching, reactive ion etching (RIE), plasma etching, and / or other physical etching mechanisms may be used. In some embodiments, chemical etching or other removal mechanisms may be used at 924. In some embodiments, the LN layer is not etched through at 924. Therefore, the LN optics may be formed by or include the ridges remaining after partial removal of portions of the LN layer. In some embodiments, the LN layer may be completely etched through in some areas. In embodiments where the hard mask includes recesses rather than apertures, the pattern transfer at 924 also removes at least some of the thinned portions of the hard mask. In some embodiments, the pattern transfer at 924 may also remove some or all of the etch stop layer exposed by the hard mask. The etching used to form the hard mask at 920 may be separated from the etching used to remove portions of the LN layer at 924. Therefore, these etchings can be optimized separately. This can result in smoother sidewalls of the optics(s) being processed.

[0053] At 926, any remaining DUV mask, ARC layer, and / or hard mask can be removed. Fabrication of the device can be completed. For example, the formed LN optical device(s) can be modularized and / or additional components can be fabricated.

[0054] For example, Figure 10-15 An embodiment of an apparatus 1000 comprising LN and formed using method 900 during processing is described. Figure 10-15The drawing is not to scale, and only a portion of device 1000 is shown. Furthermore, device 1000 is for illustrative purposes and may not represent a specific device. For example, sidewalls are shown as vertical and flat, while the top surface is shown as horizontal and flat. However, some variations are generally present.

[0055] Figure 10 The apparatus 1000 is depicted after layers 904, 906, and 908 have been completed. Therefore, it is shown to include a substrate 1001, a bottom layer 1002, an LN layer 1010, a hard mask layer 1030, an ARC layer 1040, and a DUV mask layer 1050, which may include a carrier wafer. The bottom layer 1002 may be an insulator, such as silicon dioxide. In this embodiment, the bottom layer 1002 is depicted as separate from the substrate 1001. In some embodiments, other layers may be present and / or one or more of the layers shown may be omitted. For example, in some embodiments, one or more bottom layers 1002 may be omitted. In the illustrated embodiment, an etch stop layer is not used. Therefore, layers 902 and 922 are omitted.

[0056] Figure 11 The apparatus 1000 is depicted after layers 910, 912, 914, and 916 have been completed. The DUV mask layer 1050 has been pre-baked, selectively exposed to DUV radiation, post-baked, and developed. Thus, the DUV mask 1050A has been formed. A portion of the ARC layer 1040 is exposed by the DUV mask 1050A.

[0057] Figure 12 The device 1000 is depicted after 918 has been completed or a portion of the ARC layer 1040 exposed by the DUV mask 1050A has been removed in other ways (e.g., as part of 920). Thus, a portion of the hard mask layer 1030 is exposed.

[0058] Figure 13 The device 1000 is depicted after step 920 has been completed. Therefore, the pattern of the DUV mask 1050A has been transferred to the hard mask 1030A. In the illustrated embodiment, the hard mask 1030A has recesses 1030B in the areas where the hard mask layer 1030 is etched. Therefore, the pattern of the DUV mask 1050A has been transferred to the hard mask 1030A.

[0059] Figure 14 The device 1000 is depicted after 924 has been completed. Therefore, LN optical devices 1010A and 1010B have been formed. LN device 1010A has sidewalls 1012A and 1014A. LN optical device 1010B has sidewalls 1012B and 1014B.

[0060] Figure 15The image depicts the device 1000 after layer 926 has been completed and the layers above LN optical devices 1010A and 1010B have been removed. The device 1000 may undergo further processing to complete optical and / or other devices using LN optical devices 1010A and / or 1010B.

[0061] The LN optical devices 1010A and 1010B are formed using DUV lithography according to method 900. Therefore, the sidewalls 1012A, 1014A, 1012B, and 1014B of the LN optical devices 1010A and 1010B have improved surface roughness. The short-range RMS surface roughness of each of the sidewalls 1012A, 1014A, 1012B, and 1014B is less than ten nanometers. In some embodiments, the short-range RMS surface roughness of each of the sidewalls 1012A, 1014A, 1012B, and 1014B is no more than five nanometers. In some embodiments, the short-range RMS surface roughness of each of the sidewalls 1012A, 1014A, 1012B, and 1014B is no more than two nanometers.

[0062] Optical devices 1010A and 1010B can have improved performance. In some embodiments, each LN optical device 1010A and 1010B has a signal loss of no more than 5 dB / cm. In some embodiments, each LN optical device 1010A and 1010B has a loss of no more than 2 dB / cm. In some such embodiments, the loss of each LN optical device in LN optical devices 1010A and 1010B is less than 1.0 dB / cm. For example, in some embodiments, this loss may not exceed 0.5 dB / cm.

[0063] Figure 16-21 An embodiment of an apparatus 1600 comprising LN and formed using method 900 during processing is described. Figure 16-21 The drawing is not to scale, and only a portion of device 1600 is shown. Furthermore, device 1600 is for illustrative purposes and may not represent a specific device. For example, the sidewalls are shown as vertical and flat, while the top surface is shown as horizontal and flat. However, some variations are generally present.

[0064] Figure 16The apparatus 1600 is depicted after layers 902, 904, 906, and 908 have been completed. Thus, a substrate 1601, a bottom layer 1602, an LN layer 1610, an etch stop layer 1620, a hard mask layer 1630, an ARC layer 1640, and a DUV mask layer 1650, which may include a carrier wafer, are shown. The bottom layer 1602 may be an insulator, such as silicon dioxide. In this embodiment, the bottom layer 1602 is depicted as separate from the substrate 1601. The etch stop layer 1620 may include amorphous silicon and / or one or more other materials insensitive to one or more etches used for the hard mask layer 1630. In some embodiments, the etch stop layer 1620 may be at least ten nanometers thick and no more than fifty nanometers thick. In some embodiments, the etch stop layer 1620 may also be removed without excessive damage to the underlying LN layer 1610. In some embodiments, other layers may be present and / or one or more of the layers shown may be omitted. For example, in some embodiments, one or more bottom layers 1602 may be omitted.

[0065] Figure 17 The apparatus 1600 is depicted after steps 910, 912, 914, 916, and 918 have been completed. The DUV mask layer 1650 has been pre-baked, selectively exposed to DUV radiation, post-baked, and developed. Thus, the DUV mask 1650A has been formed. A portion of the ARC layer 1640 exposed by the DUV mask 1650A has been removed. Therefore, the ARC layer portion 1640A remains. A portion of the hard mask layer 1630 is exposed.

[0066] Figure 18 The device 1600 is depicted after step 920 has been completed. Therefore, the pattern of the DUV mask 1650A has been transferred to the hard mask 1630A. In the illustrated embodiment, the hard mask 1630A has apertures 1630B in the areas where the hard mask layer 1630 has been etched. Therefore, portions of the etch stop layer 1620 are exposed. Thus, the pattern of the DUV mask 1650A has been transferred to the hard mask 1630A.

[0067] Figure 19 The apparatus 1600 is depicted after the etch stop layer 1620 has been selectively etched at 922, either as part of transferring a pattern to the LN layer 1610. Therefore, the exposed area of ​​the etch stop layer 1620 has been removed, leaving a portion 1620A of the etch stop layer. In some embodiments, at 922, the etch stop layer 1620 does not need to be completely removed. In this embodiment, the LN layer 1610 may be covered by a portion of the etch stop layer. This portion is then removed by pattern transfer at 924.

[0068] Figure 20The device 1600 is depicted after 924 has been completed. Therefore, LN optical devices 1610A and 1610B have been formed. LN device 1610A has sidewalls 1612A and 1614A. LN optical device 1610B has sidewalls 1612B and 1614B.

[0069] Figure 21 The image depicts the device 1600 after 926 has been completed and the layers above the LN optical devices 1610A and 1610B have been removed. The device 1600 may undergo further processing to complete optical and / or other devices using the LN optical devices 1610A and / or 1610B.

[0070] The LN optical devices 1610A and 1610B are formed using DUV lithography according to method 900. Therefore, the sidewalls 1612A, 1614A, 1612B, and 1614B of the LN optical devices 1610A and 1610B have improved surface roughness. The short-range RMS surface roughness of each of the sidewalls 1612A, 1614A, 1612B, and 1614B is less than ten nanometers. In some embodiments, the short-range RMS surface roughness of each of the sidewalls 1612A, 1614A, 1612B, and 1614B does not exceed five nanometers. In some embodiments, the short-range RMS surface roughness of each of the sidewalls 1612A, 1614A, 1612B, and 1614B does not exceed two nanometers.

[0071] Optical devices 1610A and 1610B can have improved performance. In some embodiments, each LN optical device 1610A and 1610B has a signal loss of no more than 5 dB / cm. In some embodiments, each LN optical device 1610A and 1610B has a loss of no more than 2 dB / cm. In some such embodiments, the loss of each LN optical device in LN optical devices 1610A and 1610B is less than 1.0 dB / cm. For example, in some embodiments, this loss may not exceed 0.5 dB / cm.

[0072] Therefore, method 900 provides LN optical devices 1010A, 1010B, 1610A, and / or 1610B that can have improved manufacturability, performance, and reduced sidewall surface roughness. Because DUV lithography is used, production volume can be increased and the time spent processing devices 1000 and 1600 can be reduced, uniformity can be improved, and reproducibility is enhanced. Furthermore, the use of DUV lithography makes it easier to scale the processing of a large number of devices in manufacturing. DUV lithography also allows for larger splicing areas. For example, in some embodiments, a splicing area of ​​at least ten millimeters by ten millimeters can undergo DUV lithography in a single irradiation. In some embodiments, the splicing area can be at least fifteen millimeters by fifteen millimeters. For example, the splicing area can be nominally twenty millimeters by twenty millimeters or larger. Therefore, the number of splices (not shown) is reduced. This not only increases production volume and reproducibility but also reduces misalignment in the optical device. Therefore, the processing and performance of optical devices including LN can be enhanced.

[0073] As discussed above, the processing techniques and apparatus described herein are applicable to one or more other nonlinear optical materials, such as one or more ferroelectric nonlinear optical materials, including but not limited to LT. For example, LT, potassium niobate, gallium arsenide, potassium titanate phosphate, lead zirconate titanate, and / or barium titanate may be used instead of LN or in addition to LN. Therefore, the performance and processing of optical devices incorporating one or more ferroelectric nonlinear optical materials can be improved.

[0074] While the foregoing embodiments have been described in some detail for clarity, the invention is not limited to the details provided. Many alternative ways of implementing the invention exist. The disclosed embodiments are illustrative and not restrictive.

Claims

1. An apparatus comprising: An optical device, at least a portion of which comprises at least one ferroelectric nonlinear optical material, wherein the at least a portion of the optical device is fabricated using ultraviolet (UV) lithography and includes sidewalls of the ferroelectric nonlinear optical material, the sidewalls having a short-range root-mean-square roughness of less than ten nanometers; The sidewalls are fabricated using UV lithography, a first etching, and a second etching. The UV lithography is used to form a mask for fabricating a hard mask from a hard mask layer. The first etching is used to remove a portion of the hard mask layer to form the hard mask. The second etching is used to remove a portion of the ferroelectric nonlinear optical material to form the sidewalls. The second etching is selected from dry etching, reactive ion etching (RIE), plasma etching, and chemical etching. The second etching differs from the first etching, such that the sidewalls have a short-range root mean square roughness of less than ten nanometers.

2. The apparatus of claim 1, wherein the at least one ferroelectric nonlinear optical material comprises at least one selected from lithium niobate, lithium tantalate, potassium niobate, gallium arsenide, potassium titanium oxyphosphate, lead zirconate titanate, and barium titanate.

3. The apparatus of claim 2, wherein the at least one ferroelectric nonlinear optical material is selected from lithium tantalate and lithium niobate.

4. The device of claim 1, wherein the sidewall has a height of at least four hundred nanometers.

5. The device of claim 1, wherein the sidewall is included in at least one splicing region, each splicing region having an area of ​​at least ten millimeters by ten millimeters.

6. The apparatus of claim 51, wherein the short-distance root mean square surface roughness does not exceed five nanometers.

7. The apparatus of claim 1, wherein the at least portion of the optical apparatus has a loss of no more than 2 dB / cm.

8. The device of claim 7, wherein the loss is less than 1.0 dB / cm.

9. The apparatus of claim 8, wherein the loss is less than 0.5 dB / cm.

10. The apparatus of claim 9, wherein the loss does not exceed 0.1 dB / cm.

11. A method of providing an optical device, comprising: A hard mask layer is provided on a ferroelectric nonlinear optical layer, the ferroelectric nonlinear optical layer comprising at least one ferroelectric nonlinear optical material; A mask is provided on the hard mask layer, the mask having a pattern formed using ultraviolet (UV) lithography; A hard mask is formed from the hard mask layer by transferring the pattern onto the hard mask layer; and The pattern is transferred from the hard mask to the ferroelectric nonlinear optical layer to form at least a portion of the optical device including the sidewalls of the ferroelectric nonlinear optical layer, the sidewalls having a short-range root-mean-square roughness of less than ten nanometers.

12. The method of claim 11, wherein providing the mask further comprises: Provide a mask layer; The mask layer is heat-treated at a baking temperature greater than 140 degrees Celsius; After the heat treatment, a portion of the mask layer is exposed using electromagnetic radiation in the UV wavelength range; and After the exposure, the mask layer is developed to form at least one aperture corresponding to the pattern in the mask layer and to form the mask.

13. The method of claim 12, wherein providing the mask further comprises: An additional heat treatment is performed after the exposure and before the development, the additional heat treatment being at an additional temperature greater than 140 degrees Celsius.

14. The method of claim 11, wherein the forming further comprises performing a first etch to remove a portion of the hard mask layer to form the hard mask; and The transfer of the pattern from the hard mask to the ferroelectric nonlinear optical layer further includes performing a second etching to remove a portion of the ferroelectric nonlinear optical material to form the sidewall. The second etching is selected from dry etching, reactive ion etching (RIE), plasma etching, and chemical etching. The second etching is different from the first etching, such that the sidewall has a short-range root mean square roughness of less than ten nanometers.

15. The method of claim 11, wherein forming at least one of the hard masks includes forming a recess in the hard mask layer corresponding to the pattern, and the method further includes providing a stop layer under the hard mask layer and removing a portion of the stop layer after forming the hard mask.

16. The method of claim 11, wherein the pattern comprises a plurality of splicing regions, each of the splicing regions having an area of ​​at least ten millimeters by ten millimeters.

17. The method of claim 11, wherein the hard mask layer comprises at least one of silicon oxide, amorphous silicon, and silicon nitride.

18. The method of claim 11, wherein the ferroelectric nonlinear optical layer comprises at least one of lithium niobate, lithium tantalate, potassium niobate, gallium arsenide, potassium titanium oxyphosphate, lead zirconate titanate, and barium titanate, and wherein the sidewall has a height of at least four hundred nanometers.

19. A method for providing an optical device, comprising: A hard mask layer is provided on a ferroelectric nonlinear optical layer, the nonlinear optical layer comprising at least one ferroelectric nonlinear optical material; A mask is provided on the hard mask layer, the mask having a pattern formed using deep ultraviolet (DUV) lithography, and providing the mask further includes: Provide a mask layer; The mask layer is heat-treated at a first temperature greater than 140 degrees Celsius, the heat treatment comprising increasing the temperature of the mask layer at a rate not exceeding 140 degrees Celsius per minute; A portion of the mask layer is exposed using electromagnetic radiation in the DUV wavelength range; After exposure at a second temperature greater than 140 degrees Celsius, an additional heat treatment is performed, which includes increasing the temperature of the mask layer at an additional rate not exceeding 140 degrees Celsius per minute. After the additional heat treatment, the mask layer is developed to form at least one aperture corresponding to the pattern in the mask layer and to form the mask; A hard mask is formed from the hard mask layer by transferring the pattern onto the hard mask layer; and The ferroelectric nonlinear optical layer is etched to transfer the pattern from the hard mask to the ferroelectric nonlinear optical layer, thereby forming at least a portion of the optical device including the sidewalls of the ferroelectric nonlinear optical layer, the sidewalls having a short-range root mean square roughness of less than ten nanometers, the etching being different from other etching used to form the hard mask by transferring the pattern to the hard mask layer.

20. The method of claim 19, wherein the ferroelectric nonlinear optical layer comprises at least one of lithium niobate, lithium tantalate, potassium niobate, gallium arsenide, potassium titanium oxyphosphate, lead zirconate titanate, and barium titanate.

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