Systems and methods for driving a display with a high bit depth

Abstract

Systems and methods are provided for changing the intensity of pixels of a display. The display subsystem may include: a display driver for receiving image frame data and commands from an image or data source that includes pixel intensity values for bit planes of an image frame; a parser for receiving the image frame data and commands and configured to determine drive waveforms having pixel drive values and pixel drive time intervals for each bit plane of the image frame data; a display backplane for receiving the drive waveforms, the display backplane including a pixel array that includes an array of pixels, each pixel being driven by a pixel circuit; and display driver circuitry for driving the pixels according to the drive waveforms; and wherein the intensity of the pixels varies for each bit plane according to the pixel drive values and the pixel drive time intervals.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 958,019, filed on Jan. 7, 2020. The entire content thereof is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to display systems. More specifically, the present disclosure relates to display systems and methods for changing the intensity of pixels of a display. Exemplary displays may include LED displays, such as a micro-LED display that uses a method combining temporal and amplitude (level) modulation of LEDs to modulate the light emission of LEDs or micro-LEDs. Background Art

[0004] Conventional micro-LED backplanes are either digitally voltage-driven or analog voltage-driven. The driving scheme attempts to convert the digital grayscale (relative luminance) value for each pixel in an image into the amount of light emitted or reflected from each pixel of the display during each frame of the video to be displayed. The digitally voltage-driven type typically has a fixed voltage or current for all bit planes or time intervals within a frame, and the intensity of a pixel is varied by changing the fixed voltage or current level applied in a binary manner. The analog driving scheme provides a static analog voltage or current for the entire video frame, but analog-driven displays suffer from inaccuracies, mismatches (non-uniformities), and drifts of the driving values during the frame time.

[0005] A digital driving scheme is preferred for improving the reproduction of grayscale values as pixel intensities on a display. However, a digital driving scheme that only uses time and on / off states as variables for turning pixels on and off for bit planes or time intervals within a frame to control the intensity (i.e., apparent luminance) of pixels for each frame imposes unnecessary limitations. For example, in a typical digital driving scheme system, an 8-bit color depth means at least 256 bit planes. Using, for example, a PWM scheme where a value of 1 corresponds to one bit plane time high and 255 bit plane times low, and then using a bit plane loading time of 50 μs means a frame minimum time of 256×50 μs = 12.8 ms, or a frame rate of 1 / 12.8 ms = 78.125 Hz. This process does not consider gamma encoding, which would require more bit planes to expand the grayscale data from gamma-encoded values into linear intensity values equivalent to 12, 14, or 16 bits. And thus, in these cases, 2 ^ 12 bit planes are required to correctly represent the desired intensity range.

[0006] If only binary weighted durations are used to represent gray levels (e.g., the MSB has 128 bit planes, MSB - 1 has 64 bit planes, etc.), the limited amount of time available to send the bit planes to the display limits the system's ability to provide a higher frame rate without loss of color depth. When using the PWM (pulse width modulation) method to represent different gray levels, where the pulse duration is proportional to the number of bit plane times that must be sent to the display to achieve the desired gray level, the ability to achieve a higher bit depth is limited by the bit plane time and the number of those bit planes that can fit within the color sub - frame time.

[0007] In addition to compressing the time required to represent different intensity levels, it is also generally possible to apply gamma correction, which is a non - linear operation that, when applied to incoming gamma - encoded gray values, provides, for example, more gray values because the intensity value of each gamma - encoded gray level is converted into a gray value or level that has a non - linear relationship with other gray values or levels, and thus requires a greater bit depth to represent the value digitally correctly. In display systems with a small bit depth and limited by the number of bit planes within the frame time, it is also more difficult to implement gamma correction because it is difficult to represent the intensity with the available small time increments. Therefore, these systems need to use some of the bit depth to map the incoming gray levels to their gamma - corrected values, and this results in a reduction in bit depth or a shortage of time in which to place a sufficient number of bit planes to allow for an accurate representation of the gamma - encoded values. SUMMARY OF THE INVENTION

[0008] In aspects of the present disclosure, a display system for driving pixels of a pixel array is provided. The display system includes: a display subsystem for displaying an image and executing commands from an image or video data source. The display subsystem includes: a display driver circuitry for receiving image frame data and commands from an image or data source, the image frame data including pixel intensity values or luminance values of bit planes of an image frame or sub - frame; a parser for receiving the image frame data and commands and configured to determine a drive waveform having a pixel drive value and a pixel drive time interval for each bit plane of the image frame data; and a display backplane for receiving the drive waveform, the display backplane including pixel driver circuitry for driving the pixels according to the drive waveform, and wherein the intensity or luminance of the pixels varies for each bit plane according to the pixel drive value and the pixel drive time interval.

[0009] Embodiments of the present disclosure combine the ability to instantaneously change the pixel drive current (globally for the entire display) during the course of a frame (e.g., a video frame) with a flexible sequence of bit planes having varying time durations that make up pulses of varying widths to give varying intensity levels. By adding additional variables (e.g., current for an LED or voltage for an LCoS), both time and current / voltage can be used to vary the intensity value represented by any part of the drive waveform or any gray value by having each intensity level represented as the sum of a series of time and current / voltage pairs.

[0010] Embodiments of the present disclosure may include: a) a display backplane IC that includes a display array or matrix composed of or constituted by a plurality of drive pixel circuits, such as current drive pixel circuits (which typically may include pixel logic gates and pixel drivers incorporating current sources such as transistors (e.g., field effect transistors)) to drive LEDs (i.e., pixel elements) coupled to the pixel circuits; b) a drive sequence (which may reside in a driver IC co-located on the backplane IC or logically in the driver) that programs, controls, or is used to change the drive current of the pixel drive circuits by setting a global voltage bias DAC for biasing the current drivers in the pixels such that when the system receives new global bias DAC settings (i.e., coinciding with one or more bit planes) multiple times per video frame, the drive current provided by the pixel circuits to the pixel elements (e.g., micro-LEDs) is instantaneously (i.e., in real time) updated; c) a mechanism, such as an SPI slave, that outputs new binary value updates to a register controlling the bias DAC through the system in accordance with commands embedded in image frame data (which may include video data) such that the bias DAC controls the global bias voltage of the current sources for the pixel array; and d) a sequence memory that stores one or more programmable maps that may vary according to desired performance or in response to environmental conditions (such as ambient lighting and temperature (to provide temperature compensation)) and that are utilized by the display driver logic to convert between input gray levels and the sequence of time-current pairs to be sent to the display backplane IC for each pixel over the course of a frame time to achieve the desired gray value.

[0011] In an embodiment of a system according to the present disclosure, a sequence generated by sequence generation software capable of creating and calibrating such a sequence may divide the available frame time into regions, where each region uses a different current drive value and uses a PWM waveform generated at the output of each pixel drive circuit in each region, as shown in the accompanying drawings. In an embodiment of a drive sequence (i.e., a set of commands that map gray-scale values to bit-plane values, timings, and current drive values) according to an embodiment of the present disclosure, the drive current to each pixel of the display or to at least a portion of the display may be changed simultaneously for each pixel of the display or a portion of the display based on one or more commands, the one or more commands being transmitted to a backplane IC containing pixel driver circuitry, along with or simultaneously with image data being transmitted to a memory element of the drive circuitry of the display. In an embodiment, the drive circuitry may be included in, integrated into, or coupled to the backplane of the display. In an embodiment of the present disclosure, the drive circuitry may or may not be integrated into or included in the backplane and may be electrically coupled to the display via one or more conductive elements.

[0012] According to a second aspect of the present disclosure, there is provided a method of operating a display system, the method comprising the steps of: receiving image frame data and commands from an image or data source, the image frame data including pixel intensity values of bit-planes of an image frame; parsing the image frame data and commands; determining a drive waveform having a pixel drive value and a pixel drive time interval for each bit-plane of the image frame data; driving pixels in a pixel array according to the drive waveform, wherein the intensity of the pixels varies according to the pixel drive value and the pixel drive time interval for each bit-plane.

[0013] Embodiments of the present disclosure overcome the above problems of conventional devices and methods and other disadvantages and deficiencies of the prior art by providing systems, methods, and apparatuses having a flexible drive scheme that allows for real-time parameter changes and enables higher bit depths at higher frame rates.

[0014] Embodiments of the present disclosure combine the ability to change the pixel drive current for the entire display and in real time during the course of an image frame with a flexible sequence of bit planes of varying time durations (i.e., changing the pixel drive current between bit planes of a single image frame). By adding additional variables to be controlled by the system, such as current for LEDs or voltage for liquid crystal on silicon (LCoS), both time and current / voltage can be used to change the intensity value represented by any part of the drive waveform and / or any gray value, which can thus change the brightness of the pixels driven by the drive waveform. Thus, according to embodiments of the present disclosure, a flexible drive system according to the present disclosure can combine two variables, such as time and current or time and voltage, and apply them in combination to represent intensity levels, and can change these parameters (i.e., time, voltage, and current) in real time and synchronously, such that a display according to embodiments of the present disclosure achieves a greater bit depth (color / intensity accuracy) without having to use as much time per frame to display information, thereby allowing for greater accuracy at the same frame rate compared to prior art systems, or a faster frame rate at the same accuracy.

[0015] These and other capabilities of the disclosed subject matter will be more fully understood after reviewing the following figures, detailed description, and claims. It should be understood that the language and terminology used herein is for the purpose of description and should not be regarded as limiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present disclosure is illustrated and described herein with reference to various figures, in which like reference numerals are used throughout to appropriately denote like system components, and in which:

[0017] Figure 1a A block diagram of a display system according to an embodiment of the present disclosure is shown.

[0018] Figure 1b Shows incorporation Figure 1a of a display system of a micro-LED display system.

[0019] Figure 1c Shows incorporation Figure 1a of a display system of an LCOS display system.

[0020] Figure 2 A flowchart of a method of operating a display system according to an embodiment of the present disclosure is shown.

[0021] Figure 3 A drive waveform generated by a method of operating a display system according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0022] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope. Accordingly, the following detailed description is not to be taken in a limiting sense, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0023] The various operations may be described sequentially as a number of discrete operations in a manner that helps to understand the embodiments; however, the order of description should not be construed as implying that these operations are order-dependent.

[0024] Descriptions may use perspective-based descriptions such as up / down, back / front, and top / bottom. Such descriptions are for convenience of discussion only and are not intended to limit the application of the disclosed embodiments.

[0025] The terms “coupled” and “connected” and their derivatives may be used. It should be understood that these terms are not intended to be synonyms. Rather, in a particular embodiment, “connected” may be used to indicate that two or more elements are in direct physical contact with each other. “Coupled” may mean that two or more elements are in direct physical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.

[0026] For descriptive purposes, phrases in the form of “A / B,” “A or B,” or “A and / or B” mean (A), (B), or (A and B). For descriptive purposes, a phrase in the form of “at least one of A, B, and C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). For descriptive purposes, a phrase in the form of “(A)B” means (B) or (AB), i.e., A is an optional element.

[0027] The specification may use the terms “embodiment” or “embodiments,” each of which may refer to one or more of the same or different embodiments. In addition, the terms “comprising,” “comprise,” “including,” “having,” etc., used with respect to embodiments are synonyms and generally are intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “including but not limited to,” etc.).

[0028] Regarding the use of any plural and / or singular terms herein, those skilled in the art may convert the plural to the singular and / or the singular to the plural to suit the context and / or application. For clarity, various singular / plural permutations may be set forth explicitly herein.

[0029] Various embodiments will now be described with reference to the accompanying drawings, in which like reference numerals are always used to refer to like elements. In the following description, for purposes of explanation, numerous specific details are set forth in order to facilitate a thorough understanding of one or more embodiments. However, in some or all instances, it will be apparent that any of the embodiments described below may be practiced without the use of the specific design details described below.

[0030] FIG. 1 shows a display system 100 according to an embodiment of the present disclosure. As Figure 1a shown, a data source 102, such as an image, image data, or video source or video data 104, such as a host. In an embodiment of the present disclosure, the host may include a processor 105, such as an application processor, that executes an application, instructions, or commands 106 (e.g., software) stored in a storage device (e.g., a memory device 107) of the host. In an embodiment of the present disclosure, the host may stream image data or an image, such as video data.

[0031] In an embodiment of the present disclosure, the data source or the host may be, for example, a mobile device, such as a smart phone, a tablet computer, a laptop computer, a head-up display system, a head-mounted device, or a hybrid device (or certain combinations of those mentioned above). In an embodiment of the present disclosure, the image, image data, and / or video data are received by a real-time data software module 107a and / or a MUX 108 of the host 102, and the real-time data software or software module 107a combines the data with commands parsed from a master sequence file containing a desired drive sequence at the multiplexer (MUX) 108 and / or the real-time data software module 107a. Additionally or alternatively, the MUX 108 may be hardware controlled by the real-time data software module 107a. In an embodiment of the present disclosure, the data combined with the commands is combined data output from the data source (e.g., the host) 102 and transmitted to the display subsystem. In an embodiment of the present disclosure, the combined data is output via the real-time data software module 107a and / or the MUX 108 of the data source 102.

[0032] In embodiments of the present disclosure, the combined data is streamed or transmitted via a communication transmission device, a data transmission device, and / or Protocol 110 to a parser logic software module or software 124 in a display driver IC 120 or a display driver circuitry 122 of a display subsystem 120. In embodiments of the present disclosure, the display driver circuitry may be incorporated into an IC (e.g., DDIC 122). In embodiments of the present disclosure, the communication transmission device and / or protocol is a MIPI controller and / or MIPI Protocol 110. In embodiments of the present disclosure, the combined data is transmitted to the MIPI controller, which uses a MIPI PHY (physical layer) to transmit the data to the display subsystem 120. In embodiments of the present disclosure, the combined data is transmitted to the parser 124 of the display driver IC 122. In embodiments of the present disclosure, the combined data is transmitted to the display driver IC 122.

[0033] In embodiments of the present disclosure, the display subsystem 120 may be a micro-LED display subsystem including: a display driver circuitry, a display panel 130 including a backplane circuitry having an integrated or electrically connected or coupled thereto, and a pixel array 140 (e.g., an array of pixel elements, such as an LED pixel array (e.g., a micro-LED pixel array)). In embodiments of the present disclosure, the LED pixel array (e.g., a micro-LED pixel array) is not included in the display backplane IC 130 or the subsystem 120.

[0034] In embodiments of the present disclosure, the display subsystem may be a liquid crystal on silicon (LCoS) display subsystem including: a display driver circuitry, a display device including a liquid crystal material or substance and a backplane having an integrated or electrically connected or coupled thereto, and a pixel array (e.g., an array of pixel elements, such as an array of reflective devices (e.g., an array of mirror elements / devices that operate to control the position of the liquid crystal in the display device when charged)). In embodiments of the present disclosure, the array of reflective devices is not included in the display backplane IC 130 or the subsystem 120.

[0035] In embodiments of the present disclosure, the display driver circuitry is internal to the display subsystem or electrically coupled to the display panel. In embodiments of the present disclosure, at least some of the display driver circuitry may be incorporated into a display driver integrated circuit (DDIC) 122. In embodiments of the present disclosure, the parser 124 may be included, incorporated, and / or integrated into the DDIC 122.

[0036] In an embodiment of the present disclosure, a display driver circuit system or subsystem 120 receives combined data from a communication and data transfer device or system 110 and converts the combined data into Serial Peripheral Interface (SPI) commands 150 and bitplane data 152. In an embodiment of the present disclosure, a parser 124 receives the combined data and parses and / or separates the combined data into commands and image data. Other logic within the DDIC 122 can then convert the image data into bitplane data. The bitplane data can then be output to a display backplane 130. In an embodiment of the present disclosure, the parser 124 and / or the DDIC parse and / or convert the combined data into (SPI) commands 150 and bitplane data 152 that are output to the display backplane 130. In an embodiment of the present disclosure, an SPI slave 163 of the driver IC 122 or the display backplane IC 130 receives the SPI commands. In an embodiment of the present disclosure, the display backplane IC 122 includes an SPI slave 163, one or more storage devices 164 (e.g., registers), a bias DAC 166, display backplane logic (e.g., pixel logic 172) and circuitry (e.g., 174), and optionally pixel electrodes 176.

[0037] In an embodiment of the present disclosure, the SPI commands 150 are commands to write to internal registers or memories. In an embodiment of the present disclosure, the bitplane data 152 is data that determines or controls the intensity or luminance of pixels when sequentially presented to a pixel array and can be in a word arrangement of data representing a series of pixels in a row or column or rectangular sub-region of the pixel array 140 or the display. One of ordinary skill in the art will appreciate that the bit depth can vary but is typically between 6 bits and 10 bits and more typically 8 bits.

[0038] Figure 1b is an illustration of a micro-LED display system 180 which, in an embodiment, can include the display system 100 of the present disclosure. The micro-LED display system 180 generally includes a pixel array 140 of individual pixel LED elements 184 disposed on a substrate 182.

[0039] Similarly, Figure 1cFIG. 0 is an illustration of an LCOS display system 190 having similar components, and in an embodiment, the LCOS display system 190 may also include the display system 100 of an embodiment of the present disclosure. In particular, a substrate 182 is provided to which or with which the display backplane 120 may be coupled. The substrate 182 may be silicon. A reflective device or layer 196, which may be an aluminum layer, has a pixel array 140 disposed thereon and coupled or integrated with the display backplane 120. A liquid crystal layer 193, an alignment layer 198, a transparent electrode (commonly within an indium tin oxide layer) 199, and a glass or other transparent material layer 197 that forms the display complete the structure. In an embodiment, such an LCOS display may include a series of individual square elements.

[0040] In an embodiment of the present disclosure, the display backplane IC 130 may be included in, incorporated into, or integrated into the display backplane 120 (which may be coupled to, for example, a reflective device 186; 196 in an LCOS display system or an LED such as a micro-LED in a micro-LED display system). The pixel array (i.e., micro-LED or LED) may be on its own substrate, where each LED is coupled to a pixel driver on the backplane. In an embodiment of the present disclosure, the display backplane 120 is coupled to a display device 180, 190 (e.g., an LCOS device) or an LCOS pixel array 140 or pixel elements (e.g., a reflective device 186; 196 or an array of LEDs or LEDs (e.g., micro-LEDs)). In an embodiment of the present disclosure, the display device 100 includes a display backplane 120, a display backplane circuitry 130, a pixel circuitry 174 (e.g., as a pixel drive circuitry or pixel circuit), and pixel elements 140a that are coupled (e.g., electrically coupled) to, integrated into, included in, and / or positioned within the DDIC 122. In an embodiment of the present disclosure, the display device 100 (including the DDIC 122) is electrically coupled to the DDIC and forms a display subsystem 120 and is assembled together in the display module 100.

[0041] In an embodiment of the present disclosure, the display subsystem 120 includes a display 197. In an embodiment of the present disclosure (as Figure 1cAs shown in [Fig.], the display 197 is an array of pixel elements 140 disposed on the backplane 120 or coupled to the backplane circuitry (e.g., pixel circuitry 170, pixel drive circuitry, or drive circuitry incorporated into, coupled to, or integrated into the backplane). In an embodiment of the present disclosure, the display subsystem 120 is an LCoS display subsystem of a liquid crystal on silicon (LCoS) display system 190. In an embodiment of the LCoS system 190 according to an embodiment of the present disclosure, the display 197 is a liquid crystal display or a liquid crystal cell (including liquid crystal 193 disposed between two substrates 196, 199), electrically coupled to the backplane 120 or backplane IC of the display subsystem or integrated with the backplane 120 or backplane IC of the display subsystem. In an embodiment of the present disclosure, one of the substrates 196 of the liquid crystal display or liquid crystal cell is the backplane 120 or backplane IC. In an embodiment of the present disclosure, the liquid crystal display or liquid crystal cell 193 is included, integrated into, or electrically coupled to the display backplane integrated circuit 130 (IC) or its substrate. In an embodiment of the present disclosure, the display backplane IC 130 is electrically coupled to one of the sides of the liquid crystal cell, e.g., the non-emitting or image-corresponding light side of the display. In an embodiment of the present disclosure, the liquid crystal cell is coupled to a silicon substrate 182, and the substrate is the same silicon substrate as the side forming the display backplane IC 120 or a silicon substrate coupled to the display backplane IC (e.g., a substrate, e.g., a silicon substrate including drive circuitry, pixel circuitry, pixel circuitry 170, and / or drive circuitry 166).

[0042] In an embodiment of the present disclosure (e.g., Figure 1bAs shown in [figure reference], the display subsystem 120 is a micro-LED display subsystem 180. In an embodiment of the present disclosure, the display subsystem 100 is a micro-LED system 180. In an embodiment of the micro-LED subsystem 180 according to an embodiment of the present disclosure, the display is an array of LEDs 184 or micro-LEDs, which are electrically coupled to the backplane 120 of the display subsystem 100 or the display backplane IC or integrated into the backplane 120 of the display subsystem 100 or the display backplane IC or integrated with the backplane 120 of the display subsystem 100 or the display backplane IC. In an embodiment of the present disclosure, an array of micro-LEDs 184 is included, integrated into the display backplane integrated circuit (IC) 122 and / or its substrate 182 or electrically coupled to the display backplane integrated circuit (IC) 122 and / or its substrate 182. In an embodiment of the present disclosure, the display backplane IC 122 is electrically coupled to one of the sides of the array of LEDs (e.g., micro-LEDs), such as the non-emitting side or the side corresponding to the light of the image of the array of LEDs (e.g., micro-LEDs). In an embodiment of the present disclosure, the array of LEDs 184 (e.g., micro-LEDs) is coupled to the silicon substrate 182, and the substrate is the same silicon substrate as the side forming the display backplane IC 122 or the silicon substrate 182 coupled to the substrate 186 (e.g., the silicon substrate of the display backplane IC) of the display backplane IC 122.

[0043] In an embodiment of the present disclosure, the array of pixels 184 includes pixel elements assembled in the array 140 or pixel elements assembled on the substrate 182 in the array. In an embodiment of the present disclosure, the array of pixels 180 is an array of light-emitting diodes (LEDs). In an embodiment of the present disclosure, the LED can be a micro-LED. In an embodiment of the present disclosure, the array 140 of pixel elements 184 is an array of reflective elements 196 that control the birefringence of the liquid crystal 193 in the LCoS device 190 or other liquid crystal devices. In an embodiment of the present disclosure, the pixel element 184 is a reflective element / device, such as a mirror. In an embodiment of the present disclosure, the pixel array 140 or the array of pixels is formed in, incorporated into, integrated into the display backplane IC 122 or coupled to the display backplane IC 122. In an embodiment of the present disclosure, the DDIC or display driver circuitry drives the operation of the pixel elements (e.g., light-emitting diodes (LEDs), micro-LEDs 184, reflective elements) of the array of pixel elements arranged on the backplane 120 of the display subsystem 100.

[0044] In embodiments of the present disclosure, the display subsystem 100 may further include a register 164, a digital-to-analog converter (DAC) (e.g., a bias DAC) 166, and an SPI slave or receiver 163 for an alternative protocol such as I2C or a custom protocol. In embodiments of the present disclosure, the SPI slave, the register, and the digital-to-analog converter (DAC) (e.g., the bias DAC) are formed in, incorporated into, or integrated with the display driver circuitry, the display backplane circuitry, and / or the display backplane IC or are coupled to the display driver circuitry, the display backplane circuitry, and / or the display backplane IC.

[0045] In embodiments of the present disclosure, the SPI slave 163 is electrically coupled to one or more registers 164 via, for example, an internal parallel bus and a write strobe. In embodiments of the present disclosure, the register is electrically coupled to a DAC (e.g., a bias DAC) 166 via, for example, a 6-bit or 8-bit DAC designed to provide a voltage suitable for biasing a current source in a pixel array. In embodiments of the present disclosure, the DAC (e.g., the bias DAC) is electrically coupled to the pixel array via, for example, a Vref signal. In embodiments of the present disclosure, the SPI slave receives SPI commands from a parser, a DDIC, and / or the display driver circuitry and generates a write strobe and parallel data that are output to one or more registers. In embodiments of the present disclosure, one or more registers receive data and store values that are continuously output to the DAC. In embodiments of the present disclosure, the DAC (e.g., the bias DAC) receives a binary value from one or more registers, converts the value to a voltage, and continuously outputs the voltage to at least a portion of the pixel array.

[0046] In embodiments of the present disclosure, at least some of the pixel elements 140a are coupled to the pixel circuitry 170. In embodiments of the present disclosure, each pixel or each pixel element that is utilized or available is electrically coupled to or integrated with the pixel circuitry. For example, the pixel circuitry shown in FIG. 1 illustrates a bias voltage applied to each pixel or pixel element in the array or each pixel or pixel element available in the array. In embodiments of the present disclosure, a pixel includes a pixel element (e.g., an LED, a micro-LED, or a reflective device) and pixel circuitry.

[0047] In an embodiment of the present disclosure, each pixel circuit 170 includes a pixel logic circuitry 172 coupled to at least one transistor 174 and a pixel electrode 176. In an embodiment of the present disclosure, the pixel logic includes logic elements (e.g., one or more logic gates or combinational logic circuits) that generate a digital output or value (e.g., an on value or an off value, or a one value or a zero value) that is output to one end of a transistor coupled thereto. In an embodiment of the present disclosure, the transistor is a field effect transistor (FET). In an embodiment of the present disclosure, the transistor is electrically coupled to a voltage source or a DAC (e.g., a bias DAC). In an embodiment of the present disclosure, the other end of the transistor is electrically coupled to the pixel electrode 176 or a pixel element. In an embodiment of the present disclosure, the pixel electrode is electrically coupled to a pixel element, such as an LED or a micro-LED. For the purposes of this disclosure, a reference to an LED is also a reference to a micro-LED. In an embodiment of the present disclosure, the display subsystem 120 is a micro-LED display subsystem, and the transistor 174 is an FET. In an embodiment of the present disclosure, the FET drives the micro-LED display and is electrically coupled (e.g., via a wire / cable) directly or indirectly (e.g., via the pixel electrode 176) to the pixel element 140a (e.g., a micro-LED) and serves as a current source to the pixel element. In an embodiment of the present disclosure, the means for on / off control of the pixel element 140a is directly or indirectly coupled to the source terminal of the FET 174. In an embodiment of the present disclosure, the output of the pixel logic is a means for on / off control or activation / deactivation of the pixel element and is connected to the source terminal of the FET 174. In an embodiment of the present disclosure, a bias voltage (e.g., a center bias voltage DAC) is received at the gate terminal of the FET, for example, from a DAC 166 such as the DAC 166 that is electrically coupled to the gate terminal of the FET 174. In an embodiment of the present disclosure, the use of a DAC enables fine (multi-value relative to on / off, e.g., 6-bit or 8-bit precision) control of the drive current.

[0048] As Figure 2As shown, a method 200 for operating a display system 100 according to an embodiment of the present disclosure is described. In an embodiment of the method of operating a display system, the method may include the step of providing the display system 100. According to an embodiment of the present disclosure, a subsequent step 220 may include receiving image frame data and commands from an image data source 120. The image frame data may be received at a real-time data software module 107a and / or a MUX 108 that receives data 194 and / or commands 106. In an embodiment of the present disclosure, the image frame data may be, for example, an image, image data, video, or video data 104 received from a memory 107 in a host 102. In an embodiment, the command 106 is a command to initiate writing bit-plane data to a pixel driver array or to update a register value, such as a bias DAC input data word. In an embodiment of the present disclosure, the real-time data software module 107a and / or the MUX 108 resides on a storage device (e.g., a memory device 107) in the data source 102 or the host. In an embodiment of the present disclosure, the data source 102 is coupled to a processor 105. The processor 105 executes instructions of the real-time data software or module 107a and / or the MUX 108. In an embodiment of the present disclosure, the data source 102 is a host device that includes a processor 105, and the processor 105 executes instructions of the real-time data software or module 107a and / or the MUX 108. In an embodiment of the present disclosure, the real-time data software or module 107a and / or the MUX 108 combines the data and commands in step 230 and generates a combined data output and outputs the combined data output to the display subsystem. By adding the command 106 to the image or video data 104 (or combining the command with the video data) at the MUX 108, the real-time data software module 107a, etc., the application of the command 106 becomes delivered in real time together with the image or video data 104. In an embodiment of the present disclosure, the combined data output is transmitted to the display subsystem via a data communication device, an interface device, and / or a communication protocol (e.g., a MIPI interface) 110 that is electrically coupled to the data source 102 and the display subsystem 120, the display driver circuitry 122, and / or the display driver IC, and may be inside or outside the display subsystem 120.

[0049] In step 240, parser 124 receives the combined data and parses the combined data, and outputs an SPI command 150 and image data - the image data is converted into image data that is converted into bitplane data 152 via the logic in DDIC 122, and the SPI command 150 and the image data are sent to the display backplane and / or the display backplane IC 130 at the same time or at different times (e.g., at different times within the same time period such as a frame or a subframe). In an embodiment, the display subsystem 120 or system according to an embodiment of the present disclosure may use parser 240 (which may be internal or external to the display driver IC) in step 240 to parse the incoming data 110 (e.g., bitplane data) and commands (e.g., commands) and then separate and format and / or convert the incoming data (e.g., bitplane data) and commands into: 1) bitplane data 152 (i.e., data containing the on / off states of at least some of the pixels in the pixels of the display backplane IC within a given time interval of the video frame); 2) local register 126 configuration, which controls the parameters of the bitplane formatting operation performed by the combination of the display driver logic and the backplane 130 by converting the received set of multi-bit gray values into a series of n bitplanes - each bitplane carrying the nth bit of the gray value of all the pixels in the pixel array), such as the time duration for mapping each bit of the incoming video data bit groups in the DDIC; and 3) commands 150 designated for SPI connection to the display backplane IC 130. In step 240, this series of operations constitutes a mechanism or means for delivering an immediate parameter change, which enables the use of both the time duration and the analog drive value corresponding to the intensity when considered together to form a drive waveform 150.

[0050] In step 250, the SPI slave 163 receives the SPI command 150 and converts it into parallel data and a write strobe pulse, and then sends or outputs the data and the strobe pulse to the register 164. In step 260, one or more of the pixel circuits 170 receive the bitplane data (e.g., the instantaneous brightness value or intensity value for each pixel of the display) and modulate their outputs to control the intensity of the pixels.

[0051] In step 270, when a new pixel drive value Vref 152 (i.e., a bias voltage or a drive current) has been written from the parser 124 to the register 164, the SPI command 150 stored in the register 164 is output or sent to the DAC 166, such as a bias DAC. In an embodiment of the present disclosure, when or upon receipt of an update command via the SPI command 150, a new value is written or can be written to the register 164.

[0052] In an embodiment of the present disclosure, in a parser 124 (which may be internal or external to the backplane IC 130), a command (e.g., a change to a global current bias DAC input word) is received, the command 106 is decoded, and an SPI command is transmitted to an SPI slave 163. In an embodiment of the present disclosure, the SPI slave 163 is included in the backplane IC 130 or integrated with or coupled to the backplane IC 130, and when an SPI command 150 is received and stored in a register 164 (if needed), and when indicated by a master drive sequence stored in the driver IC 122 or driver logic, the parser 124 outputs bitplane data 152, which is sequentially loaded into the pixel array 140 to control the state of each pixel 140a over a given time period.

[0053] In step 890, the bias voltage in combination with the output of the pixel logic determines when current flows to the pixel electrode 176, which is electrically coupled to the pixel element 140a (e.g., an LED, a micro-LED, or a mirror) or directly coupled to the pixel element such that the pixel element 140a is turned on or off (i.e., activated or deactivated). In an embodiment of the present disclosure, in step 290, the bias voltage in combination with the output of the pixel logic determines when current flows to the pixel electrode 176, which is electrically coupled to the pixel element 140a (e.g., an LED, a micro-LED, or a mirror) or directly coupled to the pixel element such that the pixel element is turned on (i.e., activated) and emits light at a level of brightness represented by the bitplane value of the bitplane data received at the corresponding pixel element. In an embodiment of the present disclosure, the total light output from the display system 100 according to an embodiment of the present disclosure is, for example, within a video frame for each pixel 140a, the sum of the products of the current value and the on / off state for each pixel (or region of pixels) for each programmed time interval.

[0054] Figure 3 A drive waveform generated according to an embodiment of the present disclosure is shown. According to Figure 2 the steps of bias generation for a pixel array via commands transmitted with incoming video data implemented by the system of FIG. 1 Figure 3 the drive waveform shown in Figure 3 The drive sequence shown in contains update time intervals (where new DAC control words are transmitted to and stored in registers of the backplane IC) and drive time intervals, shown as multiple "current regions", where driving at a certain current level takes a programmable amount of time. The drive waveform for each pixel or series of pixels of the pixel array can be transmitted to the display backplane IC 130 as a command.

[0055] The embodiments herein have many benefits and advantages. The embodiments herein overcome the limitations of analog systems, which only change the current and keep the pixels always powered on, or digital driving will only have binary on / off states. The embodiments of the present disclosure provide a system in which both current and voltage parameters can be simultaneously controlled within a given time period for how long the current is on the pixel. Due to the flexible programmability of the format, various different mapping schemes are feasible and customizable.

[0056] The subject matter described herein can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structural means disclosed in this specification and their structural equivalents, or in combinations thereof. The subject matter described herein can be implemented as one or more computer program products, e.g., tangibly embodied in an information carrier (e.g., in a machine-readable storage device) or implemented in a propagated signal for execution by, or to control the operation of, data processing apparatus (e.g., a programmable processor, a computer, or multiple computers). A computer program (also referred to as a program, software, software application, or code) can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file. A program can be stored in a portion of a file that holds other programs or data, in a single file dedicated to the program being discussed, or in multiple coordinated files (e.g., files that store one or more modules, subroutines, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a communication network.

[0057] The processes and logical flows described in this specification, including the method steps of the subject matter described herein, can be performed by one or more programmable processors executing one or more computer programs to perform the functions of the subject matter described herein by operating on input data and generating output. The processes and logical flows can also be performed by, and the apparatus of the subject matter described herein can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0058] By way of example, processors suitable for executing computer programs include both general and special purpose microprocessors, as well as any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The basic elements of a computer are a processor for executing the instructions and one or more memory devices for storing the instructions and data. Generally, a computer will also include or be operatively coupled to one or more mass storage devices such as magnetic disks, magneto-optical disks, or optical disks for receiving data therefrom or transferring data thereto or both. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, by way of example including: semiconductor memory devices (such as EPROM, EEPROM, and flash memory devices); magnetic disks (such as internal hard disks or removable disks); magneto-optical disks; and optical disks (such as CD and DVD disks). The processor and the memory may be supplemented by, or incorporated in, special purpose logic circuitry.

[0059] The subject matter described herein may be implemented in the following computing systems that include backend components (such as data servers), middleware components (such as application servers), or frontend components (such as client computer mobile devices, wearable devices having a graphical user interface or a web browser through which a user may interact with an implementation of the subject matter described herein), or any combination of such backend, middleware, and frontend components. The components of the system may be interconnected by any form or medium of digital data communication such as a communication network. Examples of communication networks include local area networks (“LANs”) and wide area networks (“WANs”), such as the Internet.

[0060] It should be understood that the disclosed subject matter is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The disclosed subject matter is capable of other embodiments and of being practiced and carried out in various ways. Further, it should be understood that the phraseology and terminology employed herein is for the purpose of description and should not be regarded as limiting. Thus, those skilled in the art will appreciate that the conception upon which this disclosure is based may readily be utilized as a basis for the design of other structures, methods, and systems for carrying out the several purposes of the disclosed subject matter. It is, therefore, important that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the disclosed subject matter.

[0061] Although the disclosed subject matter has been described and illustrated in the foregoing exemplary embodiments, it should be understood that the present disclosure is by way of example only and that many changes may be made to the details of the implementation of the disclosed subject matter without departing from the spirit and scope of the disclosed subject matter, which is limited only by the appended claims.

Claims

1. A display system for driving pixels of a pixel array, comprising: A display subsystem for displaying an image and executing commands from an image or video data source, the display subsystem comprising: A display driver circuitry for receiving image frame data and commands from the image or video data source, the image frame data comprising pixel intensity values or luminance values of bit planes of an image frame or sub-frame; A parser for receiving the image frame data and the commands and configured to determine drive waveforms having pixel drive values and pixel drive time intervals for each bit plane of the image frame data; and A display backplane for receiving the drive waveforms, the display backplane comprising pixel driver circuitry for driving the pixels according to the drive waveforms, and wherein the intensity or luminance of each pixel is represented by a combination of the pixel drive value and the pixel drive time interval, wherein the intensity or luminance of each pixel varies for each bit plane according to both the corresponding pixel drive value and the corresponding pixel drive time interval, Wherein: The drive waveforms for each pixel or series of pixels of the pixel array are transmitted as commands to the display backplane; and The image frame data is transmitted to a memory element of the display driver circuitry.

2. The system according to claim 1, wherein, The display driver circuitry further comprises a digital-to-analog converter driven by a register, the digital-to-analog converter for converting a digital control word to a bias voltage to control the drive current of the pixel driver circuitry for all pixels.

3. The system according to claim 2, wherein The display backplane provides both bit plane digital data and a bias voltage to the pixel driver circuitry for driving all pixels of the pixel array, and wherein the drive waveforms change the pixel drive values.

4. The system according to claim 1, further comprising a sequence memory for storing one or more programmable maps for modifying at least one of the pixel drive values and the pixel drive time intervals according to desired performance or ambient lighting or temperature compensation.

5. The system according to claim 4, wherein, The display driver circuitry converts at least one of the pixel drive values or the pixel drive time intervals according to the programmable map.

6. The system according to claim 1, wherein, The image frame comprises a series of frame regions, each frame region comprising a plurality of bit planes, and each frame region having a different global bias and thus having different intensity values.

7. The system according to claim 1, wherein The image or video data source comprises one or more of an image, image data, or video source.

8. The system according to claim 1, wherein, The image or video data source is a host, the host comprising a processor that executes an application stored on or streamed to the host.

9. The system according to claim 1, wherein The pixel comprises a light-emitting diode, and wherein the pixel drive value comprises a pixel drive current.

10. The system according to claim 9, wherein, The pixel comprises liquid crystal on silicon, and wherein the pixel drive value comprises a voltage.

11. The system according to claim 1, wherein At least one of the display backplane or the display driver circuitry is an integrated circuit.

12. The system according to claim 1, wherein, The display subsystem further includes a receiver for receiving commands from the parser, the receiver generating a write strobe pulse and parallel data that are output to one or more registers.

13. The system according to claim 12, wherein The display subsystem further includes a digital-to-analog converter for determining the pixel drive value based on the value output from the one or more registers.

14. The system according to claim 1, wherein The display driver circuitry includes pixel circuits for each pixel of the pixel array.

15. The system according to claim 14, wherein The pixel circuit includes pixel logic circuitry connected to at least one transistor, and the transistor is connected to a pixel electrode of the pixel, and wherein the pixel logic circuitry includes logic elements that generate digital values that are output to the at least one transistor to activate or deactivate current flowing into the pixel electrode.

16. The system according to claim 15, wherein, The at least one transistor is electrically coupled to a voltage source or a digital-to-analog converter and the pixel electrode, and wherein the transistor is a field effect transistor.

17. The system according to claim 16, wherein, The transistor receives a bias voltage from the voltage source or output of the digital-to-analog converter and provides a drive current to the pixel electrode with fine control.

18. A method of operating a display system, the method comprising: Receiving image frame data and commands from an image or video data source, the image frame data including pixel intensity values of bit planes of an image frame; Parsing the image frame data and commands; Determining drive waveforms having pixel drive values and pixel drive time intervals for each bit plane of the image frame data; And Driving pixels in a pixel array according to the drive waveforms, wherein the intensity of each pixel is represented by a combination of the pixel drive value and the pixel drive time interval, and wherein the intensity of each pixel varies for each bit plane according to both the corresponding pixel drive value and the corresponding pixel drive time interval, Wherein: The drive waveforms for each pixel or series of pixels of the pixel array are transmitted to the display backplane as commands; and The image frame data is transmitted to a memory element of the display driver circuitry.

19. A display subsystem, comprising: A display driver configured to receive image frame data and commands from an image or video data source, the image frame data including pixel intensity values or luminance values of bit planes of an image frame or sub-frame; A parser configured to receive the image frame data and the commands, the parser determining drive waveforms having pixel drive values and pixel drive time intervals for each bit plane of the image frame data; And A display backplane configured to receive the drive waveforms, the display backplane including pixel driver circuitry for driving pixels of a pixel array according to the drive waveforms, wherein the intensity or luminance of each pixel is represented by a combination of the pixel drive value and the pixel drive time interval, and wherein the intensity or luminance of each pixel varies for each bit plane according to both the corresponding pixel drive value and the corresponding pixel drive time interval, Wherein: Drive waveforms for each pixel or series of pixels of the pixel array are transmitted as commands to the display backplane; and The image frame data is transmitted to a memory element of the display driver.

Images