Circuit configuration and electronic device

Abstract

A circuit structure and an electronic device, the circuit structure (100) comprises a first substrate (10), a second substrate (12) and a chip (11); wherein the chip (11) and the second substrate (12) are both carried on the first substrate (10); the second substrate (12) is provided with a cable connection area (121); the chip (11) is electrically connected with the cable connection area (121) on the second substrate (12) through a jumper or a wiring layer on the first substrate (10). The circuit structure (100) can realize flexible setting of the number of cables (13) electrically connected with the chip (11).

Description

Technical Field

[0001] This application relates to chip packaging technology, and in particular to a circuit structure and electronic device. Background Technology

[0002] With the development of electronic science and technology, the operating frequency and functional complexity of chips used in various industries such as communications and the Internet are constantly increasing. Here, "chip" can also refer to a bare die, typically fabricated on semiconductors such as silicon, silicon carbide, and silicon oxide. Because chips are usually small and fragile, they are usually mounted on a substrate and connected to other chips or PCBs via external wiring to achieve their circuit functions. The more complex the chip's circuit structure and the more functions it performs, the more wiring is required.

[0003] In related technologies, multiple connectors are typically placed on the substrate carrying the chip, and connecting lines are connected to the substrate through these connectors. These connectors are usually pluggable and manufactured by connector manufacturers; that is, the number of connecting lines connected by the same type of connector and the applicable signal transmission rate range are usually fixed. Within a certain signal transmission rate range, it becomes impossible to accommodate more connecting lines. Therefore, how to flexibly set the number of connecting lines becomes a problem that needs to be solved. Summary of the Invention

[0004] The circuit structure and electronic equipment provided in this application allow for flexible configuration of the number of cables electrically connected to the chip.

[0005] To solve the above-mentioned technical problems, this application adopts the following technical solution:

[0006] In a first aspect, embodiments of this application provide a circuit structure comprising: a first substrate, a second substrate, and a chip; wherein the chip and the second substrate are both carried on the first substrate; a cable connection area is provided on the second substrate; and the chip is electrically connected to the cable connection area on the second substrate via a jumper or a wiring layer on the first substrate.

[0007] This implementation allows for flexible configuration of the number of connected cables by adjusting the size of the second substrate and the cable density on it. For example, the size of the second substrate can be increased or the cable density on it can be raised to increase the number of connected cables; conversely, the size of the second substrate can be decreased or the cable density on it can be lowered to reduce the number of connected cables. This enables flexible configuration of the number of cables electrically connected to the chip.

[0008] In conjunction with the first aspect, in one possible implementation, the circuit structure further includes a cable; the cable is fixed to the second substrate and electrically connected to the cable connection area.

[0009] In conjunction with the first aspect, in one possible implementation, the chip is encapsulated in a packaging material, and the chip is separated from the second substrate by the packaging material.

[0010] The phrase "chip is encapsulated in packaging material" can mean that the chip is completely encased within the packaging material, or that the top or sides of the chip are exposed to facilitate the attachment of a heatsink. The packaging material can include, but is not limited to, plastic encapsulation materials and metal encapsulation materials.

[0011] In conjunction with the first aspect, in one possible implementation, the chip and the second substrate are encapsulated in a packaging material, and the cable protrudes outward from the packaging material.

[0012] The term "encapsulated material" here can refer to the chip and substrate being completely encapsulated within the encapsulation material, or it can refer to the chip and the second substrate being partially encapsulated. For example, the top or sides of the chip may be exposed to facilitate the attachment of a heatsink, and portions of the second substrate containing cable connection areas may be exposed for cable maintenance.

[0013] In conjunction with the first aspect, in one possible implementation, the cable is soldered to the cable connection area.

[0014] In conjunction with the first aspect, in one possible implementation, a solid adhesive is provided at the welding position between the cable and the cable connection area, the solid adhesive being used to reinforce the welding position.

[0015] In conjunction with the first aspect, in one possible implementation, the cable is bonded to the cable connection area by conductive adhesive.

[0016] In conjunction with the first aspect, in one possible implementation, the second substrate is soldered onto the first substrate by solder balls.

[0017] In conjunction with the first aspect, in one possible implementation, the cable connection area includes a first surface that contacts the solder ball and a second surface that does not contact the solder ball, the cable connection area being disposed on the second surface; the second substrate also has a via, the via connecting the solder ball and the cable connection area; the chip is electrically connected to the cable connection area through a wiring layer on the first substrate, the solder ball, and the via.

[0018] The vias mentioned here can include through-holes and blind vias. The second surface can refer to the surface of the second substrate away from the first substrate, or it can refer to the interior of the second substrate. When the cable connection area is located on the surface of the second substrate away from the first substrate, the vias are through-holes connecting the cable connection area and the solder balls; when the cable connection area is located inside the second substrate, the vias are blind vias connecting the cable connection area and the solder balls.

[0019] In conjunction with the first aspect, in one possible implementation, the first substrate is further provided with a protective ring; the protective ring is disposed in the region between the chip and the second substrate.

[0020] By incorporating a protective ring, damage to the chip during installation can be prevented, thus protecting the chip. Furthermore, the protective ring also prevents moisture from entering the chip, protecting its electrical performance from dampness.

[0021] Secondly, embodiments of this application provide an electronic device, which includes the circuit structure and peripheral circuits as described in the first aspect, wherein the chip in the circuit structure transmits signals to the peripheral circuits through leads. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a top view of a circuit structure provided in an embodiment of this application;

[0024] Figure 2 The embodiments provided in this application are as follows Figure 1 Side view of the circuit structure shown;

[0025] Figure 3 The embodiments provided in this application are as follows Figure 1 Another side view of the circuit structure shown;

[0026] Figure 4 This is a top view of yet another circuit structure provided in the embodiments of this application;

[0027] Figure 5a The embodiments provided in this application are as follows Figure 4 A side view of one implementation of the circuit structure shown;

[0028] Figure 5b The embodiments provided in this application are as follows Figure 4The circuit structure shown is a side view of another implementation method;

[0029] Figure 5c The embodiments provided in this application are as follows Figure 4 The circuit structure shown is a side view of another implementation method;

[0030] Figure 6 This is a top view of yet another circuit structure provided in the embodiments of this application;

[0031] Figure 7 The embodiments provided in this application are as follows Figure 6 Side view of the circuit structure shown;

[0032] Figure 8 This is a top view of yet another circuit structure provided in the embodiments of this application;

[0033] Figure 9 The embodiments of this application provide the following: Figure 8 A cross-sectional view of the circuit structure AA' shown;

[0034] Figure 10 This is a top view of another circuit structure provided in the embodiments of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] The terms "first," "second," and similar terms used in this article do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, "a" or "one" and similar terms do not indicate a quantity limitation, but rather indicate the existence of at least one. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0037] In the implementation of this application, "and / or" describes the relationship between related objects, indicating that there can be three kinds of relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0038] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0039] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple pin lines means two or more pin lines.

[0040] Please refer to Figure 1 , Figure 2 , Figure 4 , Figure 5a , Figure 1 A top view of a circuit structure provided in an embodiment of this application is shown. Figure 2 for Figure 1 The side view of the circuit structure shown. Figure 4 A top view of another circuit structure provided in an embodiment of this application is shown. Figure 5a for Figure 4 The circuit structure shown is a side view.

[0041] exist Figure 1 , Figure 4 In the circuit structure 100, there are a first substrate 10, a chip 11, a second substrate 12, and a cable 13.

[0042] The first substrate 10 includes a first region A1 where a chip is disposed and a second region A2 where no chip is disposed. The chip 11 is disposed in the first region A1 of the first substrate 10. A second substrate 12 is disposed in the second region A2 on the upper surface of the first substrate 10 where no chip is disposed. The lower surface of the second substrate 12 can be soldered onto the first substrate 10 using solder balls 141. A cable connection region 121 can be disposed on the second substrate 12. One or more circuits within the chip 11 are connected via jumpers (e.g.,...). Figure 1 , Figure 2 ) or the wiring layer of the first substrate 10 (e.g. Figure 4 , Figure 5a The chip 11 is electrically connected to the cable connection area 121. The cable connection area 121 is used to fix the cable and realize the electrical connection between the chip 11 and the cable 13. Thus, the chip 11 is connected to the PCB board, other chips, circuits or components through the cable 13, thereby realizing various circuit functions.

[0043] In this embodiment, the chip 11 can be encapsulated by a packaging material, thereby separating the chip 11 from the second substrate 12 by the packaging material. It should be noted that being encapsulated by the packaging material can mean that the chip 11 is completely encapsulated within the packaging material, or it can mean that the top or sides of the chip 11 are exposed to facilitate the attachment of a heat sink. The packaging material can include, but is not limited to, plastic encapsulation materials and metal encapsulation materials.

[0044] Cable 13 typically includes conductors and a shielding layer wrapped around the conductors for electromagnetic shielding. This shielding layer can be made of metal or other materials. When chip 11 is far from other chips or components and high-frequency signals need to be transmitted, the shielding layer on cable 13 can reduce the attenuation of high-frequency signals and ensure the reliability of the transmitted high-frequency signals.

[0045] In one possible implementation, the chip 11 and the second substrate 12 can be encapsulated by a packaging material, with the cable 13 protruding outward from the packaging material. This encapsulation can mean that the chip 11 and the substrate 12 are completely encapsulated within the packaging material, or it can mean that the chip 11 and the second substrate 12 are partially encapsulated. For example, the top or side of the chip 11 may be exposed to facilitate the attachment of a heat sink, and the portion of the second substrate 12 where the cable connection area is located may be exposed for cable maintenance.

[0046] In this embodiment, the upper surface of the second substrate 12 may be provided with a plurality of mutually insulated cable connection areas 121. The cable connection areas 121 may be formed after etching and developing the metal layer. The number of cable connection areas 121 may be the same as the number of leads of the chip 11.

[0047] In one implementation of this embodiment, the cable connection area 121 may be provided with pads, and the cable 13 may be soldered onto the pads of the second substrate 12. Specifically, solder paste may be applied to the pads of the second substrate 12. Then, the solder paste is melted at high temperature. At high temperature, the cable 13 is placed in the molten solder paste. The cable 13 is kept fixed in the solder paste, and the solder paste is cooled, at which point the solder paste solidifies. Thus, the cable 13 is soldered onto the pads through the solder paste.

[0048] In another implementation of this embodiment, conductive adhesive can be applied to the cable connection area 121 of the second substrate 12. Then, the cable 13 is bonded to the cable connection area 121 of the second substrate 12 using the conductive adhesive.

[0049] In one possible implementation, to make the connection between the cable 13 and the second substrate 12 more secure, a solid adhesive 16 can be applied at the connection point of the cable connection area 121 between the cable 13 and the second substrate 12. This solid adhesive 16 is used to reinforce the connection point. Figure 3 As shown.

[0050] In one possible implementation, the chip can be connected to the cable connection area 121 of the second substrate 12 via wire bonding (i.e., via jumper wires) to connect with the cable 13, as shown below. Figure 1 , Figure 2 , Figure 3 As shown. At this time, the chip 11 can be disposed on the first region A1 of the first substrate 10 by means such as sintering or bonding. In this implementation, the first substrate 10 may not have a wiring layer, and the chip 11 can be directly connected to the cable connection area 121 of the second substrate 12 via bonding wire 15. Specifically, when the cable connection area 121 of the second substrate 12 is provided with pads, these pads are typically conductive. One end of the bonding wire 15 is connected to one end of the chip 11 via a pressure bonding process, and the other end is connected to the cable connection area 121 of the second substrate 12 via a pressure bonding process. When the cable connection area 121 of the second substrate 12 is coated with conductive adhesive, one end of the bonding wire 15 is connected to one end of the chip 11 via a pressure bonding process, and the other end is connected to the cable connection area 121 of the second substrate 12 via an adhesive bonding process.

[0051] In one possible implementation, the chip can also be disposed on the surface of the first substrate 10 in a flip-chip or surface-mount configuration. In this case, the chip 11 can be soldered to a first region A1 on the upper surface of the first substrate 10 using solder balls 142, such as... Figure 4 , Figure 5a As shown. The first substrate 10 may have a single layer or multiple wiring layers. The integrated circuit on the chip 11 is electrically connected to the wiring layers on the first substrate 10 via solder balls 142. The wiring layer may include patterned wires 17, which may be disposed on the surface of the first substrate 10 or formed on the wiring layer inside the first substrate 10. Figure 4 The diagram illustrates four conductive lines 17. These four conductive lines 17 are insulated from each other on the first substrate 10; however, they can be electrically connected to one or more circuits within the chip 11 via solder balls 142. In specific applications, the number of conductive lines and their positions on the substrate can be determined based on the chip's structure. The conductive lines can be metal traces, or other materials or types of wires, and are not limited here. In a specific process, a metal layer can be deposited first, and then the metal layer can be etched and developed using photoresist to obtain the conductive lines 17.

[0052] In this implementation, the wire 17 extends from a first region A1 on the first substrate 10 where the chip 11 is disposed to a second region A2 on the first substrate 10 where the chip 11 is not disposed. The cable connection region 121 disposed on the second substrate 12 is connected to the wire 17 via solder balls 142.

[0053] In one possible implementation, the cable connection area can be located on the bottom surface of the second substrate 12 that contacts the solder ball 141, such as... Figure 5b As shown. The cable connection area can be directly connected to the solder ball 141, or connected to the solder ball 141 through a wiring layer provided on the bottom surface. In this way, the chip 11 is electrically connected to the cable 13 through the solder ball 142, the wire 17, the solder ball 141, and the cable.

[0054] In one possible implementation, the cable connection area is located on the top surface of the second substrate 12 that does not contact the solder ball 141, such as... Figure 5a As shown. At this time, vias 18 connecting the top and bottom surfaces of the second substrate 12 can be provided on the second substrate 12. The number of vias 18 can be the same as the number of wires 17 on the first substrate 10. Each wire 17 is led from the lower surface of the second substrate 12 to the cable connection area 121 on the top surface of the second substrate 12 through a wire in one of the vias 18. The position of the vias 18 on the second substrate 12 can be set according to the application scenario and the number of vias 18, and is not specifically limited here. For example, the area formed by the orthographic projection of the via 18 onto the first substrate 10 covers the solder balls 141 of the second area A2. Furthermore, a wiring layer can also be provided within the second substrate 12 to change the position of the vias 18 and the connection relationship between the vias 18 and the solder balls 141. Each cable 13 is bonded to the cable connection area 121 of the second substrate 12 by soldering or by bonding with conductive adhesive. In this way, each lead of chip 11 is led to the area on the first substrate 10 where the second substrate 12 is provided through one of the wires 17. Then, through the solder ball 141 and the wire in the through hole 18, the bottom surface of the second substrate 12 is connected to the cable connection area 121 on the top surface of the second substrate 12. The cable connection area 121 is connected to the cable 13, thereby realizing the signal exchange between chip 11 and the peripheral circuit.

[0055] In one possible implementation, the cable connection area is located inside the second substrate, such as... Figure 5c As shown. At this time, a blind via can be provided on the second substrate 12 to connect the cable connection area and the solder ball 141 (the cable connection area can be directly connected to the solder ball 141 through the blind via, or indirectly connected to the solder ball 141 through the wiring layer inside the second substrate and the blind via). Furthermore, a blind via can be formed on the side of the second substrate 12 away from the chip 11 to connect the cable 13 to the cable connection area. At this time, the chip 11 can be electrically connected to the cable 13 through the solder ball 142, the wire 17, the solder ball 141, and the blind via formed on the second substrate, as shown. Figure 5c As shown.

[0056] In this embodiment, the number of connected cables 13 can be flexibly set by adjusting the size of the second substrate 12 and the cable arrangement density on the second substrate. For example, the size of the second substrate 12 can be increased or the cable arrangement density on the second substrate 12 can be increased to increase the number of connected cables; or the size of the second substrate 12 can be decreased or the cable arrangement density on the second substrate 12 can be reduced to decrease the number of connected cables. Thus, the number of cables electrically connected to the chip can be flexibly set.

[0057] In conventional techniques, the cable 13 is typically directly mounted on the first substrate 10. However, when the cable 13 is directly mounted on the first substrate 10, various factors during the soldering process may damage the first substrate 10, reducing the yield of the cable 13 and increasing manufacturing costs. Compared to directly mounting the cable 13 on the first substrate 10, this embodiment improves the yield of the first substrate 10 by mounting the cable 13 on the second substrate 12. Furthermore, the position of the second substrate 12 on the first substrate 10 can be adjusted to accommodate warping of the first substrate 10, increasing the flexibility of the cable 13 mounting.

[0058] exist Figures 1-5c The diagram illustrates, by way of example, a circuit structure 100 with a second substrate 12. In some implementations, the circuit structure 100 may also be as follows: Figure 6 , Figure 7 As shown. Among them, Figure 6 This is another top view of the circuit structure. Figure 7 for Figure 6 A side view of the circuit structure shown. Figure 6 In the circuit structure 100, a second substrate 12 and a second substrate 22 are respectively disposed on both sides of the chip 11. In other scenarios, the second substrate 12 and the second substrate 22 may also be disposed at other locations on the first substrate 10.

[0059] Preferably, the second substrate 12 and the second substrate 22 are symmetrically disposed at both ends of the chip 11. Cables 13 for connecting to the leads of the chip are respectively disposed on the second substrate 12 and the second substrate 22. The connection relationship between the second substrate 12 and the second substrate 22 and the first substrate 10, the structure of the second substrate 12 and the second substrate 22, the connection method between the cable 13 and the second substrate 12, and the connection method between the chip 11 and the cable 13 can be referred to... Figures 1-5c The relevant descriptions in the illustrated embodiments will not be repeated here. Figure 6 , Figure 7The diagram illustrates, by way of example, a schematic diagram of a structure in which patterned wires are disposed on a first substrate 10 to enable connection between a chip and a lead.

[0060] By providing a second substrate 12 and a second substrate 22 on a first substrate 10, and symmetrically arranging the second substrate 12 and the second substrate 22 on both sides of the chip 11, the manufacturing process can be simplified. For example, a structure such as... Figure 6 When the patterned wires 17 are shown, since the wires 17 are symmetrically distributed at both ends of the chip 11, for Figure 6 One of the wires 17 on the left and one of the wires 17 on the right of the chip 11 are located on the same extension line. During the patterning process, a simple mask can be used to etch and develop the metal layer that forms the wire, thereby improving the yield of the wire fabrication.

[0061] Please continue to refer to this. Figure 8 , Figure 9 This illustrates yet another schematic diagram of the circuit structure provided in this application. Figure 8 This is a top view of the circuit structure. Figure 9 for Figure 8 The circuit structure shown is a cross-sectional view along AA'.

[0062] exist Figure 8 , Figure 9 In the circuit structure 100, a first substrate 10, a chip 11, a chip 21, a second substrate 12, and a second substrate 22 are included. The first substrate 10 includes a first side B1 and a second side B2 opposite to the first side, with the first side B1 and the second side B2 extending along the y-axis. The second substrate 12 is disposed on the side of the first substrate 10 near the first side B1, and the second substrate 22 is disposed on the side of the first substrate 10 near the second side B2. Cables 13 are disposed on the second substrates 12 and 22. The chip 11 is connected to the cable 13 disposed on the second substrate 12 through the second substrate 12; the chip 21 is connected to the cable 13 disposed on the second substrate 22 through the second substrate 22.

[0063] In circuit structures, at least one chip is typically mounted on the same substrate, and it can also support two, three, or even more chips. In some scenarios, each chip may include multiple leads. For example, assuming that two chips are mounted on the first substrate 11, and each chip includes eight leads, the circuit structure would require at least 16 leads. If a second substrate 12 and a second substrate 22 are used to set the leads, then eight leads need to be set on the second substrate 12 and eight leads need to be set on the second substrate 22. Since the same substrate usually extends in one direction (e.g., the second substrate 12 extends along the y-axis), this would fix the eight cables 13 in the y-axis direction, reducing the flexibility of the cable 13 arrangement. Therefore, when there are too many leads in the circuit structure, in order to improve the flexibility of the leads in the circuit structure, multiple second substrates 12 are usually used, and each second substrate has fewer leads (e.g., ...). Figure 8 As shown, two second substrates 12 and two second substrates 22 are respectively provided, and three cables 13 are connected to the upper surface of each second substrate 12 and each second substrate 22.

[0064] Optional, in Figure 8 , Figure 9 In the circuit structure shown, the two second substrates 12 are arranged in a straight line along the y-axis; the two second substrates 22 are arranged in a straight line along the y-axis.

[0065] Optionally, the first substrate 10 further includes a third side B3 extending along the x-axis direction, and a substrate 32 may also be disposed on the first substrate 10 near the third side B3. A cable 13 is disposed on the substrate 32, and the chip 11 or chip 21 is connected to the cable 13 disposed on the substrate 32 via the substrate 32, such as... Figure 10 As shown.

[0066] Optionally, the first substrate 10 further includes a fourth side B4 extending along the x-axis direction, and a substrate 42 may also be disposed on the first substrate 10 near the fourth side B4. A cable 13 is disposed on the substrate 42, and the chip 11 or chip 21 is connected to the cable 13 disposed on the substrate 42 via the substrate 42, such as... Figure 10 As shown.

[0067] It should be noted here that... Figure 10 The illustration schematically shows a scenario where a second substrate 12, a second substrate 22, a substrate 32, and a substrate 42 are respectively disposed on a first substrate 10. Whether the second substrates 12, 22, 32, and 42 need to be disposed simultaneously on the first substrate 10, and the number of each substrate, is determined based on the number of chips, the number of chip leads, the position of the leads on the chips, and the chip packaging method. Furthermore, the number of cables 13 disposed on each substrate is also determined according to the application scenario and is not specifically limited here.

[0068] In circuit structures that include multiple chips, when there are too many leads in the circuit structure, in order to avoid the pattern on the upper surface of the substrate being too complex, or to avoid too many bonding wires between the chip and the leads causing short circuits between adjacent pins, or to avoid too many wires on the same layer causing excessive distributed inductance and distributed capacitance, resulting in signal interference during high-frequency signal transmission, the first substrate 10 is usually provided with multiple wiring layers. The wires in each wiring layer and the wires in the middle wiring layer are interconnected with each lead of the chip through vias, buried vias, etc.

[0069] Specifically, such as Figure 9 As shown, the first substrate 10 is provided with at least two wiring layers. Chip 11 is connected to the second substrate 12 through wires in wiring layer 171, and chip 21 is connected to the second substrate 22 through wires in wiring layer 172. Figure 9 As can be seen, the wires in wiring layer 171 and wiring layer 172 extend from the area where the chip is disposed in the first substrate 10 to the areas where the first substrate 12 and the second substrate 22 are located, respectively. In the area where the chip is disposed, the wires in wiring layer 171 are led to the upper surface of the first substrate 10 through the wires in the through holes, and are connected to the leads of the chip 11; the wires in wiring layer 172 are led to the upper surface of the first substrate 10 through the wires in the through holes, and are connected to the leads of the chip 21. In the area where the first substrate 12 is located, the wires in wiring layer 171 are led to the upper surface of the first substrate 10 through the wires in the through holes, and are connected to the lower surface of the second substrate 12; in the area where the second substrate 22 is located, the wires in wiring layer 172 are led to the upper surface of the first substrate 10 through the wires in the through holes, and are connected to the lower surface of the second substrate 22. The second substrates 12 and 22 may each have multiple through-holes penetrating their upper and lower surfaces. The wires in the wiring layer 171 can be led through these through-holes to the cable connection areas on the upper surface of the second substrate 12, corresponding one-to-one with the cables 13 disposed on the second substrate 12. Similarly, the wires in the wiring layer 172 can be led through these through-holes to the cable connection areas on the upper surface of the second substrate 22, corresponding one-to-one with the cables 13 disposed on the second substrate 22. The mounting processes for cables 13 with the second substrates 12 and 22, for the second substrates 12 and 22 with the first substrate 10, and for chips 11 and 21 with the first substrate 10 can be referenced. Figures 1-5c The relevant descriptions of the circuit structure shown will not be repeated here.

[0070] from Figure 9As can be seen, by forming wires in wiring layers 171 and 172, the wiring can be embedded inside the upper and lower surfaces of the first substrate 10, thereby achieving electrical isolation between the wires located on the two wiring layers, reducing signal interference between the wires, and improving the reliability of signal transmission.

[0071] It should be noted that the number of wiring layers is not limited to... Figure 9 The two layers shown can also include three or four layers, depending on the application scenario. No specific limitation is made here.

[0072] In some alternative implementations, the first substrate 10 is also provided with a protective ring, such as... Figure 8 , Figure 9 As shown. From Figure 8 As can be seen, the protective ring 19 surrounds chips 11 and 21, separating them from the second substrates 12 and 22. By providing the protective ring 19, damage to the chips during installation can be avoided, thus protecting the chips. Furthermore, the protective ring 19 also prevents moisture from entering the chip, preventing moisture from affecting its electrical performance. In this implementation, the first substrate 10 is a multilayer board. Wiring layers 171 are used to bury the wires connecting chip 11 and cable 13 within the first substrate 10, and wiring layers 172 are used to bury the wires connecting chip 21 and cable 13 within the second substrate 12. By burying the wires inside the first substrate 10, compared to placing the wires on the upper surface of the first substrate 10, the protective ring 19 can be prevented from cutting the wires, leading to wire breakage or interconnection of multiple wires, thus improving the contact between the chip and the leads.

[0073] This application also provides an electronic device, which includes... Figures 1-10 The circuit structure 100 shown in any embodiment and the peripheral circuit disposed on the circuit structure 100. The circuit structure 100 is connected to the wires, components or PCB board in the peripheral circuit through the cable 13 shown in any of the above embodiments, so that the chip in the circuit structure 100 can transmit or exchange signals with the components in the peripheral circuit through the cable 13.

[0074] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A circuit structure, characterized in that, It includes a first substrate, a second substrate, and a chip; wherein, Both the chip and the second substrate are mounted on the first substrate; The second substrate has a cable connection area; The chip is electrically connected to the cable connection area on the second substrate via a jumper or a wiring layer on the first substrate. The first substrate is further provided with a protective ring and at least two wiring layers, wherein the at least two wiring layers include wires to embed the wiring of the wires inside the first substrate. The protective ring is disposed in the area between the chip and the second substrate; The chip is encapsulated in a packaging material, which separates the chip from the second substrate.

2. The circuit structure according to claim 1, characterized in that, The circuit structure also includes cables; The cable is fixed on the second substrate and electrically connected to the cable connection area.

3. The circuit structure according to claim 2, characterized in that, The chip and the second substrate are encapsulated in a packaging material, and the cable protrudes outward from the packaging material.

4. The circuit structure according to claim 1 or 3, characterized in that, The cable is welded to the cable connection area.

5. The circuit structure according to claim 4, characterized in that, Solid adhesive is applied at the welding position between the cable and the cable connection area to reinforce the welding position.

6. The circuit structure according to claim 1 or 3, characterized in that, The cable is bonded to the cable connection area with conductive adhesive.

7. The circuit structure according to any one of claims 1-6, characterized in that, The second substrate is soldered onto the first substrate using solder balls.

8. The circuit structure according to claim 7, characterized in that, The cable connection area includes a first surface that contacts the solder ball and a second surface that does not contact the solder ball, with the cable connection area disposed on the second surface; The second substrate is also provided with vias, the vias connecting the solder balls and the cable connection area; The chip is electrically connected to the cable connection area through the wiring layer on the first substrate, the solder balls, and the vias.

9. An electronic device, characterized in that, The circuit includes the circuit structure and peripheral circuitry as described in any one of claims 1-8, wherein the chip in the circuit structure transmits signals to the peripheral circuitry via the cable.

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