Light receiving device for lidar and lidar

Abstract

The application provides a light receiving device of a laser radar, comprising: a plurality of receiving units, wherein each receiving unit comprises at least one photodetector configured to receive a light signal and convert the light signal into an electrical signal; a power switch circuit coupled with the plurality of receiving units respectively, for gating part of the photodetectors in each receiving unit and providing a bias voltage for the part of the photodetectors; and a plurality of integration circuits, each of which is coupled with each receiving unit respectively, for integrating and outputting the electrical signal. The light receiving device of the laser radar provided by the application can reduce the number of power switch circuits, thereby reducing the PCB area, saving cost and power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of laser detection, in particular to a light receiving device of a laser radar and a laser radar comprising the same. BACKGROUND

[0002] Silicon photomultiplier (SiPM) is a commonly used high-sensitivity photodetector, each pixel of which is composed of a plurality of avalanche diodes working in Geiger mode, as shown in FIG. 1, the circuit model of which can be simplified as a diode with a signal output port. Figure 1

[0003] In a laser radar light receiving device using a silicon photomultiplier as a photodetector, by measuring the electrical signal (including current and voltage) on the silicon photomultiplier and integrating it over a period of time, the integration result can represent the number of photons received by the pixel in this period of time.

[0004] Current laser radar systems usually have dozens or even hundreds of photodetectors, such as 128 or 256 photodetectors, in order to realize the current integration function of each photodetector, it is necessary to design a lot of current integration circuits, which is usually unacceptable in terms of cost, power consumption and printed circuit board (PCB) area.

[0005] The contents of the background section merely represent the knowledge of the discloser and do not necessarily represent the state of the art in the field. SUMMARY

[0006] In view of at least one defect of the prior art, the present application provides a light receiving device of a laser radar and a laser radar, which can reduce the number of power switch circuits, thereby reducing the PCB area, saving cost and power consumption.

[0007] The present application provides a light receiving device of a laser radar, comprising:

[0008] a plurality of receiving units, wherein each receiving unit comprises at least one photodetector, the photodetector being configured to receive a light signal and convert the light signal into an electrical signal;

[0009] a power switch circuit coupled with the plurality of receiving units respectively, for gating part of the photodetectors in each receiving unit and providing a bias voltage for the part of the photodetectors;

[0010] a plurality of integration circuits, each integration circuit being coupled with each receiving unit respectively, for integrating and outputting the electrical signal.

[0011] ​According to an aspect of the present application, wherein in each receiving unit, one end of the at least one photodetector is shared and coupled to an input end of the integration circuit, and the unshared end of the at least one photodetector is coupled to the power switch circuit to receive the bias voltage.

[0012] According to an aspect of the present application, wherein the power switch circuit comprises a voltage input end and at least one voltage output end, wherein the voltage input end is configured to receive the bias voltage, and each voltage output end is respectively coupled to the unshared end of one or more photodetectors in each receiving unit.

[0013] According to an aspect of the present application, wherein the power switch circuit further comprises an address input end configured to receive address bits to enable the partial photodetectors and output the bias voltage from the voltage output end corresponding to the address bits.

[0014] According to an aspect of the present application, wherein the integration circuit comprises:

[0015] a first switch unit, a first end of which is coupled to the shared end of the at least one photodetector, a second end of which is grounded, and a control end of which receives a control signal to turn on or off the first switch unit;

[0016] a first capacitor, a first end of which is coupled to the shared end of the at least one photodetector, and a second end of which is grounded, and a first end of which outputs the integration result of the electrical signal as an output end of the integration circuit.

[0017] According to an aspect of the present application, wherein the first switch unit comprises a tri-state buffer, a configured output end of which is coupled to the shared end of the at least one photodetector, and an enable control end of which receives the control signal, and the tri-state buffer is used to switch the state of the output end between a low level and a high impedance state according to the control signal.

[0018] According to an aspect of the present application, wherein when the power switch circuit enables the partial photodetectors in each receiving unit, the first switch unit of the corresponding integration circuit is turned off, the first capacitor is charged, and the time of each charging of the first capacitor is the same; and when the power switch circuit ends the enablement, the first switch unit of the corresponding integration circuit is turned on, and the first capacitor is discharged.

[0019] According to an aspect of the present application, further comprising:

[0020] an analog-to-digital converter coupled to the output end of the integration circuit to sample the integration result of the electrical signal within the time of charging of the first capacitor.

[0021] According to an aspect of the present application, the analog-to-digital converter samples the integration result of the electrical signal each time.

[0022] According to an aspect of the present application, the period of sampling the integration result of the electrical signal by the analog-to-digital converter matches the period of the first switch unit being turned on and off.

[0023] According to an aspect of the present application, the integration circuit comprises:

[0024] a transimpedance amplifier, an input end of which is coupled to a common end of the at least one photodetector;

[0025] a first resistor, a first end of which is coupled to an output end of the transimpedance amplifier, and a second end of which outputs the integration result of the electrical signal as an output end of the integration circuit;

[0026] a second capacitor, a first end of which is coupled to the second end of the first resistor, and a second end of which is grounded.

[0027] According to an aspect of the present application, the receiving unit comprises a photodetector array, the photodetectors being photomultiplier tubes, in each receiving unit, the anodes of a plurality of photomultiplier tubes are commonly connected or the cathodes of a plurality of photomultiplier tubes are commonly connected, the cathodes or the anodes are respectively coupled to one voltage output end of the power switch circuit, and the integration circuit outputs the integration result of the direct current component of the electrical signal.

[0028] The present application also provides a laser radar, comprising:

[0029] a light emitting device configured to emit a probe light beam for probing a target object; and

[0030] The light receiving device as described above, wherein the plurality of receiving units are configured to receive a return light beam reflected by the probe light beam on the target object and convert the return light beam into an electrical signal.

[0031] The present application also provides a method for receiving a radar return using the light receiving device as described above, comprising:

[0032] selecting and providing a bias voltage to part of the photodetectors in each receiving unit through the power switch circuit;

[0033] receiving the return light beam through the selected photodetectors in each receiving unit and converting the return light beam into an electrical signal;

[0034] outputting the electrical signal through the plurality of integration circuits corresponding to the plurality of receiving units.

[0035] The embodiment of the present application provides a light receiving device of a laser radar, part of photoelectric detectors in each receiving unit is selected by a power switch circuit, and an electric signal is integrated and output by an integration circuit coupled with the plurality of receiving units respectively. The light receiving device of the laser radar provided by the present application can reduce the number of power switch circuits, thereby reducing the PCB area, saving the cost and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0036] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of the specification, illustrate the present application, and are used together with the embodiments to explain the present application, and do not constitute a limitation on the present application. In the drawings:

[0037] Figure 1 An anode, a cathode and a fast output port of a silicon photomultiplier are shown;

[0038] Figure 2A A silicon photomultiplier array is shown;

[0039] Figure 2B A pin diagram of the silicon photomultiplier array is shown; Figure 2A A pin diagram of the silicon photomultiplier array is shown;

[0040] Figure 3 Power management and integration circuits of a silicon photomultiplier array in the prior art are schematically shown;

[0041] Figure 4 A light receiving device of a laser radar in the prior art is schematically shown;

[0042] Figure 5 A light receiving device of a laser radar according to a preferred embodiment of the present application is schematically shown;

[0043] Figure 6 A light receiving device of a laser radar according to a preferred embodiment of the present application is schematically shown;

[0044] Figure 7A A light receiving device of a laser radar according to a preferred embodiment of the present application is schematically shown;

[0045] Figure 7B An integration circuit of the light receiving device according to a preferred embodiment of the present application is schematically shown;

[0046] Figure 8 The on-off period of the first switch unit and the charge-discharge period of the first capacitor according to a preferred embodiment of the present application are schematically shown;

[0047] Figure 9 A light receiving device of a laser radar according to a preferred embodiment of the present application is schematically shown;

[0048] Figure 10 A light receiving device of a laser radar according to a preferred embodiment of the present application is schematically shown;

[0049] Figure 11 An integration circuit according to a preferred embodiment of the present application is schematically shown;

[0050] Figure 12 A light receiving device including a single silicon photomultiplier according to a preferred embodiment of the present application is schematically shown;

[0051] Figure 13 A laser radar according to a preferred embodiment of the present application is schematically shown;

[0052] Figure 14 A method of receiving a return light beam according to a preferred embodiment of the present application is shown. DETAILED DESCRIPTION

[0053] Hereinafter, certain exemplary embodiments are described simply. As can be recognized by those skilled in the art, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and description are to be regarded as illustrative in nature and not restrictive.

[0054] In the description of the present application, it is to be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like are based on the orientations or positional relationships shown in the drawings, and are for the purpose of facilitating the description of the present application and simplifying the description only, and do not indicate or imply that the indicated devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are for the purpose of description only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless specifically limited otherwise.

[0055] In the description of the application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, or electrical connection or can communicate with each other; can be directly connected, or indirectly connected through an intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0056] In the present application, unless otherwise explicitly specified and limited, the "upper" or "lower" of the first feature to the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the "upper", "above" and "on" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The "under", "below" and "under" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0057] The following disclosure provides many different embodiments or examples for implementing different structures of the application. In order to simplify the disclosure of the application, the components and arrangements of specific examples are described in the following. Of course, they are only examples, and the purpose is not to limit the application. In addition, the application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0058] The embodiments of the present application are described below in conjunction with the accompanying drawings, it should be understood that the embodiments described herein are only used to illustrate and explain the present application, and are not used to limit the present application.

[0059] In order to make the silicon photomultiplier into working state, it is necessary to apply a voltage Vbias = Vca - Va to the silicon photomultiplier. When no photons enter the photosensitive surface of the silicon photomultiplier, the avalanche diode inside the silicon photomultiplier will not act, so no current will be generated; when the photosensitive surface of the silicon photomultiplier receives photons, the avalanche diode inside the silicon photomultiplier will avalanche, and the silicon photomultiplier will generate current, and the current size can represent the size of the received light intensity.

[0060] Multiple silicon photomultipliers in a laser radar are usually arranged in a one-dimensional linear array, and the anodes or cathodes of the multiple silicon photomultipliers are connected together. As shown in Figure 2A Fig. 1, a silicon photomultiplier array composed of 16 silicon photomultipliers with common anodes, Figure 2B Fig. 2 shows Figure 2A a pin diagram of the silicon photomultiplier array of Fig. 1, where F1-F16 are 16 pulse signal output terminals of the silicon photomultiplier array, C1-C16 are 16 cathodes of the silicon photomultiplier array, and ANODE is a common anode of the silicon photomultiplier array.

[0061] The light receiving device of a laser radar is usually composed of multiple silicon photomultiplier arrays, and only one silicon photomultiplier in each silicon photomultiplier array is usually in working state at the same time. It is easy to know that if there are M silicon photomultiplier arrays in the light receiving device, and the number of silicon photomultipliers in each silicon photomultiplier array is N, then the total number of silicon photomultipliers is M*N.

[0062] Therefore, in order to save power consumption, in the actual light receiving device, an N-of-1 power switch circuit can be used to control the power supply, and only one silicon photomultiplier is powered at a time. The N-of-1 power switch circuit selects one of the N voltage output terminals for power supply at a time, and each voltage output terminal is powered for about several microseconds at a time. During this period, the current generated on the silicon photomultiplier is integrated, and the integration result can represent the number of received photons of the silicon photomultiplier. As shown in Figure 3 Fig. 3, in the prior art, an integration circuit is used in combination with a power switch circuit. Figure 3 The receiving unit shown in Fig. 4 is preferably a silicon photomultiplier array composed of 16 silicon photomultipliers with common anodes, and an integration circuit is used in combination with a 16-of-1 power switch circuit to integrate the current of the currently powered voltage output terminal, where the integration circuit is used to obtain the direct current component to represent the size of the received light intensity; the FASTOUT port (F1-F16) outputs an alternating current pulse signal. The address line of the power switch circuit is A0-A3, as shown in Table 1: when it represents 0 (0000), the voltage output terminal C1 of the power switch circuit is enabled to select the first silicon photomultiplier in the silicon photomultiplier array (selected through the port C1 of the silicon photomultiplier array), and the first silicon photomultiplier in the silicon photomultiplier array is powered through the voltage input terminal VBIAS of the power switch circuit. The first silicon photomultiplier receives the current generated by the echo signal, and integrates the current using the integration circuit to obtain the corresponding voltage value to represent the intensity of the echo signal.

[0063]

[0064]

[0065] Table 1

[0066] Wherein, the current flow direction of the light receiving device is power supply VBIAS -> integration circuit VCC -> integration circuit ACC_IN -> power supply switch circuit VBIAS -> power supply switch circuit C1 -> silicon photomultiplier array C1 -> silicon photomultiplier array common anode ANODE -> ground.

[0067] In the prior art, there are M silicon photomultiplier arrays in the light receiving device of the laser radar, and it is known that in order to realize power management and energy integration, M 16-to-1 power switches and M integration circuits are needed. As shown in Figure 4 , with the increase of the value of M, the cost, PCB area and power consumption of the power switch circuit and the integration circuit will be multiplied.

[0068] The present application provides a light receiving device of a laser radar composed of a power switch circuit and an integration circuit, which only uses one N-to-1 power switch circuit to realize the power management of M*N photoelectric detectors, wherein the M*N photoelectric detectors refer to the light receiving device having M silicon photomultiplier arrays, and each silicon photomultiplier array includes N photoelectric detectors. The light receiving device provided by the present application saves the PCB area and cost, further reduces the volume of the light receiving device, and reduces the power consumption of the radar system.

[0069] According to one preferred embodiment of the present application, as shown in Figure 5 , the present application provides a light receiving device 100 of a laser radar, which includes a plurality of receiving units 110, a power switch circuit 120 and a plurality of integration circuits 130. Each receiving unit 110 includes at least one photoelectric detector, which is configured to receive a light signal and convert the light signal into an electrical signal. The power switch circuit 120 is coupled to each receiving unit 110 respectively, to select and provide a bias voltage for part of the photoelectric detectors in each receiving unit. Each integration circuit 130 is coupled to each receiving unit 110 respectively, to integrate and output the electrical signal.

[0070] As shown in Figure 5 , according to one preferred embodiment of the present application, in the light receiving device 100, the receiving unit 110 includes a photoelectric detector array, and the photoelectric detector is a silicon photomultiplier. In each receiving unit 110, the anodes or cathodes of the plurality of silicon photomultipliers are shared, and the cathodes or anodes are respectively coupled to one of the voltage output terminals of the power switch circuit 120. The integration circuit 130 outputs the integration result of the direct current component of the electrical signal.

[0071] Preferably, in each receiving unit 110, one end of the at least one photodetector is common and coupled to an input of the integration circuit 130, and the non-common end of the at least one photodetector is coupled to the power switching circuit 120 to receive the bias voltage.

[0072] As shown in FIG. 1, the light receiving device 100 includes two receiving units 110-1 and 110-2. Each receiving unit 110 includes a plurality of photodetectors, a power switching circuit 120, and an integration circuit 130. Figure 6 As shown in FIG. 2, according to a preferred embodiment of the present application, the receiving units 110-1 and 110-2 each include a silicon photomultiplier array composed of silicon photomultipliers with 16 common anodes as shown in FIG. 3. Figure 6 As shown in FIG. 3, the silicon photomultiplier array includes 16 silicon photomultipliers with common anodes. The pin diagram of the silicon photomultiplier array is shown in the figure, where C1-C16 are the cathodes of the 16 silicon photomultipliers of the receiving unit 110-1, F1-F16 are the fast output ports of the 16 silicon photomultipliers of the receiving unit 110-1, and ANODE is the common anode of the 16 silicon photomultipliers of the receiving unit 110-1. Figure 6 It is shown in the embodiment that the light receiving device 100 includes two silicon photomultiplier arrays, but those skilled in the art will readily understand that the receiving unit 110 can include more or fewer photodetectors, the light receiving device 100 can include more receiving units 110, or only one receiving unit 110, all of which are within the scope of the present application.

[0073] In the embodiment, the 16 silicon photomultipliers of the silicon photomultiplier array have common anodes and are coupled to the input of the integration circuit 130, and the power switching circuit 120 is gated by being coupled to the cathodes of the 16 silicon photomultipliers respectively and outputs the bias voltage. Those skilled in the art will readily understand that the plurality of silicon photomultipliers of the silicon photomultiplier array can also be connected in parallel with the cathodes, and be gated by independent anodes and output the bias voltage, all of which are within the scope of the present application.

[0074] Preferably, the power switching circuit 120 includes a voltage input and at least one voltage output, where the voltage input is configured to receive the bias voltage, and each voltage output is coupled to the non-common end of one or more photodetectors in each receiving unit 110 respectively. As shown in FIG. 4, the voltage input C1, C2, …, C16 of the power switching circuit 120 is coupled to the non-common end C1, C2, …, C16 of the plurality of photodetectors of the receiving unit 110-1, the receiving unit 110-2 respectively, to output the bias voltage to gate part of the photodetectors. Figure 6

[0075] Preferably, the power switching circuit 120 further includes an address input configured to receive an address bit to gate the part of the photodetectors and output the bias voltage from the voltage output corresponding to the address bit. As shown in FIG. 5, the address input of the power switching circuit 120 is coupled to the address input of the receiving unit 110-1, the receiving unit 110-2 respectively, to output the bias voltage from the voltage output corresponding to the address bit to gate part of the photodetectors. Figure 6 ​As shown, the address input terminals A0-A3 of the power switch circuit 120 are configured to receive address bits and output bias voltages from the voltage output terminals (C1, C2...C16) corresponding to the address bits to select the corresponding photodetectors.

[0076] Figure 6 The pinout diagram of the power switch circuit 120 is also shown. Figure 6 In the illustrated embodiment, the power switch circuit 120 includes an address input terminal A[3:0], a bias voltage input terminal VBIAS, and 16 voltage output terminals C1-C16, which are respectively coupled to the cathodes of the 16 silicon photomultiplier tubes of receiving units 110-1 and 110-2. Based on the input signal from the address input terminal VBIAS, the bias voltage is output from one of the voltage output terminals C1-C16 to select the corresponding silicon photomultiplier tube.

[0077] Figure 6 In this embodiment, each voltage output terminal of the power switch circuit 120 corresponds to a silicon photomultiplier tube, and each silicon photomultiplier tube is selected separately. This is only a preferred embodiment. Those skilled in the art will readily understand that one voltage output terminal of the power switch circuit 120 can select multiple silicon photomultiplier tubes, allowing multiple silicon photomultiplier tubes in receiving units 110-1 and 110-2 to detect simultaneously. This embodiment is also within the protection scope of this invention.

[0078] like Figure 6 As shown, integrator circuits 130-1 and 130-2 are coupled to the common terminal of receiver units 110-1 and 110-2, respectively, to integrate the current generated on the silicon photomultiplier tube within a certain time to characterize the number of received photons.

[0079] Figure 6In the shown embodiment, M=2, N=16, where M represents the total number of silicon photomultiplier arrays of the light receiving device 100, and N represents the number of silicon photomultipliers in one silicon photomultiplier array. Specifically, the common terminals of the receiving unit 110-1 and the receiving unit 110-2 are coupled to the integrating circuit 130-1 and the integrating circuit 130-2, respectively, the voltage output terminals C1-C16 of the power switch circuit 120 are coupled to the port C1-C16 of the receiving unit 110-1 and the receiving unit 110-2, respectively, the address terminals of the power switch circuit 120 are A0-A3, when the input address is 0 (0000), the voltage output terminal C1 of the power switch circuit 120 is enabled to select the first silicon photomultiplier in the receiving unit 110-1 and the receiving unit 110-2, and the first silicon photomultiplier in the receiving unit 110-1 and the receiving unit 110-2 is powered by the voltage input terminal VBIAS, the first silicon photomultiplier receives the echo signal to generate a current (from the cathode to the anode), and the integrating circuit 130-1 and the integrating circuit 130-2 are connected to the anode common terminal ANODE of the receiving unit 110-1 and the receiving unit 110-2, respectively, to integrate the current and obtain the corresponding voltage value to represent the intensity of the echo signal.

[0080] For any M>2, the power switch circuit 120 still only needs one set, and the preferred embodiment of the present application further simplifies the circuit design, reduces the circuit cost, and saves the PCB area.

[0081] According to another preferred embodiment of the present application, the present application also provides a low-cost integrating circuit, as shown in Figure 7A The integrating circuit 130-1 and 130-2 respectively includes: a first switch unit 131 and a first capacitor 132. Wherein the first end of the first switch unit 131 is coupled to the common terminal of at least one photodetector of the receiving unit 110-1, 110-2 (as shown in ANODE), the second end is grounded, and the control end receives a control signal to open or close the first switch unit 131. Figure 7A The first end of the first capacitor 132 is coupled to the common terminal of the at least one photodetector (as shown in ANODE), and the second end is grounded, and the first end is used as the output terminal of the integrating circuit 130 to output the integration result of the electric signal. Figure 7A

[0082] According to one preferred embodiment of the present application, as shown in Figure 7A When the power switch circuit 120 selects part of the photodetectors in the receiving unit 110-1, 110-2, the first switch unit 131 (preferably K1, K2) of the corresponding integrating circuit 130-1, 130-2 is disconnected, and the first capacitor 132 Figure 7A Figure 7A ​​The capacitors C1 and C2 are preferred for charging, and the first capacitor 132 is charged for the same amount of time each time. When the power switch circuit 120 ends the selection, the first switching unit 131 of the corresponding integrating circuit 130 is turned on, and the first capacitor 132 is discharged.

[0083] According to a preferred embodiment of the present invention, such as Figure 7A As shown, one of the silicon photomultiplier tubes is selected using the power switch circuit 120, and the first switching unit 131 ( Figure 7A The control terminal of the preferred switches (K1 and K2) receives the control signal. Taking switch K1 as an example, the control signal uses the system clock, and ACC_CLR1 is high, causing switch K1 to open. The photocurrent generated by the selected silicon photomultiplier tube flows from the cathode to the anode of the silicon photomultiplier tube, which is the first capacitor 132 (…). Figure 7A The preferred method is to charge the capacitor (C1). Figure 8 The charging (integration)-discharging process of capacitor C1 is shown. Typically, the integration time t (charging time) is 1-2 µs. Since the light intensity is usually uniform, the integration process is a linearly increasing process. The voltage V across capacitor C1 is... C1 for:

[0084]

[0085] Depend on Figure 8 It can be seen that, since the number of photons received by each photodetector may be different each time, therefore Figure 8 The current used to charge capacitor C1 varies each time. In the above formula, V0 is the initial voltage across capacitor C1, determined by the characteristics of the first switching unit 131. The first switching unit 131 can be a transistor, MOSFET, analog switch, etc. Since a MOSFET can be equivalent to a very small resistor when it is turned on, when a MOSFET is used as the first switching unit 131, V0 can be considered to be 0, which is closest to the ideal integrating circuit.

[0086] According to a preferred embodiment of the present invention, such as Figure 9 As shown, the integrating circuits 130-1 and 130-2 each include a first switching unit 131 and a first capacitor 132. The first switching unit 131 includes NMOS transistors Q1 and Q2. The gates of NMOS transistors Q1 and Q2 are coupled to ACC_CLR1 and ACC_CLR2, respectively, and the NMOS transistors are controlled according to the output voltages of ACC_CLR1 and ACC_CLR2. The source and drain of NMOS transistors Q1 and Q2 are coupled to the first capacitor 132. Figure 9 The two ends of capacitors C1 and C2 are preferably connected, and the drain is coupled to ACC_OUT1 and ACC_OUT2 as the output terminal of the integration result on capacitors C1 and C2, while the source is grounded.

[0087] According to a preferred embodiment of the present application, the light receiving device 100 further comprises an analog-to-digital converter. As shown in the figure, the analog-to-digital converter (ADC) is coupled with the output terminal (ACC OUT1) of the integration circuit 130-1, to sample the integration result of the electrical signal during the charging time of the first capacitor 132 (preferably C1), to obtain a digital signal representing the integration result, which is input to the FPGA for processing. Figure 7B Figure 7B As shown in the figure, the voltage signal during the charging of the first capacitor 132 (preferably C1) is collected by the analog-to-digital converter (ADC) connected to ACC OUT1, so as to read out the amplitude of the voltage signal. After the integration time t, the first switch unit 131 (preferably K1) is turned on by controlling the control terminal of the first switch unit 131, ACC CLR1 is low, and the first capacitor 132 is discharged, following the RC discharge curve. Then, the next silicon photomultiplier can be selected by the power switch circuit, and the above process is repeated, wherein the time interval of each sampling of the analog-to-digital converter is equal, as shown in the figure, and the dashed line is the voltage sampling time point on the first capacitor 132, which is within the charging time of the first capacitor 132 when the first switch unit 131 is off, and preferably, the voltage sampling time point is the time when the first switch unit 131 is switched from off to on.

[0088] As shown in the figure, the voltage signal during the charging of the first capacitor 132 (preferably C1) is collected by the analog-to-digital converter (ADC) connected to ACC OUT1, so as to read out the amplitude of the voltage signal. After the integration time t, the first switch unit 131 (preferably K1) is turned on by controlling the control terminal of the first switch unit 131, ACC CLR1 is low, and the first capacitor 132 is discharged, following the RC discharge curve. Then, the next silicon photomultiplier can be selected by the power switch circuit, and the above process is repeated, wherein the time interval of each sampling of the analog-to-digital converter is equal, as shown in the figure, and the dashed line is the voltage sampling time point on the first capacitor 132, which is within the charging time of the first capacitor 132 when the first switch unit 131 is off, and preferably, the voltage sampling time point is the time when the first switch unit 131 is switched from off to on. Figure 7B Figure 7B As shown in the figure, the voltage signal during the charging of the first capacitor 132 (preferably C1) is collected by the analog-to-digital converter (ADC) connected to ACC OUT1, so as to read out the amplitude of the voltage signal. After the integration time t, the first switch unit 131 (preferably K1) is turned on by controlling the control terminal of the first switch unit 131, ACC CLR1 is low, and the first capacitor 132 is discharged, following the RC discharge curve. Then, the next silicon photomultiplier can be selected by the power switch circuit, and the above process is repeated, wherein the time interval of each sampling of the analog-to-digital converter is equal, as shown in the figure, and the dashed line is the voltage sampling time point on the first capacitor 132, which is within the charging time of the first capacitor 132 when the first switch unit 131 is off, and preferably, the voltage sampling time point is the time when the first switch unit 131 is switched from off to on. Figure 7B Figure 8 Figure 8

[0089] According to a preferred embodiment of the present application, the period of sampling the integration result of the electrical signal by the analog-to-digital converter matches the period of turning on and off the first switch unit 131.

[0090] ​​​​​Furthermore, the period of some photodetectors in the power switch circuit 120 selecting the receiving unit 110, and the period of the first switching unit 131 being turned on and off, are matched with the sampling period of the analog-to-digital converter. The period t1 during which the analog-to-digital converter samples the integral result of the electrical signal is equal to one complete cycle of ACC_CLR being at a high level and a low level, that is, equal to one cycle of the first switching unit 131 being turned on and off. Preferably, alignment can be achieved through the system clock. By aligning the timing of each trigger signal with the system clock, when the power switch circuit 120 selects a portion of the photodetectors in the receiving unit 110, the first switch unit 131 is turned off, and the first capacitor 132 is charged; when the power switch circuit 120 stops selecting that portion of the photodetectors, the first switch unit 131 is turned on, and the first capacitor 132 stops charging. At this time, the analog-to-digital converter (ADC) coupled to the integrating circuit 130 samples the charging voltage on the first capacitor 132 so that the charging (integration) time of the first capacitor 132 is the same each time, and the analog-to-digital converter (ADC) can sample the peak value of the charging voltage to improve the accuracy of the voltage value used to characterize the number of received photons.

[0091] According to another preferred embodiment of the present invention, the first switching unit 131 includes a tri-state buffer configured to have its output terminal coupled to a common terminal of the at least one photodetector, and to enable the control terminal to receive a control signal. The tri-state buffer is used to switch the state of the output terminal between a low level and a high impedance state according to the control signal.

[0092] like Figure 10 As shown, the power switch circuit 120 selects some of the photodetectors in the receiving units 110-1, 110-2..., where the receiving units 110-1, 110-2... are silicon photomultiplier arrays with 16 silicon photomultiplier tubes, configured to receive optical signals and convert them into electrical signals. The integrating circuits 130-1, 130-2... are coupled to the receiving units 110-1, 110-2... to integrate and output the electrical signal. The integrating circuit 130 includes a first switching unit 131 and a first capacitor 132, where the first switching unit 131 includes a tri-state buffer. Using the tri-state buffer as the first switching unit 131, when nCLR is 1, the output terminal Y of the tri-state buffer is in a high-impedance state (noe), and the current to the first capacitor 132... Figure 10 The diagram shows the charging (integration) of capacitor C, and the voltage signal during capacitor C charging is acquired using an analog-to-digital converter (ADC) to read the amplitude of the voltage signal. When nCLR is 0, the output Y of the tri-state buffer is low, and the charge on the capacitor is released. The tri-state buffer has a switching speed of 3ns, which is faster than that of a MOSFET or analog switch, thereby improving the accuracy of signal acquisition.

[0093] The integrating circuit 130 can also be used as follows:Figure 11 The integral circuit 130 includes a transimpedance amplifier 133, an input end of which is coupled to the common end of the at least one photodetector; a first resistor 134, a first end of which is coupled to the output end of the transimpedance amplifier, and a second end of which outputs the integral result of the electrical signal as an output end of the integral circuit; and a second capacitor 135, a first end of which is coupled to the second end of the first resistor 134, and a second end of which is grounded. The transimpedance amplifier 133 converts the current signal input by ACC_IN into a voltage signal, the voltage signal charges the second capacitor 135 through the first resistor 134, and the back end of ACC_OUT is connected to an analog-to-digital converter for collecting the voltage signal when the second capacitor 135 is charged, so as to read out the amplitude of the voltage signal. In addition to the connection mode shown in the figure, the second capacitor 135 can also be connected in parallel with the transimpedance amplifier 133 to form the integral circuit. Figure 11 The integral circuit 130 includes a transimpedance amplifier 133, an input end of which is coupled to the common end of the at least one photodetector; a first resistor 134, a first end of which is coupled to the output end of the transimpedance amplifier, and a second end of which outputs the integral result of the electrical signal as an output end of the integral circuit; and a second capacitor 135, a first end of which is coupled to the second end of the first resistor 134, and a second end of which is grounded. The transimpedance amplifier 133 converts the current signal input by ACC_IN into a voltage signal, the voltage signal charges the second capacitor 135 through the first resistor 134, and the back end of ACC_OUT is connected to an analog-to-digital converter for collecting the voltage signal when the second capacitor 135 is charged, so as to read out the amplitude of the voltage signal. In addition to the connection mode shown in the figure, the second capacitor 135 can also be connected in parallel with the transimpedance amplifier 133 to form the integral circuit.

[0094] According to another preferred embodiment of the present application, for using a single silicon photomultiplier in a separate package instead of a silicon photomultiplier array, the anodes or cathodes of all the photodiodes are directly connected in parallel, which can be converted into the light receiving device 100 provided by the present application, as shown in the figure. Figure 12 As shown in the figure, the light receiving device 100 includes a plurality of receiving units 110, i.e., receiving units 110-1, 110-2, 110-3, …, wherein each receiving unit 110 includes one photodetector, i.e., a silicon photomultiplier. As shown in the figure, a plurality of silicon photomultipliers are configured as receiving units 110-1, 110-2, … to receive optical signals and convert the optical signals into electrical signals; a power switch circuit 120 controls the conduction and disconnection of each silicon photomultiplier, i.e., selects some silicon photomultipliers in the receiving units 110-1, 110-2, …; and an integral circuit 130 is connected to the common anode of the plurality of receiving units 110, and is used to integrate and output the electrical signals.

[0095] The preferred embodiment of the present application provides a light receiving device of a laser radar, which selects some photodetectors in each receiving unit through a power switch circuit, and integrates and outputs the direct current component of the electrical signals through the integral circuit coupled to the plurality of receiving units. The light receiving device of the laser radar provided by the present application can reduce the number of power switch circuits, thereby reducing the PCB occupation area, saving the cost and power consumption.

[0096] According to one preferred embodiment of the present application, as shown in the figure, the present application also provides a laser radar 200, which includes: Figure 13 As shown in the figure, the laser radar 200 includes:

[0097] a light emitting device 210 configured to emit a probe light beam for detecting a target object; and

[0098] The light receiving device 100 as described above, wherein the plurality of receiving units 110 are configured to receive a return light beam reflected on a target object by the probe light beam and convert the return light beam into an electrical signal.

[0099] According to a preferred embodiment of the present application, as shown in Figure 14 The present application also provides a method 10 for receiving a return light beam using the light receiving device 100 as described above, comprising:

[0100] In step S101, part of the photodetectors in each receiving unit 110 are gated by the power switch circuit 120 and provided with a bias voltage;

[0101] In step S102, the return light beam is received by the gated photodetectors in each receiving unit 110 and converted into an electrical signal;

[0102] In step S103, the electrical signal is integrated and output by the plurality of integrating circuits 130 corresponding to the plurality of receiving units 110.

[0103] In summary, by using the method provided by the present application, the light receiving device containing M*N silicon photomultipliers only needs 1 power switch circuit with M voltage output terminals and M first switch units and first capacitors to achieve, which can save M-1 power switch circuits compared with the original method. Thus, the PCB area and cost are saved, the circuit power consumption is reduced, the volume of the light receiving device is reduced, and the integration of the receiving end of the radar system is improved.

[0104] Finally, it should be noted that: the above only for the preferred embodiments of the present application, and not for limiting the present application, although the foregoing detailed description of the present application is made with reference to the foregoing embodiments, for those skilled in the art, it still can be modified to the technical solutions recorded in the foregoing embodiments, or equivalent replacement of some technical features. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1.A light receiving device of a laser radar, comprising: a plurality of receiving units, wherein each receiving unit comprises a plurality of photodetectors configured to receive a light signal and convert the light signal into an electrical signal; a power switch circuit comprising a voltage output end coupled to each receiving unit to gate a part of the photodetectors in each receiving unit and provide a bias voltage to the part of the photodetectors; a plurality of integration circuits each coupled to a receiving unit to integrate the electrical signal and output an integrated result. wherein in each receiving unit, one end of the plurality of photodetectors is shared and coupled to an input end of the integration circuit, and the other end of the plurality of photodetectors is coupled to the power switch circuit to receive the bias voltage. 2.The light receiving device of claim 1, wherein the power switch circuit comprises a voltage input end configured to receive a bias voltage and at least one voltage output end, and each voltage output end is coupled to the other end of one or more photodetectors in each receiving unit. 3.The light receiving device of claim 2, wherein the power switch circuit further comprises an address input end configured to receive an address bit to gate the part of the photodetectors and output the bias voltage from the voltage output end corresponding to the address bit. 4.The light receiving device of any one of claims 2-3, wherein the integration circuit comprises: a first switch unit having a first end coupled to the shared end of the at least one photodetector, a second end grounded, and a control end receiving a control signal to open or close the first switch unit; a first capacitor having a first end coupled to the shared end of the at least one photodetector and a second end grounded, and the first end as an output end of the integration circuit to output the integrated result of the electrical signal. 5.The light receiving device of claim 4, wherein the first switch unit comprises a tri-state buffer having an output end coupled to the shared end of the at least one photodetector and an enable control end receiving the control signal, and the tri-state buffer is configured to switch the state of the output end between a low level and a high impedance state according to the control signal. 6.The light receiving device of claim 4, wherein when the power switch circuit gates the part of the photodetectors in each receiving unit, the first switch unit of the corresponding integration circuit is turned off, the first capacitor is charged, and the time of each charging of the first capacitor is the same; and when the power switch circuit ends the gating, the first switch unit of the corresponding integration circuit is turned on, and the first capacitor is discharged. 7.The light receiving device of claim 6, further comprising: an analog-to-digital converter coupled to the output end of the integration circuit to sample the integrated result of the electrical signal during the time of each charging of the first capacitor. 8.The light receiving device of claim 7, wherein the analog-to-digital converter samples the integrated result of the electrical signal output by different photodetectors each time. 9.The optical receiving device of claim 7 or 8, wherein a period of sampling the integration result of the electrical signal by the analog-to-digital converter matches a period of turning on and off the first switching unit. 10.The optical receiving device of any one of claims 1-3, wherein the integration circuit comprises: a trans-impedance amplifier, an input end of which is coupled with a common end of the at least one photodetector; a first resistor, a first end of which is coupled with an output end of the trans-impedance amplifier, and a second end of which outputs the integration result of the electrical signal as an output end of the integration circuit; and a second capacitor, a first end of which is coupled with the second end of the first resistor, and a second end of which is grounded. 11.The optical receiving device of claim 1, wherein the receiving unit comprises a photodetector array, the photodetectors being photomultiplier tubes, in each receiving unit, anodes of a plurality of photomultiplier tubes are commonly connected or cathodes of the plurality of photomultiplier tubes are commonly connected, and the cathodes or the anodes are respectively coupled with one voltage output end of the power supply switching circuit, and the integration circuit outputs the integration result of the direct current component of the electrical signal. 12.A laser radar comprising: an optical transmitting device configured to transmit a probe light beam for probing a target object; and the optical receiving device of any one of claims 1-11, wherein the plurality of receiving units are configured to receive a return light beam reflected by the probe light beam on the target object and convert the return light beam into an electrical signal. 13.A method of receiving a return light beam using the optical receiving device of any one of claims 1-11, comprising: selecting, by the power supply switching circuit, part of the photodetectors in each receiving unit and providing a bias voltage for the part of the photodetectors; receiving, by the selected photodetectors in each receiving unit, the return light beam and converting the return light beam into an electrical signal; and outputting, by the plurality of integration circuits corresponding to the plurality of receiving units, the electrical signal. 14.The method of claim 13, wherein the part of the photodetectors in each receiving unit is selected by the power supply switching circuit according to a preset selection rule. ​ ​ ​ ​ ​ ​ ​ ​

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