Method for generating automobile wheel speed signal using logic coding control

Abstract

The present invention discloses a method for generating a vehicle wheel speed signal using logic coding control. The method sets a plurality of voltage input ports with high and low levels connected to the input end based on a circuit of two cascaded operational amplifiers, and resistors with the same resistance are set between the input end and the plurality of voltage input ports with high and low levels. By adjusting the parameter settings in the circuit, the two operational amplifiers are made to work in virtual short and virtual open characteristics, thereby making the circuit simulate and output vehicle wheel speed signals of different current levels. The present invention can simulate the signal of the wheel speed sensor according to different needs without using the actual wheel speed sensor load, and provides an economical and applicable tool for bench testing of automotive electronics.

Description

Technical Field

[0001] The invention belongs to the technical field of automobile bench testing, and is a method for controlling an automobile wheel speed circuit, and is a method for simulating the generation of an automobile wheel speed signal by adopting logic coding control. Background Art

[0002] The ESC system is an important part of automobile safety. Among them, the wheel speed sensor is a key component of the ESC system, responsible for providing the ESC system with the status information of each wheel. Therefore, the wheel speed sensor signal is an indispensable input signal source for the vehicle bench test.

[0003] At present, in the vehicle bench test, the method of generating wheel speed signals includes building a real environment, using a power system such as a motor to drive the gear ring, thereby generating relative rotation with the fixed wheel speed sensor, and then generating the corresponding wheel speed signal. This solution has the disadvantages of high cost of environment construction, long design time, and inconvenient maintenance. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for simulating the generation of automobile wheel speed signals using logic coding control to solve the problems raised in the above-mentioned background technology. The method can simulate the signal of the wheel speed sensor according to different needs without using the actual wheel speed sensor load, thereby providing an economical and applicable tool for bench testing of automobile electronics.

[0005] The technical problem solved by the present invention is achieved by adopting the following technical solutions:

[0006] The method is based on a circuit of two cascaded operational amplifiers, and multiple voltage input ports with high and low levels connected to the input end are set, and resistors with the same resistance are set between the input end and the multiple voltage input ports with high and low levels. By adjusting the parameter settings in the circuit, the two operational amplifiers are made to work in virtual short and virtual open characteristics, so that the circuit simulates and outputs automobile wheel speed signals of different current levels, which solves the problem of simulating the signal of the wheel speed sensor without using the actual wheel speed sensor load.

[0007] The virtual short refers to the voltage at the non-inverting input terminal and the voltage at the inverting input terminal of the operational amplifier being consistent.

[0008] The virtual off state means that the current flowing into the inverting input terminal of the operational amplifier is zero.

[0009] The automobile wheel speed signal generating device adopted in the method is mainly composed of an MCU single-chip computer logic encoding module and a voltage signal conversion current signal module connected in sequence. The output of the MCU single-chip computer logic encoding module is set to four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4, and the four-wire logic square wave signal port is connected to the four input ports of the voltage signal conversion current signal module.

[0010] The frequencies of the four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 output by the MCU single-chip logic encoding module are adjustable through the internal MCU single-chip, and the level of each logic square wave signal port is divided into two types: high level and low level.

[0011] The voltage signal conversion current signal module includes an operational amplifier U22A and an operational amplifier U21B; the non-phase input terminal of the operational amplifier U22A is grounded via a capacitor C58, the non-phase input terminal of the operational amplifier U22A is connected to four input ports GPIO1, GPIO2, GPIO3, and GPIO4 via resistors R81, R82, R83, and R84, respectively, the inverting input terminal of the operational amplifier U22A is grounded via resistors R65 and capacitor C55, the output terminal of the operational amplifier U22A is connected to the inverting input terminal of the operational amplifier U22A via resistor R66, and the output terminal of the operational amplifier U22A is grounded via capacitor C51;

[0012] The output end of the operational amplifier U22A is connected to the non-inverting input end of the operational amplifier U21B, the output end of the operational amplifier U21B is connected to the gate of the MOS tube M1 via the resistor R72, the source of the MOS tube M1 is connected to the inverting input end of the operational amplifier U21B, the source of the MOS tube M1 is grounded via the resistor R68, and the drain of the MOS tube M1 serves as the output port I_OUT of the voltage signal conversion current signal module.

[0013] The MCU single-chip logic encoding module, the voltage signal conversion current signal module, and the controller connection need to share the same ground wire.

[0014] The resistors R81-R84 and the capacitor C58 form a first-order RC low-pass filter for suppressing electromagnetic noise, and the resistance values ​​of the resistors R81-R84 are equal.

[0015] The resistance ratio of the resistor R66 to the resistor R65 is 2:1, and the resistance value of the resistor R68 is 350 Ω.

[0016] The MOS tube M1 is an NMOS tube.

[0017] The innovation of the present invention lies in the ingenious use of an existing circuit of two cascaded operational amplifiers to control the working characteristics of the two operational amplifiers, thereby affecting the amplitude change of the output voltage of the front-stage operational amplifier to control the amplitude of the loop current by the rear-stage operational amplifier, thereby achieving the purpose of controlling the current by the voltage.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] In the absence of actual wheel speed sensor operation, the MCU single-chip logic encoding module outputs different coding instructions to simulate the signal of the wheel speed sensor. It is simple and convenient to use, low cost, and provides an economical and applicable tool for the research and development of automobile test benches. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the overall use and connection of the device of the present invention.

[0021] Figure 2 This is a circuit schematic diagram of the voltage signal conversion current signal module of the present invention.

[0022] Table 1 is a signal logic truth table of the voltage signal conversion current signal module of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0024] like Figure 1 As shown, the specific implementation device includes an MCU single-chip logic encoding module 1 and a voltage signal conversion current signal module 2, which are mainly composed of the MCU single-chip logic encoding module 1 and the voltage signal conversion current signal module 2 connected in sequence. The MCU single-chip logic encoding module 1 outputs a four-wire logic square wave signal port GPIO1, GPIO2, GPIO3, and GPIO4, and the four-wire logic square wave signal port is connected to the four input ports GPIO1, GPIO2, GPIO3, and GPIO4 of the voltage signal conversion current signal module 2. The MCU single-chip logic encoding module 1 and the voltage signal conversion current signal module 2 together constitute a device for simulating the generation of a vehicle wheel speed signal.

[0025] The MCU single-chip logic encoding module 1 outputs four voltage signals of different high and low levels. The voltage signal conversion current signal module 2 receives the four voltage signals and converts the voltage signals into four levels of current signals of 0mA, 7mA, 14mA, and 28mA required by the controller 3 to simulate and obtain different levels of vehicle wheel speed signals.

[0026] In the specific implementation, a controller 3 may also be included. The output port of the voltage signal conversion current signal module 2 is connected to the voltage input port of the controller 3, and the vehicle wheel speed signal is input to the controller 3. The controller 3 receives vehicle wheel speed signals of different current levels to determine the current vehicle operation state, acceleration, deceleration, etc. The controller 3 performs corresponding oil pressure maintenance and pressure reduction actions on the actuator in this state.

[0027] The frequencies of the four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 output by the MCU single-chip logic encoding module 1 are adjustable through the internal MCU single-chip, and the levels of each logic square wave signal port are divided into two types: high level and low level.

[0028] In a specific implementation, the four logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 output by the MCU single-chip logic encoding module 1 have a high level of 3.3V and a low level of 0V.

[0029] like Figure 2 As shown, the voltage signal conversion current signal module 2 includes an operational amplifier U22A and an operational amplifier U21B; the non-phase input terminal of the operational amplifier U22A is grounded via a capacitor C58, the non-phase input terminal of the operational amplifier U22A is connected to four input ports GPIO1, GPIO2, GPIO3, and GPIO4 via resistors R81, R82, R83, and R84, respectively, the inverting input terminal of the operational amplifier U22A is grounded via resistors R65 and capacitor C55, the output terminal of the operational amplifier U22A is connected to the inverting input terminal of the operational amplifier U22A via resistor R66, and the output terminal of the operational amplifier U22A is grounded via capacitor C51;

[0030] At the same time, the positive voltage input terminal and the negative voltage input terminal of the operational amplifier U22A are connected to the power supply voltage and the ground respectively, and the positive voltage input terminal of the operational amplifier U22A is grounded via the capacitor C25.

[0031] The output end of the operational amplifier U22A is connected to the non-inverting input end of the operational amplifier U21B, the output end of the operational amplifier U21B is connected to the gate of the MOS tube M1 via the resistor R72, the source of the MOS tube M1 is connected to the inverting input end of the operational amplifier U21B, the source of the MOS tube M1 is grounded via the resistor R68, and the drain of the MOS tube M1 serves as the output port I_OUT of the voltage signal conversion current signal module 2.

[0032] At the same time, the positive voltage input terminal and the negative voltage input terminal of the operational amplifier U21B are connected to the power supply voltage and the ground respectively, and the positive voltage input terminal of the operational amplifier U21B is grounded via the capacitor C59. The operational amplifier U22A plays the role of voltage amplitude amplification, and the operational amplifier U21B and the MOS tube M1 control the current to achieve the role of step current control.

[0033] In a specific implementation, the resistance ratio of the resistor R66 to the resistor R65 is 2:1, the resistance value of the resistor R68 is 350Ω, and the MOS tube M1 is an NMOS tube.

[0034] In a specific implementation, for the four ports GPIO1, GPIO2, GPIO3, and GPIO4 of the MCU single-chip logic encoding module (1), the port GPIO1 is connected to one end of the resistor R81, the port GPIO2 is connected to one end of the resistor R82, the port GPIO3 is connected to one end of the resistor R83, and the port GPIO4 is connected to one end of the resistor R84.

[0035] Among them, point A is set at the non-inverting input terminal of the operational amplifier U22A, point B is set at the inverting input terminal of the operational amplifier U22A, point C is set at the output terminal of the operational amplifier U22A, and point D is set at the inverting input terminal of the operational amplifier U21B.

[0036] Resistors R81, R82, R83 and R84 are all connected to point A; one end of capacitor C58 is connected to point A, and the other end is grounded.

[0037] The specific model of the operational amplifier U22A is OP-2810. Pin VIN1+ is connected to point A as the non-inverting input terminal. Pin V+ is simultaneously connected to the power supply terminal +12V and one end of capacitor C25. The other end of capacitor C25 is grounded. Pin V- of the operational amplifier U22A is grounded. Pin VIN1- is connected to resistor R56, capacitor C55, and a section of resistor R66 as the inverting input terminal. One end of resistor R65 is connected to point C, the other end of resistor R65 is grounded, the other end of capacitor C55 is grounded, point C is grounded via capacitor C51, and pin VO1 of the operational amplifier U22A is connected to point C as the output terminal.

[0038] The operational amplifier U21B model is OP-2810, and the pin VIN2+ is connected to point B as the non-inverting input terminal, and the pin VIN2- of the operational amplifier U21B is connected to one end of the resistor R68 and the source pin No. 3 of the MOS tube M1 at point D as the inverting input terminal, and the other end of the resistor R68 is grounded. The pin V+ of the operational amplifier U21B is connected to the power supply terminal +12V and one end of the capacitor C59 respectively, and the other end of the capacitor C59 is grounded. The pin V- of the operational amplifier U21B is grounded, and the pin VO2 of the operational amplifier U21B is connected to one end of the resistor R72, and the other end of the resistor R72 is connected to the gate pin No. 1 of the MOS tube M1. The drain pin No. 2 of the MOS tube M1 is connected to the input end of the controller 3 as the I_OUT port.

[0039] The operational amplifier U22A and the operational amplifier U21B in the specific implementation of the present invention work in a state of deep negative feedback, and at this time, the two operational amplifiers work in their virtual short and virtual open characteristics. Virtual short means that the voltage at the non-inverting input terminal and the inverting input terminal of the operational amplifier are consistent, and virtual open means that the current flowing into the inverting input terminal of the operational amplifier is zero.

[0040] For the virtual short of the operational amplifier U22A and the operational amplifier U21B, that is, the voltages at the pin voltage VIN1+ and the pin voltage VIN1- of the operational amplifier U22A are consistent, and the voltages at the pin voltage VIN2+ and the pin voltage VIN2- of the operational amplifier U21B are consistent.

[0041] When the operational amplifier U22A and the operational amplifier U21B are virtually disconnected, the current flowing into the pin VIN1- of the operational amplifier U22A is almost zero, and the current flowing into the pin VIN1- of the operational amplifier U21B is almost zero.

[0042] In a specific implementation, operational amplifier U22A and operational amplifier U21B operate in virtual short and virtual open characteristics.

[0043] According to the two characteristics of virtual short and virtual open, the input voltage V1 represents the size of the GPIO1 input voltage, the input voltage V2 represents the size of the GPIO2 input voltage, the input voltage V3 represents the size of the GPIO4 input voltage, and the input voltage V4 represents the size of the GPIO4 input voltage.

[0044] The resistance values ​​of R81, R82, R83, and R84 are equal. According to the superposition theorem of linear circuits, the voltage at point A is (V1+V2+V3+V4) / 4. Because the voltage at the positive input terminal of pin 3 of the virtual short operational amplifier U22A is almost equal to the voltage at the negative input terminal of pin 2, the voltage at point B at the output of the operational amplifier U22A is (V1+V2+V3+V4) / 4. Since point C is connected to the ground through resistor R66, point B, and resistor R65 in turn, and the resistance ratio of resistors R66 and R65 is 2:1, according to the virtual disconnection characteristics of the operational amplifier U22A, the voltage at point C is 3*(V1+V2+V3+V4) / 4.

[0045] Since the voltage at the non-inverting input terminal of pin 5 of the virtual short operational amplifier U21B is almost equal to the voltage at the inverting input terminal of pin 6, the voltage at point D at the output terminal of the operational amplifier U21B is: 3* (V1+V2+V3+V4) / 4.

[0046] The current flowing into the resistor R68 is: 3*(V1+V2+V3+V4) / (4*R68). Since the operational amplifier U21B satisfies the virtual off state, the current flowing through the resistor R68 and the current of the output port I_OUT are: 3*(V1+V2+V3+V4) / (4*R68).

[0047] When R68=350Ω is set, the output current terminal I_OUT≈0.0021*(V1+V2+V3+V4).

[0048] When V1 input logic is high, the potential is 3.3V; V2, V3, V4 input logic is low, the potential is 0V: it is obtained that I_OUT = 0.0021*(3.3+0+0+0)≈7mA.

[0049] When V1 and V2 inputs are logic high, the potential is 3.3V; V3 and V4 inputs are logic low, the potential is 0V: it is obtained that I_OUT = 0.0021*(3.3+3.3+0+0)≈14mA.

[0050] When V1, V2, and V3 inputs are logic high, the potential is 3.3V; V4 input is logic low, the potential is 0V: it is obtained that I_OUT = 0.0021*(3.3+3.3+3.3+0)≈21mA.

[0051] When V1, V2, V3, and V4 inputs are logic high, the potential is 3.3V; it is obtained that I_OUT = 0.0021*(3.3+3.3+3.3+3.3)≈28mA.

[0052] In a specific implementation, the four logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 output by the MCU single-chip logic encoding module (1) have a high level of 3.3V representing 1 and a low level of 0V representing 0.

[0053] The combination of the four logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 is shown below:

[0054] Table 1

[0055] GPIO1 GPIO2 GPIO3 GPIO4 I_OUT 0 0 0 0 ≈0mA 1 0 0 0 ≈7mA 1 1 0 0 ≈14mA 1 1 1 0 ≈21mA 1 1 1 1 ≈28mA

[0056] As can be seen in the table,

[0057] When the level types of the logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 are 0, 0, 0, and 0 respectively, the output port I_OUT = 0mA;

[0058] When the level types of the logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 are 1, 0, 0, and 0 respectively, the output port I_OUT = 7mA;

[0059] When the level types of the logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 are 1, 1, 0, and 0 respectively, the output port I_OUT = 14mA;

[0060] When the level types of the logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 are 1, 1, 1, and 0 respectively, the output port I_OUT = 21mA;

[0061] When the level types of the logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 are 1, 1, 1, and 1 respectively, the output port I_OUT=28mA.

[0062] The embodiment of the present invention is described by taking the output port I_OUT generating a 1 kHz, 50% duty cycle, low 7 mA, high 14 mA current square wave signal as an example.

[0063] Step 1: If Figure 1 As shown, the four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 output by the MCU single-chip logic encoding module 1 are sent to the voltage signal conversion current signal module 2, and the output port I_OUT of the voltage signal conversion current signal module 2 is connected to the controller 3.

[0064] Step 2: Initialize the output port I_OUT current to 0mA, and control the MCU single-chip logic encoding module to output the corresponding four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4 with a level logic type of 0, 0, 0, 0;

[0065] Step 3: The MCU logic encoding module 1 switches the output of the four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4. The level logic type is 1, 0, 0, 0, and the holding time is 0.5ms. At this time, the output port I_OUT current is 7mA.

[0066] Step 4: The MCU single-chip logic encoding module 1 switches the output of the four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3, and GPIO4, and the level logic type is 1, 1, 0, 0, and the holding time is 0.5ms. At this time, the output port I_OUT current is 14mA.

[0067] Step 5: Repeat steps 3 and 4, the device can continuously generate a 1KHz, 50% duty cycle, low 7mA, high 14mA current square wave signal to provide to the controller 3.

[0068] In addition to the above preferred embodiments, the present invention has other implementation modes. Those skilled in the art may make various changes and modifications based on the present invention. As long as they do not depart from the spirit of the present invention, they should all fall within the scope defined in the claims of the present invention.

[0069] Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Claims

1. A method for generating a vehicle wheel speed signal using logic coding control, Features: Methods: Based on a circuit of two operational amplifiers cascaded, multiple voltage input ports with high and low levels connected to the input end are set, and resistors with the same resistance are set between the input end and the multiple voltage input ports with high and low levels. By adjusting the parameter settings in the circuit, the two operational amplifiers are made to work in virtual short and virtual open characteristics, so that the circuit simulates the output of automobile wheel speed signals of different current levels. The virtual short refers to the voltage at the positive input terminal and the voltage at the negative input terminal of the operational amplifier being consistent; The virtual disconnection means that the current flowing into the inverting input terminal of the operational amplifier is zero; The method adopts an automobile wheel speed signal generating device, which is mainly composed of an MCU single-chip logic encoding module (1) and a voltage signal conversion current signal module (2) connected in sequence. The MCU single-chip logic encoding module (1) outputs a four-wire logic square wave signal port GPIO1, GPIO2, GPIO3, and GPIO4, and the four-wire logic square wave signal port is connected to four input ports of the voltage signal conversion current signal module (2).

2. A method for generating a vehicle wheel speed signal using logic coding control according to claim 1, Features: The frequencies of the four-wire logic square wave signal ports GPIO1, GPIO2, GPIO3 and GPIO4 output by the MCU single-chip logic encoding module (1) are adjustable through the internal MCU single-chip, and the level of each logic square wave signal port is divided into two types: high level and low level.

3. A method for generating a vehicle wheel speed signal using logic coding control according to claim 1, Features: The voltage signal conversion current signal module (2) comprises an operational amplifier U22A and an operational amplifier U21B; the non-phase input terminal of the operational amplifier U22A is grounded via a capacitor C58, the non-phase input terminal of the operational amplifier U22A is connected to four input ports GPIO1, GPIO2, GPIO3, and GPIO4 via resistors R81, R82, R83, and R84, respectively; the inverting input terminal of the operational amplifier U22A is grounded via resistors R65 and capacitor C55, respectively; the output terminal of the operational amplifier U22A is connected to the ground via resistors R66 The output end of the operational amplifier U22A is connected to the inverting input end of the operational amplifier U22A, and the output end of the operational amplifier U22A is grounded via the capacitor C51; the output end of the operational amplifier U22A is connected to the non-inverting input end of the operational amplifier U21B, and the output end of the operational amplifier U21B is connected to the gate of the MOS tube M1 via the resistor R72, the source of the MOS tube M1 is connected to the inverting input end of the operational amplifier U21B, the source of the MOS tube M1 is grounded via the resistor R68, and the drain of the MOS tube M1 serves as the output port I_OUT of the voltage signal conversion current signal module (2).

4. A method for generating a vehicle wheel speed signal using logic coding control according to claim 1, Features: The MCU single-chip logic encoding module (1), the voltage signal conversion current signal module (2), and the controller (3) need to share the same ground wire when connected.

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