Storage system and tag component

Abstract

One embodiment of the present application provides a storage system with improved heat dissipation performance, and a label member that appropriately diffuses heat generated in the storage system. One embodiment relates to a storage system including a substrate, a first semiconductor device, a second semiconductor device, and a label member. The first semiconductor device is disposed on a first surface of the substrate. The second semiconductor device is disposed on the first surface of the substrate. The label member includes a first portion that diffuses heat generated from the first semiconductor device, a second portion that diffuses heat generated from the second semiconductor device, and a third portion that is disposed between the first portion and the second portion and suppresses heat conduction between the first semiconductor device and the second semiconductor device.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-48945 (filed on March 23, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to a storage system and a tag component. Background Technology

[0003] SSDs (Solid State Drives) contain electronic components. These components generate heat when the SSD is operating. Therefore, heat dissipation is crucial for the SSD. Sometimes, resin labels are affixed to the surface of the components mounted on the SSD. Generally, resin labels have low thermal conductivity, resulting in poor heat dissipation. Summary of the Invention

[0004] One embodiment of the present invention provides a storage system with improved heat dissipation performance and a tag component.

[0005] One embodiment of the storage system includes a first substrate, a first semiconductor device, a second semiconductor device, and a tag member. The first semiconductor device is disposed on a first surface of the first substrate. The second semiconductor device is disposed on the first surface of the first substrate. The tag member has a first portion for diffusing heat from the first semiconductor device, a second portion for diffusing heat from the second semiconductor device, and a third portion disposed between the first portion and the second portion for suppressing heat conduction between the first semiconductor device and the second semiconductor device. Attached Figure Description

[0006] Figure 1A This is a top view showing an example of a label component involved in the implementation.

[0007] Figure 1B It is along Figure 1A A sectional view along line II.

[0008] Figure 2A This is a top view of the storage system according to the first embodiment.

[0009] Figure 2B It is along Figure 2A A sectional view along line II-II.

[0010] Figure 2C It is along Figure 2A A cross-sectional view along line III-III.

[0011] Figure 3This is a cross-sectional view of the storage system according to the first embodiment mounted on the second substrate.

[0012] Figure 4A This is a top view of the storage system according to the second embodiment.

[0013] Figure 4B It is along Figure 4A A cross-sectional view along line IV-IV.

[0014] Figure 4C It is along Figure 4A A cross-sectional view of the VV line.

[0015] Figure 5 This is a cross-sectional view of the storage system according to the second embodiment mounted on the second substrate.

[0016] Figure 6A This is a top view of the storage system according to the third embodiment.

[0017] Figure 6B It is along Figure 6A A sectional view along line VI-VI.

[0018] Figure 6C This is a bird's-eye view showing an example of the storage system according to the third embodiment.

[0019] Figure 7A This is a top view of the storage system according to the fourth embodiment.

[0020] Figure 7B It is along Figure 7A A sectional view along line VII-VII.

[0021] Figure 8A This is a cross-sectional view of the storage system according to the fifth embodiment.

[0022] Figure 8B This is a top view of the tag component used in the storage system according to the fifth embodiment.

[0023] Figure 8C This is a cross-sectional view showing the storage system according to the fifth embodiment configured as an SSD device.

[0024] Figure 9 This is a top view of the label component involved in a variation of the implementation method 1.

[0025] Figure 10 (a) is a cross-sectional view of the label component involved in variation 2 of the embodiment. Figure 10 (b) is with Figure 10 A schematic diagram of the thermal conductivity at each X position corresponding to (a).

[0026] Figure 11 (a) is a cross-sectional view of the label component involved in variation 3 of the embodiment. Figure 11 (b) is with Figure 11 A schematic diagram of the thermal conductivity at each X position corresponding to (a).

[0027] Figure 12 This is a block diagram of the storage system involved in the implementation method.

[0028] Figure 13 This is a bird's-eye view of an electronic device equipped with the storage system described in the implementation method.

[0029] Label Explanation

[0030] Storage systems 1A, 1B, 1C, 1D, and 1E

[0031] 2. Host equipment (electronic equipment)

[0032] 4, 4M, 4D First Substrate

[0033] 4a, 4Ma, 4Da Page 1

[0034] 4b, 4Mb, 4Db Page 2

[0035] 5, 5D, 5U1, 5U2 Low thermal conductivity components

[0036] 6, 6M1, 6M2, 6M3, 61, 62, 63 High thermal conductivity components

[0037] 7, 7A, 7B, 7C, 7D, 7E Label components

[0038] 8 2nd base board

[0039] 9D and 9M connectors

[0040] 100 Connecting part

[0041] 10, 10A, 10B NAND flash memory

[0042] 12. 15A~15D Metal threaded parts

[0043] 13 Thread cut

[0044] 15H groove

[0045] 19. Hollow Section

[0046] 20. Memory controller

[0047] 21 CPU

[0048] 22. Internal RAM

[0049] 23. Host I / F Circuit

[0050] 24 Power Management Integrated Circuits (PMICs)

[0051] 25. Dynamic Random Access Memory (DRAM)

[0052] 26 NAND I / F Circuits

[0053] 27 DRAM I / F Circuit

[0054] 30. Housing

[0055] 30U upper casing

[0056] 30D lower shell

[0057] 32-keyboard

[0058] 34. Palm rest

[0059] 50, 52 power cords Detailed Implementation

[0060] The embodiments will be described with reference to the accompanying drawings. In the following description or accompanying drawings, the same reference numerals are used for the same constituent elements and descriptions are omitted. The drawings are schematic. Furthermore, the embodiments shown below are illustrative examples of apparatuses and methods for embodying the technical concept. Various modifications can be made to the embodiments within the scope of patent claims.

[0061] (Label component)

[0062] Figure 1A This is a top view showing an example of the label component 7 involved in the implementation method. Additionally, Figure 1B It is along Figure 1A A sectional view along line II. (e.g.) Figure 1A As shown, label component 7 extends in the XY plane. The X direction is the direction of the long side of label component 7, the Y direction is the direction of the short side of label component 7, and the Z direction represents the direction perpendicular to the XY plane.

[0063] like Figure 1A and Figure 1BAs shown, the label component 7 according to the embodiment includes a first high thermal conductivity component 6M1, a second high thermal conductivity component 6M2, and a low thermal conductivity component 5. The first high thermal conductivity component 6M1 corresponds to a first region, allowing heat generation in the first region to diffuse. The second high thermal conductivity component 6M2 corresponds to a second region, allowing heat generation in the second region to diffuse. A portion of the low thermal conductivity component 5 is disposed between the first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2, suppressing heat conduction between the first region and the second region. That is, a portion of the low thermal conductivity component 5 suppresses heat conduction between the first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2. Here, the first region and the second region correspond to the regions where semiconductor devices are disposed, serving as the objects for heat dissipation by the label attaching component 7.

[0064] like Figure 1B As shown, a portion of the low thermal conductivity component 5 is configured in the Z direction to not overlap with the first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2, respectively. Another portion of the low thermal conductivity component 5 is configured in the Z direction to overlap with the first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2, respectively. The first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2 are formed in a laminated manner with the low thermal conductivity component 5. Alternatively, the first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2 may be embedded within the low thermal conductivity component 5.

[0065] The label component 7 thus constructed has different thermal conductivity depending on the region. The thermal conductivity of the first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2 are both greater than the thermal conductivity of the low thermal conductivity component 5. The label component 7 has thermal conductivity characteristics that vary according to different regions in a structure in which multiple semiconductor devices are disposed on a substrate.

[0066] The first high thermal conductivity component 6M1 is an example of Part 1, the second high thermal conductivity component 6M2 is an example of Part 2, and a portion of the low thermal conductivity component 5 is an example of Part 3.

[0067] The first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2 are, for example, composed of a metal layer, a conductive polymer, etc. As the metal layer, materials with metals of good thermal or electrical conductivity, such as Cu (copper), Al (aluminum), Mo (molybdenum), and W (tungsten), can be used. As the conductive polymer, polythiophene-based or polyaniline-based polymer films with good stability, film-forming properties, and transparency can be used.

[0068] On the other hand, the low thermal conductivity component 5 is made of an insulating material that suppresses thermal conduction between the heat of the first high thermal conductivity component 6M1 and the heat of the second high thermal conductivity component 6M2. As the insulating material, it can be made of, for example, polyethylene terephthalate (PET) resin, acrylic adhesives, epoxy adhesives, silicone resins, etc. PET resin is a thermoplastic polyester obtained by polycondensation of terephthalic acid or dimethyl terephthalate and ethylene glycol. Furthermore, the low thermal conductivity component 5 can also be formed using a laminated structure of the aforementioned insulating material. Additionally, a layer for printing characters can also be included in the laminated structure of the aforementioned insulating material. Furthermore, the label component 7 according to the embodiment can also have a flexible structure.

[0069] The label component 7 involved in the implementation is formed, for example, by bonding insulating material with an adhesive or by vapor-depositing insulating material.

[0070] (First Embodiment)

[0071] Figure 2A This is a top view of the storage system 1A according to the first embodiment. Additionally, Figure 2B It is along Figure 2A A sectional view along line II-II. Additionally... Figure 2C It is along Figure 2A A cross-sectional view along line III-III.

[0072] The storage system 1A according to the first embodiment includes a first substrate 4, first semiconductor devices 10A and 10B, a second semiconductor device 20, and a tag component 7.

[0073] The first substrate 4 includes a connecting portion 100 and a groove portion 15H. The groove portion 15H is provided at one end of the first substrate 4 in the X direction. The connecting portion 100 is provided at the other end of the first substrate 4 that is separated from the groove portion 15H in the X direction.

[0074] The first substrate 4 is, for example, a circuit board made of a printed wiring substrate. The first substrate 4 has a first surface 4a and a second surface 4b opposite to the first surface 4a. For example... Figure 2A As shown, the first substrate 4 is arranged extending in the XY plane. The X direction is the direction of the long side of the first substrate 4, the Y direction is the direction of the short side of the first substrate 4, and the Z direction is the direction perpendicular to the XY plane. The same applies in the following description.

[0075] like Figure 2B As shown, the first semiconductor devices 10A and 10B are disposed on the first surface 4a side of the first substrate 4.

[0076] The first semiconductor devices 10A and 10B are, for example, NAND flash memory. In the following description, the first semiconductor devices 10A and 10B will also be referred to as NAND flash memory 10A and 10B. The NAND flash memory 10A and 10B have a first permissible operating temperature T1.

[0077] The second semiconductor device 20 is disposed on the first surface 4a side of the first substrate 4. The second semiconductor device 20 is, for example, a memory controller that controls NAND flash memories 10A and 10B. In the following description, the second semiconductor device 20 will also be referred to as memory controller 20. Generally, the memory controller 20 has a second operating temperature T2 that is higher than the first operating temperature T1.

[0078] As described above, the tag component 7 has a first high thermal conductivity component 6M1, a second high thermal conductivity component 6M2, and a low thermal conductivity component 5. The first high thermal conductivity component 6M1 diffuses the heat generated by the NAND flash memory 10A and 10B. The second high thermal conductivity component 6M2 diffuses the heat generated by the memory controller 20. A portion of the low thermal conductivity component 5 suppresses thermal conduction between the heat generated by the NAND flash memory 10A and 10B and the heat generated by the memory controller 20. Thus, the tag component 7 has a thermal conductivity that varies by region.

[0079] In the storage system 1A according to the first embodiment, such as Figure 2B and Figure 2C As shown, the label component 7 is disposed on the second surface 4b side of the first substrate 4.

[0080] like Figure 2B and Figure 2C As shown, the first high thermal conductivity component 6M1 is disposed below the NAND flash memory 10A and 10B in the negative direction of the Z direction, separated by the first substrate 4.

[0081] The second high thermal conductivity component 6M2 is disposed below the storage controller 20 in the negative direction of the Z direction, separated from the first substrate 4.

[0082] The storage system 1A according to the first embodiment includes a tag component 7, which has a structure in which thermal conductivity varies by region. Therefore, in the region where the storage controller 20 is located, the storage system 1A actively dissipates heat through the second high thermal conductivity component 6M2. Furthermore, in the region where the NAND flash memory 10A and 10B are located, the storage system 1A suppresses heat from the second high thermal conductivity component 6M2 through a portion of the low thermal conductivity component 5, and actively dissipates heat through the first high thermal conductivity component 6M1.

[0083] (Storage system mounting structure)

[0084] Figure 3 This is a cross-sectional view of the storage system 1A according to the first embodiment mounted on a host device.

[0085] When the storage system 1A is connected to the host device via the connection part 100, the storage system 1A can communicate with the host device via the connection part 100. While the storage system 1A is connected to the host device via the connection part 100, the storage system 1A can be further connected to the host device via the slot 15H. The host device includes at least a connector (not shown) connected to the connection part 100 and a second substrate 8. The connector of the host device is mounted on the second substrate 8. The second substrate 8 is, for example, a circuit board made of a printed wiring board. Alternatively, the second substrate 8 may be, for example, a metal frame.

[0086] like Figure 3 As shown, the storage system 1A is mounted to the second substrate 8 via a slot 15H and a metal threaded member 12. The metal threaded member 12 connects the first substrate 4 and the second substrate 8 via the slot 15H provided on the first substrate 4 of the storage system 1A and the threaded cutout 13 provided on the second substrate 8. A portion of the first high thermal conductivity member 6M1 is exposed on the inner wall of a portion of the tag member 7 corresponding to the slot 15H. Furthermore, a portion of the wiring that serves as the reference potential (ground potential) of the host device is exposed on the inner wall of the threaded cutout 13.

[0087] In this way, the first high thermal conductivity component 6M1 of the label component 7 is thermally connected to the second substrate 8 via the metal thread 12.

[0088] The storage system 1A is connected to a connector mounted on the second substrate 8 via a connection portion 100. When the connector mounted on the second substrate 8 has a high thermal conductivity component, the connector and the tag component 7 can be made into thermal contact.

[0089] The storage system 1A according to the first embodiment can transmit the heat generated by the NAND flash memory 10A and 10B to the second substrate 8 via the first high thermal conductivity member 6M1 and the metal threaded member 12. Additionally, the heat generated by the storage controller 20 can be transmitted from the connection portion 100 to the outside via the second high thermal conductivity member 6M2. That is, the heat generated by the NAND flash memory 10A and 10B is transmitted to the tag member 7 having the first high thermal conductivity member 6M1. The heat transmitted to the tag member 7 is dissipated to the second substrate 8 via the contacting metal threaded member 12. Furthermore, the heat generated by the storage controller 20 is dissipated through the second substrate. In other words, the heat generated by the controller 20 is transmitted to the tag member 7 having the second high thermal conductivity member 6M2. The heat transmitted to the tag member 7 is dissipated to the second substrate 8 via the second substrate 8 in contact with the tag member 7, or via a connector mounted on the second substrate 8. The heat generated by the NAND flash memory 10A and 10B that is transmitted to the first high thermal conductivity component 6M1 and the heat generated by the memory controller 20 that is transmitted to the second high thermal conductivity component 6M2 are mutually suppressed by a part of the low thermal conductivity component 5.

[0090] The storage system 1A according to the first embodiment follows, for example, the M.2 standard, which is the standard for built-in expansion cards in computers. The dimensions of the first substrate 4 of the storage system 1A, according to the M.2 standard, are, for example, a width of 22 mm in the Y direction and a length of approximately 30 mm, 42 mm, 80 mm, or 110 mm in the X direction. In this case, for the tag member 7, a width of approximately 20 mm in the Y direction and a length of approximately 28 mm, 40 mm, 75 mm, or 100 mm in the X direction are sufficient.

[0091] (Effects of the first embodiment)

[0092] According to the first embodiment, by having a label member attached to the second surface 4b of the first substrate 4, the generated heat can be properly diffused or the heat propagation can be suppressed, thus providing a storage system 1A with improved heat dissipation performance.

[0093] The storage system 1A according to the first embodiment includes: first semiconductor devices 10A and 10B having a first operating allowable temperature T1, a second semiconductor device 20 having a second operating allowable temperature T2, and a tag member 7. The heat generated by the first semiconductor devices 10A and 10B and the second semiconductor device 20, which have different device structures, is controlled to dissipate heat to the outside through the tag member 7 having a first high thermal conductivity member 6M1 and a second high thermal conductivity member 6M2, thereby enabling active heat dissipation.

[0094] (Second Implementation)

[0095] Figure 4AThis is a top view of the storage system 1B according to the second embodiment. Figure 4B It is along Figure 4A A cross-sectional view along line IV-IV. Additionally... Figure 4C It is along Figure 4A A cross-sectional view of the VV line.

[0096] The storage system 1B according to the second embodiment, like the first embodiment, includes a first substrate 4, NAND flash memory 10A and 10B (an example of a first semiconductor device), a storage controller 20 (an example of a second semiconductor device), and a tag component 7. In the storage system 1B, as... Figure 4B and Figure 4C As shown, the label component 7 is disposed on the first surface 4a side of the first substrate 4.

[0097] like Figure 4B and Figure 4C As shown, the first high thermal conductivity component 6M1 is positioned above the NAND flash memory 10A and 10B in the positive direction of the Z direction.

[0098] The second high thermal conductivity component 6M2 is positioned above the storage controller 20 in the positive direction of the Z direction.

[0099] In the storage system 1B according to the second embodiment, a tag component 7 is also provided, which has different thermal conductivity depending on the region. Therefore, in the region where the storage controller 20 is located, heat is actively diffused by the second high thermal conductivity component 6M2. Furthermore, in the region where the NAND flash memory 10A and 10B are located, heat from the second high thermal conductivity component 6M2 is suppressed by a portion of the low thermal conductivity component 5, and heat is actively diffused by the first high thermal conductivity component 6M1.

[0100] (Storage system mounting structure)

[0101] Figure 5 This is a cross-sectional view of the storage system 1B according to the second embodiment mounted on a host device.

[0102] The storage system 1B according to the second embodiment is similar to that in the first embodiment in that it can be connected to the host device via the connection part 100 for communication. Furthermore, the storage system 1B can be further connected to the host device via the slot 15H. The configuration of the host device is the same as in the first embodiment.

[0103] like Figure 5As shown, the storage system 1B is mounted to the second substrate 8 via a slot 15H and a metal threaded member 12. The metal threaded member 12 connects the first substrate 4 and the second substrate 8 via the slot 15H provided on the first substrate 4 of the storage system 1B and the threaded cutout 13 provided on the second substrate 8. A portion of the first high thermal conductivity component 6M1 is exposed on the inner wall of a portion of the tag component 7 corresponding to the slot 15H. Furthermore, a portion of the wiring that serves as the reference potential (ground potential) of the host device is exposed on the inner wall of the threaded cutout 13.

[0104] In this way, the first high thermal conductivity component 6M1 of the label component 7 is thermally connected to the second substrate 8 via the metal thread 12.

[0105] The storage system 1B is connected to the connector mounted on the second substrate 8 via the connection part 100. This allows the connector mounted on the second substrate 8 and the tag component 7 to come into contact and be thermally connected.

[0106] The storage system 1B according to the first embodiment can transfer the heat generated by the NAND flash memory 10A and 10B to the second substrate 8 via the first high thermal conductivity member 6M1 and the metal threaded member 12. In addition, the heat generated by the storage controller 20 can be dissipated to the outside from its upper part, the connection part 100, etc. via the second high thermal conductivity member 6M2.

[0107] (Effects of the second implementation method)

[0108] According to the second embodiment, by attaching the tag member 7 to the first surface 4a of the first substrate 4, the generated heat can be properly diffused, and a storage system with improved heat dissipation performance can be provided.

[0109] (Third Implementation)

[0110] Figure 6A This is a top view of the storage system 1C according to the third embodiment. Additionally, Figure 6B It is along Figure 6A A sectional view along line VI-VI.

[0111] like Figure 6A As shown, the storage system 1C according to the third embodiment includes a first substrate 4, a plurality of first semiconductor devices 10, a second semiconductor device 20, a power management integrated circuit (PMIC) 24, a dynamic random access memory (DRAM) 25, a tag component 7A, and metal threaded parts 15A to 15D.

[0112] like Figure 6BAs shown, a plurality of first semiconductor devices 10 are disposed on the first surface 4a side of the first substrate 4.

[0113] Each of the first semiconductor devices 10 is, for example, a NAND flash memory. The first semiconductor device 10 has a first allowable operating temperature T1. In the following description, the first semiconductor device 10 will also be referred to as a NAND flash memory 10.

[0114] The second semiconductor device 20 is disposed on the first surface 4a side of the first substrate 4. The second semiconductor device 20 has a second operating allowable temperature T2 that is higher than the first operating allowable temperature T1.

[0115] The second semiconductor device 20 is a memory controller that controls each NAND flash memory 10. In the following description, the second semiconductor device 20 will also be referred to as memory controller 20.

[0116] PMIC 24 and DRAM 25 are disposed on the first surface 4a side of the first substrate 4. PMIC 24 supplies power to the first semiconductor device 10 and the second semiconductor device 20. DRAM 25 is used as working memory when the second semiconductor device 20 controls the first semiconductor device 10.

[0117] Tag component 7A includes a first high thermal conductivity component 6M1, a second high thermal conductivity component 6M2, a third high thermal conductivity component 6M3, and a low thermal conductivity component 5. The first high thermal conductivity component 6M1 diffuses heat from the multiple NAND flash memory units 10. The second high thermal conductivity component 6M2 diffuses heat from the memory controller 20. The third high thermal conductivity component 6M3 diffuses heat from the PMIC 24. A portion of the low thermal conductivity component 5 suppresses thermal conduction between the NAND flash memory units 10 and the memory controller 20. Additionally, a portion of the low thermal conductivity component 5 suppresses thermal conduction between the NAND flash memory units 10 and the PMIC 24. Tag component 7A has different thermal conductivity rates depending on the region.

[0118] like Figure 6B As shown, the label component 7A is disposed on the first surface 4a side of the first substrate 4. Figure 6A Alternatively, as shown in 6B, the first high thermal conductivity component 6M1 is disposed above the plurality of NAND flash memory 10 in the positive Z-direction. The second high thermal conductivity component 6M2 is disposed above the memory controller 20 in the positive Z-direction. The third high thermal conductivity component 6M3 is disposed above the PMIC 24 in the positive Z-direction.

[0119] The storage system 1C according to the third embodiment, like storage systems 1A and 1B, includes a tag member 7A with a structure having different thermal conductivity depending on the region. Therefore, in the region where the storage controller 20 is located, storage system 1C actively dissipates heat through the second high thermal conductivity member 6M2. Furthermore, in the region where NAND flash memory 10A and 10B are located, storage system 1C suppresses heat from the second high thermal conductivity member 6M2 and the third high thermal conductivity member 6M3 through a portion of the low thermal conductivity member 5, and actively dissipates heat through the first high thermal conductivity member 6M1. Further, in the region where PMIC 24 is located, heat from the first high thermal conductivity member 6M1 and the second high thermal conductivity member 6M2 is suppressed through a portion of the low thermal conductivity member 5, and actively dissipates heat through the third high thermal conductivity member 6M3.

[0120] (Example of a storage system configuration)

[0121] Figure 6C This is a perspective view illustrating an example of the storage system 1C according to the third embodiment. The storage system 1C is, for example, an SSD (Solid State Drive). The storage system 1C according to the third embodiment meets the FF (Form Factor) standard related to the shape of a 2.5-inch SSD. The storage system 1C includes a housing 30 formed by a first housing (upper housing) 30U and a second housing (lower housing) 30D.

[0122] like Figure 6A As shown, the first high thermal conductivity component 6M1 is connected to the housing 30 via metal threaded parts 15A and 15B.

[0123] The second high thermal conductivity component 6M2 is connected to the housing 30 via a metal threaded part 15C.

[0124] The third high thermal conductivity component 6M3 is connected to the housing 30 via a metal threaded part 15D.

[0125] The heat generated in the NAND flash memory 10, storage controller 20 and PMIC 24 of the storage system 1C is transferred through the aforementioned tag component 7A to the constituent components of the storage system 1, the first housing (upper housing) 30U and the second housing (lower housing) 30D, where it is dissipated.

[0126] As a result, the temperature of the NAND flash memory 10 can be maintained within a suitable operating temperature range, ensuring proper operation of the storage system 1C. Furthermore, the layout of the NAND flash memory 10, storage controller 20, PMIC 24, and DRAM 25 mounted on the first substrate 4 housed in the housing 30 is an example, and can be appropriately modified according to the required storage capacity, the size of the storage system 1C's casing, etc. Alternatively, multiple first substrates 4 can be housed in the housing 30.

[0127] (Effects of the third embodiment)

[0128] According to the third embodiment, by attaching the label member to the first surface 4a of the first substrate 4, the generated heat can be properly diffused, and a storage system with improved heat dissipation performance can be provided.

[0129] (Fourth implementation)

[0130] Figure 7A This is a top view of the storage system 1D according to the fourth embodiment. Additionally, Figure 7B It is along Figure 7A A sectional view along line VII-VII.

[0131] The storage system 1D according to the fourth embodiment includes a first substrate 4, a first semiconductor device 10, a second semiconductor device 20, a PMIC 24, a DRAM 25, a tag component 7A, and metal threaded parts 15A to 15D.

[0132] like Figure 7B As shown, the first semiconductor device 10 is disposed on the first surface 4a side of the first substrate 4.

[0133] Each of the first semiconductor devices 10 includes, for example, a NAND flash memory. The first semiconductor device 10 has a first allowable operating temperature T1. In the following description, the first semiconductor device 10 will also be referred to as a NAND flash memory 10.

[0134] The second semiconductor device 20 is disposed on the first surface 4a side of the first substrate 4. The second semiconductor device 20 has a second operating allowable temperature T2 that is higher than the first operating allowable temperature T1.

[0135] The second semiconductor device 20 is a memory controller that controls each NAND flash memory 10. In the following description, the second semiconductor device 20 will also be referred to as memory controller 20.

[0136] PMIC24 and DRAM25 are configured on the first surface 4a side of the first substrate 4.

[0137] Tag component 7A includes a first high thermal conductivity component 6M1, a second high thermal conductivity component 6M2, a third high thermal conductivity component 6M3, and a low thermal conductivity component 5. The first high thermal conductivity component 6M1 diffuses heat from the NAND flash memory 10. The second high thermal conductivity component 6M2 diffuses heat from the memory controller 20. The third high thermal conductivity component 6M3 diffuses heat from the PMIC 24. A portion of the low thermal conductivity component 5 suppresses thermal conduction between the NAND flash memory 10 and the memory controller 20. Additionally, a portion of the low thermal conductivity component 5 suppresses thermal conduction between the NAND flash memory 10 and the PMIC 24. Tag component 7A has different thermal conductivity rates depending on the region.

[0138] like Figure 7B As shown, the label component 7A is disposed on the second surface 4b side of the first substrate 4, which is opposite to the first surface 4a.

[0139] like Figure 7B As shown, the first high thermal conductivity component 6M1 is disposed below the plurality of NAND flash memory 10 in the negative direction of the Z direction.

[0140] The second high thermal conductivity component 6M2 is positioned below the storage controller 20 in the negative Z direction.

[0141] The third high thermal conductivity component 6M3 is positioned below the PMIC24 in the negative Z direction.

[0142] The storage system 1D according to the fourth embodiment, like storage systems 1A to 1C, includes tag components 7A with varying thermal conductivity depending on the region. Therefore, in the region where the storage controller 20 is located, storage system 1D actively dissipates heat via the second high thermal conductivity component 6M2. Furthermore, in the region where NAND flash memories 10A and 10B are located, storage system 1D suppresses heat from the second high thermal conductivity component 6M2 and the third high thermal conductivity component 6M3 via a portion of the low thermal conductivity component 5, and actively dissipates heat via the first high thermal conductivity component 6M1. Further, in the region where the PMIC 24 is located, heat from the first high thermal conductivity component 6M1 and the second high thermal conductivity component 6M2 is suppressed via a portion of the low thermal conductivity component 5, and actively dissipates heat via the third high thermal conductivity component 6M3.

[0143] The storage system 1D according to the fourth embodiment is capable of... Figure 6C Similarly, it is configured as an SSD device. The storage system 1D includes a housing 30 formed by a first housing (upper housing) 30U and a second housing (lower housing) 30D.

[0144] like Figure 7AAs shown, the first high thermal conductivity component 6M1 is connected to the housing 30 via metal threaded parts 15A and 15B.

[0145] The second high thermal conductivity component 6M2 is connected to the housing 30 via a metal threaded part 15C.

[0146] The third high thermal conductivity component 6M3 is connected to the housing 30 via a metal threaded part 15D.

[0147] The heat generated in the NAND flash memory 10, storage controller 20 and PMIC 24 included in the storage system 1D is transferred through the tag component 7A to the constituent components of the storage system 1D, the first housing (upper housing) 30U and the second housing (lower housing) 30D, where it is dissipated.

[0148] (Effects of the fourth embodiment)

[0149] According to the fourth embodiment, by attaching the tag member 7A to the second surface 4b of the first substrate 4, the generated heat can be properly diffused, and a storage system with improved heat dissipation performance can be provided.

[0150] (Fifth Embodiment)

[0151] Figure 8A This is a cross-sectional view of the storage system 1E according to the fifth embodiment. Additionally, Figure 8B This is a top view of the tag component 7B applied to the storage system 1E according to the fifth embodiment. Additionally, Figure 8C This is a cross-sectional view of the storage system 1E according to the fifth embodiment as an SSD device.

[0152] The storage system 1E according to the fifth embodiment includes a first substrate 4M and a first substrate 4D disposed above the first substrate 4M in the positive direction of the Z direction. Sometimes the first substrate 4M is referred to as a mother substrate, and the first substrate 4D is referred to as a daughter substrate.

[0153] The first substrate 4M has a first surface 4Ma and a second surface 4Mb opposite to the first surface 4Ma. A plurality of NAND flash memory 10s and a memory controller 20 are disposed on the first surface 4Ma side of the first substrate 4M. Additionally, a plurality of NAND flash memory 10s are disposed on the second surface 4Mb side of the first substrate 4M.

[0154] The first substrate 4D has a first surface 4Da and a second surface 4Db opposite to the first surface 4Da. A plurality of NAND flash memory 10s are disposed on the first surface 4Da side of the first substrate 4D, and a plurality of NAND flash memory 10s are also disposed on the second surface 4Db side of the first substrate 4D.

[0155] A tag component 7B is disposed between the first substrate 4M and the first substrate 4D.

[0156] Furthermore, connectors 9M and 9D are disposed between the first substrate 4M and the first substrate 4D to electrically connect the first substrate 4M and the first substrate 4D. Connector 9M is disposed on the first surface 4Ma side of the first substrate 4M, and connector 9D is disposed on the second surface 4Db side of the first substrate 4D. Signal transmission between the plurality of NAND flash memory 10 disposed on the first substrate 4M and the memory controller 20 disposed on the first substrate 4D, as well as power transmission between the first substrate 4M and the first substrate 4D, are implemented via connectors 9M and 9D.

[0157] The label component 7B has a first high thermal conductivity component 6M1, a second high thermal conductivity component 6M2, and a low thermal conductivity component 5. For example... Figure 8B As shown, the tag component 7B has a cavity 19. With the tag component 7B positioned between the first substrate 4M and the first substrate 4D, connectors 9M and 9D are positioned in the cavity 19. A first high thermal conductivity component 6M1 diffuses the heat generated by the NAND flash memory 10. A second high thermal conductivity component 6M2 diffuses the heat generated by the memory controller 20.

[0158] like Figure 8A As shown, the first high thermal conductivity component 6M1 is disposed above the NAND flash memory 10 disposed on the first surface 4Ma side of the first substrate 4M, in the positive direction of the Z direction. Furthermore, as... Figure 8A As shown, the first high thermal conductivity component 6M1 is disposed below the NAND flash memory 10 disposed on the second surface 4Db side of the first substrate 4D in the negative direction of the Z direction.

[0159] like Figure 8A As shown, the second high thermal conductivity component 6M2 is positioned above the memory controller 20, which is located on the first surface 4Ma side of the first substrate 4M, in the positive direction of the Z-direction. Furthermore, as... Figure 8A As shown, the second high thermal conductivity component 6M2 is disposed below the NAND flash memory 10 disposed on the first surface 4Da side of the first substrate 4D in the negative direction of the Z direction.

[0160] (Example of a storage system configuration)

[0161] like Figure 8C As shown, the storage system 1E includes a housing 30 formed by a first housing (upper housing) 30U and a second housing (lower housing) 30D.

[0162] A portion of the first high thermal conductivity component 6M1 contacts the first outer casing (upper casing) 30U. Additionally, a portion of the second high thermal conductivity component 6M2 contacts the first outer casing (upper casing) 30U.

[0163] The heat generated in the NAND flash memory 10 and the storage controller 20 of the storage system 1E is transmitted through the aforementioned tag component 7B to the constituent components of the storage system 1E, the first housing (upper housing) 30U and the second housing (lower housing) 30D, where it is dissipated.

[0164] As a result, the temperature of the NAND flash memory 10 can be maintained within a suitable operating temperature range, ensuring the proper functioning of the storage system 1E.

[0165] (Effects of the fifth embodiment)

[0166] According to the fifth embodiment, by attaching the tag member 7B between a plurality of first substrates (4D, 4M), the generated heat can be appropriately diffused, and a storage system with improved heat dissipation performance can be provided.

[0167] (Example of a modified label component)

[0168] (Variation Example 1)

[0169] Figure 9 This is a top view of the label component 7C involved in a variation of the embodiment 1.

[0170] like Figure 9 As shown, the label component 7C according to Variation 1 of the embodiment includes a plurality of high thermal conductivity components 6 and a plurality of low thermal conductivity components 5. The plurality of high thermal conductivity components 6 extend in the X direction. Additionally, the plurality of low thermal conductivity components 5 also extend in the X direction. Figure 9 As shown, multiple high thermal conductivity components 6 and multiple low thermal conductivity components 5 are alternately arranged in the Y direction. Therefore, the label component 7C according to the modified embodiment 1 has high thermal conductivity in the X direction and low thermal conductivity in the Y direction.

[0171] (The effect of variation 1)

[0172] The label component 7C in the modified embodiment 1 has the characteristics of high thermal conductivity in the X direction and low thermal conductivity in the Y direction perpendicular to the X direction by arranging multiple high thermal conductivity components and multiple low thermal conductivity components in parallel with each other, and can control the directionality of thermal conduction.

[0173] (Variation Example 2)

[0174] The high thermal conductivity component 6 does not need to be a single layer; it can be multi-layered. Furthermore, it is not necessary for all layers to have the same shape. Alternatively, the high thermal conductivity component 6 can be configured as a multi-layered structure, with each layer having a different size (or range or area) of the high thermal conductivity component 6.

[0175] Figure 10 (a) is a cross-sectional view of the label component 7D involved in variation 2 of the embodiment.

[0176] like Figure 10 As shown in (a), the label component 7D involved in the variation of embodiment 2 includes a plurality of high thermal conductivity components 61, 62, 63 and low thermal conductivity components 5. Figure 10 As shown in (a), multiple high thermal conductivity components 61, 62, and 63 are stacked with low thermal conductivity components 5 sandwiched in the Z direction. In addition, low thermal conductivity components 5 are also arranged in the positive direction of the Z direction of the high thermal conductivity component 61 and the negative direction of the Z direction of the high thermal conductivity component 63.

[0177] Multiple high thermal conductivity components 61, 62, and 63 extend in the X direction (or Y direction). For example, Figure 10 As shown in (a), the lengths of the multiple high thermal conductivity components 61, 62, and 63 extending in the X direction are different.

[0178] Figure 10 (b) indicates that it is related to Figure 10 A schematic diagram showing the distribution of thermal conductivity TC in the Z direction at each position in the X direction corresponding to (a).

[0179] like Figure 10 As shown in (b), the label component 7D involved in Variation 2 of the embodiment has a thermal conductivity TC = TC1 in the range X = 0 to X1, X6 to XM where three layers of high thermal conductivity components 61, 62, and 63 are present. In the range X = X1 to X2, X5 to X6 where two layers of high thermal conductivity components 61 and 62 are present, the thermal conductivity TC is lower than TC1. When X = X2 and X5, TC = TC2. In the range X = X2 to X3, X4 to X5 where one layer of high thermal conductivity component 61 is present, the thermal conductivity TC further decreases. In the range X = X3 to X4 where no high thermal conductivity components are present, the thermal conductivity TC = TC0. The value of TC0 is smaller than TC2.

[0180] (Effect of Variation Example 2)

[0181] In the label component 7D according to the modified example 2 of the embodiment, the distribution of thermal conductivity TC can be adjusted by adjusting the length, size, area or range of a plurality of high thermal conductivity components that are stacked on each other in a certain direction.

[0182] (Variation Example 3)

[0183] Figure 11 (a) is a cross-sectional view of the label component 7E involved in variation 3 of the embodiment.

[0184] like Figure 11 As shown in (a), the label component 7E involved in variation 3 of the embodiment includes a plurality of high thermal conductivity components 61, 62, 63 and low thermal conductivity components 5. Figure 11 As shown in (a), multiple high thermal conductivity components 61, 62, and 63 are stacked with low thermal conductivity components 5 sandwiched in the Z direction. In addition, low thermal conductivity components 5 are also arranged in the positive direction of the Z direction of the high thermal conductivity component 61 and the negative direction of the Z direction of the high thermal conductivity component 63.

[0185] In addition, multiple high thermal conductivity components 61, 62, and 63 extend in the X direction (or Y direction). For example, Figure 11 As shown in (a), the multiple high thermal conductivity components 61, 62, and 63 extend for different lengths in the X direction. The difference from Modified Example 2 is that the high thermal conductivity component 61 extends continuously in the X direction within the range of X = 0 to XM. Other configurations are the same as in Modified Example 2.

[0186] Figure 11 (b) indicates that it is related to Figure 11 A schematic diagram showing the distribution of thermal conductivity TC in the Z direction at each position in the X direction corresponding to (a).

[0187] like Figure 11 As shown in (b), in the variation of embodiment 3, the label component 7E has a thermal conductivity TC = TC1 in the range X = 0 to X1, X6 to XM where three layers of high thermal conductivity components 61, 62, and 63 are present. In the range X = X1 to X2, X5 to X6 where two layers of high thermal conductivity components 61 and 62 are present, the thermal conductivity TC is lower than TC1. When X = X2 and X = X5, TC = TC2. In the range X = X3 to X4 where one layer of high thermal conductivity component 61 is present, the thermal conductivity TC further decreases. Figure 11 In (b), the thermal conductivity TC represented by the dashed line corresponds to the distribution of thermal conductivity TC in Modification 2, and the thermal conductivity TC represented by the solid line corresponds to the distribution of thermal conductivity TC in Modification 3. In the range X = X3 to X4 where a layer of high thermal conductivity component 61 exists, the thermal conductivity TC of Modification 3 increases by ΔTC compared to Modification 2.

[0188] (The effect of variation example 3)

[0189] In the label component 7E according to the variation of the embodiment 3, the distribution of thermal conductivity TC can be adjusted by adjusting the length, size, area or range of a plurality of high thermal conductivity components stacked on top of each other in a certain direction.

[0190] (Storage system composition)

[0191] Next, the configuration of the blocks of the storage system involved in the implementation method will be described.

[0192] Figure 12 This is a block diagram of the storage system 1 according to the embodiment. The storage system 1 according to the embodiment is configured as an SSD. Figure 12 As shown, the storage system 1 includes multiple NAND flash memories 10, DRAM 25, a storage controller 20, and a PMIC 24. The storage system 1 can be connected to the host device 2.

[0193] NAND flash memory 10 is a non-volatile memory capable of storing data in a non-volatile manner and can operate independently. Furthermore, the number of NAND flash memories 10 is not particularly limited and can be designed to be any number. The NAND flash memory 10 and the memory controller 20 are connected via multiple channels. As a non-volatile memory other than NAND flash memory, NOR flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), ferroelectric random access memory (FeRAM), and magnetic tunnel junction (MTJ) resistive elements can be used.

[0194] DRAM25 is a volatile memory capable of temporarily storing data. Furthermore, the number of volatile memories in the storage system 1 can be designed to be arbitrary. Additionally, the volatile memory is not limited to DRAM. For example, SRAM (Static Random Access Memory) or similar materials can also be used as volatile memory.

[0195] The storage controller 20 is capable of commanding various operations on the NAND flash memory 10 and DRAM 25. Furthermore, the storage controller 20 is capable of performing operations based on commands from the external host device 2, as well as operations independent of commands from the host device 2.

[0196] PMIC 24 supplies the necessary power to memory controller 20 via power line 52. PMIC 24 supplies the necessary power to NAND flash memory 10 and DRAM 25 via power line 50. PMIC 24 may include, for example, a DC-DC converter, an LDO (Low Drop Output) regulator, a switching regulator, etc.

[0197] like Figure 12 As shown, the memory controller 20 includes, for example, a CPU (Central Processing Unit) 21, internal RAM (Random Access Memory) 22, host I / F circuitry 23, NAND I / F circuitry 26, and DRAM I / F circuitry 27. The configuration of the memory controller 20 is merely an example and is not limited thereto.

[0198] CPU 21 controls the overall operation of memory controller 20. For example, CPU 21 responds to a read command received from host device 2 by issuing a read command and sending the issued command to NAND I / F circuit 26.

[0199] Built-in memory 22 is a storage area used as the working area of ​​CPU 21. For example, parameters for managing NAND flash memory 10, various management tables, etc., are expanded in built-in memory 22. For example, built-in memory 22 maintains a wait queue (command queue) for commands received from host device 2. Additionally, built-in memory 22 maintains an address translation table used to translate the logical address associated with data requested for writing from host device 2 into the physical block address (PBA) of NAND flash memory 10. This address translation table is stored in NAND flash memory 10, for example, and is read and expanded into built-in memory 22 during startup of storage system 1. For example, volatile memory such as SRAM can be used as built-in memory 22.

[0200] The host I / F circuit 23 is connected to the host device 2 and is responsible for communication between the storage system 1 and the host device 2. For example, the host I / F circuit 23 controls the transmission of data, commands, and addresses between the storage system 1 and the host device 2. The host I / F circuit 23 supports communication I / F standards such as SATA, SAS, and PCIe (registered trademark). That is, the host device 2 connected to the storage system 1 can be, for example, a computer with I / F including SATA, SAS, and PCIe.

[0201] The NAND I / F circuit 26 is connected to the NAND flash memory 10 and is responsible for communication between the storage controller 20 and the NAND flash memory 10. The NAND I / F circuit 26 is constructed based on the NAND I / F standard.

[0202] DRAM I / F circuit 27 is connected to DRAM 25 and is responsible for communication between memory controller 20 and DRAM 25. DRAM I / F circuit 27 is constructed based on the DRAM I / F standard. However, the configuration of DRAM I / F circuit 27 is not limited to this and can be changed based on the type of volatile memory.

[0203] (Electronic devices)

[0204] Figure 13 This is a perspective view illustrating an example of an electronic device 2 according to the embodiment. Electronic device 2 is an example of a host device 2, such as a personal computer. The storage system 1 according to the embodiment is, for example, housed within the internal space under the palm rest 34 on the front side of the keyboard 32. NAND flash memory 10A, 10B and a storage controller 20 are, for example, mounted on the first substrate 4 of the storage system 1.

[0205] The electronic device 2 according to the embodiment includes a storage system 1 that interfaces with a host device 2. The storage system 1 includes a first substrate 4, first electronic components 10A and 10B (examples of first semiconductor devices), a second electronic component 20 (example of a second semiconductor device), and a tag component 7. The first electronic components 10A and 10B are disposed on a first surface of the first substrate 4 and have a first permissible operating temperature. The second electronic component is disposed on the first surface of the first substrate 4 and has a second permissible operating temperature higher than the first permissible operating temperature. The tag component 7 includes a first high thermal conductivity component, a second high thermal conductivity component, and a low thermal conductivity component, and is attached to the first substrate 4. The first high thermal conductivity component is an example of a first portion that diffuses heat from the first electronic component; the second high thermal conductivity component is an example of a second portion that diffuses heat from the second electronic component 20; and the low thermal conductivity component is an example of a third portion that suppresses heat conduction between the first electronic components 10A and 10B and the second electronic component 20.

[0206] The heat generated in the storage controller 20 included in the storage system 1 is dissipated through the tag component 7 via the constituent components of the electronic device 2, and is discharged together with the exhaust from the exhaust port (not shown) of the electronic device 2 by airflow generated by the fan built into the side of the electronic device 2. As a result, the temperature of the NAND flash memory 10A and 10B can be maintained within a suitable operating temperature range, ensuring the proper functioning of the electronic device 2.

[0207] Furthermore, the layout of NAND flash memory 10A, 10B and memory controller 20 mounted on the first substrate 4 of the memory system 1 housed in the electronic device 2 is an example. This layout can be appropriately modified according to the required storage capacity of the memory system 1, the size of the mounting space of the memory system 1 in the electronic device 2, etc. Additionally, multiple memory systems 1 can be housed in the electronic device 2. Furthermore, any of the memory systems 1, 1A, 1B, 1C, 1D, and 1E described in the first to fifth embodiments can be used in the memory system 1 housed in the electronic device 2. Additionally, the tag component 7 described in the embodiments can be used as the tag component. Figure 1A and Figure 1B The variations of the implementation method involve label components 7A, 7B, 7C, 7D, and 7E (Figures 6-7, 8). Figure 9 , Figure 10 , Figure 11 ).

[0208] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage system comprising: A first substrate having a first surface; A first semiconductor device is disposed on the first surface of the first substrate; A second semiconductor device, disposed on the first surface of the first substrate, spaced apart from the first semiconductor device in a first direction; and The tag component includes a first portion that diffuses heat from the first semiconductor device and is positioned in a second direction perpendicular to the first direction at a location corresponding to the position where the first semiconductor device is positioned; a second portion that diffuses heat from the second semiconductor device and is positioned in the second direction at a location corresponding to the position where the second semiconductor device is positioned; and a third portion that suppresses heat conduction between the heat of the first portion and the heat of the second portion. The third part is formed of an insulating material. A portion of the third part is located between the first part and the second part in the first direction, and the first part and the second part are embedded in the third part in such a way that the first part and the second part are not exposed on the surface of the third part. The first thermal conductivity of the first part and the second thermal conductivity of the second part are both higher than the third thermal conductivity of the third part.

2. The storage system according to claim 1, The label component is disposed on the first surface side of the first substrate.

3. The storage system according to claim 1, The first substrate also has a second surface opposite to the first surface. The label component is disposed on the second side.

4. The storage system according to any one of claims 1 to 3, further comprising: shell; and A metal threaded component, which connects to the housing. The first part is connected to the housing via the metal threaded fitting.

5. The storage system according to any one of claims 1 to 3, comprising: A second substrate, which sandwiches the label component, faces the first substrate; and A connector that connects the first substrate and the second substrate.

6. The storage system according to any one of claims 1 to 3, The first substrate also has a first end portion and a groove formed at the first end portion. The storage system also features: A second substrate, which is different from the first substrate; and A metal threaded component that connects the first substrate and the second substrate via the groove. The first part is connected to the second substrate via the metal threaded part.

7. The storage system according to claim 6, The first substrate also has a second end, different from the first end, and a connector disposed at the second end. The second part is configured close to the connector.

8. The storage system according to any one of claims 1 to 3, The first semiconductor device includes a NAND flash memory, and the second semiconductor device includes a memory controller for controlling the NAND flash memory.

9. A tag component mounted on a substrate having a first semiconductor device and a second semiconductor device, the first semiconductor device and the second semiconductor device being spaced apart in a first direction, the tag component comprising: The first part is disposed in the substrate at a position corresponding to the position where the first semiconductor device is disposed in a second direction perpendicular to the first direction; The second part is disposed in the substrate in the second direction at a position corresponding to the position where the second semiconductor device is disposed; and Part 3 suppresses heat conduction between the heat of Part 1 and the heat of Part 2. The third part is formed of an insulating material. A portion of the third part is located between the first part and the second part in the first direction, and the first part and the second part are embedded in the third part in such a way that the first part and the second part are not exposed on the surface of the third part. The first thermal conductivity of the first part and the second thermal conductivity of the second part are both higher than the third thermal conductivity of the third part.

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