Semiconductor memory device

Abstract

Embodiments provide a semiconductor storage device capable of suppressing power consumption and heat generation. The semiconductor storage device of the embodiments has a plastic package including: an inductor; a first storage chip including a step-up circuit that steps up a first voltage to a second voltage using the inductor; and a second storage chip having a terminal supplied with the second voltage from the first storage chip.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2021-044868 (filed on March 18, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] One embodiment of this disclosure relates to a semiconductor memory device. Background Technology

[0003] As non-volatile memories such as flash memory continue to increase in density and performance, they tend to increase power consumption and heat generation during operation. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor memory device that can suppress power consumption and heat generation.

[0005] According to one embodiment of the present disclosure, a semiconductor memory device is provided, comprising: a memory chip having a plurality of non-volatile memory cells having charge corresponding to written data stored in a charge storage region; an inductor; a boost circuit that generates a boost voltage obtained by boosting a reference voltage using the inductor; and a package that houses the memory chip, the inductor, and the boost circuit, the memory chip having a terminal that is supplied with the boost voltage or connected to one end of the inductor. Attached Figure Description

[0006] Figure 1 This is a diagram showing a schematic structure of the semiconductor memory device according to the first embodiment.

[0007] Figure 2 This is a circuit diagram illustrating an example of the internal structure of a boost circuit.

[0008] Figure 3 This diagram illustrates the construction of a boost circuit that boosts a reference voltage.

[0009] Figure 4 yes Figure 3 Voltage waveforms of each part.

[0010] Figure 5 This diagram illustrates an example of a chip with a boost circuit housed within a package.

[0011] Figure 6 This is a diagram showing a schematic structure of the semiconductor memory device according to the second embodiment.

[0012] Figure 7 It is a block diagram showing a schematic structure of a storage system having the semiconductor storage device according to the first embodiment or the second embodiment.

[0013] Label Explanation

[0014] 10 Storage system; 11, 11a, 11b Semiconductor storage devices; 12 NAND memory chip; 13 Inductor; 14 Boost circuit; 15 Package; 16 Chip; 21 Transistor (switching element); 22 Diode; 23 Resistor voltage divider circuit; 24 Control circuit; 25 Capacitor; 26 Gate driver; 27 Stabilization filter; 100 NAND flash memory; 101 NAND bus; 102 Host bus; 110 Memory cell array; 120 Row decoder; 130 Driver circuit; 140 Column control circuit; 150 Register group; 160 Sequencer; 200 Controller; 210 Host interface circuit; 220 Internal RAM; 230 Processor (CPU); 240 Buffer memory; 250 NAND interface circuit; 260 ECC circuit. Detailed Implementation

[0015] Hereinafter, embodiments of the semiconductor memory device will be described with reference to the accompanying drawings. The description will focus on the main components of the semiconductor memory device, but additional components and functions not shown or described may exist within the semiconductor memory device. The following description does not exclude components and functions not shown or described.

[0016] (First Embodiment)

[0017] Figure 1 This is a diagram showing the schematic structure of the semiconductor memory device 11 according to the first embodiment. Figure 1 The semiconductor storage device 11 has a storage chip 12 including non-volatile storage cells.

[0018] The non-volatile memory cell has a charge accumulation region where charge corresponding to the written data is accumulated. This embodiment can be widely applied to semiconductor memory devices 11 having non-volatile memory cells including such charge accumulation regions. A representative example of the semiconductor memory device 11 according to this embodiment is a flash memory. Flash memories include NAND and NOR types, but this embodiment can be applied to any type. Flash memories have a floating gate and a charge trapping film as charge accumulation regions, but this embodiment is independent of the type of charge accumulation region. Hereinafter, a memory chip 12 having NAND flash memory will be mainly described.

[0019] Figure 1The semiconductor memory device 11 includes a package 15 housing the memory chip 12, inductor 13, and boost circuit 14 described above. Package 15 can be of various shapes and / or sizes, but this embodiment is independent of the type of package 15. Representative examples of packages 15 applicable to this embodiment include SIP, ZIP, DIP, PGA, SOP, SOJ, SON, QFP, QFJ, QFN, LGA, and BGA, but other packages 15 may also be used.

[0020] The boost circuit 14 housed in package 15 uses inductor 13 to boost the reference voltage Vin. The reference voltage Vin is supplied from outside package 15 via pin P1. The reference voltage Vin can also be the power supply voltage of the semiconductor memory device 11. The voltage level of the reference voltage Vin is envisioned to be a voltage level commonly used in the substrate of package 15 on which the semiconductor memory device 11 is mounted, for example, around 2.5V or 3.3V.

[0021] In typical NAND flash memory, high voltages of around 12V or 26V are used during writing (programming). Therefore, a low reference voltage of around 2.5V (Vin) is input to the NAND flash memory, and a boost circuit built into the NAND flash memory generates a high voltage. This boost circuit typically consists of a charge pump using capacitors. The majority of the power consumed by the charge pump is used for pulling up the voltage level; the power consumed during writing using the high voltage generated by the charge pump is only a few percent of the total power consumption. The large amount of power consumed in pulling up the voltage level means that this power consumption becomes heat, and boost circuits using charge pumps have a high heat generation problem.

[0022] Recently, technology for high-density mounting of more NAND memory chips 12 within a package 15 has been continuously developing, and the miniaturization and integration of each NAND memory chip 12 are also progressing. Conventional NAND memory chips have internal boost circuits; therefore, the higher the density of NAND memory chips 12 mounted within the package 15, the greater the heat generation and power consumption of the package 15. In particular, high-density mounting technology integrating a large number of NAND memory chips 12 has recently become practical. When packaging with a large number of stacked NAND memory chips 12, the boost circuits 14 within each NAND memory chip 12 are arranged close together vertically, potentially leading to a significant increase in heat generation at certain locations within the package 15.

[0023] The upper limit of the temperature at which the NAND memory chip 12 can operate stably is about 85°C. Therefore, a storage system with the NAND memory chip 12 has a structure that monitors the temperature of the NAND memory chip 12 and reduces the access speed and / or performance of the NAND memory chip 12 when the temperature is close to 85°C. Such a structure is called thermal throttling.

[0024] Recent electronic devices tend towards thinner and smaller designs, aiming to densely integrate highly integrated NAND flash memory chips 12 into packages 15. Such packages 15 have little internal space, resulting in poor heat dissipation and a tendency for the NAND flash memory chips 12 to overheat. Therefore, thermal regulation is necessary, but the resulting reduction in access speed and / or performance of the NAND flash memory chips 12 can be a major cause of performance degradation in electronic devices such as smartphones, tablets, and PCs.

[0025] Based on the above background, this embodiment is characterized by the use of an inductor 13 instead of a charge pump for the boost circuit 14 within the package 15. This reduces power consumption and heat generation in the boost circuit 14, and improves power efficiency.

[0026] In this embodiment, the boost circuit 14 is not built into the memory chip 12, but is provided independently within the package 15. The boosted voltage Vbst, after being boosted by the boost circuit 14, is supplied to the terminal (first terminal) TL1 of the memory chip 12. When multiple memory chips 12 are provided within the package 15, a single boost circuit 14 is shared among these multiple memory chips 12, which can further suppress heat generation and further improve power efficiency.

[0027] Furthermore, there is no limitation on the number of memory chips 12 housed in the package 15 in this embodiment; either only one memory chip 12 can be provided, or multiple memory chips 12 can be provided.

[0028] Figure 1 Package 15 incorporates an inductor 13. The inductor 13 is, for example, a spiral or loop wiring pattern formed on a substrate. One end of the inductor 13 is connected to the boost circuit 14, and the other end is connected to pin P1 of package 15. Pin P1 is the location for signal exchange with the outside of package 15, sometimes referred to as a terminal or pad, but in this specification as pin P1. A reference voltage Vin is supplied from outside package 15 via pin P1 to the other end of inductor 13.

[0029] besides, Figure 1The package 15 may also have a pin (pin 2) P2 that connects to the terminals of the memory chip 12. The type of signal input or output to this pin 2 P2 is not particularly important.

[0030] The memory chip 12 has a terminal TL1 for receiving the boosted voltage Vbst supplied by the boost circuit 14 and a terminal TL2 connected to a pin (pin 2) P2 of the package 15. The voltage level of the signal transmitted and received between terminal TL2 and pin 2 P2 is assumed to be lower than the voltage level of the boosted voltage Vbst.

[0031] Figure 2 This is a circuit diagram showing an example of the internal structure of the boost circuit 14. Figure 2 The boost circuit 14 includes a switching element 21, a diode 22 (rectifier circuit), a resistor divider circuit 23, and a control circuit 24. An inductor 13 and a capacitor 25 are connected to the boost circuit 14. The boost circuit 14 may also include the inductor 13 and the capacitor 25, but in this embodiment, the inductor 13 and the capacitor 25 are not included in the boost circuit 14.

[0032] like Figure 1 As shown, inductor 13 is connected between pin P1 of package 15 and terminal TL1 of memory chip 12. Switching element 21 within boost circuit 14 is connected between terminal TL1 and ground. More specifically, switching element 21 can be constructed from a MOS (Metal Oxide Semiconductor) transistor 21. Figure 1 In this text, switching element 21 represents an example of NMOS transistor 21, but switching element 21 can also be PMOS transistor 21. Hereinafter, for example, switching element 21 composed of NMOS transistor 21 will be simply referred to as transistor 21.

[0033] The drain of transistor 21 is connected to terminal TL1, and the source is connected to ground. The anode of diode 22 is connected to the drain of transistor 21. The cathode voltage of diode 22 is the output voltage (boost voltage Vbst) of boost circuit 14. A resistor divider circuit 23 and a capacitor 25 are connected in parallel between the cathode of diode 22 and ground. For example, diode 22 has a P-type semiconductor layer disposed on a substrate and an N-type semiconductor layer disposed on the substrate such that a PN junction is formed at the interface with the P-type semiconductor layer.

[0034] The resistor divider circuit 23 feeds back the voltage obtained by dividing the cathode voltage of diode 22 by the ratio of the resistance values ​​of the two resistor elements R1 and R2 (voltage division ratio) to the control circuit 24. The control circuit 24 controls the gate voltage of transistor 21 so that the divided voltage from the resistor divider circuit 23 matches a predetermined reference voltage. For example, the resistor elements R1 and R2 are polysilicon layers or metal layers disposed on the substrate.

[0035] Inductor 13 can efficiently store electrical energy, thus enabling the output voltage of boost circuit 14, which exits from the cathode of diode 22, to be higher than the reference voltage Vin. Capacitor 25 is provided to smooth the output voltage of boost circuit 14.

[0036] like Figure 2 As indicated by the dashed line, the boost circuit 14 may also have at least one of a gate driver 26 and a stabilization filter 27. The gate driver 26 converts the output voltage of the control circuit 24 into a voltage level suitable for the gate voltage of the transistor 21. The stabilization filter 27 suppresses noise in the divided voltage output from the resistor divider circuit 23.

[0037] Figure 3 This diagram illustrates the construction of the boost circuit 14, which boosts the reference voltage Vin. Figure 4 yes Figure 3 Voltage waveforms of each part. Figure 4 The diagram shows the waveforms of the gate voltage of transistor 21 in boost circuit 14, the current flowing in inductor 13, the output voltage (boost voltage Vbst) of boost circuit 14, and the drain voltage of transistor 21.

[0038] A pulsed voltage signal VGN is periodically input to the gate of transistor 21. This causes transistor 21 to periodically turn on. When transistor 21 is on, current flows from inductor 13 to the drain-source interface of transistor 21, storing power in inductor 13. Figure 4 As shown, the current flowing in inductor 13 increases approximately linearly during the period when transistor 21 is on. When transistor 21 is off, current flows from inductor 13 through diode 22 to capacitor 25 through the power stored in inductor 13. During the period when transistor 21 is off, the current flowing in inductor 13 decreases approximately linearly. Figure 4 As shown, the drain voltage of transistor 21 drops approximately to near ground voltage during the period when transistor 21 is on, and remains approximately constant during the period when it is off. Capacitor 25 smooths the boost voltage Vbst, so although the boost voltage Vbst has slight fluctuations, it becomes a voltage approximately close to DC voltage.

[0039] The power loss in the boost circuit 14 of this embodiment is mainly due to the copper loss of the inductor 13, the on-resistance of the transistor 21, and the on-resistance of the diode 22. However, compared with the case where a boost circuit is constructed using a charge pump, the power loss can be suppressed. Therefore, compared with the case where a boost circuit is constructed using a charge pump, the heat generation can be suppressed.

[0040] Figure 1 and Figure 2 The boost circuit 14 shown can be constructed by mounting separate circuit components on a substrate, or it can be housed in a chip independent of the memory chip 12.

[0041] Figure 5 This is a schematic diagram showing the structure of a semiconductor memory device 11a in which a chip 16 housing a boost circuit 14 is disposed within a package 15. Figure 5 The package 15 internally houses multiple memory chips 12 and a chip 16 that contains a boost circuit 14. The inductor 13 and capacitor 25, connected to the boost circuit 14, are difficult to form within the chip 16 and are therefore configured independently of the chip 16 within the package 15. Figure 5 As shown, by using the boost circuit 14 as chip 16, the manufacture of package 15 becomes easier. Alternatively, multiple chips 16 having the same or different types of boost circuits 14 can be arranged within package 15.

[0042] Thus, in the semiconductor memory devices 11 and 11a according to the first embodiment, the boost circuit 14 that generates a boost voltage Vbst using the inductor 13 is provided within the package 15 independently of the memory chip 12. Therefore, the power consumption and heat generation of the memory chip 12 can be reduced. According to the package 15 of this embodiment, the boost voltage Vbst can be supplied from one boost circuit 14 to multiple memory chips 12. Therefore, the more memory chips 12 are stacked within the package 15, the more the power consumption and heat generation of the package 15 can be suppressed. In particular, when the boost circuit 14 is provided within the memory chip 12, when multiple memory chips 12 are stacked, the multiple boost circuits 14 are arranged close together vertically, and the heat generation in certain parts of the package 15 will increase. However, in this embodiment, the boost circuit 14 is not provided within the memory chip 12, so there is no risk of abnormally high temperature in certain parts of the package 15. Furthermore, the boost circuit 14 of this embodiment uses an inductor 13 to generate the boost voltage Vbst instead of a charge pump, thus improving power efficiency compared to a boost circuit that uses a charge pump.

[0043] Furthermore, in the above description, as an example, the inductor 13 is described as a spiral or loop wiring pattern formed on a substrate. The configuration is not limited to the spiral or loop wiring pattern described above. The inductor 13 is configured within the package 15 to satisfy the aforementioned connection relationships with other structures.

[0044] (Second Implementation)

[0045] In the first embodiment, a boost circuit 14 is provided in the package 15 independently of the memory chip 12, but the boost circuit 14 may also be configured in the memory chip 12.

[0046] Figure 6 This is a diagram showing the schematic structure of the semiconductor memory device 11b according to the second embodiment. Figure 6 The semiconductor memory device 11 has a plurality of memory chips 12 configured within a package 15.

[0047] Figure 6 The semiconductor memory device 11 includes a first memory chip 12a and a second memory chip 12b. The first memory chip 12a has a boost circuit 14 that uses an inductor 13 to boost a first voltage to a second voltage. The second memory chip 12b has a terminal from which the second voltage is supplied from the first memory chip 12a. When multiple second memory chips 12b are present, the second voltage is supplied from the first memory chip 12a to each of the multiple second memory chips 12b. Alternatively, multiple first memory chips 12a and multiple second memory chips 12b may also be present.

[0048] Specifically, package 15 is a plastic package. The plastic package has a resin body covering the inductor 13 and the memory chip 12. The resin body is formed, for example, from epoxy resin.

[0049] In package 15, in addition to the multiple memory chips 12, an inductor 13 and a capacitor 25 are also packaged. One end of the capacitor 25 is connected to the output node of the rectifier circuit 22, and the other end of the capacitor 25 is set to ground potential.

[0050] The first memory chip 12a has a built-in boost circuit 14, while the second memory chip 12b does not. The boost voltage Vbst generated in the first memory chip 12a with the built-in boost circuit 14 is used for writing to the NAND flash memory within the first memory chip 12a, and is also supplied to the second memory chip 12b, which does not have the boost circuit 14. The inductor 13 connected to the transistor 21 in the boost circuit 14 and the capacitor 25 disposed between the cathode of the diode 22 and the ground node are large in size, making it difficult to incorporate them into the first memory chip 12a. Therefore, the inductor 13 and the capacitor 25 are disposed independently of the first memory chip 12a within the package 15.

[0051] The first memory chip 12a has a first terminal TL1 connected to one end of the inductor 13, and a second terminal TL2 connected to the output node of the rectifier circuit 22 and one end of the capacitor 25. The first memory chip 12a and the second memory chip 12b have a third terminal TL3 connected to one end of the capacitor 25. The first memory chip 12a and the second memory chip 12b each have a fourth terminal TL4 that is supplied with a third voltage lower than the second voltage.

[0052] Thus, in the second embodiment, a boost circuit 14 is provided in at least one of the plurality of memory chips 12 disposed within the package 15. Furthermore, the boost voltage Vbst generated by the boost circuit 14 is supplied to the memory chips 12 that do not have the boost circuit 14. Therefore, it is sufficient that most of the memory chips 12 within the package 15 do not require a boost circuit 14, thereby suppressing power consumption and heat generation. In addition, the boost circuit 14 in this embodiment, like the boost circuit 14 in the first embodiment, utilizes an inductor 13 instead of a charge pump for voltage boosting, thus improving power efficiency.

[0053] Furthermore, as an example, the inductor 13 described above is, for instance, a spiral or loop wiring pattern formed on a substrate. However, the configuration described is not limited to a spiral or loop wiring pattern formed on a substrate. The inductor 13 is configured within the package 15 to satisfy the aforementioned connection relationships with other structures.

[0054] (Third Implementation)

[0055] The third embodiment describes the specific structure of a storage system 10 having the semiconductor storage device described in the first or second embodiment.

[0056] Figure 7This is a block diagram illustrating a schematic structure of a storage system 10 having the semiconductor storage devices 11, 11a, and 11b according to the first or second embodiment. Hereinafter, an example of a NAND flash memory 100 will be described where the semiconductor storage devices 11, 11a, and 11b are semiconductor storage devices 11, 11a, and 11b. Figure 7 Storage systems such as SSDs (Solid State Drives) are examples of such systems.

[0057] Figure 7 The storage system 10 includes a NAND flash memory 100 and a controller 200. As will be described later, sometimes the NAND flash memory 100 and the controller 200 are mounted on different substrates.

[0058] Figure 7 The NAND flash memory 100 has multiple storage cells and stores data in a non-volatile manner. Figure 7 The NAND flash memory 100 has Figure 1 NAND memory chips 12, etc.

[0059] The controller 200 can also be configured to connect to the NAND flash memory 100 via, for example, a NAND bus 101 provided within a signal transmission cable, and to connect to the host device 300 via a host bus 102. The controller 200 controls the NAND flash memory 100 and responds to commands received from the host device 300, accessing the NAND flash memory 100. The host device 300 is, for example, an electronic device such as a personal computer, and the host bus is a bus with various interfaces. The NAND bus transmits and receives signals via a NAND interface such as Toggle IF.

[0060] The controller 200 includes a host interface circuit 210, an internal memory (RAM) 220, a processor (CPU) 230, a buffer memory 240, a NAND interface circuit 250, and an ECC (Error Checking and Correcting) circuit 260.

[0061] The host interface circuit 210 is connected to the host device 300 via the host bus, and transmits commands and data received from the host device 300 to the CPU 230 and the buffer memory 240, respectively. Additionally, it responds to commands from the CPU 230 and transmits data from the buffer memory 240 to the host device 300.

[0062] CPU 230 controls the overall operation of controller 200. For example, when CPU 230 receives a write command from host device 300, it responds by issuing a write command to NAND interface circuit 250. The same applies to read and erase operations. Furthermore, CPU 230 performs various processes, such as wear leveling, for managing NAND flash memory 100. Moreover, the operations of controller 200 described below can be implemented either by CPU-executed firmware or by hardware.

[0063] The NAND interface circuit 250 is connected to the NAND flash memory 100 via the NAND bus in the signal transmission cable, and is responsible for communication with the NAND flash memory 100. Furthermore, the NAND interface circuit 250 sends various signals to the NAND flash memory 100 based on commands received from the CPU 230, and also receives signals from the NAND flash memory 100. The buffer memory 240 temporarily holds written and read data.

[0064] RAM 220, such as DRAM or SRAM, is a semiconductor memory and is used as the working area of ​​CPU 230. Furthermore, RAM 220 holds firmware, various management tables, and other data used to manage the NAND flash memory 100.

[0065] ECC circuit 260 performs error detection and error correction processing related to the data stored in NAND flash memory 100. That is, ECC circuit 260 generates error correction codes when writing data, assigns them to the written data, and decodes them when reading data.

[0066] Next, the structure of the NAND flash memory 100 will be described. For example... Figure 7 As shown, the NAND flash memory 100 includes a memory cell array 110, a row decoder 120, a driver circuit 130, a column control circuit 140, a register group 150, a sequencer 160, a high voltage generation circuit 170, and a low voltage generation circuit 171.

[0067] The storage cell array 110 comprises multiple block BLKs, each including multiple non-volatile storage cells associated with rows and columns. Figure 6 As an example, four blocks BLK0 to BLK3 are illustrated. Furthermore, the storage cell array 110 stores data provided from the controller 200.

[0068] The row decoder 120 selects one of the blocks BLK0 to BLK3, and further selects the row direction of the selected block BLK. The driver circuit 130 supplies voltage to the selected block BLK via the row decoder 120.

[0069] When reading data, the column control circuit 140 senses the data read from the memory cell array 110 and performs necessary calculations. It then outputs the data DAT to the controller 200. When writing data, it transmits the write data DAT received from the controller 200 to the memory cell array 110.

[0070] Register set 150 includes an address register, a command register, etc. The address register holds the address received from controller 200. The command register holds the command received from controller 200.

[0071] The sequencer 160 controls the overall operation of the NAND flash memory 100 based on various information held in the register group 150.

[0072] High-voltage generation circuit 170 and low-voltage generation circuit 171 generate internal power supply voltages corresponding to the reference voltage Vin input to the NAND flash memory 100. High-voltage generation circuit 170 generates a high-level programming voltage, such as that used when writing data to memory cells. For example, it is used as the input voltage to drivers and row decoders within the NAND flash memory 100. Low-voltage generation circuit 171 generates a low-level internal voltage for driving digital circuits. This internal voltage is used, for example, as the input voltage to register banks, sequencers, and column control circuits 140 within the NAND flash memory 100.

[0073] In the storage system 10 of this embodiment, both a low voltage and a high voltage can be used for the reference voltage Vin input to the NAND flash memory 100, with the high voltage being input to the high voltage generation circuit 170. The high voltage generation circuit 170 is efficient at generating internal voltage from the high voltage, thus suppressing heat generation and reducing power consumption.

[0074] The technical solutions disclosed herein are not limited to the various embodiments described above, but also include various modifications that can be conceived by those skilled in the art, and the effects of this disclosure are not limited to the above content. That is, various additions, changes, and partial deletions can be made without departing from the conceptual idea and spirit of this disclosure derived from the content specified in the claims and their equivalents.

Claims

1. A semiconductor memory device comprising a plastic package, the plastic package including: Inductor; The first memory chip includes a boost circuit that uses the inductor to boost a first voltage to a second voltage; as well as The second memory chip has a terminal on which the second voltage is supplied from the first memory chip. The boost circuit includes: A switching element, one end of which is connected to the inductor, and the other end which becomes ground potential; A rectifier circuit, connected to the inductor, rectifies the output voltage of the switching element; and The control circuit controls the switching element to be turned on or off based on the output voltage of the rectifier circuit. The plastic package includes a capacitor, one end of which is connected to the output node of the rectifier circuit, and the potential of the other end becomes the ground potential. The first memory chip has a first terminal connected to one end of the inductor and a second terminal connected to the output node and the first end of the capacitor. The first memory chip and the second memory chip each have a third terminal connected to one end of the capacitor. The first memory chip and the second memory chip each have a fourth terminal that is supplied with a third voltage that is lower than the second voltage. The plastic package has a first pin that is supplied with the first voltage and connected to the other end of the inductor, and a second pin that is supplied with the third voltage and connected to the second terminal.

2. The semiconductor memory device according to claim 1, The output voltage of the switching element is output from the connection path between the switching element and the inductor.

3. The semiconductor memory device according to claim 1, The capacitor is disposed inside the plastic package independently of the first memory chip and the second memory chip.

4. The semiconductor memory device according to claim 1, The plastic package has a resin body covering the inductor, the first memory chip, and the second memory chip.

5. The semiconductor memory device according to claim 1, The device comprises a plurality of second memory chips, each supplied with the second voltage from the first memory chip.

6. The semiconductor memory device according to claim 1, The rectifier circuit has a P-type semiconductor layer disposed on a substrate and an N-type semiconductor layer disposed on the substrate such that a PN junction is formed at the interface portion with the P-type semiconductor layer.

7. The semiconductor memory device according to claim 1, The switching element includes a MOS transistor, or metal-oxide-semiconductor transistor, disposed on a substrate.

8. The semiconductor memory device according to claim 1, The boost circuit has multiple resistive elements that generate a voltage divider voltage obtained by dividing the output voltage of the rectifier circuit. The control circuit switches the switching element on or off based on the voltage divider voltage. The plurality of resistive elements are polysilicon layers or metal layers disposed on a substrate.

9. The semiconductor memory device according to claim 1, The inductor includes a spiral or ring-shaped wiring pattern disposed on a substrate.

10. The semiconductor memory device according to claim 1, The first memory chip and the second memory chip each have at least one of NAND flash memory and NOR flash memory.

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