A device and method for processing discontinuous data transmission of a decision feedback equalizer

Abstract

The present invention relates to a device and method for processing non-continuous data transmission of a decision feedback equalizer in a memory subsystem. The device includes: a plurality of transmission end detection triggers configured to sample a read data enable signal; a flag trigger; a first logic circuit configured to generate a load enable signal in response to the transmission end detection trigger and the flag trigger; a second logic circuit configured to generate load data in response to the transmission end detection trigger, the flag trigger and the read data enable signal; a plurality of first-in-first-out buffers configured to receive the load enable signal and the load data and unload the load data according to data selection as a transmission end indicator; and a plurality of bypass triggers configured to generate a bypass signal in response to the transmission end indicator. In addition, the bypass signal and the transmission end indicator determine the idle data or the trigger data as the output data. In addition, the output data is multiplied by the coefficient in the decision feedback equalizer.

Description

Technical Field

[0001] The present invention generally relates to a memory subsystem using a decision feedback equalizer, and more particularly to an apparatus and method for processing non-continuous data transmission of a decision feedback equalizer in a memory subsystem. Background Art

[0002] In high-speed physical interfaces, a decision feedback equalizer (DFE) is usually added to the receiver to eliminate the impact of inter-symbol interference (ISI) and thus improve the signal integrity of the input data.

[0003] Many efforts have been made to improve decision feedback equalizers for reliable data transmission. The following references discuss some examples.

[0004] US2018114564A1 discloses a device including a receiver circuit and a data buffer circuit. The receiver circuit may include a decision feedback equalizer (DFE). The data buffer circuit may be configured to initialize the state of the receiver circuit in response to a control signal before receiving a command sequence associated with a directional access to a memory system. The control signal generally indicates the detection of a discontinuous clock associated with the start of a command sequence. The data buffer circuit may generate one or more tap enable signals for determining a plurality of clock cycles during which the contribution of one or more taps of the decision feedback equalizer (DFE) is delayed.

[0005] US2015010047A1 teaches a method comprising receiving an input signal at an input end of a receiver and retrieving a data sampling signal and an error sampling signal from the input signal. The method also includes applying an adaptive process to generate a feedback code using the data sampling signal and the error sampling signal for feedback to a decision feedback equalizer module. In addition, the method also includes converting the feedback code into a corresponding voltage value and assigning the corresponding voltage value as a tap weight of the decision feedback equalizer module. The method finally includes generating an edge sampling signal by applying a decision feedback equalizer to an input signal using a decision feedback equalizer module, wherein the decision feedback equalizer is based on the tap weight.

[0006] The aforementioned references and other solutions may be directed to providing an improved decision feedback equalizer. However, they still have many limitations and disadvantages, for example, they do not provide a solution to handle the misalignment problem caused by discontinuous data transmission of the decision feedback equalizer.

[0007] Figure 1An existing four-tap decision feedback equalizer is shown. The decision feedback equalizer can determine the value of the current sample by adding the current input value to the weighted values ​​of the first four unit intervals (UI) of the data. For example, the current trigger D0 value is equal to the sum of the previous trigger D3 value weighted by W0, the previous trigger D2 value weighted by W1, the previous trigger D1 value weighted by W2, the previous trigger D0 value weighted by W3, and the current input value. The decision feedback equalizer is suitable for continuous data transmission. However, when there is discontinuous data transmission, misalignment problems may occur.

[0008] Figure 2 The waveform diagram is for the case of non-continuous data transmission, where two groups of data transmission are separated by two idle data UIs. The actual obtained value obtained from the decision feedback equalizer of the "J" UI should come from the weighted sum of the two UIs of idle data and the "G" and "H" UIs. However, during the idle time, the data strobe is not triggered, resulting in the idle data not being sampled. Therefore, the existing decision feedback equalizer will improperly take the values ​​of the first four data UIs, namely "H", "G", "F" and "E". Therefore, there is a misalignment between the triggers D0-D3 and the actual state of the I / O pads.

[0009] Therefore, there is still a need to provide an apparatus and method for handling non-continuous data transmission in a decision feedback equalizer in a memory subsystem. Summary of the invention

[0010] The following brief summary of the invention provides a basic understanding of some aspects of the invention. This brief summary is not an extensive overview of the invention, and its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that follows.

[0011] The object of the present invention is to provide a device for processing discontinuous data transmission of a decision feedback equalizer in a memory subsystem.

[0012] Another object of the present invention is to provide a device capable of detecting the end of a group of data transmission.

[0013] Still another object of the present invention is to provide an apparatus that can determine how many idle data unit intervals there are between a group of data transmissions and a subsequent group of data transmissions.

[0014] It is another object of the present invention to provide a device capable of providing bypass staggered arrangement for internal triggers of a decision feedback equalizer during idle time.

[0015] Yet another object of the present invention is to provide a method for processing non-continuous data transmission of a decision feedback equalizer in a memory subsystem.

[0016] Therefore, these objects can be achieved by following the teachings of the present invention. The present invention relates to a device for processing non-continuous data transmission of a decision feedback equalizer in a memory subsystem. The device includes: a plurality of transmission end detection triggers, which are configured to sample a read data enable signal; a flag trigger; a first logic circuit, which is configured to generate a load enable signal in response to the transmission end detection trigger and the flag trigger; a second logic circuit, which is configured to generate load data in response to the transmission end detection trigger, the flag trigger and the read data enable signal; a plurality of first-in-first-out buffers, which are configured to receive the load enable signal and the load data, and unload the load data as a transmission end indicator according to data selection; and a plurality of bypass triggers, which are configured to generate a bypass signal in response to the transmission end indicator. In addition, the bypass signal and the transmission end indicator decide idle data or trigger data as output data. In addition, the output data is multiplied by the coefficients in the decision feedback equalizer.

[0017] The present invention also relates to a method for processing non-continuous data transmission of a decision feedback equalizer in a storage subsystem. The method includes the following steps: sampling a read data enable signal through a plurality of transmission end detection triggers; generating a load enable signal by a first logic circuit in response to the transmission end detection trigger and a flag trigger; generating load data by a second logic circuit in response to the transmission end detection trigger, the flag trigger and the read data enable signal; receiving the load enable signal and the load data by a plurality of first-in-first-out buffers, and unloading the load data as a transmission end indicator according to data selection; and generating a bypass signal by a plurality of bypass triggers in response to the transmission end indicator. In addition, the bypass signal and the transmission end indicator determine idle data or trigger data as output data. In addition, the output data is multiplied by the coefficient in the decision feedback equalizer.

[0018] The foregoing and other objects, features, aspects and advantages of the present invention will become more easily understood in conjunction with the detailed description provided herein below and with appropriate reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to understand the above-mentioned features of the present invention in detail, the present invention briefly summarized above can be specifically described by embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present invention and therefore should not be regarded as limiting the scope of the present invention, and the present invention may allow other equivalent embodiments.

[0020] These and other features, benefits and advantages of the present invention will become apparent by reference to the following drawings, like reference numerals referring to like structures throughout the views, wherein:

[0021] Figure 1 A prior art four-tap decision feedback equalizer is shown.

[0022] Figure 2 It is a waveform diagram in the case of non-continuous data transmission, in which two groups of data transmission are separated by two idle data UIs.

[0023] Figure 3 FIG. 4 is a waveform diagram of a group of data transmissions occurring on the trigger D3 at the end of the transmission according to an embodiment of the present invention.

[0024] Figure 4 FIG. 4 is a waveform diagram of a group of data transmissions occurring on the trigger D1 at the end of the transmission according to an embodiment of the present invention.

[0025] Figure 5 A waveform diagram showing the validation of the read data enable signal to the DDR4 / 5 physical interface by the memory controller for 4 cycles.

[0026] Figure 6 for Figure 5 Waveform diagram when the DFI clock is half rate.

[0027] Figure 7 The logic between two transmission end detection triggers and a flag trigger according to an embodiment of the present invention is shown.

[0028] Figure 8 A first logic circuit according to an embodiment of the present invention is shown.

[0029] Fig. 9 A second logic circuit according to an embodiment of the present invention is shown.

[0030] Fig.10 A second first-in-first-out buffer according to an embodiment of the present invention is shown.

[0031] Fig.11 A first first-in-first-out buffer according to an embodiment of the present invention is shown.

[0032] Fig.12 A waveform diagram of an example in which transfer end_w0[1:0]==2'b11 is shown.

[0033] Fig.13 A waveform diagram of an example in which transfer end_w1[1:0]==2'b01 is shown.

[0034] Fig.14 A bypass trigger circuit for a second FIFO buffer according to an embodiment of the present invention is shown.

[0035] Fig.15A waveform diagram of a bypass trigger circuit for a second FIFO buffer according to an embodiment of the present invention is shown.

[0036] Fig.16 A bypass trigger circuit for a first FIFO buffer according to an embodiment of the present invention is shown.

[0037] Fig.17 A waveform diagram of a bypass trigger circuit for a first FIFO buffer according to an embodiment of the present invention is shown.

[0038] Fig.18 A plurality of bitwise OR operators for generating a bypass signal according to an embodiment of the present invention are shown.

[0039] Fig.19 A decision feedback equalizer according to an embodiment of the present invention is shown.

[0040] Fig. 20 The waveform diagram shows an example of four idle data UIs between two sets of data transmissions.

[0041] Fig.21 The waveform diagram shows an example of two idle data UIs between two sets of data transmissions. DETAILED DESCRIPTION

[0042] As required, detailed embodiments of the present invention are disclosed herein. However, it should be understood that the disclosed embodiments are merely examples of the present invention, which can be implemented in various forms. Therefore, the specific structural and functional details disclosed herein should not be interpreted as restrictive, but only as the basis of the claims. It should be understood that the drawings and their detailed description are not intended to limit the present invention to the specific forms disclosed, on the contrary, the present invention will cover all modifications, equivalent forms and alternative forms within the scope of the present invention defined by the claims. In the terms used throughout this application, the word "may" means the meaning of permission (i.e., it means that it is possible), rather than the mandatory meaning (i.e., it must). Similarly, the word "include, including, includes" means including but not limited to. In addition, unless otherwise specified, the word "a, an" means "at least one", and the word "plurality" means one or more. In the case of using abbreviations or technical terms, they represent the commonly recognized meanings in the technical field.

[0043] Hereinafter, the present invention is described with reference to the accompanying drawings by various embodiments, wherein the reference numerals used in the accompanying drawings correspond to similar elements throughout the specification. However, the present invention can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, the embodiments provided make this disclosure sufficient and complete, and will fully convey the scope of the present invention to those skilled in the art. In the following detailed description, numerical values ​​and ranges are provided for various aspects of the described embodiments. These numerical values ​​and ranges should only be considered as examples, and are not intended to limit the scope of the claims. In addition, many materials are identified as being suitable for various aspects of implementation. These materials will be considered exemplary, and are not intended to limit the scope of the present invention.

[0044] The present invention relates to a device for processing discontinuous data transmission of a decision feedback equalizer in a memory subsystem, comprising a plurality of transmission end detection triggers (2), a flag trigger (4), a first logic circuit (6), a second logic circuit (8), a plurality of first-in-first-out buffers (10A and 10B) and a plurality of bypass triggers. The plurality of transmission end detection triggers (2) are configured to sample a read data enable signal. The first logic circuit (6) is configured to generate a load enable signal in response to the transmission end detection trigger (2) and the flag trigger (4). The second logic circuit (8) is configured to generate load data in response to the transmission end detection trigger (2), the flag trigger (4) and the read data enable signal. The plurality of first-in-first-out buffers (10A and 10B) are configured to receive the load enable signal and the load data, and unload the load data as a transmission end indicator according to data selection. The plurality of bypass triggers are configured to generate a bypass signal in response to the transmission end indicator. In addition, the bypass signal and the transmission end indicator determine idle data or trigger data as output data. In addition, the output data is multiplied by a coefficient in the decision feedback equalizer.

[0045] According to an embodiment of the present invention, the device can be applied to LPDDR4 / 5 and DDR4 / 5 memory subsystems.

[0046] The present invention will be described in detail with reference to the accompanying drawings.

[0047] Figure 3 FIG. 4 is a waveform diagram of a group of data transmissions occurring on the trigger D3 at the end of the transmission according to an embodiment of the present invention. Figure 41 is a waveform diagram of a group of data transmissions occurring on the trigger D1 at the end according to an embodiment of the present invention. If the number of data strobes is an odd number, the end of a group of data transmissions may occur on the trigger D1; if the number of strobes is an even number, the end of a group of data transmissions may occur on the trigger D2. In order to detect which trigger the end of a group of data transmissions occurs on, two first-in-first-out (FIFO) buffers (10A and 10B) are provided. Fig.10 and 11 , a first FIFO buffer (10A) named fifo_w1 is used to detect the end of a group of data transfers occurring on flip-flop D3, and a second FIFO buffer (10B) named fifo_w0 is used to detect the end of a group of data transfers occurring on flip-flop D1. Both FIFO buffers (10A and 10B) have N entries, where N is a power of 2. For example, the two FIFO buffers (10A and 10B) can have 4 entries, 8 entries, or 16 entries. Each entry of the two FIFO buffers (10A and 10B) has two bits.

[0048] According to an embodiment of the present invention, the DDR4 / 5 physical interface is connected to the memory controller via the DDR PHY interface protocol (DFI protocol). The memory controller validates the read data enable (rddata_en) signal to the DDR4 / 5 physical interface to indicate that it wants to receive data from the memory device. The number of cycles of the valid rddata_en signal determines the number of cycles of the data strobe that will be triggered. Figure 5 The waveform diagram of the read data enable signal being validated to the DDR4 / 5 physical interface by the memory controller for 4 cycles is shown, so the data strobe sent from the memory device has 4 pulses. The number of data strobes in this embodiment is four, which is an even number. When CRC data or pre-coding / post-coding is present, the number of data strobes may be an odd number. Figure 6 for Figure 5 The waveform diagram of the DFI clock is half rate, so rddata_en is represented by rddata_en_p0 and rddata_en_p1. In the following embodiments, it is assumed that the DFI clock is half the frequency of the DRAM device clock. In other embodiments, the DFI clock may have the same frequency as the DRAM device clock or the DFI clock may be one quarter of the frequency of the DRAM device clock.

[0049] According to an embodiment of the present invention, two transmission end detection triggers (2) named e_d0 and e_d1 are provided for sampling 2-bit rddata_en signals (rddata_en_p0 and rddata_en_p1) from the DFI interface. A flag trigger (4) named "rolling" is also provided, which acts as a 1-bit flag. Figure 7 The logic between two transmission end detection flip-flops (2) and flag flip-flops (4) is shown. For each cycle, the value of the next rollover is equal to the value of the current rollover plus the values ​​of e_d0 and e_d1.

[0050] According to an embodiment of the present invention, Figure 8 As shown, a first logic circuit (6) is provided to generate a load enable signal in response to a transfer end detection trigger (2) and a flag trigger (4). The first logic circuit (6) includes a plurality of bitwise AND operators and a plurality of bitwise OR operators. Fig. 9 As shown, a second logic circuit (8) is also provided to generate load data in response to the transfer end detection trigger (2), the flag trigger (4) and the read data enable signal. The second logic circuit (8) also includes a plurality of bitwise AND operators and a plurality of bitwise OR operators. Next, the operations of the first logic circuit (6) and the second logic circuit (8) will be explained.

[0051] The value of the next "scroll" = the value of the current "scroll" + the value of e_d0 + the value of e_d1.

[0052] In the first cycle, the value of "roll" is initialized to 0.

[0053] For each cycle, if "roll" == 0, the following situations may occur:

[0054] If e_d0==1 and e_d1==0, or e_d0==0 and e_d1==1, the load enable signal is valid for fifo_w0.

[0055] If e_d0 == 1 and e_d1 == 1, the load enable signal is valid for fifo_w0 and fifo_w1.

[0056] If e_d0==1 and e_d1==0 and rddata_en_p0==0, the load data of 2'b01 is loaded into fifo_w0.

[0057] If e_d0==1 and e_d1==0 and rddata_en_p0==1, the load data of 2′b11 is loaded into fifo_w0.

[0058] If e_d0==1 and e_d1==1 and rddata_en_p0==0 and rddata_en_p1==0, the load data of 2′b01 is loaded into fifo_w1.

[0059] If e_d0==1 and e_d1==1 and rddata_en_p0==0 and rddata_en_p1==1, the load data of 2′b11 is loaded into fifo_w1.

[0060] In other cases, the load data of 2'b00 is loaded into two FIFO buffers (10A and 10B), ie, fifo_w0 and fifo_w1.

[0061] For each cycle, if "roll" == 1, the following situations may occur:

[0062] If e_d0==1 and e_d1==0, or e_d0==0 and e_d1==1, the load enable signal is valid for fifo_w1.

[0063] If e_d0 == 1 and e_d1 == 1, the load enable signal is valid for fifo_w0 and fifo_w1.

[0064] If e_d0==1 and e_d1==0 and rddata_en_p0==0, the load data of 2'b01 is loaded into fifo_w1.

[0065] If e_d0==1 and e_d1==0 and rddata_en_p0==1, the load data of 2′b11 is loaded into fifo_w1.

[0066] If e_d0==1 and e_d1==1 and rddata_en_p0==0 and rddata_en_p1==0, the load data of 2′b01 is loaded into fifo_w0.

[0067] If e_d0==1 and e_d1==1 and rddata_en_p0==0 and rddata_en_p1==1, the load data of 2′b11 is loaded into fifo_w0.

[0068] In other cases, the load data of 2'b00 is loaded into two FIFO buffers (10A and 10B), ie, fifo_w0 and fifo_w1.

[0069] According to an embodiment of the present invention, the FIFO buffers (10A and 10B) indicate the location where the end of a group of data transfers occurs. For example, if fifo_w0 is loaded with load data of 2'b01 or 2'b11, the end of a group of data transfers occurs on trigger D1, because the second FIFO buffer (10B) named fifo_w0 is used to detect the end of a group of data transfers occurring on trigger D1. If fifo_w1 is loaded with load data of 2'b01 or 2'b11, the end of a group of data transfers occurs on trigger D3, because the first FIFO buffer (10A) named fifo_w1 is used to detect the end of a group of data transfers occurring on trigger D3.

[0070] According to an embodiment of the present invention, the FIFO buffer (10A and 10B) unloads the loaded data according to the data strobe as a transmission end indicator. The clock used here is the non-inverting frequency-divided 90 degree strobe for fifo_w0 and the inverting frequency-divided 90 degree strobe for fifo_w1 (equivalent to the frequency-divided 270 degree strobe). Fig.12 , the transfer end indicator from fifo_w0 is unloaded on the rising edge of the 90 degree division strobe. The unloaded data or transfer end indicator is called transfer end_w0 (end_of_transfer_w0), which is 2 bits wide. Fig.13 , the transfer end indicator from fifo_w1 is unloaded according to the falling edge of the frequency division 90 degree strobe. The unloaded data or transfer end indicator is called transfer end_w1 (end_of_transfer_w1), which is 2 bits wide.

[0071] According to an embodiment of the present invention, the transmission end indicator indicates the idle time between the end of a group of data transmissions and the beginning of a group of consecutive data transmissions. The idle time includes two, four or more unit intervals, with two unit intervals increasing each time. For example, if the value of transmission end_w0[1] is 1, two idle data UIs can be seen after the trigger D1 captures the last valid data. If the value of transmission end_w0[1] is 0, four or more idle UIs can be seen after the trigger D1 captures the last valid data. Similarly, if the value of transmission end_w1[1] is 1, two idle UIs can be seen after the trigger D3 captures the last valid data. If the value of transmission end_w1[1] is 0, four or more idle UIs can be seen after the trigger D3 captures the last valid data. Fig.12 The waveform diagram shows an example in which transmission end_w0[1:0]==2'b11, and two idle times U1 can be seen after the first group of data transmission. Fig.13The waveform diagram shows an example in which transfer end_w0[1:0] == 2'b01, four or more idle times UI can be seen after the first set of data transmission.

[0072] Fig.14 A bypass trigger circuit for a second FIFO buffer (10B) fifo_w0 is shown. The bypass trigger circuit includes four bypass triggers, namely bypass_w0[2], bypass_w0[3], bypass_w0[0] and bypass_w0[1]. The end of transmission indicator (i.e., end of transmission_w0[0]) can be used to trigger the logic of four bypass triggers (bypass_w0[3:0]). For example, bypass_w0[2] is timed by end of transmission_w0[0], and its value is set to 1. Then, it is reset to 0 at the next falling edge of the frequency division 0 degree gating (or its equivalent frequency division 180 degree gating). In addition, bypass_w0[3], bypass_w0[0] and bypass_w0[1] are set to 1 at the rising edge of bypass_w0[2]. Bypass_w0[3] is then reset to 0 at the next falling edge of the frequency division 90 degree gating (or its equivalent frequency division 270 degree gating). BYPASS_W0[0] is then reset to 0 on the next rising edge of the divide-by-0 degree strobe, and BYPASS_W0[1] is then reset to 0 on the falling edge of the divide-by-90 degree strobe.

[0073] Fig.15 The waveform diagram of bypass_w0[3:0] according to an embodiment of the present invention is shown, which are asynchronously set when transfer end_w0[0] is valid, and then they are reset to 0 in the manner discussed in the previous paragraphs.

[0074] Fig.16 A bypass trigger circuit for a first FIFO buffer (10A) fifo_w1 is shown. The bypass trigger circuit includes four bypass triggers, namely bypass_w1[2], bypass_w1[3], bypass_w1[0] and bypass_w1[1]. Transmission end_w1[0] can be used to trigger the logic of four bypass triggers bypass_w1[3:0]. For example, bypass_w1[0] is timed by transmission end_w1[0], and its value is set to 1 and then reset to 0 at the rising edge of the next frequency division 0 degree gating. In addition, bypass_w1[1], bypass_w1[2] and bypass_w1[3] are set to 1 at the rising edge of bypass_w1[0]. Bypass_w1[1] is then reset to 0 at the next rising edge of the frequency division 90 degree gating. Bypass_w0[2] is then reset to 0 on the next falling edge of the divide-by-0 gate (or the equivalent rising edge of the divide-by-180 gate). Bypass_w0[3] is then reset to 0 on the falling edge of the divide-by-90 gate (or the equivalent rising edge of the divide-by-270 gate).

[0075] Fig.17The waveforms of bypass_w1[3:0] are shown, which are asynchronously set when transfer end_w1[0] is valid, and then they are reset to 0 in the manner discussed in the previous paragraph.

[0076] According to an embodiment of the present invention, Fig.18 As shown, bypass_w0[3:0] and bypass_w1[3:0] can be combined by a bitwise OR operator to generate a new set of bypass signals bypass[3:0].

[0077] Fig.19 A decision feedback equalizer according to an embodiment of the present invention is shown. The decision feedback equalizer includes a plurality of multiplexers. Each multiplexer can select appropriate idle data or trigger data as output data to be multiplied by each coefficient based on the inputs of bypass [3:0], transmission end_w0 [1], and transmission end_w1 [1]. The logic description of the operation of the multiplexer is as follows.

[0078] For flip-flop D0:

[0079] a. If both bypass[0] and transfer end_w1[1] are valid, select the flip-flop D2 data; if only bypass[0] is valid, select the idle data, otherwise select the previous data of flip-flop D0. The result of the selection is multiplied by the coefficient W3.

[0080] b. If both bypass[1] and transfer end_w1[1] are valid, select the trigger D3 data; if only bypass[1] is valid, select the idle data, otherwise select the trigger D1 data. The result of the selection is multiplied by the coefficient W2.

[0081] c. If bypass [2] is invalid, select the trigger D2 data; if bypass [2] is valid, select the idle data and multiply it by the coefficient W1.

[0082] d. If bypass [3] is invalid, the trigger D3 data is selected; if bypass [3] is valid, the idle data is selected and multiplied by the coefficient W0.

[0083] For trigger D1:

[0084] a. If both bypass[1] and transfer end_w1[1] are valid, select the trigger D3 data; if only bypass[1] is valid, select the idle data, otherwise select the trigger D1 data. The result of the selection is multiplied by the coefficient W3.

[0085] b. If bypass [2] is invalid, select the trigger D2 data; if bypass [2] is valid, select the idle data and multiply it by the coefficient W2.

[0086] c. If bypass [3] is invalid, select the trigger D3 data. If bypass [3] is valid, select the idle data and multiply it by the coefficient W1.

[0087] d. If bypass [0] is invalid, the trigger D3 data is selected; if bypass [0] is valid, the idle data is selected and multiplied by the coefficient W0.

[0088] For trigger D2:

[0089] a. If both bypass[2] and transfer end_w0[1] are valid, select the data of flip-flop D0; if only bypass[2] is valid, select the idle data, otherwise select the previous data of flip-flop D2. The result of the selection is multiplied by the coefficient W3.

[0090] b. If both bypass[3] and transfer end_w0[1] are valid, select the trigger D1 data; if only bypass[3] is valid, select the idle data; otherwise select the trigger D3 data. The result of the selection is multiplied by the coefficient W2.

[0091] c. If bypass [0] is invalid, the trigger D0 data is selected; if bypass [0] is valid, the idle data is selected and multiplied by the coefficient W1.

[0092] d. If bypass [1] is invalid, the trigger D1 data is selected; if bypass [1] is valid, the idle data is selected and multiplied by the coefficient W0.

[0093] For trigger D3:

[0094] a. If both bypass[3] and transfer end_w0[1] are valid, select the trigger D1 data. If only bypass[1] is valid, select the idle data. Otherwise, select the trigger D3 data. The result of the selection is multiplied by the coefficient W3.

[0095] b. If bypass [0] is invalid, select the trigger D0 data. If bypass [0] is valid, select the idle data and multiply it by the coefficient W2.

[0096] c. If bypass [1] is invalid, select the trigger D1 data. If bypass [3] is valid, select the idle data and multiply it by the coefficient W1.

[0097] d. If bypass [2] is invalid, the trigger D2 data is selected. If bypass [0] is valid, the idle data is selected and multiplied by the coefficient W0.

[0098] The present invention also relates to a method for processing non-continuous data transmission of a decision feedback equalizer in a storage subsystem, the method comprising the following steps: sampling a read data enable signal through a plurality of transmission end detection triggers (2); generating a load enable signal by a first logic circuit (6) in response to the transmission end detection trigger (2) and a flag trigger (4); generating load data by a second logic circuit (8) in response to the transmission end detection trigger (2), the flag trigger (4) and the read data enable signal; receiving the load enable signal and the load data by a plurality of first-in-first-out buffers (10A and 10B), and unloading the load data as a transmission end indicator according to data selection; and generating a bypass signal by a plurality of bypass triggers in response to the transmission end indicator. In addition, the bypass signal and the transmission end indicator determine the idle data or the trigger data as the output data. In addition, the output data is multiplied by the coefficient in the decision feedback equalizer.

[0099] The present invention will be described in more detail below by examples, from which the advantages of the present invention can be more easily understood and put into practice. However, it should be understood that the following examples are not intended to limit the scope of the present invention in any way.

[0100] Examples

[0101] In the first example, there are four idle UIs between two data transfers. The end of the first data transfer occurs on the D1 flip-flop. Therefore, transfer end_w0[1:0] is 2'b01. The idle data value is assumed to be 1. Fig. 20 , the operation of this example is described as follows:

[0102] a) At time point 11, there is the last data block in UI'K' of the first data transmission, which is sampled into flip-flop D1 at the rising edge of the divided 90 degree strobe.

[0103] b) At time point 11, transfer_w0[0] is also valid, which causes bypass_w0[3:0] to be valid.

[0104] c) From time point 12 to 15, there are four idle data UIs.

[0105] d) At time point 16, the falling edge of the divided 0 degree strobe samples the next valid data "L" into flip-flop D2. The decision feedback equalizer of flip-flop D2 evaluates the logic discussed previously, where:

[0106] i. Only bypass [2] is valid (transmission end_w0 [1] is invalid), and the idle data is selected and multiplied by the coefficient W3.

[0107] ii. Only bypass [3] is valid (transmission end_w0 [1] is invalid), and the idle data is selected and multiplied by the coefficient W2.

[0108] iii. Select idle data to multiply by coefficient W1 because bypass [0] is valid.

[0109] iv. Select idle data to multiply by coefficient W0 because bypass [1] is valid.

[0110] e) At time 17, bypass [2] is invalid. The falling edge of the divided 90 degree strobe samples the valid data "M" into flip-flop D3. The decision feedback equalizer of flip-flop D3 evaluates the logic discussed previously, where:

[0111] i. Only bypass [3] is valid (transmission end_w0 [1] is invalid), and the idle data is selected and multiplied by the coefficient W3.

[0112] ii. Select idle data to multiply by coefficient W2 because bypass [1] is valid.

[0113] iii. Select idle data to multiply by coefficient W1 because bypass [1] is valid.

[0114] iv. Bypass [2] is invalid, so the trigger D2 data is selected to be multiplied by the coefficient W0.

[0115] f) At time 18, bypass [3] is invalid. The rising edge of the divide-by-0 degree strobe samples valid data "N" into flip-flop D0. The decision feedback equalizer of flip-flop D0 evaluates the logic discussed previously, where:

[0116] i. Bypass [0] is still valid, so the idle data is selected and multiplied by the coefficient W3.

[0117] ii. Bypass [1] is still valid, so the idle data is selected and multiplied by the coefficient W2.

[0118] iii. Select the trigger D2 data to be multiplied by the coefficient W1 because bypass [2] is no longer valid.

[0119] iv. Select the trigger D3 data to be multiplied by the coefficient W0, since bypass [3] is no longer valid.

[0120] g) At time 19, bypass [0] is invalid. The rising edge of the divided 90 degree strobe samples the valid data "P" into flip-flop D1. The decision feedback equalizer of flip-flop D1 evaluates the logic described above, where:

[0121] i. Bypass [1] is still valid, so the idle data is selected and multiplied by the coefficient W3.

[0122] ii. Select the trigger D2 data to be multiplied by the coefficient W2 because bypass [2] is no longer valid.

[0123] iii. Select the trigger D3 data to be multiplied by the coefficient W1 because bypass [3] is no longer valid.

[0124] iv. Select the flip-flop D0 data to be multiplied by the coefficient W0, since bypass [0] is no longer valid.

[0125] In the second example, there are two idle UIs between the two sets of data transfers. The end of the first data transfer occurs on the D3 flip-flop. Therefore, transfer end_w1[1:0] is 2'b11. The idle data value is assumed to be 1. Fig.21 , the operation of this example is described as follows:

[0126] a) At time point 9, there is the last data block "H", which is sampled into flip-flop D3 at the falling edge of the divided-by-90 degree strobe.

[0127] b) From time point 10 to time 11, there are two idle UIs.

[0128] c) At time point 12, the rising edge of the divided-by-0 degree strobe samples the next valid data "J" into flip-flop D0. The decision feedback equalizer of flip-flop D0 evaluates the logic described above, where:

[0129] i, bypass[0] and transfer end_w1[1] are all valid, and then the trigger D2 data is selected to be multiplied by the coefficient W3.

[0130] ii. Bypass[1] and transfer end_w1[1] are both valid, and then the trigger D3 data is selected to be multiplied by the coefficient W2.

[0131] iii. Select idle data to multiply by coefficient W1 because bypass [2] is valid.

[0132] iv. Select idle data to multiply by coefficient W0 because bypass [3] is valid.

[0133] d) At time 13, bypass [0] is invalid and the rising edge of the 90 degree gate samples the valid data at flip-flop D1. The decision feedback equalizer of flip-flop D1 evaluates the logic described above, where:

[0134] i, bypass[1] and transfer end_w1[1] are all valid, and then the trigger D3 data is selected and multiplied by the coefficient W3.

[0135] ii. Select idle data to multiply by coefficient W2 because bypass [2] is valid.

[0136] iii. Select idle data to multiply by coefficient W1 because bypass [3] is valid.

[0137] iv. Bypass [0] is invalid, so the trigger D0 data is selected to be multiplied by the coefficient W0.

[0138] e) At time 14, bypass [1] is inactive. The falling edge of the divided-by-0 degree strobe samples the valid data at flip-flop D2. The decision feedback equalizer of flip-flop D2 evaluates the logic described above, where:

[0139] i. Bypass [2] is still valid, so the idle data is selected and multiplied by the coefficient W3.

[0140] ii. Bypass [3] is still valid, so the idle data is selected and multiplied by the coefficient W2.

[0141] iii. Select the trigger D0 data to be multiplied by the coefficient W1 because bypass [0] is no longer valid.

[0142] iv. Select the trigger D1 data to be multiplied by the coefficient W0, since bypass [1] is no longer valid.

[0143] f) At time 15, bypass [2] is invalid. The falling edge of the divided 90 degree strobe samples the valid data at flip-flop D3. The decision feedback equalizer of flip-flop D3 evaluates the logic described above, where:

[0144] i. Bypass [3] is still valid, so the idle data is selected and multiplied by the coefficient W3.

[0145] ii. Select the flip-flop D0 data to be multiplied by the coefficient W2 because bypass [0] is no longer valid.

[0146] iii. Select the trigger D1 data to be multiplied by the coefficient W1 because bypass [1] is no longer valid.

[0147] iv. Select the trigger D2 data to be multiplied by the coefficient W0 because bypass [2] is no longer valid.

[0148] The above-described apparatus overcomes the problems and deficiencies of the prior art. For example, the apparatus of the present invention utilizes FIFO buffers (10A and 10B) to determine when the previous set of transmissions ends and how much idle data UI exists before the subsequent set of transmissions begins. In addition, the apparatus of the present invention utilizes bypass logic to provide staggered idle data bypass for the decision feedback equalizer to properly handle non-continuous data streams.

[0149] Various modifications to these embodiments will be apparent to those skilled in the art through the description and drawings. The principles associated with the various embodiments described herein may be applied to other embodiments. Therefore, the description of the invention is not intended to be limited to the embodiments associated with the attached drawings. Figure 1The present invention is not limited to the embodiments shown, but provides the broadest scope consistent with the principles and novel and inventive features disclosed or suggested herein. Therefore, all alternatives, modifications and changes made according to the present invention fall within the scope of the present invention and the appended claims.

[0150] In the appended claims and the preceding description of the present invention, unless the context requires otherwise due to expressive language or necessary meaning, the word "comprise" or variations of "comprises" (comprises, comprising) are used in an inclusive sense. That is, in various embodiments of the present invention, the presence of the stated features is specified but the presence or addition of other features is not excluded.

Claims

1. A device for processing discontinuous data transmission of a decision feedback equalizer in a memory subsystem, characterized in that: The device comprises: a plurality of transfer end detection triggers (2) configured to sample a read data enable signal; Flag trigger (4); a first logic circuit (6) configured to generate a load enable signal in response to the transfer end detection trigger (2) and the flag trigger (4); a second logic circuit (8) configured to generate load data in response to the transfer end detection trigger (2), the flag trigger (4) and the read data enable signal; a plurality of first-in-first-out buffers (10A, 10B) configured to receive the load enable signal and the load data and unload the load data according to a data strobe as a transfer end indicator; and a plurality of bypass triggers configured to generate bypass signals in response to the end-of-transmission indicator; wherein the bypass signal and the transmission end indicator determine idle data or trigger data as output data; Wherein, the output data is multiplied by the coefficients in the decision feedback equalizer.

2. The device according to claim 1, characterized in that The first logic circuit (6) includes a plurality of bitwise AND operators and a plurality of bitwise OR operators.

3. The device according to claim 1, characterized in that The second logic circuit (8) includes a plurality of bitwise AND operators and a plurality of bitwise OR operators.

4. The device according to claim 1, characterized in that The apparatus also includes a plurality of multiplexers configured to select the idle data or the trigger data based on the bypass signal and the end-of-transmission indicator.

5. The device according to claim 1, characterized in that The apparatus also includes a plurality of bitwise OR operators to generate the bypass signal.

6. A method for processing discontinuous data transmission of a decision feedback equalizer in a storage subsystem, characterized in that: The method comprises the following steps: The read data enable signal is sampled by a plurality of transfer end detection triggers (2); A first logic circuit (6) generates a load enable signal in response to the transmission end detection trigger (2) and the flag trigger (4); The second logic circuit (8) generates load data in response to the transmission end detection trigger (2), the flag trigger (4) and the read data enable signal; A plurality of first-in-first-out buffers (10A, 10B) receive the load enable signal and the load data, and unload the load data according to data strobe as a transmission end indicator; and generating a bypass signal by a plurality of bypass triggers in response to the transmission end indicator; wherein the bypass signal and the transmission end indicator determine idle data or trigger data as output data; Wherein, the output data is multiplied by the coefficients in the decision feedback equalizer.

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