Magnetic storage unit with integrated storage and computing

Abstract

The present invention provides a magnetic storage unit that integrates storage and computing, comprising: a heavy metal layer, a magnetic tunnel junction located on the surface of the heavy metal layer, and an electrode on the surface of the magnetic tunnel junction. The magnetic tunnel junction comprises: a free layer, a barrier layer, and a reference layer stacked in sequence. The free layer is disposed adjacent to the heavy metal layer, and the interaction between the heavy metal layer and the free layer is a spin-orbit moment and a DMI effect. The heavy metal layer has at least three power ports, including two input ports and a control port. The states of the two input ports and the control port jointly determine the direction of current in the heavy metal layer, thereby further determining the resistance state information of the magnetic tunnel junction. The present invention can fully utilize the physical properties of SOT-MRAM for in-memory computing.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic memory, and in particular to a magnetic storage unit integrating storage and computing. Background Art

[0002] In recent years, with the development of big data and AI, the demand for computing power in related applications has also increased. However, in traditional von Neumann architecture computers, computing and storage are separated. The frequent access and storage of data consumes a lot of power, which has become a bottleneck for intelligent computing.

[0003] The integrated storage and computing architecture is considered an effective means of addressing the storage wall and memory access power consumption wall issues currently encountered in the von Neumann architecture. In this architecture, the storage unit directly incorporates logical computing capabilities, effectively eliminating data movement latency and power consumption.

[0004] Spin-orbit torque magnetic RAM (SOT-MRAM) boasts high write speed, low power consumption, high integration, programmable logic, and CMOS compatibility, making it ideal for designing integrated storage and computing computers. However, there is currently no effective magnetic storage unit that can achieve this integration. Summary of the Invention

[0005] To solve the above problems, the present invention provides a magnetic storage unit with integrated storage and computing, which can fully utilize the physical properties of SOT-MRAM to perform in-memory computing.

[0006] In a first aspect, the present invention provides a magnetic storage unit integrating storage and computing, comprising:

[0007] Heavy metal layer;

[0008] a magnetic tunnel junction located on the surface of the heavy metal layer, the magnetic tunnel junction comprising: a free layer, a barrier layer, and a reference layer stacked in sequence, the free layer being adjacent to the heavy metal layer, and the interaction between the heavy metal layer and the free layer being spin-orbit moment and DMI effect;

[0009] an electrode, wherein the electrode is located on a surface of the reference layer;

[0010] The heavy metal layer has at least three power ports, including two input ports and one control port. The states of the two input ports and the control port jointly determine the direction of the current in the heavy metal layer, thereby further determining the resistance state information of the magnetic tunnel junction.

[0011] The electrode has a reading terminal, and when reading the resistance state information of the magnetic tunnel junction, the reading terminal inputs a reading voltage.

[0012] Optionally, the magnetic anisotropy of the magnetic tunnel junction is perpendicular magnetic anisotropy.

[0013] Optionally, the cross-section of the heavy metal layer is Y-shaped, with three sides of equal length and angles of 120°, and the two input terminals and the control terminal are respectively located at three ends of the Y-shaped heavy metal layer.

[0014] Optionally, when the control terminal is open and the Y-shaped heavy metal layer current flows from one input terminal to the other input terminal, if the current direction is clockwise, the magnetic tunnel junction is in a low-resistance state; if the current direction is counterclockwise, the magnetic tunnel junction is in a high-resistance state;

[0015] When the current of the Y-shaped heavy metal layer flows from any two ends of the three ends to the other end, the resistance state of the magnetic tunnel junction changes;

[0016] When the Y-shaped heavy metal layer current flows from any one of the three ends to the other two ends, the resistance state of the magnetic tunnel junction remains unchanged.

[0017] Optionally, the material combination of the free layer and the heavy metal layer is any one of Co / Pt, CoFe / Pt, CoFeB / Pt, Co / W, CoFe / W, CoFeB / W, Co / Ir, Co / Tb, CoFeB / Mo, CoFeB / Cr, and CoFeB / Ta.

[0018] In a second aspect, the present invention provides a data selector, comprising: a magnetic storage unit with integrated storage and computing as provided in the first aspect, a first NMOS tube and a first PMOS tube, the control end of the heavy metal layer is grounded, one input end of the heavy metal layer is connected to the drain of the first NMOS tube, the source of the first NMOS tube inputs a high-level signal, the other input end of the heavy metal layer is connected to the drain of the first PMOS tube, the source of the first PMOS tube inputs a high-level signal, the gate of the first NMOS tube and the gate of the first PMOS tube respectively serve as two input ends of the data selector.

[0019] In a third aspect, the present invention provides a full subtractor, comprising: a magnetic storage unit with integrated storage and computing as provided in the first aspect and a second NMOS tube, the control end of the heavy metal layer is connected to the drain of the second NMOS tube, the source of the second NMOS tube inputs a high-level signal, the gate of the second NMOS tube serves as the control end of the full subtractor, and the two input ends of the heavy metal layer serve as the two input ends of the full subtractor.

[0020] In a fourth aspect, the present invention provides a full adder, comprising: a magnetic storage unit with integrated storage and computing as provided in the first aspect, a third NMOS transistor, and an inverter, wherein the control end of the heavy metal layer is connected to the drain of the third NMOS transistor, a high-level signal is input to the source of the third NMOS transistor, the gate of the third NMOS transistor serves as the control end of the full adder, one input end of the heavy metal layer is connected to the output end of the inverter, and the other input end of the heavy metal layer and the input end of the inverter serve as two input ends of the full adder.

[0021] In a fifth aspect, the present invention provides an array structure comprising: a plurality of units arranged in rows and columns, wherein each unit comprises the magnetic storage unit with integrated storage and computing as provided in the first aspect, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor;

[0022] An input end of the heavy metal layer is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the word line CWL, and the source of the fourth NMOS transistor is connected to the bit line RBL;

[0023] Another input end of the heavy metal layer is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the word line RWL, and the drain of the fifth NMOS transistor is connected to the bit line CBL;

[0024] The control end of the heavy metal layer is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the word line CWWL, the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the word line RWWL, and the source of the seventh NMOS transistor is grounded;

[0025] The reading end of the heavy metal layer is connected to the source of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected to the word line WL, and the drain of the eighth NMOS transistor is connected to the source line;

[0026] Among them, the word line WL is used to read the resistance value of the magnetic tunnel junction, the word lines CWL and RWL respectively control the on and off of the magnetic storage cells on the target column and target row, the word lines CWWL and RWWL respectively control whether the magnetic storage cells on the target column and target row are grounded, the bit lines CBL and RBL are respectively used to input data to the two input terminals of the magnetic storage cells, and the source line SL voltage is at a high level.

[0027] The present invention provides a magnetic storage unit with integrated storage and computation, which fully utilizes the physical properties of SOT-MRAM for in-memory computation. It combines the high speed and low power consumption of SOT-MRAM, eliminates the need for external magnetic field assistance, and boasts a high level of integration. The integrated magnetic storage unit can perform a variety of arithmetic and logical calculations and can be further used to construct arithmetic and logical computing devices such as data selectors, full subtractors, full adders, and 2-bit multipliers. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A three-dimensional view of a magnetic storage unit provided in one embodiment of the present invention;

[0029] Figure 2 To correspond Figure 1 a side view of the magnetic memory cell shown;

[0030] Figure 3 A schematic diagram of a magnetic storage unit implementing different logics according to an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of a data selector provided by an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of a full subtractor provided in one embodiment of the present invention;

[0033] Figure 6 Flowchart for subtraction operation of full subtractor;

[0034] Figure 7 A schematic diagram of a full adder provided in one embodiment of the present invention;

[0035] Figure 8 Flowchart for addition operation of full adder;

[0036] Figure 9 A schematic diagram of an array structure provided in one embodiment of the present invention;

[0037] Figure 10 Schematic diagram of 2-bit multiplication operation for array structure;

[0038] Figure 11 Schematic diagram of the calculation flow of n-bit multiplier. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0040] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0041] Example 1

[0042] The embodiment of the present invention provides a magnetic storage unit with integrated storage and computing functions, such as Figure 1 and Figure 2 As shown, Figure 1 is a three-dimensional view of a magnetic storage unit. Figure 2 The figure shows a side view of a magnetic storage unit. The magnetic storage unit includes a heavy metal layer 101, a magnetic tunnel junction (MTJ) 102 located on the surface of the heavy metal layer 101, and an electrode 103 on the surface of the MTJ. The MTJ 102 includes at least a free layer 1021, a barrier layer 1022, and a reference layer 1023 stacked in sequence from bottom to top. The free layer 1021 is adjacent to the heavy metal layer 101. The interaction between the heavy metal layer 101 and the free layer 1021 is the spin-orbit moment (SOT) and the Dzyaloshinskii-Moriya interaction (DMI) effect. The electrode 103 is located on the surface of the reference layer 1023. Among them, the heavy metal layer 101 has at least three power-on ports, including two input terminals A and B and a control terminal S. The states of the two input terminals A and B and the control terminal S jointly determine the current direction of the heavy metal layer 101, so as to further determine the resistance state information of the magnetic tunnel junction 102; in addition, the electrode 103 also has a reading terminal M. When reading the resistance state information of the magnetic tunnel junction 102, the reading terminal M inputs a read voltage Vread.

[0043] Furthermore, in this embodiment, the magnetic anisotropy of the magnetic tunnel junction 102 is perpendicular magnetic anisotropy. The material of the free layer 1021 is any one of Co, Fe, CoFe, and CoFeB, and the material of the heavy metal layer 101 is any one of Pt, W, Mo, Ir, Tb, Cr, and Ta. Common combinations of the free layer 1021 and the heavy metal layer 101 can be any one of Co / Pt, CoFe / Pt, CoFeB / Pt, Co / W, CoFe / W, CoFeB / W, Co / Ir, Co / Tb, CoFeB / Mo, CoFeB / Cr, and CoFeB / Ta.

[0044] The heavy metal layer 101 can be implemented in various forms. For example, the cross-section of the heavy metal layer 101 can be designed to be Y-shaped, with three sides of equal length and an included angle of 120°. The two input terminals A and B and the control terminal S are located at the three ends of the Y-shaped heavy metal layer. It should be noted that the three powered ports can be arbitrarily defined as input terminals or control terminals.

[0045] Figure 1 The magnetic storage cell shown is a four-port logic device. The resistance state of the magnetic tunnel junction changes depending on the current flowing through the heavy metal layer. Specifically, when the control terminal S is open and a Y-shaped heavy metal layer current flows from one input terminal to the other, if the current direction is clockwise (from A to B in this case), the magnetic tunnel junction is in a low-resistance state; if the current direction is counterclockwise (from B to A in this case), the magnetic tunnel junction is in a high-resistance state. If current flows through all three terminals, when the Y-shaped heavy metal layer current flows from any two of the three terminals to the other, the resistance state of the magnetic tunnel junction changes, that is, from a low-resistance state to a high-resistance state, or from a high-resistance state to a low-resistance state; when the Y-shaped heavy metal layer current flows from any one of the three terminals to the other two, the resistance state of the magnetic tunnel junction remains unchanged.

[0046] Based on the above resistance change characteristics, the magnetic storage unit with integrated storage and calculation in this embodiment can realize various logical calculations. First, the following definition is made: the values of the two input terminals A and B of the heavy metal layer are represented by A i and B i The voltage of 0 indicates logic "0", and the voltage of high level Vdd indicates logic "1". The voltage of control terminal S can be 0, Vdd or open circuit. The data currently stored in the magnetic tunnel junction is recorded as X i , the next stored data of the magnetic tunnel junction is recorded as X i+1 , X i and X i+1 Indicates the resistance state of the magnetic tunnel junction. In this embodiment, 0 and 1 represent the low resistance state and high resistance state of the magnetic tunnel junction, respectively. i =0 indicates that the magnetic tunnel junction is currently in a low resistance state, X i =1 indicates that the magnetic tunnel junction is currently in high resistance state. i+1 =0 indicates the low resistance state of the magnetic tunnel junction after writing, X i+1 =1 indicates that the magnetic tunnel junction is in a high-resistance state after writing.

[0047] Logical calculation 1: Figure 3 As shown in (a), when the control terminal S of the heavy metal layer is open, X i When it is 0 and 1, the magnetic storage unit performs the actual implication (IMP) and reverse implication (RNIMP) operations respectively, and its logical expression can be expressed as:

[0048]

[0049] The corresponding truth table is shown in Table 1.

[0050] Table 1

[0051]

[0052] Logical calculation 2: Figure 3 As shown in (b), when the control terminal S of the heavy metal layer is at a high level Vdd, X i When it is 0 or 1, the exclusive OR (XOR) and exclusive NOR (XNOR) operations are performed respectively, and the logical expressions can be expressed as:

[0053]

[0054] The corresponding truth table is shown in Table 2.

[0055] Table 2

[0056]

[0057] Logical calculation 3: Figure 3 As shown in (c), when the control terminal S of the heavy metal layer is grounded, X i When it is 0 or 1, AND and NAND operations are performed respectively. The logical expressions can be expressed as follows:

[0058]

[0059] The corresponding truth table is shown in Table 3.

[0060] Table 3

[0061]

[0062] Logical calculation 4: By fixing the input of a certain input terminal, the ternary logic is simplified to binary logic. Figure 3 As shown in (d), when the control terminal S is open and A is at a high level Vdd, an AND operation can be performed, and its logical expression can be expressed as:

[0063] X i+1 =B i X i (4)

[0064] The corresponding truth table is shown in Table 4.

[0065] Table 4

[0066] <![CDATA[X i ]]> <![CDATA[B i ]]> <![CDATA[X i+1 ]]> 0 0 0 0 1 0 1 0 0 1 1 1

[0067] Logical calculation 5: By fixing the input of a certain input terminal, the ternary logic is simplified to binary logic. Figure 3 As shown in (e), when the control terminal S is grounded and B is at a high level Vdd, an exclusive OR (XOR) operation can be implemented, and its logical expression can be expressed as:

[0068]

[0069] The corresponding truth table is shown in Table 5.

[0070] Table 5

[0071] <![CDATA[X i ]]> <![CDATA[A i ]]> <![CDATA[X i+1 ]]> 0 0 0 0 1 1 1 0 1 1 1 0

[0072] The present invention provides a magnetic storage unit that integrates memory and computation. This unit fully utilizes the physical properties of SOT-MRAM for in-memory computation, retaining the high speed and low power consumption characteristics of SOT-MRAM. It also requires no external magnetic field assistance and boasts a high level of integration. The magnetic storage unit can perform a variety of arithmetic and logical calculations.

[0073] Based on the integrated storage and calculation magnetic storage unit provided in the first embodiment, various arithmetic and logic computing devices can be constructed, as described in detail below.

[0074] Example 2

[0075] The embodiment of the present invention provides a data selector, which can be referred to Figure 4 The data selector includes the integrated storage and computing magnetic storage unit provided in the first embodiment, an NMOS transistor NM1, and a PMOS transistor PM1. The control terminal S of the heavy metal layer is grounded. An input terminal A of the heavy metal layer is connected to the drain of NM1. A high-level signal Vdd is input to the source of NM1. Another input terminal B of the heavy metal layer is connected to the drain of PM1. A high-level signal Vdd is input to the source of PM1. A gate C of NM1 and a gate D of PM1 serve as two input terminals of the data selector, respectively. The resistance state information of the magnetic tunnel junction serves as a selection signal of the data selector.

[0076] The data of the two input terminals are still recorded as A i and B i , the logical expression of the data selector can be expressed as:

[0077]

[0078] The corresponding truth table is shown in Table 6.

[0079] Table 6

[0080]

[0081] Example 3

[0082] The embodiment of the present invention provides a full subtractor, which can be referred to Figure 5 The full subtractor includes the integrated storage and computing magnetic storage unit provided in Example 1 and an NMOS transistor NM2. The control terminal S of the heavy metal layer is connected to the drain of NM2. The source of NM2 inputs a high-level signal Vdd. The gate of NM2 serves as the control terminal S1 of the full subtractor. The two input terminals A and B of the heavy metal layer serve as the two input terminals of the full subtractor.

[0083] The values 0 and 1 of the control terminal S1 correspond to the operations of equations (1) and (2) respectively. If A and B continuously input data and read the resistance state X of the MTJ, the logic of the i-th operation is as follows:

[0084]

[0085] The process of subtraction using this logic is as follows Figure 6 As shown in FIG, a serial subtractor is shown, in which the borrow information Ci is stored in the MTJ and the difference Di is read during the calculation.

[0086] Example 4

[0087] The embodiment of the present invention provides a full adder, which can be referred to Figure 7 The full adder includes the integrated storage and computing magnetic storage unit provided in Example 1, an NMOS transistor NM3, and an inverter INV. The control terminal S of the heavy metal layer is connected to the drain of NM3. The source of NM3 inputs a high-level signal Vdd. The gate of NM3 serves as the control terminal S2 of the full adder. The input terminal B of the heavy metal layer is connected to the output terminal of the inverter INV. The other input terminal A of the heavy metal layer and the input terminal B2 of the inverter INV serve as the two input terminals of the full adder.

[0088] The values 0 and 1 of the control terminal S2 correspond to the operations of equations (1) and (2) respectively. If A and B2 continuously input data and read the resistance state X of the MTJ, the logic of the i-th operation is as follows:

[0089]

[0090] The process of using this logic to perform addition is as follows Figure 8 As shown in FIG, a serial adder is shown, in which the carry information Ci is stored in the MTJ, and the sum Si is read during the calculation.

[0091] Example 5

[0092] The embodiment of the present invention provides an array structure, such as Figure 9As shown, the array structure includes a plurality of units distributed in rows and columns, wherein each unit further includes the storage-computing integrated magnetic storage unit provided in Example 1 and five NMOS transistors, denoted as NM4, NM5, NM6, NM7, and NM8. An input terminal A of the heavy metal layer is connected to the drain of NM4, the gate of NM4 is connected to the word line CWL, and the source of NM4 is connected to the bit line RBL; another input terminal B of the heavy metal layer is connected to the source of NM5, the gate of NM5 is connected to the word line RWL, and the drain of NM5 is connected to the bit line CBL; a control terminal S of the heavy metal layer is connected to the drain of NM6, the gate of NM6 is connected to the word line CWWL, the source of NM6 is connected to the drain of NM7, the gate of NM7 is connected to the word line RWWL, and the source of NM7 is grounded; a read terminal M of the heavy metal layer is connected to the source of NM8, the gate of NM8 is connected to the word line WL, and the drain of NM8 is connected to the source line SL;

[0093] Among them, the word line WL is used to read the resistance value of the magnetic tunnel junction, the word lines CWL and RWL respectively control the on and off of the magnetic storage cells on the target column and target row, the word lines CWWL and RWWL respectively control whether the magnetic storage cells on the target column and target row are grounded, the bit lines CBL and RBL are respectively used to input data to the two input terminals of the magnetic storage cells, and the source line SL voltage is a high-level signal Vdd.

[0094] based on Figure 9 The array structure can implement 2-bit multiplication. The calculation process of 2-bit multiplication can be referred to Table 7. 2-bit multiplication can be calculated through a three-step process including initialization. Its logical relationship can be expressed using AND and XOR operations as follows:

[0095]

[0096] Table 7

[0097]

[0098] When performing array calculations, you need to initialize it first and set all X to 0. Figure 10As shown, when a 2-bit multiplication operation is performed on a 2×2 array, except for the word line used for reading, the remaining word lines are all high first, and the four row and column bit lines input a1, b1, a2, and b2 respectively. Then all MTJs will perform the AND / XOR operation of formula (3) to calculate the product of a1, b1, a2, and b2. Then the first word line CWWL is set to a low level, and the four row and column bit lines input 1, 1, a1b2 (read from the MTJ after the operation), and a2b1 (read from the MTJ after the operation). Then the four MTJs perform the operations of unchanged, formula (5), formula (3), and formula (4) respectively. The calculation results are the product values in formula (9) and are stored in the MTJ.

[0099] Furthermore, based on the 2-bit multiplier and n-bit adder, an n-bit multiplier can also be implemented based on the Vedic algorithm. The calculation process is as follows Figure 11 shown.

[0100] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A magnetic storage unit integrating storage and computing, characterized in that: include: Heavy metal layer; A magnetic tunnel junction located on the surface of the heavy metal layer, the magnetic tunnel junction comprising: a free layer, a barrier layer, and a reference layer stacked in sequence, the free layer being adjacent to the heavy metal layer, the interaction between the heavy metal layer and the free layer being spin-orbit moment and DMI effect, and the magnetic anisotropy of the magnetic tunnel junction being perpendicular magnetic anisotropy; an electrode, wherein the electrode is located on a surface of the reference layer; The heavy metal layer has at least three power-on ports, including two input ports and one control port. The cross-section of the heavy metal layer is Y-shaped, and the two input ports and the control port are respectively located at the three ends of the Y-shaped heavy metal layer. The states of the two input ports and the control port jointly determine the direction of the current in the heavy metal layer, thereby further determining the resistance state information of the magnetic tunnel junction. When the control terminal is open and the heavy metal layer current flows from one input terminal to the other input terminal, if the current direction is clockwise, the magnetic tunnel junction is in a low resistance state; if the current direction is counterclockwise, the magnetic tunnel junction is in a high resistance state; When the heavy metal layer current flows from any two of the three terminals to the other terminal, the resistance state of the magnetic tunnel junction changes; When the heavy metal layer current flows from any one of the three terminals to the other two terminals, the resistance state of the magnetic tunnel junction remains unchanged; The electrode has a reading terminal, and when reading the resistance state information of the magnetic tunnel junction, the reading terminal inputs a reading voltage.

2. The magnetic storage unit with integrated storage and computing according to claim 1, characterized in that: The three sides of the Y-shaped heavy metal layer are equal in length and all have an included angle of 120°.

3. The magnetic storage unit with integrated storage and computing according to claim 1, characterized in that: The material combination of the free layer and the heavy metal layer is any one of Co / Pt, CoFe / Pt, CoFeB / Pt, Co / W, CoFe / W, CoFeB / W, Co / Ir, Co / Tb, CoFeB / Mo, CoFeB / Cr, and CoFeB / Ta.

4. A data selector, characterized in that: include: The storage and computing integrated magnetic storage unit, the first NMOS tube and the first PMOS tube as described in any one of claims 1-3, the control end of the heavy metal layer is grounded, one input end of the heavy metal layer is connected to the drain of the first NMOS tube, the source of the first NMOS tube inputs a high-level signal, the other input end of the heavy metal layer is connected to the drain of the first PMOS tube, the source of the first PMOS tube inputs a high-level signal, and the gate of the first NMOS tube and the gate of the first PMOS tube respectively serve as two input ends of a data selector.

5. A full attenuator, characterized in that: include: The storage and computing integrated magnetic storage unit and the second NMOS tube as described in any one of claims 1-3, the control end of the heavy metal layer is connected to the drain of the second NMOS tube, the source of the second NMOS tube inputs a high-level signal, the gate of the second NMOS tube serves as the control end of the full subtractor, and the two input ends of the heavy metal layer serve as the two input ends of the full subtractor.

6. A full adder, characterized in that include: The magnetic storage unit, third NMOS tube and inverter with integrated storage and computing as described in any one of claims 1-3, the control end of the heavy metal layer is connected to the drain of the third NMOS tube, the source of the third NMOS tube inputs a high-level signal, the gate of the third NMOS tube serves as the control end of the full adder, one input end of the heavy metal layer is connected to the output end of the inverter, and the other input end of the heavy metal layer and the input end of the inverter serve as two input ends of the full adder.

7. An array structure, characterized in that: include: A plurality of units distributed in rows and columns, wherein each unit comprises the magnetic storage unit with integrated storage and computing according to any one of claims 1 to 3, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, and an eighth NMOS transistor, An input end of the heavy metal layer is connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the word line CWL, and the source of the fourth NMOS transistor is connected to the bit line RBL; Another input end of the heavy metal layer is connected to the source of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the word line RWL, and the drain of the fifth NMOS transistor is connected to the bit line CBL; The control end of the heavy metal layer is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the word line CWWL, the source of the sixth NMOS transistor is connected to the drain of the seventh NMOS transistor, the gate of the seventh NMOS transistor is connected to the word line RWWL, and the source of the seventh NMOS transistor is grounded; The reading end of the heavy metal layer is connected to the source of the eighth NMOS transistor, the gate of the eighth NMOS transistor is connected to the word line WL, and the drain of the eighth NMOS transistor is connected to the source line; Among them, the word line WL is used to read the resistance value of the magnetic tunnel junction, the word lines CWL and RWL respectively control the on and off of the magnetic storage cells on the target column and target row, the word lines CWWL and RWWL respectively control whether the magnetic storage cells on the target column and target row are grounded, the bit lines CBL and RBL are respectively used to input data to the two input terminals of the magnetic storage cells, and the source line SL voltage is at a high level.

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