Etching method

Abstract

An embodiment of the present invention relates to an etching method. In etching using a catalyst, processing defects are not likely to occur. The etching method of the embodiment includes the following steps: forming a first layer on a substrate having a first and second region on a main surface, wherein the first layer is provided with a plurality of openings or one or more openings defining a plurality of island-shaped portions in a portion covering the first region, and the portion covering the second region is a continuous film; forming a catalyst layer containing a precious metal on a portion of the main surface exposed in the plurality of openings or the one or more openings by a plating method; forming a second layer, wherein the second layer covers a portion of the catalyst layer adjacent to a boundary between the first and second regions, exposing a portion of the catalyst layer spaced from the boundary; and, in the presence of the catalyst layer and the second layer, etching the substrate with an etchant containing an oxidant and hydrogen fluoride.

Description

[0001] This application is based on Japanese Patent Application No. 2021-044887 (filing date: 3 / 18 / 2021), and claims priority from the Japanese Patent Application No. 2021-044887. The entire contents of the Japanese Patent Application No. 2021-044887 are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to etching methods. Background Art

[0003] MacEtch (Metal-Assisted Chemical Etching) is a method for etching the surface of a semiconductor using a noble metal as a catalyst. According to the MacEtch method, for example, a concave portion with a high aspect ratio can be formed on a semiconductor substrate. Summary of the invention

[0004] The problem to be solved by the present invention is to prevent processing defects from occurring easily in etching using a catalyst.

[0005] According to one aspect, an etching method is provided, which includes the following steps: forming a first layer on a substrate comprising a semiconductor material and having a first region and a second region adjacent to each other on a main surface, wherein the first layer covers the first region and the second region, a plurality of openings or more than one opening defining a plurality of island-shaped portions are provided in the portion covering the first region, and a portion covering the second region is a continuous film; forming a catalyst layer comprising a precious metal on a portion of the main surface exposed in the plurality of openings or the more than one opening by a plating method; forming a second layer covering a portion of the catalyst layer adjacent to a boundary between the first region and the second region and exposing a portion of the catalyst layer spaced from the boundary; and, in the presence of the catalyst layer and the second layer, etching the substrate with an etchant comprising an oxidant and hydrogen fluoride.

[0006] According to another aspect, an etching method is provided, which includes the following steps: forming a mask layer on a substrate comprising a semiconductor material and having a first region and a second region adjacent to each other on a main surface, the mask layer comprising a first portion covering the first region and provided with a plurality of openings or one or more openings defining a plurality of island-shaped portions, and a second portion covering the second region as a continuous film, the height of the second portion at a position adjacent to a boundary between the first region and the second region being larger relative to the main surface than the height of the first portion relative to the main surface; forming a catalyst layer comprising a precious metal on a portion of the main surface exposed in the plurality of openings or the one or more openings by a plating method; and etching the substrate with an etchant comprising an oxidant and hydrogen fluoride in the presence of the catalyst layer and the mask layer.

[0007] According to the above method, it is possible to reduce the occurrence of processing defects in etching using a catalyst. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a top view showing an example of a capacitor that can be manufactured by the methods of the first and second embodiments.

[0009] Figure 2 It is along Figure 1 A cross-sectional view of the capacitor taken along line II-II shown in FIG.

[0010] Figure 3 This is a cross-sectional view showing one step in the method for manufacturing the capacitor according to the first embodiment.

[0011] Figure 4 It is a cross-sectional view showing another step in the method for manufacturing the capacitor according to the first embodiment.

[0012] Figure 5 Yes means through Figure 4 The top surface diagram of the structure obtained by the process.

[0013] Figure 6 It is a cross-sectional view showing another step in the method for manufacturing the capacitor according to the first embodiment.

[0014] Figure 7 It is a cross-sectional view showing another step in the method for manufacturing the capacitor according to the first embodiment.

[0015] Figure 8 Yes means through Figure 7 The top surface diagram of the structure obtained by the process.

[0016] Fig. 9 It is a cross-sectional view showing another step in the method for manufacturing the capacitor according to the first embodiment.

[0017] Fig.10 It is a cross-sectional view showing another step in the method for manufacturing the capacitor according to the first embodiment.

[0018] Fig.11 Yes means through Fig. 9 and Fig.10 A cross-sectional view of the structure obtained by the process.

[0019] Fig.12 This is an electron microscope photograph showing an example of a structure obtained when the second layer is omitted.

[0020] Fig.13 This is an electron microscope photograph showing an example of a structure obtained when the second layer is provided.

[0021] Fig.14 This is a cross-sectional view showing one step in the method for manufacturing the capacitor according to the second embodiment.

[0022] Fig.15 Yes means through Fig.14 The top surface diagram of the structure obtained by the process.

[0023] Fig.16 It is a cross-sectional view showing other steps in the method for manufacturing the capacitor according to the second embodiment.

[0024] Fig.17 It is a cross-sectional view showing another step in the method for manufacturing the capacitor according to the second embodiment.

[0025] Fig.18 It is a cross-sectional view showing a modified example of the method for manufacturing the capacitor according to the second embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, the embodiments will be described with reference to the drawings. It should be noted that components having the same or similar functions are denoted by the same reference numerals throughout the drawings, and repeated descriptions are omitted.

[0027] <First Embodiment>

[0028] The etching method of the first embodiment includes the following steps: forming a first layer on a substrate containing a semiconductor material and having a first region and a second region adjacent to each other on a main surface, wherein the first layer covers the first region and the second region, a plurality of openings or one or more openings defining a plurality of island-shaped portions are provided in the portion covering the first region, and a portion covering the second region is a continuous film; forming a catalyst layer containing a precious metal on a portion of the main surface exposed in the plurality of openings or the one or more openings by a plating method; forming a second layer covering a portion of the catalyst layer adjacent to a boundary between the first region and the second region and exposing a portion of the catalyst layer spaced from the boundary; and, in the presence of the catalyst layer and the second layer, etching the substrate with an etchant containing an oxidant and hydrogen fluoride.

[0029] The method for manufacturing a structure according to the first embodiment includes forming one or more recessed portions in the substrate by the etching method.

[0030] The manufacturing method of the semiconductor device of the first embodiment includes: forming one or more recesses in the above-mentioned substrate by the above-mentioned etching method; forming a lower electrode on the side wall of the above-mentioned one or more recesses; forming a dielectric layer on the above-mentioned lower electrode; and forming an upper electrode on the above-mentioned dielectric layer.

[0031] A method of manufacturing a capacitor as an example of a semiconductor device as a structure using the above-mentioned etching method will be described below.

[0032] Figure 1 and Figure 2 An example of a capacitor that can be manufactured by the method of the first embodiment is shown in FIG.

[0033] Figure 1 and Figure 2 The capacitor 1 shown in Figure 2 As shown in FIG. 1 , the conductive substrate CS, the conductive layer 20 b and the dielectric layer 30 are included.

[0034] It should be noted that in each figure, the X direction is a direction parallel to the main surface of the conductive substrate CS, and the Y direction is a direction parallel to the main surface of the conductive substrate CS and perpendicular to the X direction. In addition, the Z direction is the thickness direction of the conductive substrate CS, that is, a direction perpendicular to the X direction and the Y direction.

[0035] The conductive substrate CS includes a semiconductor material such as silicon. The conductive substrate CS is a substrate having conductivity at least on the surface facing the conductive layer 20b. At least a portion of the conductive substrate CS functions as a lower electrode of the capacitor.

[0036] The conductive substrate CS has a first main surface S1, a second main surface S2, and an end surface extending from the edge of the first main surface S1 to the edge of the second main surface S2. Here, the conductive substrate CS has a flat substantially rectangular parallelepiped shape. The conductive substrate CS may have other shapes.

[0037] The first main surface S1, which is the upper surface of the conductive substrate CS, includes a first area A1 and a second area A2. The first area A1 corresponds to a portion of the conductive substrate CS where a recess TR described later is provided. The second area A2 is equal in height to the first area A1. The second area A2 is adjacent to the first area A1. Here, the first area A1 has a rectangular shape, and the second area A2 surrounds the first area A1.

[0038] In the portion corresponding to the first area A1 in the conductive substrate CS, a plurality of recesses TR each having a shape extending in one direction and arranged in the width direction are provided. The recesses TR are open in the first area A1. The recesses TR are spaced apart from each other. Here, the recesses TR are a plurality of channels each extending in the Y direction and arranged in the X direction.

[0039] The portion of the conductive substrate CS sandwiched between one and the other of the adjacent recesses TR is a convex portion. Each of the convex portions has a shape extending in the Y direction and is arranged in the X direction. That is, in the portion of the conductive substrate CS corresponding to the first area A1, a plurality of wall portions each having a shape extending in the Y direction and the Z direction and arranged in the X direction are provided as convex portions.

[0040] It should be noted that the “longitudinal direction” of a concave portion or a convex portion is the longitudinal direction of an orthographic projection of the concave portion or the convex portion on a plane perpendicular to the thickness direction of the conductive substrate.

[0041] The length of the opening of the recess TR is in the range of 10 to 500 μm according to one example, and in the range of 50 to 100 μm according to another example.

[0042] The width of the opening of the recess TR, that is, the distance between adjacent convex portions in the width direction, is preferably 0.3 μm or more. If the width or distance is reduced, a larger capacitance can be achieved. However, if the width or distance is reduced, it becomes difficult to form a stacked structure including the dielectric layer 30 and the conductive layer 20b in the recess TR.

[0043] The depth of the recessed portion TR or the height of the protruding portion is in the range of 10 to 300 μm according to one example, and in the range of 50 to 100 μm according to another example.

[0044] The distance between adjacent recesses TR in the width direction, that is, the thickness of the convex portion, is preferably 0.1 μm or more. If the distance or thickness is reduced, a larger capacitance can be achieved. However, if the distance or thickness is reduced, the convex portion is more likely to be damaged.

[0045] It should be noted that, here, the cross section of the recess TR perpendicular to the longitudinal direction is rectangular. These cross sections may not be rectangular. For example, these cross sections may have a tapered shape.

[0046] The conductive substrate CS includes a substrate 10 and a conductive layer 20 a .

[0047] The substrate 10 has the same shape as the conductive substrate CS. The substrate 10 is a substrate containing a semiconductor material, such as a semiconductor substrate. The substrate 10 is preferably a substrate containing silicon such as a silicon substrate. Such a substrate can be processed using a semiconductor process.

[0048] The conductive layer 20a is provided on the substrate 10. Here, the conductive layer 20a plays a role as a lower electrode of the capacitor. The conductive layer 20a is formed of, for example, polycrystalline silicon doped with impurities to improve conductivity, or a metal or alloy such as molybdenum, aluminum, gold, tungsten, platinum, nickel, and copper. The conductive layer 20a may have a single-layer structure or a multi-layer structure.

[0049] The thickness of the conductive layer 20a is preferably in the range of 0.05 μm to 1 μm, and more preferably in the range of 0.1 μm to 0.3 μm. If the conductive layer 20a is thin, there is a possibility that discontinuous portions will be generated in the conductive layer 20a, or the sheet resistance of the conductive layer 20a will become too large. If the conductive layer 20a is thickened, the manufacturing cost will increase.

[0050] Here, as an example, the substrate 10 is set to be a semiconductor substrate such as a silicon substrate, and the conductive layer 20a is set to be a high-concentration doped layer doped with impurities at a high concentration in the surface area of ​​the semiconductor substrate. In this case, if the convex portions are sufficiently thin, the entire convex portions can be doped with impurities at a high concentration.

[0051] In addition, when the conductivity of the substrate 10 is high, the conductive layer 20a can be omitted and the substrate 10 can be used as a conductive substrate CS. For example, when the substrate 10 is a semiconductor substrate made of a semiconductor doped with P-type or N-type impurities or a metal substrate, the conductive layer 20a can be omitted. In this case, at least the surface area of ​​the substrate 10, for example, the entire substrate 10, plays the role of the conductive layer 20a.

[0052] The conductive layer 20b functions as an upper electrode of the capacitor. The conductive layer 20b is provided on the first region A1 and covers the side walls and the bottom surface of the recess TR.

[0053] Conductive layer 20b is formed of, for example, polysilicon doped with impurities to improve conductivity, or metal or alloy such as molybdenum, aluminum, gold, tungsten, platinum, nickel, and copper. Conductive layer 20b may have a single-layer structure or a multi-layer structure.

[0054] The thickness of the conductive layer 20b is preferably in the range of 0.05 μm to 1 μm, and more preferably in the range of 0.1 μm to 0.3 μm. If the conductive layer 20b is thin, a discontinuous portion may be generated in the conductive layer 20b, or the sheet resistance of the conductive layer 20b may become too large. If the conductive layer 20b is thick, it may be difficult to form the conductive layer 20a and the dielectric layer 30 with sufficient thickness.

[0055] It should be noted that in Figure 2 In the embodiment, the conductive layer 20b is provided in such a manner that the recess TR is completely buried by the conductive layer 20b and the dielectric layer 30. The conductive layer 20b may also be a layer conforming to the surface of the conductive substrate CS. That is, the conductive layer 20b may also be a layer having a substantially uniform thickness. In this case, the recess TR is not completely buried by the conductive layer 20b and the dielectric layer 30.

[0056] The dielectric layer 30 is sandwiched between the conductive substrate CS and the conductive layer 20b. The dielectric layer 30 is a layer conforming to the surface of the conductive substrate CS. The dielectric layer 30 electrically insulates the conductive substrate CS and the conductive layer 20b from each other.

[0057] The dielectric layer 30 is made of, for example, an organic dielectric or an inorganic dielectric. As the organic dielectric, for example, polyimide can be used. As the inorganic dielectric, a strong dielectric can also be used, for example, a normal dielectric such as silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, and tantalum oxide is preferred. The change in dielectric constant of these normal dielectrics due to temperature is small. Therefore, if a normal dielectric is used for the dielectric layer 30, the heat resistance of the capacitor 1 can be improved.

[0058] The thickness of the dielectric layer 30 is preferably in the range of 0.005 μm to 0.5 μm, and more preferably in the range of 0.01 μm to 0.1 μm. If the dielectric layer 30 is thin, there is a possibility that a discontinuous portion will be generated in the dielectric layer 30, or a short circuit will occur between the conductive substrate CS and the conductive layer 20b. In addition, if the dielectric layer 30 is thinned, the withstand voltage will be lowered even if there is no short circuit, and the possibility of short circuit will increase when voltage is applied. If the dielectric layer 30 is thickened, the withstand voltage will be higher, but the capacitance will be reduced.

[0059] The portion of the dielectric layer 30 located on the second area A2 is opened so as to surround the first area A1. That is, the dielectric layer 30 exposes the conductive layer 20a at this position. Here, the portion of the dielectric layer 30 provided on the first main surface S1 is opened in a frame shape.

[0060] The capacitor 1 further includes an insulating layer 60 , a first internal electrode 70 a , a second internal electrode 70 b , a first external electrode 70 c , and a second external electrode 70 d .

[0061] The first inner electrode 70a is provided on the first area A1. The first inner electrode 70a is electrically connected to the conductive layer 20b. Here, the first inner electrode 70a is a rectangular electrode located at the center of the first main surface S1.

[0062] The second inner electrode 70b is provided on the second area A2. The second inner electrode 70b contacts the conductive substrate CS at the position of the opening provided in the dielectric layer 30. Thus, the second inner electrode 70b is electrically connected to the conductive substrate CS. Here, the second inner electrode 70b is a frame-shaped electrode arranged so as to surround the first inner electrode 70a.

[0063] The first internal electrode 70a and the second internal electrode 70b may have a single-layer structure or a multi-layer structure. Each layer constituting the first internal electrode 70a and the second internal electrode 70b is formed of a metal such as molybdenum, aluminum, gold, tungsten, platinum, copper, nickel, or an alloy containing one or more of these.

[0064] The insulating layer 60 covers the conductive layer 20b, the portion of the dielectric layer 30 located on the first main surface S1, the first internal electrode 70a, and the second internal electrode 70b. The insulating layer 60 is partially opened at a portion of the first internal electrode 70a and a portion of the second internal electrode 70b.

[0065] The insulating layer 60 may have a single-layer structure or a multi-layer structure. Each layer constituting the insulating layer 60 is formed of, for example, an inorganic insulator such as silicon nitride and silicon oxide, or an organic insulator such as polyimide and novolac resin.

[0066] The first external electrode 70c is provided on the insulating layer 60. The first external electrode 70c contacts the first internal electrode 70a at the position of one or more openings provided in the insulating layer 60. Thus, the first external electrode 70c is electrically connected to the first internal electrode 70a. Figure 1 In FIG. 7 , the region 70R1 is a region where the first outer electrode 70c is in contact with the first inner electrode 70a.

[0067] The second external electrode 70d is provided on the insulating layer 60. The second external electrode 70d contacts the second internal electrode 70b at the position of the remaining opening provided in the insulating layer 60. Thus, the second external electrode 70d is electrically connected to the second internal electrode 70b. Figure 1 In FIG. 7 , the region 70R2 is a region where the second outer electrode 70d and the second inner electrode 70b are in contact.

[0068] The first external electrode 70c has a laminated structure including a first metal layer 70c1 and a second metal layer 70c2. The second external electrode 70d has a laminated structure including a first metal layer 70d1 and a second metal layer 70d2.

[0069] The first metal layers 70c1 and 70d1 are formed of, for example, copper. The second metal layers 70c2 and 70d2 cover the upper surfaces and end surfaces of the first metal layers 70c1 and 70d1, respectively. The second metal layers 70c2 and 70d2 are made of, for example, a laminated film of a nickel or nickel alloy layer and a gold layer. The second metal layers 70c2 and 70d2 may be omitted.

[0070] The first external electrode 70c or the first internal electrode 70a may further include a barrier layer at a position adjacent to the interface therebetween. In addition, the second external electrode 70d or the second internal electrode 70b may further include a barrier layer at a position adjacent to the interface therebetween. As a material for the barrier layer, titanium may be used, for example.

[0071] The capacitor 1 is manufactured, for example, by the following method. Figure 3 to Figure 11 At the same time, an example of a method for manufacturing capacitor 1 is described.

[0072] In this method, first, prepare Figure 3 As described below, here, as an example, the conductive layer 20a is formed by doping the surface region of the substrate 10 with impurities at a high concentration. Therefore, one main surface and the other main surface of the substrate 10 correspond to the substrate 10 shown in FIG. Figure 2 The first main surface S1 and the second main surface S2 will be described at the same time.

[0073] The first main surface S1 has a Figure 2 The first area A1 and the second area A2 are described at the same time.

[0074] Here, as an example, the substrate 10 is set to be a single crystal silicon wafer. There is no particular problem with the surface orientation of the single crystal silicon wafer. In this example, a silicon wafer whose first main surface S1 is a (100) surface is used. As the substrate 10, a silicon wafer whose first main surface S1 is a (110) surface may also be used.

[0075] Next, a recessed portion is formed in the substrate 10 by MacEtch (Metal-Assisted Chemical Etching).

[0076] That is, first, Figure 3 As shown in , the first layer 90 is formed on the first main surface S1 of the substrate 10 .

[0077] In the portion of the first layer 90 covering the first area A1, a plurality of openings are provided. Here, the plurality of openings are a plurality of slits 90S arranged in the width direction. The length direction of the slits 90S is parallel to the Y direction and arranged in the X direction. In addition, the portion of the first layer 90 covering the second area A2 is a continuous film. The first layer 90 is a first mask layer that prevents the portion of the first main surface S1 covered by the first layer 90 from contacting the noble metal described later.

[0078] The plurality of openings provided in the first layer 90 may have shapes other than slits. For example, the first layer 90 may include a plurality of through holes each of which has a circular, elliptical, or polygonal shape and is arranged in two directions intersecting each other.

[0079] Alternatively, instead of providing a plurality of openings, one or more openings defining a plurality of island-shaped portions may be provided in the first layer 90. In this case, pillar-shaped protrusions can be generated at positions corresponding to the island-shaped portions by etching described later.

[0080] Examples of the material of the first layer 90 include organic materials such as polyimide, fluororesin, phenolic resin, acrylic resin, and novolac resin, and inorganic materials such as silicon oxide and silicon nitride.

[0081] The first layer 90 can be formed, for example, by an existing semiconductor process. The first layer 90 formed of an organic material can be formed, for example, by photolithography. The first layer 90 formed of an inorganic material can be formed, for example, by film formation of an inorganic material layer using a vapor deposition method, formation of a mask using photolithography, and patterning of the inorganic material layer using etching. Alternatively, the first layer 90 formed of an inorganic material can be formed by oxidation or nitridation of a surface region of the substrate 10, formation of a mask using photolithography, and patterning of an oxide or nitride layer using etching.

[0082] Then, if Figure 4 and Figure 5 As shown in FIG. 8 , the catalyst layer 80 including a precious metal is formed on the portion of the first main surface S1 exposed in the slit 90S by a plating method.

[0083] The catalyst layer 80 is, for example, a discontinuous layer containing a noble metal. Here, as an example, the catalyst layer 80 is set to be a granular layer made of catalyst particles 81 containing a noble metal.

[0084] The noble metal is, for example, one or more of gold, silver, platinum, rhodium, palladium, and ruthenium. The catalyst layer 80 and the catalyst particles 81 may further include a metal other than the noble metal, such as titanium.

[0085] The plating method used to form the catalyst layer 80 is, for example, electrolytic plating, reduction plating, or displacement plating. Among these methods, displacement plating is particularly preferred because it can deposit metal directly and substantially uniformly in the region of the first main surface S1 not covered by the first layer 90 .

[0086] However, regardless of the plating method, the balance of metal supply from the plating solution and metal consumption caused by its precipitation is different in the area near the boundary between the first area A1 and the second area A2 and the area sufficiently spaced from the boundary. Specifically, in the area near the boundary between the first area A1 and the second area A2, metal precipitation into the slit 90S is more likely to occur than in the area sufficiently spaced from the boundary. Therefore, the catalyst layer 80 includes the first catalyst part 80a where the metal is precipitated at an appropriate density, and the second catalyst part 80b where the metal is precipitated at a high density. As described below, the second catalyst part 80b is prone to poor processing.

[0087] Therefore, in this method, Figure 6 to Figure 8 As shown in , the second layer 95 is formed. The second layer 95 includes a portion 95A extending along the longitudinal direction of the slits 90S and a portion 95B extending along the arrangement direction of the slits 90S.

[0088] The second layer 95 is a second mask layer that prevents the etchant 100 described later from reaching the second catalyst portion 80b. The second layer 95 is formed so as to cover the portion of the catalyst layer 80 adjacent to the boundary between the first region A1 and the second region A2 and to expose the portion of the catalyst layer 80 spaced from the boundary. Thus, the second catalyst portion 80b is covered by the second layer 95 without covering at least a portion of the first catalyst portion 80a.

[0089] The second layer 95 is formed according to the width of the portion located on the first area A1, that is, Figure 8 The middle widths D1 and D2 are preferably formed in a range of 20 to 100 μm, more preferably in a range of 20 to 50 μm. If the width is increased, the entire second catalyst portion 80b can be reliably covered with the second layer 95. However, if the width is increased, the portion of the first catalyst portion 80a covered by the second layer 95 becomes wider.

[0090] It should be noted that the widths D1 and D2 may be equal to each other. Alternatively, the widths D1 and D2 may be different. For example, the width D1 may be larger than the width D2.

[0091] The second layer 95 is preferably formed to have a thickness in the range of 0.1 to 10 μm, more preferably in the range of 0.5 to 1 μm. If the second layer 95 is thickened, the entire second catalyst portion 80b can be reliably covered with the second layer 95. However, if the second layer 95 is thickened, the cost becomes high.

[0092] Examples of the material of the second layer 95 include organic materials such as polyimide, fluororesin, phenolic resin, acrylic resin, and novolac resin, and inorganic materials such as silicon oxide and silicon nitride.

[0093] The second layer 95 can be formed, for example, by an existing semiconductor process. The second layer 95 formed of an organic material can be formed, for example, by photolithography. The second layer 95 formed of an inorganic material can be formed by, for example, forming an inorganic material layer by vapor deposition, forming a mask by photolithography, and patterning the inorganic material layer by etching. The material of the second layer 95 is preferably an organic material.

[0094] As the second layer 95 is formed, the material of the second layer 95 may adhere to the portion of the first catalyst portion 80a that should not be covered by the second layer 95. Such adhesion may reduce the catalytic activity. Therefore, after the second layer 95 is formed, it is preferable to remove the adhesion from the exposed portion of the first catalyst portion 80a by, for example, etching. For example, when an organic material is used as the material of the second layer 95, it is preferable to perform ashing. It should be noted that if Figure 6 The structure of Figure 7 As shown in FIG. 1 , the second layer 95 is thinned.

[0095] Next, the substrate 10 is etched due to the action of the noble metal as a catalyst, thereby forming a recessed portion in the first main surface S1.

[0096] Specifically, if Fig. 9 As shown in , the substrate 10 is etched with the etchant 100 . For example, the substrate 10 is immersed in the liquid etchant 100 , and the etchant 100 is brought into contact with the substrate 10 .

[0097] The etchant 100 contains an oxidizing agent and hydrogen fluoride.

[0098] The concentration of hydrogen fluoride in the etchant 100 is preferably in the range of 1 mol / L to 20 mol / L, more preferably in the range of 5 mol / L to 10 mol / L, and further preferably in the range of 3 mol / L to 7 mol / L. When the concentration of hydrogen fluoride is low, it is difficult to achieve a high etching rate. When the concentration of hydrogen fluoride is high, excessive side etching may occur.

[0099] The oxidant can be selected from, for example, hydrogen peroxide, nitric acid, AgNO3, KAuCl4, HAuCl4, K2PtCl6, H2PtCl6, Fe(NO3)3, Ni(NO3)2, Mg(NO3)2, Na2S2O8, K2S2O8, KMnO4, and K2Cr2O7. Hydrogen peroxide is preferred as the oxidant because it does not produce harmful byproducts or contaminate semiconductor elements.

[0100] The concentration of the oxidant in the etchant 100 is preferably in the range of 0.2 mol / L to 8 mol / L, more preferably in the range of 2 mol / L to 4 mol / L, and further preferably in the range of 3 mol / L to 4 mol / L.

[0101] The etchant 100 may further include a buffer. The buffer includes, for example, at least one of ammonium fluoride and ammonia. According to one example, the buffer is ammonium fluoride. According to another example, the buffer is a mixture of ammonium fluoride and ammonia.

[0102] The etchant 100 may further contain other components such as water.

[0103] When such an etchant 100 is used, the material of the substrate 10, here silicon, is oxidized in the region of the substrate 10 where the etchant 100 can reach and is close to the catalyst particles 81. The oxide thus produced is dissolved and removed by hydrofluoric acid. In contrast, the above-mentioned reaction does not occur in the region of the substrate 10 where no catalyst particles 81 are present nearby. In addition, even in the region of the substrate 10 where the catalyst particles 81 are present nearby, the above-mentioned reaction does not occur in the region where the etchant 100 cannot reach through the second layer 95. Therefore, only the portion where the etchant 100 can reach and is close to the catalyst particles 81 is selectively etched.

[0104] As the etching progresses, the catalyst particles 81 move toward the second main surface S2, where the same etching as described above is performed. Fig.10 As shown in , etching is performed in a direction perpendicular to the first main surface S1 from the first main surface S1 toward the second main surface S2 at the position of the portion of the first catalyst portion 80a that is not covered by the second layer 95.

[0105] In this way, a layer of Fig.11 The recess TR shown in .

[0106] Thereafter, the first layer 90, the second layer 95, and the catalyst layer 80 are removed from the substrate 10. It should be noted that the first layer 90 may be removed from the substrate 10 after the catalyst layer 80 is formed and before the second layer 95 is formed.

[0107] Next, a Figure 2 The conductive layer 20a shown in the figure is formed into a conductive substrate CS. As described above, the conductive layer 20a is the lower electrode of the capacitor. The conductive layer 20a can be formed, for example, by doping impurities at a high concentration in the surface area of ​​the substrate 10. The conductive layer 20a formed of polycrystalline silicon can be formed, for example, by LPCVD (low pressure chemical vapor deposition). The conductive layer 20a formed of a metal can be formed, for example, by electrolytic plating, reduction plating or displacement plating.

[0108] The plating solution is a liquid containing a salt of the metal to be plated. As the plating solution, a general plating solution such as a copper sulfate plating solution containing copper sulfate pentahydrate and sulfuric acid, a copper pyrophosphate plating solution containing copper pyrophosphate and potassium pyrophosphate, and a nickel sulfamate plating solution containing nickel sulfamate and boron can be used.

[0109] Conductive layer 20a is preferably formed by a plating method using a plating solution containing a salt of the plated metal, a surfactant and supercritical or subcritical carbon dioxide. In this plating method, the surfactant is sandwiched between particles formed by supercritical carbon dioxide and a continuous phase formed by a solution containing a salt of the plated metal. That is, in the plating solution, micelles are formed in the surfactant, and supercritical carbon dioxide is taken into these micelles.

[0110] In a conventional plating method, the metal to be plated may be insufficiently supplied to the vicinity of the bottom of the recessed portion, which is particularly significant when the ratio D / W between the depth D and the width or diameter W of the recessed portion is large.

[0111] The micelles ingested with supercritical carbon dioxide can also easily enter narrow gaps. Moreover, along with the movement of these micelles, the solution containing the salt of the plated metal also moves. Therefore, according to the plating method using a plating solution containing the salt of the plated metal, a surfactant and supercritical or subcritical carbon dioxide, a conductive layer 20a with uniform thickness can be easily formed.

[0112] As described above, here, as an example, the conductive layer 20a is formed by doping the surface region of the substrate 10 with impurities at a high concentration. That is, here, the surface region of the first main surface S1 side of the substrate 10 is used as the conductive layer 20a.

[0113] Next, the dielectric layer 30 is formed on the conductive layer 20a. The dielectric layer 30 can be formed, for example, by CVD (chemical vapor deposition) or by oxidizing, nitriding, or oxynitriding the surface of the conductive layer 20a.

[0114] Next, a conductive layer 20b is formed on the dielectric layer 30. The conductive layer 20b is the upper electrode of the capacitor as described above. As the conductive layer 20b, for example, a conductive layer formed of polysilicon or metal is formed. Such a conductive layer 20b can be formed, for example, by the same method as described above for the conductive layer 20a.

[0115] Next, an opening is formed in the dielectric layer 30. Here, a portion of the dielectric layer 30 located on the first main surface S1 is opened in a frame shape. The opening can be formed, for example, by forming a mask by photolithography and patterning by etching.

[0116] Next, a metal layer is formed into a film and patterned to obtain the first internal electrode 70a and the second internal electrode 70b. The first internal electrode 70a and the second internal electrode 70b can be formed by a combination of film formation by sputtering or plating and photolithography, for example.

[0117] Thereafter, the insulating layer 60 is formed. The insulating layer 60 has openings at positions corresponding to a portion of the first internal electrode 70a and a portion of the second internal electrode 70b. The insulating layer 60 can be formed by a combination of film formation using CVD and photolithography, for example.

[0118] Next, the first external electrode 70c and the second external electrode 70d are formed on the insulating layer 60. Specifically, first, the first metal layers 70c1 and 70d1 are formed. Next, the second metal layers 70c2 and 70d2 are formed. The first metal layers 70c1 and 70d1 and the second metal layers 70c2 and 70d2 can be formed by, for example, a combination of film formation using sputtering or plating and photolithography.

[0119] Then, the structure obtained by the above operation is cut. Figure 1 and Figure 2 The capacitor 1 shown in FIG.

[0120] In the capacitor 1 , the recess TR is provided in the first main surface S1 , and the stacked structure including the dielectric layer 30 and the conductive layer 20 b is provided not only on the first main surface S1 but also in the recess TR. Therefore, the capacitor 1 can achieve a large capacitance.

[0121] In the above-mentioned method, processing defects are less likely to occur in etching using a catalyst. This will be described below.

[0122] As in reference Figure 4 and Figure 5As described above, the precious metal is easily precipitated into the slit 90S in the region near the boundary between the first region A1 and the second region A2 as compared to the region sufficiently spaced from the boundary. As a result, the catalyst layer 80 includes the first catalyst portion 80a where the precious metal is precipitated at an appropriate density and the second catalyst portion 80b where the precious metal is precipitated at a high density.

[0123] This is because the balance of metal supply from the plating solution and metal consumption caused by its precipitation is different between the area near the boundary between the first area A1 and the second area A2 and the area sufficiently spaced from the boundary. More specifically, this is because no slit 90S is provided at the position of the second area A2 in the first layer 90, so the area of ​​the area where the plating solution should supply metal near the boundary between the first area A1 and the second area A2 is smaller than the area of ​​the area where the plating solution should supply metal sufficiently spaced from the boundary.

[0124] Without forming the second layer 95, the reference Fig. 9 and Fig.10 In the case of etching described above, in the region where the first catalyst portion 80a is formed, etching is performed in a direction perpendicular to the first main surface S1. However, in this case, in the region where the second catalyst portion 80b is formed, processing defects such as etching in a direction inclined relative to the first main surface S1, uneven etching in the direction of progress, and ineffective etching in a direction perpendicular to the first main surface S1 occur. As a result, for example, Fig.12 The structure shown in .

[0125] If the second layer 95 is formed, the supply of the etchant 100 to the second catalyst portion 80b is hindered. Therefore, etching is not performed at the position corresponding to the second layer 95, and the above-mentioned processing defects do not occur. Therefore, for example, Fig.13 The structure shown in .

[0126] <Second Embodiment>

[0127] The etching method of the second embodiment includes the following steps: forming a mask layer on a substrate comprising a semiconductor material and having a first region and a second region adjacent to each other on a main surface, the mask layer comprising a first portion covering the above-mentioned first region and having a plurality of openings or one or more openings defining a plurality of island-shaped portions, and a second portion covering the above-mentioned second region as a continuous film, the height of the above-mentioned second portion at a position adjacent to a boundary between the above-mentioned first region and the above-mentioned second region being larger with respect to the above-mentioned main surface as a reference than the height of the above-mentioned first portion with respect to the above-mentioned main surface as a reference; forming a catalyst layer comprising a precious metal on a portion of the above-mentioned main surface exposed in the above-mentioned plurality of openings or the above-mentioned one or more openings by a plating method; and, in the presence of the above-mentioned catalyst layer and the above-mentioned mask layer, etching the above-mentioned substrate with an etchant comprising an oxidant and hydrogen fluoride.

[0128] The method for manufacturing a structure according to the second embodiment includes forming one or more recessed portions in the substrate by the etching method.

[0129] The manufacturing method of the semiconductor device of the second embodiment includes: forming one or more recesses in the above-mentioned substrate through the above-mentioned etching method; forming a lower electrode on the side wall of the above-mentioned one or more recesses; forming a dielectric layer on the above-mentioned lower electrode; and, forming an upper electrode on the above-mentioned dielectric layer.

[0130] A method of manufacturing a capacitor as an example of a semiconductor device as a structure using the above-mentioned etching method will be described below.

[0131] According to the method of the second embodiment, for example, the capacitor 1 illustrated in the first embodiment can be manufactured. In the second embodiment, the capacitor 1 is manufactured by the following method.

[0132] That is, first, Fig.14 As shown in , a mask layer 98 is formed on the first main surface S1 of the substrate 10. The substrate 10 is the same as that described in the first embodiment.

[0133] The mask layer 98 includes a first portion 98 a and a second portion 98 b .

[0134] The first portion 98a is a portion of the mask layer 98 that covers the first region A1. The first portion 98a has a plurality of openings. Here, the plurality of openings are a plurality of slits 90S arranged in the width direction. The length direction of the slits 90S is parallel to the Y direction and is arranged in the X direction.

[0135] The plurality of openings provided in the first portion 98a may have shapes other than slits. For example, in the first portion 98a, as the plurality of openings, a plurality of through holes each having a circular, elliptical or polygonal shape and arranged in two directions intersecting each other may be provided.

[0136] Alternatively, instead of providing a plurality of openings, one or more openings defining a plurality of island-shaped portions may be provided in the first portion 98a. In this case, pillar-shaped protrusions can be generated at positions corresponding to the island-shaped portions by etching described later.

[0137] The second portion 98b is a portion of the mask layer 98 that covers the second region A2. The second portion 98b is a continuous film. The height H2 of the second portion 98b at a position adjacent to the boundary between the first region A1 and the second region A2 with reference to the first main surface S1 is A or H2 B It is larger than the height H1 of the first portion 98 a based on the first main surface S1 .

[0138] The mask layer 98 is Fig.14 and Fig.15 The laminate of the first layer 90 and the second layer 96 shown in FIG. The first portion 98a is a portion of the first layer 90 covering the first area A1. The second portion 98b is a combination of the second layer 96 and a portion of the first layer 90 covering the second area A2.

[0139] The first layer 90 is formed on the first main surface S1. The first layer 90 is the same as that described in the first embodiment. That is, the first layer 90 plays the same role as that described in the first embodiment.

[0140] The first layer 90 covers the first area A1 and the second area A2.

[0141] A plurality of openings are provided in the portion covering the first area A1 in the first layer 90. Here, the plurality of openings are a plurality of slits 90S arranged in the width direction. The longitudinal direction of the slits 90S is parallel to the Y direction and arranged in the X direction.

[0142] The plurality of openings provided in the first layer 90 may also have shapes other than slits. For example, in the first layer 90, as the plurality of openings, a plurality of through holes each of which has a circular, elliptical, or polygonal shape and is arranged in two directions intersecting each other may be provided. Alternatively, in the first layer 90, instead of providing a plurality of openings, one or more openings defining a plurality of island-shaped portions may be provided.

[0143] The portion of the first layer 90 covering the second region A2 is a continuous film. The portion of the first layer 90 covering the second region A2 and the portion of the first layer 90 covering the first region A1 are equal in height.

[0144] For example, the material described in the first embodiment can be used as the material of the first layer 90. The first layer 90 can be formed by the same method as described in the first embodiment, for example.

[0145] The second layer 96 is formed on the first layer 90. The second layer 96 exposes the portion of the first layer 90 that covers the first region A1. Furthermore, the second layer 96 covers the second region A2 in the first layer 90 at least at a position adjacent to the boundary between the first region A1 and the second region A2. Here, the second layer 96 has a frame shape that surrounds the first region A1.

[0146] As the material of the second layer 96, for example, the material exemplified for the second layer 95 in the first embodiment can be used. The second layer 96 can be formed by, for example, the same method as that described for the second layer 95 in the first embodiment.

[0147] As described below, the second layer 96 prevents excessive supply of metal from the plating solution to the first main surface S1 in the region near the boundary between the first region A1 and the second region A2 during the plating process for forming the catalyst layer 80. As a result, the density of the catalyst metal can be made almost equal in the slit 90S near the boundary between the first region A1 and the second region A2 and in the slit 90S sufficiently spaced from the boundary.

[0148] The mask layer 98 may also be formed integrally. For example, first, a photosensitive resin layer is formed on the first layer 90. As the photosensitive resin, for example, a positive photoresist is used. Next, the photosensitive resin layer is exposed, for example, using a grating mask, or exposed twice or more. As a result, the first and second exposed portions and unexposed portions having different exposure amounts are generated in the photosensitive resin layer. Thereafter, by performing development or the like, the mask layer 98 formed integrally can be obtained.

[0149] The height H2 of the second portion 98b at the position adjacent to the boundary with respect to the first main surface S1 is A or H2 B The ratio of the height H1 of the first portion 98 a based on the first main surface S1 is preferably in the range of 2-5, and more preferably in the range of 2-3.

[0150] Here, the height H1 is the thickness of the first layer 90. In addition, the height H2 AThe height H2 is the height of the second portion 98b at a position adjacent to the portion extending in the longitudinal direction of the slit 90S in the above-mentioned boundary, with reference to the first main surface S1. That is, here, the height H2 A The height H2 is the height of the portion 96A of the second layer 96 extending along the longitudinal direction of the slit 90S with respect to the first main surface S1. B is the height of the second portion 98b at a position adjacent to the portion extending in the arrangement direction of the slits 90S in the above-mentioned boundary, with reference to the first main surface S1. That is, here, the height H2 B It is the height of the portion 96B extending along the arrangement direction of the slits 90S in the second layer 96 with the first main surface S1 as a reference.

[0151] In addition, the height H of the second portion 98b based on the first portion 98a is A or H B The distance D in the direction parallel to the first main surface S1 from the portion of the second portion 98b having the highest height relative to the first main surface S1 to the plurality of openings or one or more openings is A or D B The ratio is preferably in the range of 1-4, more preferably in the range of 2-4.

[0152] Here, the distance D A It is the distance in the arrangement direction of the slits 90S from the portion 96A extending along the longitudinal direction of the slits 90S in the second layer 96 to the slits 90S. B It is the distance in the length direction of the slit 90S from the portion 96B extending along the arrangement direction of the slits 90S in the second layer 96 to the slit 90S.

[0153] Here, the height H A is the height of the second portion 98b at a position adjacent to the portion extending in the longitudinal direction of the slit 90S in the above-mentioned boundary, with respect to the first portion 98a. That is, here, the height H A is the thickness of the portion of the second layer 96 extending along the length direction of the slit 90S. B is the height of the second portion 98b at a position adjacent to the portion extending in the arrangement direction of the slits 90S in the above-mentioned boundary, with respect to the first portion 98a. That is, here, the height H B It is the thickness of the portion of the second layer 96 extending along the arrangement direction of the slits 90S.

[0154] When these ratios are increased, in the plating process for forming the catalyst layer 80 , the amount of metal supplied from the plating solution to the first main surface S1 decreases in the region near the boundary between the first region A1 and the second region A2 .

[0155] The height H1 is preferably in the range of 0.1 to 10 μm, and more preferably in the range of 0.5 to 1 μm.

[0156] Height H2 A and H2 B It is preferably in the range of 0.2 to 20 μm, and more preferably in the range of 1 to 3 μm. A and H2 B They can be equal to each other or different.

[0157] Height A and H B It is preferably in the range of 0.1 to 10 μm, and more preferably in the range of 0.5 to 2 μm. A and H B They can be equal to each other or different.

[0158] Distance D A and D B It is preferably in the range of 0.05 to 0.5 μm, and more preferably in the range of 0.1 to 0.2 μm. A and D B They can be equal to each other or different.

[0159] After the mask layer 98 is formed as described above, Fig.16 As shown in , the catalyst layer 80 is formed on the portion of the first main surface S1 exposed in the slit 90S. The material of the catalyst layer 80 can be, for example, the material exemplified in the first embodiment. The catalyst layer 80 can be formed by, for example, the same method as described in the first embodiment.

[0160] Then, if Fig.17 As shown in , the substrate 10 is etched with an etchant 100 containing an oxidizing agent and hydrogen fluoride in the presence of the catalyst layer 80 and the mask layer 98. Thus, the recess TR is formed in the first main surface S1.

[0161] For example, the etchant 100 described in the first embodiment can be used. This etching is performed by the same method as described in the first embodiment, for example.

[0162] Next, the mask layer 98 and the catalyst layer 80 are removed from the substrate 10. Thereafter, as described in the first embodiment, the conductive layer 20a, the dielectric layer 30, and the conductive layer 20b are formed. Furthermore, as described in the first embodiment, the first internal electrode 70a, the second internal electrode 70b, the insulating layer 60, the first external electrode 70c, and the second external electrode 70d are formed and cut. As described above, Figure 1 and Figure 2 The capacitor 1 shown in FIG.

[0163] In the capacitor 1 , the recess TR is provided in the first main surface S1 , and the stacked structure including the dielectric layer 30 and the conductive layer 20 b is provided not only on the first main surface S1 but also in the recess TR. Therefore, the capacitor 1 can achieve a large capacitance.

[0164] As described above, in this method, the second layer 96 prevents excessive supply of metal from the plating solution to the first main surface S1 in the region near the boundary between the first region A1 and the second region A2 during the plating process for forming the catalyst layer 80. As a result, the density of the catalyst metal in the slit 90S near the boundary between the first region A1 and the second region A2 and in the slit 90S sufficiently spaced from the boundary can be made almost equal. Therefore, similarly to the first embodiment, processing defects in etching using the catalyst can be less likely to occur.

[0165] The methods described in the first and second embodiments can be modified in various ways.

[0166] For example, in the first and second embodiments, a capacitor is described as an example of a structure, but the technology described above for the capacitor can also be applied to other structures.

[0167] In the methods described in the first and second embodiments, before forming the catalyst layer 80, the height of the portion corresponding to the slit 90S in the first region A1 may be made higher than the height of the remaining portion of the first region A1. For example, the height of the portion not covered by the first layer 90 in the first region A1 may be made lower by etching. Alternatively, the height of the portion corresponding to the slit 90S in the first region A1 may be made higher by epitaxial growth. In this case, unevenness in the direction of etching is less likely to occur.

[0168] In the method described in the second embodiment, the second layer 96 is formed along the entire boundary between the first area A1 and the second area A2. The portion 96B of the second layer 96 extending along the arrangement direction of the slits 90S may be formed as follows. Fig.18 As shown in FIG. 1 , the second layer 96 is provided only in the vicinity of a portion 96A extending in the longitudinal direction of the slit 90S.

[0169] When the recessed portion TR is a channel, the convex portion sandwiched by the adjacent recessed portion TR has a partition shape. In this case, if processing defects occur at a certain position of the recessed portion TR throughout its entire length during etching for forming the recessed portion TR, the convex portion adjacent to the recessed portion TR may collapse. On the other hand, even if processing defects occur only at the end of a certain position of the recessed portion TR during etching for forming the recessed portion TR, the convex portion adjacent to the recessed portion TR is unlikely to collapse.

[0170] Therefore, even if the Fig.18 In the case of the structure shown in , even in etching for forming the recessed portion TR, collapse of the convex portion sandwiched between adjacent recessed portions TR can be less likely to occur.

[0171] It should be noted that the present invention is not limited to the above-mentioned embodiment as it is, and the constituent elements can be deformed and concretized in the implementation stage without departing from the scope of its purpose. In addition, various inventions can be formed by the appropriate combination of multiple constituent elements disclosed in the above-mentioned embodiment. For example, several constituent elements can also be deleted from all the constituent elements shown in the embodiment. And then, the constituent elements in different embodiments can also be appropriately combined.

Claims

1. An etching method comprising the following steps: A first layer is formed on a substrate including a semiconductor material and having a first region and a second region adjacent to each other on one main surface, wherein the first layer covers the first region and the second region, a plurality of openings or one or more openings defining a plurality of island-shaped portions are provided in a portion covering the first region, and a portion covering the second region is a continuous film; forming a catalyst layer containing a noble metal on the portion of the main surface exposed in the plurality of openings or the one or more openings by a plating method; forming a second layer that covers a portion of the catalyst layer adjacent to a boundary between the first region and the second region and exposes a portion of the catalyst layer spaced from the boundary; as well as The substrate is etched with an etchant containing an oxidizing agent and hydrogen fluoride in the presence of the catalyst layer and the second layer.

2. The etching method according to claim 1, wherein: In the first layer, a plurality of slits arranged in the width direction are provided as the plurality of openings.

3. The etching method according to claim 1, wherein: The substrate is etched in the presence of the first layer except for the catalyst layer and the second layer.

4. The etching method according to claim 1, wherein: The second layer is formed so that a width of a portion located on the first region is within a range of 20 to 100 μm.

5. The etching method according to claim 1, wherein: As the catalyst layer, a granular layer made of particles containing the noble metal is formed.

6. An etching method comprising the following steps: A mask layer is formed on a substrate including a semiconductor material and having a first region and a second region adjacent to each other on one main surface, the mask layer including a first portion covering the first region and provided with a plurality of openings or one or more openings defining a plurality of island-shaped portions, and a second portion as a continuous film covering the second region, wherein a height of the second portion at a position adjacent to a boundary between the first region and the second region with respect to the main surface as a reference is larger than a height of the first portion with respect to the main surface as a reference; forming a catalyst layer containing a noble metal on the portion of the main surface exposed in the plurality of openings or the one or more openings by a plating method; as well as The substrate is etched with an etchant containing an oxidizing agent and hydrogen fluoride in the presence of the catalyst layer and the mask layer.

7. The etching method according to claim 6, wherein: In the mask layer, a plurality of slits arranged in a width direction are provided as the plurality of openings.

8. The etching method according to claim 6, wherein: The forming of the mask layer comprises: forming a first layer on the substrate, the first layer covering the first region and the second region, the plurality of openings or the one or more openings of the predetermined plurality of island-shaped portions being provided in a portion covering the first region, and the portion covering the second region being a continuous film; and A second layer is formed, the second layer exposing the portion of the first layer covering the first region and covering the second region in the first layer at least at a position adjacent to the boundary.

9. The etching method according to claim 6, wherein: A ratio of the height of the second portion from the main surface to the height of the first portion from the main surface at a position adjacent to the boundary is in a range of 2-5.

10. The etching method according to claim 6, wherein: A ratio of a height of the second portion relative to the first portion to a distance in a direction parallel to the main surface from a portion of the second portion having a maximum height relative to the main surface to the plurality of openings or the one or more openings is in a range of 1 to 4.

11. The etching method according to claim 6, wherein: As the catalyst layer, a granular layer made of particles containing the noble metal is formed. 12 . A method for producing a structure, comprising forming one or more recessed portions in the substrate by the etching method according to claim 1 .

13. A method for manufacturing a semiconductor device, comprising: forming one or more recesses in the substrate by the etching method according to any one of claims 1 to 11; forming a lower electrode on the sidewalls of the one or more recesses; forming a dielectric layer on the lower electrode; as well as An upper electrode is formed on the dielectric layer.

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