Etching method

Abstract

The present invention provides an etching method that takes into account both a high etching rate of a silicon oxide film and a low etching rate of a silicon nitride film, to etch the silicon oxide film with high precision at a high selectivity with respect to the silicon nitride film. An etching method is a dry etching method that etches a film structure, in which a silicon oxide film is sandwiched by a silicon nitride film above and below to form a film layer, at an end portion of which a side wall of a groove or a hole is formed, in a state where a gas for processing is supplied into a processing chamber without using plasma, wherein hydrogen fluoride gas is supplied so that the wafer is cooled to -30°C or lower, preferably -30°C to -60°C, and the silicon oxide film is etched in a lateral direction from the end portion.

Description

Technical Field

[0001] This invention relates to an etching method for processing a film layer of a substrate-shaped sample, such as a semiconductor wafer, formed in advance on the surface of the sample as a process for manufacturing semiconductor devices. In particular, it relates to an etching method for removing silicon oxide film by supplying gas particles to the processing chamber in a structure in which a silicon oxide film and a silicon nitride film of the sample are stacked as a film structure on the upper surface of the sample. Background Technology

[0002] In semiconductor devices, to meet the demands for lower power consumption and increased storage capacity, further miniaturization and three-dimensional device fabrication are pursued. In the manufacturing of three-dimensional devices, due to their three-dimensional and complex structure, in addition to the existing "vertical (anisotropic) etching" which etches the wafer surface vertically, "isotropic etching," which can also be performed laterally, is frequently used. Previously, isotropic etching was performed using wet processing with a chemical solution. However, with advancements in miniaturization, problems such as pattern collapse caused by the surface tension of the chemical solution and etching residues in fine gaps have become apparent. Furthermore, the need for large amounts of chemical solution processing is also problematic. Therefore, in isotropic etching, it is necessary to replace the existing wet processing using chemical solutions with a dry processing method that does not use chemical solutions.

[0003] In semiconductor devices, silicon oxide films are widely used, and therefore, dry etching processes have been known for a long time. For example, Japanese Patent Application Publication No. 07-169738 (Patent Document 1) describes a technique for etching silicon oxide material layers using plasma at temperatures below 0°C using an alcohol and CF-based gas. Furthermore, Japanese Patent Application Publication No. 2013-074200 (Patent Document 2) describes etching away deposits at temperatures below 30°C using a mixture of hydrogen fluoride and methanol without plasma.

[0004] On the other hand, in the manufacturing process of semiconductor devices, in the film stacking process of 3D-NAND flash memory, which is a three-dimensional semiconductor element, and in the processing around the gate of FinFET, there is a requirement for a technique to etch oxide films with high selectivity and isotropic control at the atomic layer level for polysilicon films and silicon nitride films. In the 3D-NAND structure, silicon oxide films (SiO2 films) and silicon nitride films (SiN) are stacked alternately in large quantities. Due to the formation of deep hole shapes and trench shapes, it is required to selectively and isotropically etch a small amount of silicon oxide film.

[0005] Regarding this subject matter, Japanese Patent Application Publication No. 2016-025195 (Patent Document 3), US Patent Application Publication No. 09613823B (Patent Document 4), Japanese Patent Application Publication No. 07-153737 (Patent Document 5), and US Patent Application Publication No. 05571375B (Patent Document 6) describe etching a silicon oxide film at a temperature of 0–30°C or room temperature–40°C without the use of plasma, using hydrogen fluoride and alcohol. Furthermore, silicon nitride is described in the aforementioned Patent Documents 3, 4, and 5.

[0006] Furthermore, Japanese Patent Application Publication No. 2005-161493 (Patent Document 7) discloses the following technology: HF2 generated from hydrogen fluoride and alcohol - Without using plasma, the etching points of a structure with a silicon oxide film formed on a silicon nitride film are etched, followed by heating and further cooling of the structure. Furthermore, US Publication No. 10319603B (Patent Document 8) discloses a technique that selectively etches the silicon nitride film laterally from a structure of silicon nitride and silicon oxide films in a layered structure at temperatures below -20°C using precursors including oxygen and fluorine.

[0007] Furthermore, US09431268B (Patent Document 9) discloses the following technique: after activating the silicon oxide film by adsorbing OH-containing elements onto its surface, the water generated during the reaction is removed by heating the substrate surface using anhydrous HF etching, thereby controlling the etching process.

[0008] Prior art literature

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 07-169738

[0011] Patent Document 2: Japanese Patent Application Publication No. 2013-074200

[0012] Patent Document 3: Japanese Patent Application Publication No. 2016-025195

[0013] Patent Document 4: US09613823B Publication

[0014] Patent Document 5: Japanese Patent Application Publication No. 07-153737

[0015] Patent Document 6: US05571375B Publication

[0016] Patent Document 7: Japanese Patent Application Publication No. 2005-161493

[0017] Patent Document 8: US 10319603B Publication

[0018] Patent document 9: US09431268B Publication Summary of the Invention

[0019] However, problems arise in the aforementioned prior art because the following aspects are not adequately considered.

[0020] That is, as described in the background art, existing wet etching methods using aqueous hydrofluoric acid solutions or buffered aqueous hydrofluoric acid solutions suffer from problems such as etching residues in fine gaps and poor etching control. On the other hand, in the case of dry etching, it is difficult to achieve both a high etching rate for the silicon oxide film and a low etching rate for the silicon nitride film, resulting in difficulties in etching the silicon oxide film with a high selectivity ratio of silicon nitride film.

[0021] Therefore, in the existing technology, the process of etching a silicon oxide film in a film structure formed by stacking silicon oxide and silicon nitride films in the vertical direction does not fully consider the problem of low processing accuracy, which prevents the desired shape of the processed film structure from being obtained and thus damages the yield of the processed product.

[0022] The present invention was made in view of the above-mentioned problems, and provides a method for etching a silicon oxide film with high precision and high selectivity relative to a silicon nitride film, while taking into account both a high etching rate of silicon oxide film and a low etching rate of silicon nitride film.

[0023] The etching method of the present invention is a dry etching method, in which a film structure is etched while a processing gas is supplied to the processing chamber and no plasma is used. The film structure is pre-formed on a wafer disposed in the processing chamber. The ends of the stacked film layers, in which silicon oxide film is sandwiched between silicon nitride film, form the sidewalls of grooves or holes. The etching method is characterized in that a hydrogen fluoride gas is supplied to cool the temperature of the wafer to a low temperature of -30°C or below, preferably -30°C to -60°C, and the silicon oxide film is etched laterally from the ends.

[0024] -Invention Effects-

[0025] It can simultaneously etch silicon oxide films at a high etch rate and silicon nitride films at a low etch rate. As a result, it can remove silicon oxide films with high precision by etching them with a higher selectivity ratio than silicon nitride films. Attached Figure Description

[0026] Figure 1 This is a schematic longitudinal sectional view illustrating the overall structure of the etching processing apparatus according to an embodiment of the present invention.

[0027] Figure 2 It means Figure 1The flowchart shown is an example of the etching process performed by the etching apparatus involved in this embodiment.

[0028] Figure 3 It is a schematic representation of what has been implemented. Figure 2 A longitudinal cross-sectional view of an example of the film structure on a wafer during the etching process shown.

[0029] Figure 4 It is a schematic representation of the meaning of... Figure 3 The image shows a longitudinal cross-sectional view of an example of the post-processed shape of a wafer with a film structure etched using a lower-than-average etching process.

[0030] Figure 5 Is Figure 2 The flowchart shown in the embodiment illustrates a modified example of the etching process.

[0031] Figure 6 It means Figure 1 The etching process apparatus involved in the illustrated embodiment is used for... Figure 5 The timing diagram shows the process flow of the etching operation involved in the modified example shown.

[0032] Figure 7 It means Figure 2 The illustrated embodiment shows a graph of the etching rate and the change in the selection ratio relative to the temperature of the wafer during the etching process.

[0033] Figure 8 It means that it has been implemented. Figure 2 A graph showing the results of the etching process involved in another variation of the etching process.

[0034] Figure 9 This is a schematic longitudinal sectional view illustrating the structure of an etching processing apparatus according to another embodiment of the present invention.

[0035] -Explanation of Figure Markers-

[0036] 1. Processing room

[0037] 2. Chips,

[0038] 3. Chip station

[0039] 11. Bottom chamber

[0040] 12··· Quartz Chamber,

[0041] 13···Discharge region,

[0042] 14. Pressure regulating valve

[0043] 15. Exhaust system

[0044] 16. Vacuum exhaust piping

[0045] 20···ICP coil,

[0046] 21. High-frequency power supply

[0047] 22. Matcher

[0048] 23··· Clustered Radiation Plate,

[0049] 24... High gas dispersion plate,

[0050] 25···Top Slab,

[0051] 26. Slotted board,

[0052] 27···Flow path,

[0053] 30···Electrodes for electrostatic adsorption

[0054] 31. DC power supply for electrostatic adsorption.

[0055] 38. Cooler

[0056] 39···Refrigerant flow path,

[0057] 50··· Mass flow controller,

[0058] 51. Gas distributor

[0059] 54··· Valve,

[0060] 55···He gas,

[0061] 59···IR lamp unit,

[0062] 60-1, 60-2, 60-3... lamps

[0063] 61···Reflector,

[0064] 64··· Power supply for the lamp,

[0065] 70. Thermocouple

[0066] 71. Thermocouple thermometer

[0067] 72···Through the window,

[0068] 73··· Power supply for the lamp,

[0069] 74. High-frequency cutoff filter.

[0070] 101···Substrate,

[0071] 102···Silicon nitride film,

[0072] 103···Silicon oxide film,

[0073] 104···Opening. Detailed Implementation

[0074] The inventors conducted research on etching single-layer films of silicon oxide (SiO2) and silicon nitride (SiN) formed on wafer surfaces using plasma-based CVD (chemical vapor deposition). More specifically, they conducted detailed studies on etching these single-layer films by supplying hydrogen fluoride (HF) gas alone or in a mixture of hydrogen fluoride gas and an inert gas such as argon (Ar) to a processing chamber containing the wafer. The results showed that, when using… Figure 7 As will be described later, under an etching pressure of 300 Pa, and with the cooler set to a temperature higher than -30°C to regulate the temperature of the cooling medium circulating on the stage holding the wafer, no etching of the silicon oxide and silicon nitride films occurs. In contrast, when the temperature is set below -30°C, especially above -50°C, the etching rate of the silicon oxide film increases dramatically, reaching 20 nm / min or higher.

[0075] In contrast, the etching rate of silicon nitride films remains relatively low, below 1 nm / min, even at temperatures below -30°C. Furthermore, it can be observed that in temperature ranges lower than -40°C, the etching rate of silicon oxide films gradually decreases as the temperature drops. Consequently, the selectivity of the etching rate of silicon oxide films relative to silicon nitride films is higher in the range of -35°C to -55°C than the values ​​before and after this range.

[0076] However, it is generally known that silicon oxide films are etched using a combination of hydrogen fluoride gas and gases of alcohol and water. The reaction formula for the silicon oxide film in this case is as disclosed in the aforementioned Patent Document 7, as shown below.

[0077] 2HF + MOH → HF2 - +MOH2 + ...(Equation 1)

[0078] SiO2+2HF2 - +MOH2 + →SiF4 + 2H2O + 2MOH···(Equation 2)

[0079] Here, M represents atoms or molecules such as H, CH3, and CH2CH3.

[0080] For example, when using hydrogen fluoride gas and methanol (methyl alcohol), hydrogen fluoride (HF)₂ molecules react with methanol (CH₃OH) to generate HF₂ as the active species according to Equation 1. - The HF2 - HF2 reacts with SiO2 to form SiF4 (boiling point -94.8℃), which volatilizes and causes etching. In the reaction shown in Formula 2 above, HF2 - On the one hand, methanol undertakes the reaction, and on the other hand, methanol extracts H+ from hydrogen fluoride molecules. + , to generate HF2 - Its function.

[0081] In contrast, in the etching of silicon oxide films by which the inventors discovered that hydrogen fluoride gas is supplied alone or mixed with an inert gas such as Ar while plasma is not used, alcohol and water are not supplied from outside the processing chamber into the processing chamber. However, since the etching rate of the silicon oxide film is high enough, it is considered that HF2... - The active species cause etching of the silicon oxide film. The inventors believe that HF2 is generated under conditions where alcohol and water are not supplied from outside the treatment room. - The reason lies in the trace amounts of moisture (H2O) present on the surface of the silicon oxide film.

[0082] As shown in Equation 1 above, in order to generate HF2 as the active species for the reaction - The reaction requires water (H2O) with MOH (M=H). However, as shown in Equation 2 above, water is also a reaction product, and it is considered necessary to remove water to promote the reaction. If water is present in excess, the reaction shown in Equation 3 occurs as described in Patent Document 9, and silicon oxide, i.e., SiO2, is generated to produce hydrofluoric acid H2SiF6.

[0083] 3SiF4 + 2H2O → SiO2 + 2H2SiF6 ··· (Equation 3)

[0084] Therefore, in order to suppress the regeneration of SiO2, which is silicon oxide, water needs to be removed rapidly. In this invention, the etching rate of the silicon oxide film increases sharply at low temperatures below -30°C.

[0085] That is, -35°C is the melting point of a 50% concentration aqueous solution of hydrofluoric acid, which is close to a saturated solution. The inventors believe that, thus, the water generated on the surface of the silicon oxide film through the reaction mixes with the supplied hydrogen fluoride gas to form a near-saturated solution of hydrofluoric acid, which becomes solid, thereby removing water from the surface of the silicon oxide film and producing an etching reaction. On the other hand, at high temperatures above -30°C, it is believed that the hydrofluoric acid is in a liquid state, meaning the water has not been removed, and the silicon oxide generation reaction shown in (Equation 3) occurs, but etching does not progress.

[0086] Alternatively, if the water produced in the reaction is completely removed by external heating, HF2 is generated as the active species. - The reaction in (Equation 1) no longer occurs, thus etching proceeds discontinuously. On the other hand, as mentioned above, a temperature such as -35°C is the temperature at which hydrofluoric acid solidifies on the silicon oxide surface. Water exists on the silicon oxide surface to a certain extent and becomes solid, thereby removing the water and causing etching. In this embodiment, by solidifying the water to prevent the reaction in (Equation 3) from occurring, it is removed from the interaction with the etching-related reaction, thus promoting the etching of the silicon oxide film.

[0087] As described above, according to this embodiment, when the temperature of the wafer is maintained at -30°C or below and -60°C or above, preferably at -35°C to -50°C, hydrogen fluoride gas is supplied to the wafer surface alone or mixed with an inert gas such as Ar. This allows for the balance between the high etching rate of the silicon oxide film and the low etching rate of the silicon nitride film on the wafer surface, enabling the silicon oxide film to be etched with high precision and a high selectivity relative to the silicon nitride film.

[0088] Hereinafter, embodiments of the present invention will be described in detail based on the accompanying drawings.

[0089] [Example 1]

[0090] [Etching Processing Equipment]

[0091] use Figure 1 The structure of the etching processing apparatus 100 according to the embodiments of the present invention will be described. Figure 1 This is a schematic longitudinal sectional view illustrating the overall structure of the etching processing apparatus according to an embodiment of the present invention.

[0092] In this figure, the etching processing apparatus 100 includes: a lower unit 57, which has a cylindrical metal vacuum container, i.e., a bottom chamber 11, having a central axis in the vertical direction; and an upper unit 58, which is placed above the bottom chamber 11 and forms the circular top surface of the bottom chamber 11. Furthermore, a vacuum exhaust section 63, including an exhaust pump for depressurizing the air inside the bottom chamber 11, is disposed below.

[0093] Inside the bottom chamber 11, there is a depressurized processing chamber 1, which is a space surrounded by its side walls and bottom. Inside the cylindrical processing chamber 1, there is a wafer stage 3 serving as a support, on which a wafer 2 is placed. At least one through hole communicating with the inside and outside of the processing chamber 1 is provided at the bottom of the bottom chamber 11 on the outer periphery of the wafer stage 3. The openings of these through holes constitute exhaust ports for discharging gases and particles from the interior of the processing chamber 1.

[0094] Furthermore, a circular plate made of dielectric material such as quartz, i.e., a cluster plate 23, is disposed opposite to the upper surface of the wafer stage 3, which is located at the center of the top surface of the processing chamber 1 and sandwiches the space for introducing gas for processing the film layer on the surface of the wafer 2. This circular plate 23 forms the top surface of the processing chamber 1 as an upper unit 58. The cluster plate 23 has multiple through holes through which the processing gas is supplied into the processing chamber 1. In this embodiment, the processing gas is a mixed gas containing multiple elements, including at least one reactive gas that reacts with the film layer of the processing object pre-positioned on the surface of the wafer 2 and a rare gas diluted to a given proportion.

[0095] The processing gas is supplied through a mass flow controller 50 configured for each gas type on a processing gas supply pipeline connected to the through hole of the cluster plate 23. The flow rate or velocity of each gas type is adjusted by the mass flow controller 50. Multiple gas pipelines are combined into one, and the combined gas is supplied as processing gas to the through hole of the cluster plate 23. Furthermore, a gas distributor 51 is configured further downstream of the processing gas supply pipeline that is combined downstream of the mass flow controller 50. Multiple gas supply pipelines, namely gas supply pipes 56, are connected to the gas distributor 51 and the cluster plate 23. The lower ends of these pipelines are configured to communicate with the through holes located in the center or outer periphery of the cluster plate 23.

[0096] In this embodiment, processing gas is supplied from the upper central portion of the processing chamber 1 through various gas supply pipes 56 configured to communicate with the through holes of the spray plate 23. The flow rate and composition of the processing gas are independently adjusted in the central and peripheral portions, respectively, to adjust the partial pressure distribution of the processing gas to the desired distribution in the respective regions near the center and periphery of the processing chamber 1. Furthermore, in Figure 1 In the example, Ar, N2, and HF are listed as elements that serve as raw materials for the processing gas, but processing gases composed of other types of raw materials may also be supplied.

[0097] Furthermore, in this embodiment, the gas obtained by vaporizing the liquid raw material can also be supplied as the processing gas through the through hole of the spray plate 23 into the processing chamber 1. For example, the gas obtained as the processing gas can also be obtained by vaporizing the liquid raw material stored in the storage section in a vapor supply device (not shown) using liquid HF or a substance including HF as raw material.

[0098] During the period when the processing gas, consisting of the vapor of the raw material, is not introduced into the processing chamber 1, a valve on the pipeline connecting the gas distributor 51 and the storage section is closed, cutting off the connection between the liquid raw material and the processing chamber 1. Preferably, a heater is installed on the pipeline through which the raw material vapor flows, receiving heat from the heater to heat the inside of the pipeline, so that the raw material vapor does not condense inside the pipeline.

[0099] In the lower part of the processing chamber 1 within the bottom chamber 11, below the wafer stage 3, an exhaust device 15 is connected via a vacuum exhaust pipe 16. This device includes an exhaust pump for depressurizing the interior of the processing chamber 1 by venting exhaust gas. The exhaust device 15 may be, for example, a turbomolecular pump, a mechanical booster pump, or a dry pump, capable of depressurizing the interior of the processing chamber 1 to a given vacuum level. Furthermore, to regulate the pressure inside the processing chamber 1, a pressure regulating valve 14 is provided on the vacuum exhaust pipe 16, which connects and communicates with the exhaust port of the bottom member of the bottom chamber 11 and the exhaust device 15. The pressure regulating valve 14 has the following structure: it has at least one plate-shaped flap disposed along a flow path that transversely traverses the exhaust gas flow of the vacuum exhaust pipe 16. By rotating the flap or moving it in the direction transverse to the flow path, the cross-sectional area of ​​the flow path is increased or decreased, thereby increasing or decreasing the flow rate or velocity of the exhaust gas flowing inside.

[0100] Regarding the bottom chamber 11 and the cylindrical upper unit 58 above it, with the latter installed, the outer periphery of the bottom surface of the cylindrical upper unit 58 is mounted and installed above the upper end of the cylindrical sidewall of the bottom chamber 11, so that sealing members such as O-rings are sandwiched between them to airtightly seal the inside and outside of the processing chamber 1. A cluster plate 23 is disposed in the central part of the lower part of the upper unit 58, and an IR lamp unit 59 with a ring shape is disposed in the area on the outer periphery of the cluster plate 23. The IR light transmission window 72 of the IR lamp unit 59 constitutes the top surface of the processing chamber 1 of the lower surface of the upper unit 58. Furthermore, the upper unit 58 has a cylindrical metal upper unit cover 62, which surrounds the IR unit 59 and the cluster plate 23 disposed in its center, and the gas supply pipe 56 connected to it above.

[0101] In this example, an IR lamp unit 59 is arranged in a ring around the outer peripheral region of the upper surface of the wafer stage 3 and the wafer 2 placed thereon. The IR lamp unit 59 has a ring-shaped lamp 60 that radiates electromagnetic waves of multiple wavelengths, including infrared light, from the lamp 60 through the transmission window 72, and the electromagnetic waves radiated from the lamp 60 into the processing chamber 1 illuminate the wafer 2 from the surrounding area. Regarding the electromagnetic waves radiated in this example, electromagnetic waves that emit more light in the wavelength range from visible light to infrared light (referred to herein as IR light) are emitted.

[0102] The IR lamp unit 59 includes: a lamp 60 arranged in a triple ring around the cluster plate 23; a ring-shaped reflector 61 covering and arranged above the lamp 60, reflecting the radiated IR light toward the center of the processing chamber 1 and downwards (towards the mounted wafer 2); and an IR light-transmitting window 72 arranged below the lamp 60, which surrounds the cluster plate 23 using a ring-shaped member made of a dielectric material through which IR light such as quartz can pass. In this example, the IR lamp 60 uses multiple ring-shaped (circular) lamps 60-1, 60-2, and 60-3 arranged concentrically around the center of the cluster plate 23 or the processing chamber 1 when viewed from above. A single lamp arranged in a spiral shape can also be used instead of these multiple lamps. Furthermore, in this embodiment, a lamp with three rings is provided, but it could also be two rings, four rings, etc.

[0103] Lamp 60 is connected to a lamp power supply 73, and a high-frequency cutoff filter 74 is provided on the power supply path that connects them to suppress noise from high-frequency power flowing into the lamp power supply 73. In addition, the lamp power supply 73 has the function of independently controlling the power supplied to each lamp 60-1, 60-2, and 60-3.

[0104] The IR lamp unit 59, which annularly surrounds the cluster plate 23, has: a top portion of an annular processing chamber 1 facing the IR light-transmitting window 72; and a cylindrical inner peripheral sidewall portion connected above its inner peripheral end and surrounding the cluster plate 23 and the gas supply pipe 56 connected to the through hole on its back side. The cylindrical inner peripheral sidewall portion is also made of a dielectric material that transmits IR light, just like the top portion. The radiated IR light passes through the cylindrical portion to irradiate the cluster plate 23 and then radiates into the processing chamber 1.

[0105] Inside the circular or cylindrical metal component of the wafer stage 3, a flow path 39 is provided through which a refrigerant for cooling the wafer stage 3 and regulating its temperature flows. A cooler 38, connected to the inlet and outlet of the flow path 39, supplies and circulates the refrigerant, whose temperature is regulated to a given range. In this embodiment, the cooler 38 is capable of regulating the refrigerant or the metal component to a temperature range of at least -30°C to -60°C, preferably -35°C to -50°C. Furthermore, a dielectric film constituting the upper surface of the metal component is disposed thereon, and multiple plate-shaped electrode plates 30 are embedded within this dielectric film, supplying direct current for fixing the wafer 2 by electrostatic adsorption. A DC power supply 31 is connected to each electrode plate 30.

[0106] Furthermore, in order to efficiently regulate the temperature of the wafer 2, a supply port for supplying helium (He) gas 55 is provided on the upper surface of the dielectric film of the wafer stage 3. When the wafer 2 is placed on the stage, He gas 55 is supplied between the back side of the wafer 2 and the dielectric film, which can promote heat transfer between the wafer 2 and the flow path 39. In addition, since heating and cooling using the wafer 2 with electrostatic adsorption also suppresses damage to the back side of the wafer 2, the dielectric film is made of resin such as polyimide.

[0107] Furthermore, inside the metal component of the wafer stage 3, a thermocouple 70 is disposed as a temperature detector (sensor) for detecting the temperature of the wafer stage 3 or the metal component, and is connected to a thermocouple thermometer 71. The output from the thermocouple thermometer 71 is sent to a control unit (not shown) that controls the operation of the etching processing apparatus 100. The arithmetic unit in the control unit detects the temperature value according to an algorithm recorded in predetermined software stored in the storage device, and sends a command signal to the lamp power supply 73 to independently adjust the output of the IR light from the lamps 60-1, 60-2, and 60-3 to achieve the desired temperature distribution of the wafer 2 based on the difference between the detected value and the desired radial temperature distribution of the wafer 2 obtained therefrom.

[0108] Furthermore, in the etching processing apparatus 100 of this embodiment, as a mechanism for cooling the wafer stage 3, in addition to using the flow path 39 for circulating the coolant internally, a Peltier element or similar thermoelectric conversion device that creates a temperature difference based on the power supplied to the interior of the wafer stage 3 can also be used. Moreover, the inner wall surface of the processing chamber 1, excluding the wafer stage 3, exposed to processing gases such as hydrogen fluoride gas and methanol gas, can be heated to a temperature in the range of, for example, 40°C to 120°C. This suppresses the adsorption of hydrogen fluoride gas and methanol gas on the surface of the internal components of the processing chamber 1, thereby reducing corrosion of the internal components.

[0109] The temperature difference between the wafer stage 3 and the set temperature of the cooler 38 is within ±1°C, as measured by the thermocouple thermometer 71 of the thermocouple 70. In addition, the temperature difference between the wafer 2 and the set temperature of the wafer stage 3 is within ±3°C (within ±2°C relative to the set temperature of the wafer stage 3).

[0110] Furthermore, the etching apparatus 100 used in this invention can heat the interior of the bottom chamber 11, excluding the wafer stage 3 which is exposed to hydrogen fluoride gas, such as the processing chamber 1. For example, a temperature of approximately 40°C to 120°C can be used. This prevents hydrogen fluoride gas from adsorbing into the interior of the bottom chamber 11 and greatly reduces corrosion inside the bottom chamber 11.

[0111] [Etching process flow]

[0112] Next, use Figure 2 , 3 4 pairs Figure 1 The etching process of the wafer 2 performed by the etching apparatus 100 shown in this embodiment will be described. Figure 2 It means Figure 1 The flowchart shown is an example of the etching process performed by the etching apparatus involved in this embodiment.

[0113] exist Figure 2 In this example, firstly, a transport port (not shown) through the side wall of the bottom chamber 11, which is arranged horizontally around the processing chamber 1 and between the inside and outside of the processing chamber 1, is used to transport the wafer 2 in and out. The wafer 2, placed on the front end of a wafer transport mechanism such as a robotic arm, which is located in a depressurized space inside another vacuum container (not shown) adjacent to the bottom chamber 11, is transported into the processing chamber 1 above the wafer stage 3 and then placed on the front end of three or more pins protruding above the upper surface of the wafer stage 3. After the robotic arm exits the processing chamber 1 and the gate is hermetically closed, the wafer 2 is placed on the upper surface of the wafer stage 3 by the descent and retraction of the pins into the wafer stage 3. Power from the DC power supply 31 for electrostatic adsorption is supplied to the electrostatic adsorption electrode 30 arranged in a dielectric film made of ceramic such as alumina or yttrium oxide that constitutes the upper surface of the wafer stage 3, thereby adsorbing and holding the wafer 2 on the upper surface of the dielectric film.

[0114] Subsequently, to facilitate heat transfer between the wafer stage 3 and the wafer 2, a heat-conducting gas such as He gas 55 is supplied to the gap between the back side of the wafer 2 and the dielectric film. As a result, the temperature of the wafer 2 gradually approaches the temperature of the wafer stage 3, which is set to be close to the temperature of the coolant flowing through the flow path 39. Figure 2The wafer cooling process is shown in step S101. In the etching process of the silicon oxide film pre-formed on the upper surface of wafer 2 in this example, the temperature of wafer 2 is maintained in the range of -30°C to -60°C, preferably -35°C to -50°C. Therefore, the coolant flowing in flow path 39 is set to a temperature lower than the temperature of wafer 2 in the etching process, for example, below -40°C, and is supplied to flow path 39 and circulated.

[0115] Next, as step S102, Ar gas 52 used to dilute the HF gas is supplied from above into the processing chamber 1 via the mass flow controller 50, the gas distributor 51, and the cluster plate 23. In this example, the initial supply of Ar gas 52 for dilution can be continued until the end of the etching process of the silicon nitride film on the upper surface of the wafer 2 is determined, or it can be repeatedly stopped or supplied and stopped (intermittently) in the middle. In addition, other inert gases, such as nitrogen (N2), can be used instead of Ar gas 52 for dilution.

[0116] Next, as step S103, with the wafer 2 held on the upper surface of the wafer stage 3 and its temperature maintained within the range of -30°C to -60°C, preferably -35°C to -50°C, HF gas is supplied to the processing chamber 1 at a given flow rate for a given time. The supplied HF gas reaches the surface of the silicon oxide film on the surface of the wafer 2, reacts with the silicon oxide to remove the silicon oxide, and performs etching.

[0117] In this embodiment, inert gases such as Ar and N2 can be used as dilution gases. Since the etching rate tends to decrease as the amount of dilution gas added increases, the etching rate can be controlled accordingly.

[0118] In this embodiment, the pressure of the processing chamber 1 in step S103 is preferably in the range of 10 Pa to 2000 Pa, and particularly preferably in the range of 100 Pa to 1000 Pa. As will be described later, the higher the pressure, the higher the etching rate of the silicon oxide film, and the slightly higher the etching temperature. On the other hand, with the increase of pressure, as will be described later, there is a tendency for the etching rate of the silicon nitride film to also increase slightly, and the result is not significantly improved.

[0119] After a given time has elapsed since the HF gas supply in step S103, the supply of HF gas to the processing chamber 1 is stopped by the operation of the flow regulator of the gas distributor 51 (step S104). In step S104, the opening of the pressure regulating valve 14 and the rotation speed of the exhaust pump of the exhaust device 15 are also adjusted to be the same as in step S103. By stopping the supply of HF gas to the processing chamber 1, the HF gas remaining in the gas phase in the processing chamber 1, along with the reaction products or other gas particles formed in the processing chamber 1, are discharged out of the processing chamber 1 through the exhaust port and the vacuum exhaust pipe 16, and the pressure inside the processing chamber 1 is reduced. Next, the supply of He gas 55 between the wafer 2 and the wafer stage 3 is stopped. At the same time, the valve 54 is opened to set the pressure on the back side of the wafer 2 to the same level as the pressure inside the processing chamber 1 (i.e., the He gas 55 on the back side of the wafer 2 is removed).

[0120] Alternatively, after step S104, the post-processing of wafer 2 can be performed.

[0121] use Figure 3 An example of the membrane structure to be used in this embodiment will be described. Figure 3 It is a schematic representation of implementation. Figure 2 A longitudinal cross-sectional view of an example of the film structure on a wafer during the etching process shown.

[0122] like Figure 3 As shown in (a), on a silicon substrate 101 of wafer 2, a film structure is formed by alternately stacking multiple silicon oxide films (SiO2 films) 103 and silicon nitride films (SixNy, SiN films) 102 in the vertical direction, and by forming holes or grooves by penetrating multiple film layers in the vertical direction (depth direction). In such a film structure, the holes or grooves have openings 104 on the surface of the uppermost film layer (silicon oxide film 103 in this figure), which is a required structure for 3D-NAND.

[0123] In this film structure, tens to hundreds of layers are stacked. In this example, the thickness of the silicon oxide film 103 is several nm to 100 nm, and the thickness of the silicon nitride film 102 is several nm to 100 nm. Therefore, the overall thickness 105 of the film structure is several μm to tens of μm. In addition, the width of the opening 104 is tens of nm to hundreds of nm.

[0124] By using Figure 2 The etching process shown is as follows: Figure 3As shown in (b), the end faces of each silicon oxide film 103 constituting the sidewall of the hole or trench react with HF gas entering the hole or trench from the opening 104, and are etched with a high selectivity relative to the silicon nitride films 102 above and below them. The end faces of each silicon oxide film 103 removed by end face etching react again with the supplied HF gas and are removed, so that the position of each silicon oxide film 103 relative to the end faces of the silicon nitride films 102 sandwiched above and below it does not change significantly, and etching proceeds in the lateral direction (left-right direction in the figure). In this example, the size 106 of the lateral etching is from a few nm to tens of nm, and is preferably around 10 nm.

[0125] When etching laterally into the silicon oxide film 103, the selectivity relative to the silicon nitride film 102 is preferably 15 or more, particularly preferably 20 or more. With a lower selectivity, the etching of the silicon nitride film 102 proceeds in parallel with the etching of the silicon oxide film 103. In such a case, as... Figure 4 As shown, the etched end of the silicon nitride film 102 is not rectangular but rounded, which may adversely affect the performance of semiconductor devices formed by such a film structure. Figure 4 It is an illustrative representation of the situation in response to... Figure 3 The image shows a longitudinal cross-sectional view of an example of the post-processed shape of a wafer with a film structure etched using a lower-than-average etching process.

[0126] Based on the inventors' experience, regarding... Figure 3 In the etching process of this example, where the film structure of the stacked silicon oxide film 103 and silicon nitride film 102 shown in (a) is 15 or more, more preferably 20 or more, at the end face of each film layer constituting the sidewall surface of the trench or hole, a etch can be obtained. Figure 3 As shown in (b), it is closer to a rectangular shape. On the other hand, when choosing a ratio less than 15, especially less than 10, such as... Figure 4 The silicon nitride film shown has rounded corners at its ends, which is not preferred.

[0127] According to the inventors' research, the alternating layering of silicon oxide film 103 and silicon nitride film 102 was achieved by changing the temperature of wafer 2. Figure 3 The etching process of the film structure shown in (a) resulted in almost no etching progress at -30°C, as expected, and a slightly smaller etching amount at -55°C. Etching was performed at temperatures ranging from -35°C to -50°C. Figure 3 The shape of (b). Furthermore, it is known that when heating is performed after these etching processes, the surface roughness caused by residues and by products on the surface of the processed laminated film is small.

[0128] As Figure 3The substrate 101 shown may be made of silicon or silicon-germanium, but is not limited to these. It is a substrate formed by alternating layers of silicon oxide film (SiO2 film) 103 and silicon nitride film (SiN film) 102. They can also be formed by methods such as plasma CVD, chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, precursor coating, and sintering.

[0129] During etching of a film structure in which the silicon oxide film 103, the object of etching, is sandwiched between two silicon nitride films 102 and the ends of the stacked film layers form the sidewalls of trenches and holes, deposits and attachments sometimes form on the surface and ends of these films. Such deposits and attachments can be removed by irradiating the wafer 2 with light from... Figure 1 The etching apparatus 100 shown uses electromagnetic waves, such as infrared radiation, emitted by the lamp 60 to heat the film structure, thereby thermally decomposing and removing deposits and adhesions formed on the surface. This allows for... Figure 3 The surface of the membrane structure shown is smoother.

[0130] Furthermore, the heating of the wafer 2 is not limited to the use of lamp 60. For example, a heater such as a heater disposed within the wafer stage 3 can be used to heat the wafer 2 through heat transfer from the wafer stage 3, or the wafer 2 can be heated from... Figure 1 The etching process apparatus 100 shown has its processing chamber 1 moved to the outside and heated inside other heating devices. In addition, when electromagnetic waves are irradiated by lamps 60-1, 60-2, and 60-3, inert gases such as Ar and N2 can be introduced into the processing chamber 1.

[0131] In the etching process of the film structure in which the ends of the silicon nitride film 102 and silicon oxide film 103, which are alternately stacked in the vertical direction as described above, form the sidewalls of trenches and holes, sometimes deposits formed during the process adhere to or are deposited on the surface of the silicon nitride film 102 and the sidewalls of the trenches and holes. The inventors analyzed such deposits and adhesions using total internal reflection infrared absorption spectroscopy and found that they included ammonium fluoride silicide.

[0132] According to the inventors' research, it is envisioned that although ammonia is not used under the conditions described above, ammonia may sometimes be generated from the nitrogen in the silicon nitride film by etching a portion of the silicon nitride film 102, thereby producing ammonium fluoride silicon (NH4)2SiF6. On the other hand, according to information such as safety data sheets, ammonium fluoride silicon is known to decompose at 145°C.

[0133] The inventors realized that after the etching process of supplying HF gas to the silicon oxide film 103 as described above, by heating the film structure or wafer 2 in a depressurized processing chamber 1, the generated deposits, including ammonium fluoride silicon, can be removed. Therefore, in Figure 2 The etching process shown includes an additional step of heating the wafer 2, which is being processed after etching, to remove deposits. This is a variation of the above embodiment and will be described next.

[0134] Figure 5 It means Figure 2 A flowchart illustrating a variation of the etching process of the illustrated embodiment. In this figure, the following... Figure 2 The process steps S101 to S104 shown are supplemented with a process step S105, which includes heating the wafer 2, and a process step S106, which includes cooling the wafer 2.

[0135] Figure 6 It means Figure 1 The etching process apparatus involved in the illustrated embodiment is used for... Figure 5 The timing diagram shows the process flow of the etching procedure in the modified example shown. Figure 5 , Figure 6 In the process, steps S101 to S104 are similar to... Figure 2 The processes shown are the same. If steps S101 to S104 are steps where the wafer 2 processing does not require subsequent heating of wafer 2, they can be omitted. Figure 6 The timing diagram shows these heating and cooling processes (steps S105, S106).

[0136] That is, with Figure 2 Similarly, in this example, the unprocessed wafer 2 is transported into the processing chamber 1 and placed on the upper surface of the wafer stage 3. It is held adsorbed and held on the upper surface of the dielectric film on the upper surface of the wafer stage 3. Then, a heat-conducting gas such as He gas 55 is supplied to the gap between the back side of the wafer 2 and the dielectric film to perform a cooling process on the wafer 2 (step S101). In this modified example, the temperature of the wafer 2 is also maintained in the range of -30°C to -60°C, preferably -35°C to -50°C.

[0137] Next, as step S102, Ar gas 52 for diluting HF gas is supplied from above into the processing chamber 1. Then, while the temperature of the wafer 2 is maintained in the range of -30°C to -60°C, preferably -35°C to -50°C, HF gas is supplied to the processing chamber 1 at a given flow rate for a given time. Etching is performed by removing silicon oxide through the reaction of the supplied HF gas with the silicon oxide film on the surface of the wafer 2 (step S103).

[0138] After a given time has elapsed in step S103, the supply of HF gas to processing chamber 1 is stopped. HF gas remaining in the gas phase within processing chamber 1, reaction products formed within processing chamber 1, or particles of other gases are discharged outside processing chamber 1, and the pressure inside processing chamber 101 is reduced. Then, the supply of He gas 55 between wafer 2 and wafer stage 3 is stopped (step S104). Simultaneously, valve 54 is opened to set the pressure on the back side of wafer 2 to the same level as the pressure inside processing chamber 1 (i.e., the He gas 55 on the back side of wafer 2 is removed).

[0139] In the example shown in this figure, the heating of wafer 2 in step S105 uses a method including... Figure 1 The IR (infrared) lamps 60-1, 60-2, and 60-3 shown are IR lamp units 59. Together with the start of step S105, power from the lamp power supply 73 is supplied to the lamps 60-1, 60-2, and 60-3 according to a command signal from a controller (not shown), irradiating the wafer 2 with electromagnetic waves including the infrared region. This heating and cooling process of the wafer 2 can be performed after steps S101 to S104 are combined and repeated multiple times until a given amount of silicon oxide film 103 is etched, or it can be performed as part of a single overall process (cycle) following steps S101 to S104, at least in each cycle.

[0140] The structure used for heating is not limited to this; for example, it can also be a method of heating the wafer stage 3, or a method of separately transferring the wafer 2 to a heating-only device and performing heating treatment. Furthermore, Ar gas or nitrogen gas can be introduced when electromagnetic waves are irradiated from the IR lamp unit 59. In addition, the heating to remove deposits can be performed multiple times as needed, and the heating and cooling steps S105 and S106 can be omitted if the amount of deposits is determined to be within acceptable limits.

[0141] Additionally, in step S105, after the controller determines that the wafer 2 has been heated to a given time or a given temperature, the operation of the IR lamp unit 59 is stopped, and step S105 ends. Then, while maintaining the supply of coolant at a given temperature to the flow path 39 inside the wafer stage 3 and the supply of He gas between the wafer 2 and the wafer stage 3, step S106 is performed to cool the wafer 2. After the cooling of the wafer 2 continues until the controller detects that the given time or given temperature has been reached, step S106 is stopped, and the etching process of the silicon oxide film 103 on the wafer 2 ends.

[0142] In addition, as a post-treatment to remove deposits and residues after etching, heating in a vacuum followed by water washing can be used. Alternatively, a cleaning process can be employed to remove surface deposits by using O2 plasma to detach and volatilize them.

[0143] [Etching Result 1]

[0144] use Figure 7 Indicates use Figures 2 to 6 An example of the result of the etching process shown. Figure 7 It means Figure 2 The illustrated embodiment shows a graph illustrating the changes in etching rate and selectivity during the etching process relative to the temperature of the wafer. In this figure, the etching rates of the individual monolayers of silicon oxide and silicon nitride films formed by plasma CVD are represented as points and lines under various conditions in which the temperature of the coolant supplied to flow path 39 varies from -25°C to -55°C.

[0145] In this example, in step S103, which is the process of etching to remove the silicon oxide film 103, the processing gas introduced into the processing chamber 1 is a mixed gas obtained by adding 100 sccm of Ar as a diluent relative to 400 sccm of hydrogen fluoride. Furthermore, the pressure in the processing chamber 1 in this process is set to 300 Pa, and the etching time is set to 120 s (sec).

[0146] Furthermore, after the etching process is completed, following 20 seconds of venting in step S104, the refrigerant temperature is set, and Ar is supplied to the processing chamber 1 at a flow rate of 500 sccm until the previous step is maintained. The opening of the pressure regulating valve 14 is set to 100% (fully open), and heating is performed for 50 seconds at a given lamp intensity. The maximum temperature reached at this time is approximately 250°C. Afterward, the lamp is turned off, and the chamber is allowed to cool for 120 seconds while Ar flows at 500 sccm.

[0147] exist Figure 7 (a) represents the result of the etching rate of the silicon oxide film and silicon nitride film depicted with dots and solid lines relative to the temperature setting of the coolant circulating in flow path 39.

[0148] According to this figure, when the coolant setting temperature is above -30°C, it can be said that neither the silicon oxide film 103 nor the silicon nitride film 102 undergoes etching. Furthermore, it is evident that the etching rate of the silicon oxide film 103 increases sharply at temperatures below -30°C. Under these processing conditions, the etching rate of the silicon oxide film 103 reaches a maximum of 30 nm / min at -40°C. Moreover, if the temperature drops below -40°C, the etching rate tends to decrease.

[0149] In contrast, it can be seen that the etching rate of the silicon nitride film is below 1 nm / min in the range of -30℃ to -55℃, and no etching occurs. Therefore, it can be concluded that under the conditions of use, in the range of -35℃ to -55℃, the silicon oxide film is selectively etched compared to the silicon nitride film. Figure 7 In (b), a graph showing the etching rate of the silicon oxide film relative to the silicon nitride film relative to the set temperature of the cooler is presented as a selection ratio. It can be seen that although there are point deviations, a selection ratio of approximately 50 or higher is shown at -35°C to -55°C.

[0150] Based on the above results, a wafer temperature of -35°C to -55°C is preferred to achieve a balance between a high etching rate for the silicon oxide film and a low etching rate for the silicon nitride film, in order to etch the silicon oxide film with high precision and a high selectivity ratio compared to the silicon nitride film. Since the silicon oxide film has a high etching rate, a wafer temperature of -35°C to -45°C is more preferred.

[0151] Furthermore, in the etching of the silicon oxide film 103 in this example, it is also possible to... Figure 5 The steps S101 to S106 shown are repeated multiple times as a single process (cycle). In this case, Figure 6 The timing diagram is repeated as needed. For example, in cases with a lot of deposits, the removal becomes easier by repeatedly performing short etching sessions or removal based on heating in a vacuum.

[0152] [Etching Result 2]

[0153] Regarding the etching process of the wafer 2 being processed in the etching apparatus 100 described as Example 1 or a variation, the etching was performed by increasing the pressure under the etching conditions. As another variation, using... Figure 8 The following explanation will be provided. Figure 8 It means that it has been implemented. Figure 2 A diagram showing the result of the etching process involved in another variation of the etching process.

[0154] Similar to Example 1, hydrogen fluoride gas was introduced into the processing chamber 1 without using plasma. The temperature of the coolant was varied within a range of -25°C to -55°C to perform etching of a pre-formed silicon oxide and silicon nitride film stack on the wafer 2. The etching results at each temperature were monitored. Here, the processing gas used for etching was a mixture obtained by adding 100 sccm of Ar as a diluent to 400 sccm of hydrogen fluoride. (The last sentence appears to be incomplete and possibly refers to a different example.) Figure 2In the embodiments or variations shown, the pressure in the processing chamber 1 was 300 Pa. Under the condition that the pressure was set to 500 Pa and everything else was the same, the etching process of step S103, which lasted for 120 seconds, was carried out.

[0155] Furthermore, after the etching process of the silicon oxide film 103 in step S103 is completed and the supply of hydrogen fluoride gas is stopped, after venting for 20 seconds as step S104, as step S105, the temperature of the coolant is set, and Ar is supplied to the processing chamber 1 at 500 sccm. With the pressure regulating valve 14 fully open, a given power is supplied to the IR lamp unit 59 to irradiate the wafer 2 with electromagnetic waves from lamps 60-1, 60-2, and 60-3, heating the wafer 2 for 50 seconds. The highest temperature of the wafer 2 in step S105 is approximately 250°C. After stopping the irradiation of electromagnetic waves from lamps 60-1, 60-2, and 60-3 and ending step S105, the wafer 2 is cooled for 120 seconds while supplying Ar at 500 sccm to the processing chamber 1.

[0156] exist Figure 8 In (a), the changes in the etching rate of the detected monolayer silicon oxide film and silicon nitride film relative to the set temperature of the coolant are shown by dots and solid lines.

[0157] As shown in the figure, when the set temperature of the coolant flowing in flow path 39 is above -30°C, neither the silicon oxide film nor the silicon nitride film undergoes etching. Furthermore, it is observed that below -30°C, the etching rate of the silicon oxide film increases dramatically. Under operating conditions, the etching rate of the silicon oxide film reaches its maximum at -35°C, showing 40 nm / min. Moreover, when the temperature is below -35°C, the etching rate tends to decrease.

[0158] It is known that Figure 7 Compared to the etching process shown in (a) where the pressure in processing chamber 1 is 300 Pa, the etching process performed at a pressure of 500 Pa... Figure 8 In case (a), the distribution of the solid line representing the etching rate of the silicon oxide film is slightly shifted toward the high-temperature side.

[0159] As described above, in this embodiment and its variations, HF2 is considered to be... - It becomes an active species, causing etching. As also described in (Equation 1), HF2... - The cause is believed to be trace amounts of water located on the surface of the silicon oxide film. On the other hand, as shown in (Equation 2), water is also a reaction product, and its removal is essential to promote the reaction.

[0160] In the above embodiments and variations, during the etching process of the silicon oxide film, the temperature of the wafer 2 or the wafer stage 3 supporting it is maintained below -30°C. It is envisioned that -35°C is the melting point of a 50% concentration aqueous solution of hydrofluoric acid, which is close to a saturated solution. On the surface of the silicon oxide film, the water generated in the reaction mixes with the supplied hydrogen fluoride gas to form a near-saturated solution of hydrofluoric acid, which becomes solid. Thus, the moisture is removed from the surface of the film structure of the wafer 2, and the etching process of the silicon oxide film proceeds.

[0161] In this modified example, it is believed that by increasing the pressure inside the processing chamber 1 from 300 Pa in Example 1 to 500 Pa, the aforementioned hydrofluoric acid becomes more readily solidified, therefore... Figure 8 As shown in (a), the curve shifts towards the high-temperature side. Furthermore, it is believed that the etching rate at -35°C is higher than... Figure 7 The high etching rate of (a) also contributed to its high efficiency.

[0162] In contrast, the etching rate of silicon nitride film is below 2 nm / min in the range of -30℃ to -55℃, resulting in almost no etching. Therefore, under the operating conditions, within the range of -35℃ to -55℃, silicon oxide film is selectively etched relative to silicon nitride film.

[0163] exist Figure 8 In (b), the ratio of the etching rate of the silicon oxide film to that of the silicon nitride film is shown by dots and solid lines as a function of the set temperature of the coolant. This ratio can be considered to represent the selectivity of these films relative to each other. As can be seen in this figure, although there are point deviations, the selectivity is as high as 70 at -35°C, while the selectivity is around 20 to 50 at -40°C to -55°C. In this modified example where the pressure is increased to 500 Pa, the overall selectivity decreases slightly.

[0164] In addition, the inventors are concerned about having Figure 3 The wafer 2, with a film structure of a stacked silicon oxide film and a silicon nitride film shown in (a), is subjected to pressure conditions by changing the temperature of the refrigerant in this modified example. Figure 5 The steps S101 to S106 are shown. Based on the inventors' research on the processing results, slight etching occurred at -30°C, but the amount of etching was small. It was determined that etching at -35°C to -50°C yielded the desired results. Figure 3 The shape of (b). In addition, by heating after etching, residues are not visible on the processed surface, and the generation of deposits and unevenness is suppressed.

[0165] [Example 2]

[0166] [Etching Processing Equipment]

[0167] Next, use Figure 9 A summary of the overall structure of the etching process apparatus, including that described in Embodiment 2 of the present invention, will be given. Figure 9 This is a schematic longitudinal sectional view illustrating the structure of an etching processing apparatus according to another embodiment of the present invention.

[0168] In the etching processing apparatus 900 shown in this figure, Figure 1 The difference in the structure of the etching processing apparatus 100 shown in the embodiment is that a plasma source 901, which is connected to the processing chamber 1 via a cylindrical flow path 27, is disposed above the bottom chamber 11, which houses the processing chamber 1 and the wafer stage 3. In this example, the plasma source 901 is connected to the bottom chamber 11 and similarly supplies processing gas to the space inside the quartz chamber 12 that constitutes the vacuum container to form plasma, which is used to clean the inner wall of the vacuum container and generate highly reactive gas using highly reactive particles in the plasma.

[0169] The plasma source 901 has an IR lamp unit 59 sandwiched above the bottom chamber 11, and a cylindrical quartz chamber 12 made of quartz plasma dielectric for forming ICP (inductively coupled plasma) inside. Multiple coils, i.e., ICP coils 20, are wound around the outer wall of the quartz chamber 12 in the vertical direction to supply high-frequency power for forming the plasma and to create a high-frequency electric field.

[0170] The high-frequency power supply 21 is electrically connected to the ICP coil 20 via a matching adapter 22. The frequency of the high-frequency power supply uses a frequency band of tens of MHz, which is 13.56 MHz in this example. A circular plate-shaped top plate 25 is disposed above the upper end of the side wall of the quartz chamber 12. In order to airtightly separate the cylindrical discharge chamber inside the quartz chamber 12 from the atmosphere surrounding the external etching processing apparatus 900, O-rings or other sealing elements are sandwiched between them to connect the two.

[0171] The top plate 25 is connected to multiple gas supply pipes, namely gas supply pipes 56, for supplying processing gas and inert gas through the interior. Below the top plate 25, there is a gas dispersion plate 24 with a circular plate shape and multiple through holes arranged in the vertical direction, and a clustering plate 23 below it. The processing gas and inert gas supplied through the gas supply pipes 56 are dispersed through the through holes of the gas dispersion plate 24 and the clustering plate 23, and are introduced into the quartz chamber 12 from top to bottom.

[0172] Gas and Figure 1Similarly, in the embodiment, the supply flow rate is adjusted by a mass flow controller 50 configured for each gas type. Furthermore, a gas distributor 51 is provided downstream of the mass flow controller, configured to independently adjust the flow rate and composition of the gas supplied to the vicinity of the center of the quartz chamber 12 and the gas supplied to the vicinity of the outer periphery, thereby regulating the distribution of partial pressures of the various gases within the quartz chamber 12. Additionally, in Figure 9 Ar, N2, HF, and O2 are listed as the gases supplied to the container, but other gases may be used as needed.

[0173] Gas introduced into a cylindrical space surrounded by a quartz chamber 12 and a top plate 25 is excited by a high-frequency induced electric field formed by an induced magnetic field, resulting in ionization and dissociation to generate plasma. The induced magnetic field is formed by high-frequency electricity supplied to the ICP coil 20. That is, the aforementioned cylindrical space is a discharge chamber.

[0174] A cylindrical flow path 27 is centrally located in the IR lamp unit 59 below the discharge chamber, communicating with the upper part of the processing chamber 1 further below. Inside this flow path 27 is a slit plate 26, made of a dielectric and permeable material such as quartz, with multiple through-holes formed in the vertical direction; it is a circular plate. Regarding the shape of the through-holes, the planar shape can be rectangular, circular, or elliptical, and is not limited to a slit. The through-holes of the slit plate 26 shield charged particles such as ions and electrons generated in the plasma formed in the discharge chamber, while allowing active species (free radicals) and neutral gas particles to pass through and enter the processing chamber 1 below.

[0175] Furthermore, the processing apparatus of this example can heat the interior of a vacuum container other than the wafer stage 3 exposed to hydrogen fluoride gas, such as the processing chamber. For example, the wall of the bottom chamber 11 can be maintained at a temperature between 40°C and 120°C. This prevents particles and byproducts of gases such as hydrogen fluoride from adsorbing onto the interior wall of the processing chamber 1, and inhibits corrosion inside the chamber.

[0176] [Etching Process]

[0177] use Figure 9 The etching apparatus 900 shown performs the same etching process as in Example 1 on the wafer 2. The etching apparatus 900 is equipped with an ICP plasma source 902, so before the etching process of the wafer 2 begins, oxygen is introduced into the discharge chamber to form oxygen plasma, and the charged particles and reactive particles formed by the oxygen plasma are used to clean the walls inside the processing chamber 1 or the discharge chamber.

[0178] As conditions for this cleaning process, the plasma for cleaning is formed for 300 seconds under the following conditions: an oxygen (O2) supply of 1000 sccm, a pressure of 50 Pa inside the discharge chamber or processing chamber 1, and a high-frequency power of 1500 W supplied to the ICP coil. This process reduces the amount of foreign matter inside the chamber.

[0179] Furthermore, as a condition for step S103 of the etching process, the coolant temperature is set to -40°C, and hydrogen fluoride gas is introduced into the processing chamber via the discharge chamber without using plasma, to etch the monolayer films of silicon oxide and silicon nitride pre-formed on wafer 2. Here, a mixed gas consisting of 600 sccm of hydrogen fluoride and 100 sccm of Ar is used for these etching processes. The pressure inside processing chamber 1 is maintained at 300 Pa, and etching is performed for 120 seconds.

[0180] Furthermore, after the etching process is completed, the processing chamber 1 is vented for 30 seconds, and then the wafer 2 is removed from the processing chamber 1. The thickness and etching rate of the silicon oxide film and the silicon nitride film are then measured. The etching rate of the silicon oxide film is 36 nm / min. In contrast, the etching rate of the silicon nitride film is 0.9 nm / min, resulting in a selectivity ratio of 40 for the etching of the silicon oxide film relative to the silicon nitride film.

[0181] Furthermore, using Figure 2 The etching process shown is for Figure 3 The film structure shown in (a), which consists of a silicon oxide film 103 and a silicon nitride film 102, is subjected to etching. The processing time for step S103 is 60 seconds. Here, no heating is performed after etching, and no obvious residue is visible on the processed surface; it is clean. As a result, it can be seen that... Figure 3 As shown in (b), the silicon oxide film can be selectively etched in a near-rectangular shape.

[0182] Furthermore, as a condition for other processing, the refrigerant temperature was set to -45°C, and single-layer etching of the silicon oxide film and silicon nitride film on wafer 2 was performed. Here, a mixed gas consisting of 500 sccm of hydrogen fluoride and 100 sccm of N2 was used for etching. The pressure inside processing chamber 1 was 300 Pa, and the etching lasted for 60 seconds.

[0183] Furthermore, after 30 seconds of venting following etching, wafer 2 is heated for 50 seconds using IR lamp unit 59. At this time, the temperature of wafer 2 is approximately 250°C, which is the highest. Then, wafer 2 is cooled for 120 seconds. Subsequently, under the same conditions as described above, hydrogen fluoride gas and N2 are supplied, and the etching process and the heating process of wafer 2 based on IR lamp unit 59 are repeated again.

[0184] Next, wafer 2 was moved out of processing chamber 1, and the film thickness and etching rate of each film layer were measured. The results showed that the etching rate of the silicon oxide film was 32 nm / min. In contrast, the etching rate of the silicon nitride film was 0.5 nm / min, and the selectivity ratio of the silicon oxide film to the silicon nitride film was 64.

[0185] Furthermore, using the same conditions, using Figure 2 The etching process shown is for Figure 3 The film structure shown in (a) consisting of a silicon oxide film 103 and a silicon nitride film 102 was etched. The results show that, as Figure 3 As shown in (b), the ends of each film layer are formed into a near-rectangular shape, and the silicon oxide film 103 is selectively etched. Furthermore, by heating the wafer 2 after the etching process and repeatedly performing two etching steps, no residues are visible on the processed surface of the film structure, and a reduction in deposits is observed.

Claims

1. An etching method, a dry etching method, wherein a film structure is etched while a processing gas is supplied to a processing chamber and no plasma is used, wherein the film structure is pre-formed on a wafer disposed in the processing chamber, and the ends of the stacked film layers, in which silicon oxide films are sandwiched between silicon nitride films, form the sidewalls of trenches or holes. The etching method is characterized in that, A gas of hydrogen fluoride is supplied to keep the temperature of the wafer below -30°C and above -60°C, and the silicon oxide film is etched laterally from the end.

2. The etching method according to claim 1, characterized in that, The wafer is etched at a temperature between -35°C and -50°C.

3. The etching method according to claim 1, characterized in that, The wafer is etched and then heated in a vacuum.

4. The etching method according to claim 1, characterized in that, The process involves repeatedly supplying the hydrogen fluoride gas to etch the wafer and then heating the etched wafer in a vacuum.

5. The etching method according to claim 1, characterized in that, An inert gas is also supplied to the hydrogen fluoride gas.

6. The etching method according to claim 3, characterized in that, The post-etching heating is performed using lamp heating.

7. The etching method according to claim 2, characterized in that, The wafer is etched and then heated in a vacuum.

8. The etching method according to claim 2, characterized in that, The process involves repeatedly supplying the hydrogen fluoride gas to etch the wafer and then heating the etched wafer in a vacuum.

9. The etching method according to claim 2, characterized in that, An inert gas is also supplied to the hydrogen fluoride gas.

10. The etching method according to claim 7, characterized in that, The post-etching heating is performed using lamp heating.

11. The etching method according to claim 3, characterized in that, An inert gas is also supplied to the hydrogen fluoride gas.

12. The etching method according to claim 4, characterized in that, The post-etching heating is performed using lamp heating.

13. The etching method according to claim 4, characterized in that, An inert gas is also supplied to the hydrogen fluoride gas.

14. The etching method according to claim 8, characterized in that, The post-etching heating is performed using lamp heating.

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