A method for reducing breakdown leakage current of radiation-resistant strip gate MOSFETs

Abstract

This invention discloses a method for reducing the breakdown leakage current of radiation-hardened strip-gate MOSFETs, belonging to the field of MOSFET fabrication. The method involves providing a substrate and forming an epitaxial layer on its surface; fabricating a hardmask self-aligned layer morphology; fabricating P-well and N+ source contacts; performing low-temperature wet oxidation SiO2 growth; performing photolithography and etching of polysilicon to form the polysilicon gate control terminal; performing photolithography and etching of the P+ body contacts and metal to finally form the MOSFET. This invention addresses the breakdown leakage current problem of radiation-hardened strip-gate MOSFETs by designing and manufacturing a dumbbell pattern for the hardmask self-aligned layer, forming a dumbbell pattern, and performing self-aligned P-well and N+ source contact processes. This achieves omnidirectional encirclement of the N+ source contacts by the P-well, eliminating the breakdown leakage current problem between the source and drain.

Description

Technical Field

[0001] This invention relates to the field of MOSFET fabrication technology, and in particular to a method for reducing the breakdown leakage current of a radiation-resistant strip gate MOSFET. Background Technology

[0002] Radiation-hardened power MOSFET devices, in addition to meeting conventional electrical parameter requirements, must also be able to withstand various ionizing radiations, high-energy particles, and cosmic rays in space over long periods of time. Therefore, the threshold voltage, drain breakdown voltage, and gate breakdown voltage of power MOSFET devices are all affected by such ionizing radiation. Thus, devices used in the aerospace field should have the ability to resist total ionizing dose (TID) and single-event effect (SEE).

[0003] Radiation hardening technology is applicable to the design and fabrication of power MOSFETs for radiation-hardened applications. In space environments, the total dose radiation effect is a significant limitation preventing MOSFET devices from functioning properly. The total dose effect occurs when gamma rays pass through the silicon dioxide dielectric layer of the device's structural region, epitaxial region, and substrate region. This causes electrons within the silicon dioxide dielectric layer to gain energy and, under the influence of an electric field, migrate towards the positive electrode of the silicon dioxide dielectric, especially at the gate oxide. This manifests as a decrease in threshold voltage, or even device leakage, leading to the device becoming uncontrollable by the drive circuit voltage and losing its normal switching function.

[0004] In the fabrication process of MOSFET power devices, a substrate material with low resistivity is required. Epitaxy is then performed on this substrate material to achieve the necessary resistivity and thickness for the MOSFET power device fabrication. For example... Figure 1 As shown, MOSFET power devices using commercially available conventional self-aligned hardmask layer gate oxide technology will experience threshold drift or leakage under irradiation without total dose hardening, failing to meet the radiation resistance requirements of circuit applications. Summary of the Invention

[0005] The purpose of this invention is to provide a method for reducing the breakdown leakage current of radiation-resistant strip gate MOSFETs, so as to solve the problem that existing radiation-resistant strip gate MOSFET power devices are prone to breakdown leakage current during the manufacturing process.

[0006] To address the aforementioned technical problems, this invention provides a method for reducing the breakdown leakage current of a radiation-resistant strip-gate MOSFET, comprising:

[0007] Provide a substrate, and form an epitaxial layer on its surface;

[0008] Create the hardmask self-aligned layer morphology;

[0009] Fabricate the P-well and N+ source contact terminals;

[0010] Low-temperature wet oxygen oxidation SiO2 growth was carried out.

[0011] Photolithography and etching of polycrystalline silicon are performed to form the polycrystalline gate control terminal;

[0012] The P+ body contact and metal are lithographically and etched to ultimately form the MOSFET.

[0013] In one implementation, creating the hardmask self-aligned layer morphology includes:

[0014] The hardmask self-aligned layer is formed in a dumbbell shape according to the pattern of the hardmask self-aligned mask; wherein,

[0015] The hardmask self-alignment layer is made of a stable and reliable material, namely silicon nitride or silicon dioxide.

[0016] In one implementation, fabricating the P-well and N+ source contact includes:

[0017] P-trap photolithography is performed on the hardmask self-aligned layer to implant P-type impurities and then high-temperature annealing is performed to form a dumbbell-shaped P-trap.

[0018] Patterning of the N+ photomask is performed on the hardmask self-alignment layer to form the pattern of the N+ source contact end;

[0019] N-type impurities are injected according to the pattern of the N+ photomask and subjected to high-temperature annealing to form N+ source contact ends; the P-well surrounds the N+ source contact ends in all directions;

[0020] The P-type impurities include B and BF2, and the injection dose is 1E12-5E14 cm⁻¹. -2 The energy is 70-5000 keV;

[0021] The N-type impurities include P and As, and the injection dose is 5E14-1E16 cm⁻¹. -2 The energy is 50-80 keV.

[0022] In one embodiment, low-temperature wet oxygen oxidation SiO2 growth includes:

[0023] First, form a polycrystalline pattern according to the pattern of the polymask;

[0024] Gate oxide SiO2 was grown at a temperature of 800℃-1000℃, with a thickness of 30nm-1000nm.

[0025] In one implementation, performing P+ body contact and metal photolithography and etching to ultimately form a MOSFET includes:

[0026] Based on the pattern of the P+ photomask, form the pattern of the P+ body contact end;

[0027] P-type impurity implantation is performed, followed by high-temperature annealing to form P+ body contact ends.

[0028] Dielectric isolation layer deposition is performed, contact holes and metal deposition photolithography are completed, and the N+ source contact, P+ body contact and polygate control terminal are all connected to form the complete structure of VDMOS power device.

[0029] In one embodiment, the injection dose of the P-type impurity is 5E14-5E15 cm⁻¹. -2 The energy is 50-100 keV.

[0030] In one embodiment, the substrate has high energy density and low resistivity, and is made of silicon or arsenic with a resistivity of 0.002-0.004 Ω·cm.

[0031] The resistivity of the epitaxial layer is 0.3-24 Ω·cm, and the thickness is 3μm-50μm.

[0032] In a method for reducing the breakdown leakage current of a radiation-resistant strip gate MOSFET provided by the present invention, a substrate is provided, and an epitaxial layer is formed on its surface; a hardmask self-aligned layer morphology is fabricated; P-well and N+ source contacts are fabricated; low-temperature wet oxidation SiO2 growth is performed; polysilicon photolithography and etching are performed to form a polysilicon gate control terminal; P+ body contacts and metal photolithography and etching are performed to finally form a MOSFET.

[0033] The present invention has the following beneficial effects:

[0034] (1) To combat the breakdown and leakage problem of radiation strip gate MOSFET, a hardmask self-aligned layer dumbbell pattern design and manufacturing process is carried out to form a dumbbell pattern. The self-aligned P-well and N+ source contact terminal process is carried out to realize that the P-well surrounds the N+ source contact terminal in all directions, eliminating the breakdown and leakage problem between the source and drain.

[0035] (2) The processing technology is simple, highly controllable, and highly operable. Attached Figure Description

[0036] Figure 1This is a schematic diagram of a conventional radiation-resistant strip hardmask self-aligned dielectric layer;

[0037] Figure 2 This is a flowchart illustrating a method for reducing the breakdown leakage current of a radiation-resistant strip gate MOSFET provided by the present invention.

[0038] Figure 3 This is a schematic diagram of a hardmask formed according to the pattern of the hardmask self-aligned dielectric layer photomask;

[0039] Figure 4 This is a schematic diagram of a P-well formed according to the pattern of the P-well mask;

[0040] Figure 5 This is a schematic diagram of the formation of the N+ source contact terminal;

[0041] Figure 6 A schematic diagram of the formation of the polycrystalline gate control pattern;

[0042] Figure 7 This is a schematic diagram of the formation of the P+ body contact end;

[0043] Figure 8 This is a schematic diagram of the formation of a contact hole;

[0044] Figure 9 This is a schematic diagram comparing the source-drain breakdown leakage current of two types of radiation-resistant strip-gate MOSFETs. Detailed Implementation

[0045] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for reducing the breakdown leakage current of a radiation-resistant strip-gate MOSFET according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] This invention provides a method for reducing the breakdown leakage current of a radiation-resistant strip gate MOSFET, the process of which is as follows: Figure 2 As shown, it includes the following steps:

[0047] Step S21: Provide a substrate and form an epitaxial layer on its surface;

[0048] Step S22: Create the pattern of the hardmask photomask to form the hardmask self-aligned dielectric layer morphology;

[0049] Step S23: Fabricate the pattern of the P-well mask to form the P-well morphology;

[0050] Step S24: Fabricate the pattern of the N+ photomask to form the N+ source contact end morphology;

[0051] Step S25: Perform gate oxide oxidation SiO2 growth;

[0052] Step S26: Perform photolithography and etching on polysilicon to form the polysilicon gate control terminal;

[0053] Step S27: Fabricate the P+ body contact and metal control terminal to form a MOSFET device.

[0054] First, a substrate is provided, which has the characteristics of high energy density and low resistivity. The material can be silicon or arsenic. In this embodiment, a silicon substrate is used as an example, with a resistivity of 0.002-0.004 Ω·cm. An epitaxial layer is formed on the surface of the substrate, with a resistivity of 3-24 Ω·cm and a thickness of 3μm-50μm.

[0055] Hardmask lithography is performed according to device requirements. First, based on the pattern of hardmask 1, a dumbbell-shaped design of the hardmask self-aligned dielectric layer is formed, such as... Figure 3 As shown, dimension a equals dimension b;

[0056] The P-well is lithographically formed according to the device requirements. First, the P-well is formed according to the pattern of the P-well photomask 2, such as... Figure 4 As shown, dimension c equals d;

[0057] The injection dose is 1E12-5E14cm -2 P-type impurities such as B and BF2 with energies of 70-5000 KeV are injected and then subjected to high-temperature annealing to form dumbbell-shaped P-wells.

[0058] According to the device requirements, N+ source contact end photolithography is performed. First, the shape of the N+ source contact end is formed according to the pattern of N+ source contact end photomask 3, such as... Figure 5 As shown, dimension e is equal to dimensions c and d;

[0059] The injection dose is 5E14-1E16cm -2 The N-type impurities such as P and As with energies of 50-80 keV are introduced and subjected to high-temperature annealing to form N+ source contact ends.

[0060] To create a polycrystalline control terminal according to device requirements, first form a polycrystalline pattern based on the pattern of the Poly 4 photomask, such as... Figure 6 As shown;

[0061] After growing a gate oxide SiO2 layer at a temperature of 800℃-1000℃ and a thickness of 30nm-1000nm, the photolithography and etching processes of polysilicon are completed simultaneously to form a polysilicon gate control terminal.

[0062] According to the device requirements, the P+ body contact terminal is fabricated. Following the pattern of the P+5 photomask, the P+ body contact terminal pattern is formed, as follows: Figure 7 As shown;

[0063] Injection of P-type impurities such as B and BF2 was performed at a dose of 5E14-5E15 cm⁻¹. -2 The energy is 50-100 keV. After injection, high-temperature annealing is performed to form P+ body contact ends.

[0064] Dielectric isolation layer deposition is performed, contact holes and metal deposition photolithography are completed, and the N+ source contact, P+ body contact and polygate control terminal are all connected to form the complete structure of VDMOS power device.

[0065] The above seven main process steps constitute the fabrication of radiation-resistant strip-gate VDMOS hardened devices. Due to the hardmask self-aligned dielectric layer design of the radiation-resistant strip-gate VDMOS, a dumbbell pattern is formed, followed by a dumbbell-shaped P-well, achieving self-aligned fabrication that fully encompasses the N+ source terminal. By completely covering both sides of the N+ source terminal with the dumbbell-shaped P-well, the inconsistency in the electric field strength curvature radius at the source-drain breakdown leakage terminals is eliminated, ultimately cutting off the current path for source-drain breakdown leakage and reducing leakage current. Figure 9 As shown.

[0066] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for reducing the breakdown leakage current of a radiation-resistant strip-gate MOSFET, characterized in that, include: Provide a substrate, and form an epitaxial layer on its surface; Create the hardmask self-aligned layer morphology; Fabricate the P-well and N+ source contact terminals; Low-temperature wet oxygen oxidation SiO2 growth was carried out. Photolithography and etching of polycrystalline silicon are performed to form the polycrystalline gate control terminal; The P+ body contact and metal photolithography and etching are performed to finally form the MOSFET; Creating the hardmask self-aligned layer topography includes: The hardmask self-aligned layer is formed in a dumbbell shape according to the pattern of the hardmask self-aligned mask; wherein, The hardmask self-alignment layer is made of a stable and reliable material, namely silicon nitride or silicon dioxide. Fabricating the P-well and N+ source contacts includes: P-trap photolithography is performed on the hardmask self-aligned layer to implant P-type impurities and then high-temperature annealing is performed to form a dumbbell-shaped P-trap. Patterning of the N+ photomask is performed on the hardmask self-alignment layer to form the pattern of the N+ source contact end; N-type impurities are injected according to the pattern of the N+ photomask and subjected to high-temperature annealing to form N+ source contact ends; the P-well surrounds the N+ source contact ends in all directions; The P-type impurities include B and BF2, and the injection dose is 1E12-5E14 cm⁻¹. -2 The energy is 70-5000 keV; The N-type impurities include P and As, and the injection dose is 5E14-1E16 cm⁻¹. -2 The energy is 50-80 keV.

2. The method for reducing the breakdown leakage current of a radiation-resistant strip-gate MOSFET as described in claim 1, characterized in that, Low-temperature wet oxygen oxidation SiO2 growth includes: First, form a polycrystalline pattern according to the pattern of the polymask; Gate oxide SiO2 was grown at a temperature of 800℃-1000℃, with a thickness of 30nm-1000nm.

3. The method for reducing the breakdown leakage current of a radiation-resistant strip-gate MOSFET as described in claim 2, characterized in that, The process of P+ body contact lithography and metal etching to ultimately form the MOSFET includes: Based on the pattern of the P+ photomask, form the pattern of the P+ body contact end; P-type impurity implantation is performed, followed by high-temperature annealing to form P+ body contact ends. Dielectric isolation layer deposition is performed, contact holes and metal deposition photolithography are completed, and the N+ source contact, P+ body contact and polygate control terminal are all connected to form the complete structure of VDMOS power device.

4. The method for reducing the breakdown leakage current of a radiation-resistant strip-gate MOSFET as described in claim 3, wherein the implantation dose of the P-type impurity is 5E14-5E15cm⁻¹. -2 The energy is 50-100 keV.

5. The method for reducing the breakdown leakage current of a radiation-resistant strip-gate MOSFET as described in claim 1, characterized in that, The substrate has high energy and low resistivity, and is made of silicon, doped with phosphorus or arsenic, with a resistivity of 0.002-0.004 Ω·cm; The resistivity of the epitaxial layer is 0.3-24 Ω·cm, and the thickness is 3μm-50μm.

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