Chip packaging methods and chips

Abstract

This application discloses a chip packaging method and a chip, relating to the field of packaging technology. The method includes: providing a semiconductor device to be packaged and a first substrate, the first substrate including a first pad; applying a first packaging material to the surface of the first pad to form an adhesive layer, attaching the substrate of the semiconductor device to be packaged to the first pad through the adhesive layer, and performing surface encapsulation treatment on the semiconductor device to be packaged and the first pad; forming a bump structure on the side of the semiconductor device to be packaged away from the substrate; providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip encapsulation treatment on the semiconductor device to be packaged and the second substrate; and performing plastic encapsulation treatment on the semiconductor device to be packaged using a second packaging material. The embodiments of this application aim to improve the heat dissipation efficiency and effect of the chip, thereby increasing the chip's lifespan.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a chip packaging method and a chip. Background Technology

[0002] For high-power chips, their high power consumption leads to increased chip temperature during operation. Current technology typically involves attaching heat sinks to the chip's surface after packaging for heat dissipation. However, due to the low thermal conductivity of the packaging material, most of the heat generated by the chip cannot be conducted to the outside, thus reducing the chip's lifespan and potentially causing it to burn out. Therefore, the heat dissipation effect of existing chip cooling solutions is limited by the packaging material, resulting in significantly reduced heat dissipation efficiency. Summary of the Invention

[0003] This application provides a chip packaging method and a chip, which aims to improve the heat dissipation efficiency and effect of the chip, thereby increasing the chip's lifespan.

[0004] In a first aspect, embodiments of this application provide a chip packaging method, the method comprising:

[0005] A semiconductor device to be packaged and a first substrate are provided, the first substrate including a first pad;

[0006] A first encapsulation material is applied to the surface of the first pad to form an adhesive layer. The substrate of the semiconductor device to be encapsulated is attached to the first pad through the adhesive layer, and the semiconductor device to be encapsulated and the first pad are subjected to surface encapsulation treatment.

[0007] A bump structure is formed on the side of the semiconductor device to be packaged that is away from the substrate;

[0008] A second substrate is provided, the bump structure is attached to the second substrate, and the semiconductor device to be packaged and the second substrate are subjected to flip-chip packaging.

[0009] The semiconductor device to be packaged is plastically encapsulated using a second encapsulation material.

[0010] Secondly, embodiments of this application also provide a chip packaging method, the method comprising:

[0011] A semiconductor device to be packaged is provided, wherein a bump structure is formed on the side of the semiconductor device to be packaged that is away from the substrate;

[0012] A second substrate is provided, the bump structure is attached to the second substrate, and the semiconductor device to be packaged and the second substrate are subjected to flip-chip packaging.

[0013] The semiconductor device to be packaged is plastically encapsulated using a second encapsulation material to enable injection molding of the semiconductor device to be packaged.

[0014] A first substrate is provided, the first substrate including a first pad;

[0015] A first encapsulation material is applied to the surface of the first pad to form an adhesive layer. The substrate of the semiconductor device to be encapsulated is attached to the first pad through the adhesive layer, and the semiconductor device to be encapsulated and the first pad are subjected to surface encapsulation treatment.

[0016] Thirdly, embodiments of this application also provide a chip, the chip comprising:

[0017] Semiconductor devices;

[0018] A first substrate, the first substrate including a first pad, the first pad being connected to the substrate of the semiconductor device via an adhesive layer;

[0019] A bump structure is disposed on the side of the semiconductor device that is away from the substrate;

[0020] The second substrate is connected to the side of the chip facing away from the substrate via the bump structure;

[0021] A filling medium is used to fill the gap between the first substrate and the second substrate and to encapsulate the semiconductor device.

[0022] This application provides a chip packaging method and a chip. The method includes: providing a semiconductor device to be packaged and a first substrate, the first substrate including a first pad; applying a first packaging material to the surface of the first pad to form an adhesive layer, attaching the substrate of the semiconductor device to be packaged to the first pad through the adhesive layer, and performing surface encapsulation treatment on the semiconductor device to be packaged and the first pad; forming a bump structure on the side of the semiconductor device to be packaged away from the substrate; providing a second substrate, attaching the bump structure to the second substrate, and performing flip-chip encapsulation treatment on the semiconductor device to be packaged and the second substrate; and performing plastic encapsulation treatment on the semiconductor device to be packaged using a second packaging material. This avoids the limitation imposed by the low thermal conductivity of the packaging material, enabling the heat generated by the chip to be conducted to the outside from both above and below the chip simultaneously, improving the chip's heat dissipation efficiency and effect, thereby extending the chip's lifespan. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic flowchart of a chip packaging method provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the structure of the first pad provided in an embodiment of this application;

[0026] Figure 3 This is a partial structural diagram of the surface encapsulation in a chip packaging method provided in an embodiment of this application;

[0027] Figure 4 This is a schematic diagram of the protrusion structure provided in one embodiment of this application;

[0028] Figure 5 This is a schematic diagram of a flip-chip packaging scenario in a chip packaging method provided in an embodiment of this application;

[0029] Figure 6 This is a schematic diagram of the structure of a chip provided in one embodiment of this application;

[0030] Figure 7 This is a schematic flowchart of a chip packaging method provided in another embodiment of this application;

[0031] Figure label:

[0032] 100. Chip

[0033] 10. Semiconductor devices;

[0034] 20. First substrate; 21. First pad; 22. Adhesive layer;

[0035] 30. Bump structure; 31. Bump metal layer; 32. Solder ball;

[0036] 40. Second substrate; 41. Second pad;

[0037] 50. Filling medium. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0040] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0041] It should also be understood that the term "and / or" as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0042] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0043] Chip packaging technology is a process that encapsulates memory chips to prevent them from contacting the outside world and causing damage. Impurities and harmful gases in the air, even water vapor, can corrode the delicate circuitry on the chip, leading to a decline in electrical performance. Different packaging technologies vary greatly in their manufacturing processes and procedures, and the packaging process plays a crucial role in ensuring the optimal performance of the memory chip.

[0044] Existing packaging technologies can generally be divided into through-hole packaging and surface mount packaging. Since the chip temperature rises during operation, in existing technologies, heat sinks are usually attached to the surface of the chip after packaging for heat dissipation. However, since the thermal conductivity of the packaging material is generally very low, it cannot effectively conduct the heat generated by the chip to the outside for heat dissipation. Therefore, the heat dissipation effect is limited by the packaging material, which greatly reduces the heat dissipation effect.

[0045] The embodiments of this application provide a chip packaging method and a chip that can avoid being limited by the low thermal conductivity of the packaging material. It can conduct the heat emitted by the chip from both the top and bottom of the chip to the outside simultaneously, thereby improving the heat dissipation efficiency and effect of the chip and thus extending the chip's lifespan.

[0046] Please see Figure 1 , Figure 1 This is a schematic flowchart of a chip packaging method provided in an embodiment of this application.

[0047] like Figure 1 As shown, the chip packaging method specifically includes steps S101-S105.

[0048] S101. Provide a semiconductor device to be packaged and a first substrate, wherein the first substrate includes a first pad.

[0049] Among them, such as Figure 2 As shown, the semiconductor device 10 to be packaged is an unpackaged die, which can be an unpackaged wafer or a die. The wafer refers to the silicon wafer used to manufacture silicon semiconductor integrated circuits. Various circuit element structures can be processed on the silicon wafer to become integrated circuit products with specific electrical functions.

[0050] Since the material of the semiconductor device 10 to be packaged is silicon, and the thermal conductivity of silicon is 118 W / mk, which is above 100 W / mk, the semiconductor device 10 to be packaged can conduct heat very well.

[0051] Among them, such as Figure 2 As shown, the first substrate 20 can be a ceramic or a printed circuit board (PCB). The first substrate 20 includes a first pad 21, which can be a metal pad, specifically a copper pad or other metal pad with good thermal conductivity, used for heat dissipation of the semiconductor device 10 to be packaged.

[0052] In some embodiments, a first pad 21 is formed on the surface of the first substrate 20.

[0053] Specifically, the surface of the first substrate 20 is configured to correspond to the substrate of the semiconductor device 10 to be packaged, and the first pad 21 can be directly soldered onto the first substrate 20. The function of the first pad 21 is heat dissipation. When the chip is working, it generates heat. At this time, the heat can be quickly radiated to the entire first substrate 20 through the first pad 21, increasing the heat dissipation area and accelerating the heat dissipation speed.

[0054] For example, the first pad 21 can be soldered at any position on the first substrate 20. Preferably, the first pad 21 can be soldered at the center position of the first substrate 20, such as... Figure 2As shown, the first substrate 20 is in a zigzag shape, and the first pad 21 is disposed at the center of the first substrate 20. Thus, a better heat dissipation effect can be achieved.

[0055] S102. Add a first encapsulation material to the surface of the first pad to form an adhesive layer, bond the substrate of the semiconductor device to be encapsulated to the first pad through the adhesive layer, and perform a surface encapsulation process on the semiconductor device to be encapsulated and the first pad.

[0056] Among them, the adhesive layer 22 can be formed by adding a first encapsulation material to the surface of the first pad 21 and is used to bond the substrate of the semiconductor device 10 to be encapsulated to the first pad 21. The first encapsulation material may include a welding material for welding the substrate of the semiconductor device 10 to be encapsulated to the first pad 21. The substrate of the semiconductor device 10 to be encapsulated can be made of SiC, Si or GaAs.

[0057] Specifically, the thermal conductivity of the welding material is 50 W / m·K. Therefore, the welding material can also conduct heat well and the adhesive layer 22 is formed by the welding material. That is, the semiconductor device 10 to be encapsulated can conduct most of the heat generated by it to the outside through the adhesive layer 22, thereby avoiding being restricted by the low thermal conductivity of the encapsulation material and enabling the heat generated by the chip to be quickly conducted to the outside from above the chip.

[0058] Specifically, the surface encapsulation includes a Quad Flat No-lead Package (QFN) or a Dual Flat No-lead Package (DFN) encapsulation. Among them, the pins of the DFN encapsulation are distributed on both sides of the package body and the overall appearance is rectangular, while the pins of the QFN encapsulation are distributed on the four sides of the package body and the overall appearance is square. The QFN encapsulation has the advantages of small size, light weight, good heat dissipation, good electrical performance, good reliability and high cost performance. Therefore, the QFN encapsulation is generally selected.

[0059] In some embodiments, print the first encapsulation material on the first pad 21 to form the adhesive layer 22, and place the substrate of the semiconductor device 10 to be encapsulated on the adhesive layer 22; weld the substrate of the semiconductor device 10 to be encapsulated to the first pad 21 so that the substrate of the semiconductor device 10 to be encapsulated is encapsulated on the first pad 21. Thus, the semiconductor device 10 to be encapsulated can conduct most of the heat generated by it to the outside through the adhesive layer 22, thereby avoiding being restricted by the low thermal conductivity of the encapsulation material and enabling the heat generated by the chip to be quickly conducted to the outside from above the chip.

[0060] For example, since the thickness of wafers from typical wafer fabs is approximately 550–725 micrometers, and the total thickness of a conventional QFN package is also 550–750 micrometers, the wafer cannot be placed inside without thinning treatment. Therefore, the wafers from the wafer fab need to undergo a wafer thinning process to obtain the semiconductor device 10 to be packaged, which allows for convenient packaging of the semiconductor device 10 within a limited space. Specifically, chemical mechanical polishing or laser cutting can be used to thin the wafer substrate.

[0061] Generally, N independent dies can be made on a single wafer. Before packaging, the wafer can be diced to separate the dies one by one, and then each die can be bonded and packaged separately. Alternatively, the wafer can be packaged before packaging, with a protective layer bonded to the top or bottom of the wafer, then the circuitry can be connected, and the wafer can be cut into individual chips, i.e., wafer-level packaging.

[0062] The separated die does not yet have leads, so it needs to be placed on a metal carrier, which has leads. After the metal carrier is connected by silver paste or adhesive film, it awaits the next step of wire bonding.

[0063] like Figure 3 As shown, the first packaging material is then printed on the first pad 21 to form an adhesive layer 22, and the substrate of the semiconductor device 10 to be packaged is placed on the adhesive layer 22 so that the substrate of the semiconductor device 10 to be packaged is attached to the adhesive layer 22. Then the substrate of the semiconductor device 10 to be packaged is soldered to the first pad 21 so that the substrate of the semiconductor device 10 to be packaged is connected to the first pad 21, that is, the substrate of the semiconductor device 10 to be packaged is packaged on the first pad 21.

[0064] Specifically, soldering the substrate of the semiconductor device 10 to be packaged onto the first pad 21 is essentially a wire bonding process for the semiconductor device 10 to be packaged, connecting the semiconductor device 10 to the pins of the first pad 21. For example, automated wire bonding equipment can be used to connect the functional pads of the semiconductor device 10 to the pins of the first pad 21 using wire bonding, connecting the chip's designed functions to the external circuit board via frame pins, thereby ensuring that the product can function normally after being powered on.

[0065] S103, A bump structure 30 is formed on the side of the semiconductor device to be packaged that is away from the substrate.

[0066] Among them, such as Figure 4 As shown, the bump structure 30 includes a bump metal layer 31 and a plurality of bumps located on the bump metal layer 31. The bump metal layer 31 can be a Cu / Ni composite layer or a Ti / Cu composite layer.

[0067] Specifically, a polybenzoxazole (PBO) layer can be formed on the side of the semiconductor device 10 to be packaged that is away from the substrate, and at least a portion of the openings can be formed in the PBO layer. A first metal layer is deposited on the surface of the PBO layer and in the openings using physical vapor deposition (PVD), and a photoresist layer is formed on the surface of the first metal layer. An opening is made again in the photoresist layer at the corresponding position through photolithography processes such as exposure and development, and a second metal layer is deposited at the opening. The first metal layer and the second metal layer together serve as a bump metal layer 31. Then, multiple bumps are electroplated on the bump metal layer 31, thereby forming a bump structure 30 on the side of the semiconductor device 10 to be packaged that is away from the substrate.

[0068] For example, lead-free solder joints can be fabricated at the input / output (I / O) terminals of an integrated circuit chip using planar processes.

[0069] S104. Provide a second substrate, attach the bump structure to the second substrate, and perform flip-chip packaging on the semiconductor device to be packaged and the second substrate.

[0070] The second substrate 40 can be ceramic or a printed circuit board. The flip package includes flip-chip technology or flip chip ball grid array (FC-BGA) packaging.

[0071] Flip-Chip packaging involves placing the chip with its functional area facing down, back to the substrate, and interconnecting it with a second substrate 40 via bumps. This is the opposite of traditional packaging where the functional area faces up. Flip-Chip packaging offers advantages such as small size, thinness, light weight, higher density, better RF performance, and stronger heat dissipation.

[0072] refer to Figure 5 In some embodiments, a second pad 41 corresponding to the bump structure 30 is formed on the surface of the second substrate 40; the bump structure 30 and the corresponding second pad 41 are aligned and mounted; the bump structure 30 is inverted on the second substrate 40 and soldered to the corresponding second pad 41, so that the bump structure 30 forms a solder ball 32, and is connected to the second substrate 40 through the solder ball 32. This allows the semiconductor device 10 to conduct most of its heat to the outside through the second substrate 40, avoiding the limitation of low thermal conductivity of the packaging material. It enables the heat generated by the chip to be conducted to the outside from both above and below the chip, improving the chip's heat dissipation efficiency and effect, thereby extending the chip's lifespan.

[0073] The second pad 41 can be a metal pad, specifically a copper pad or other metal pad with good thermal conductivity, used to dissipate heat from the semiconductor device 10 to be packaged.

[0074] Specifically, a second pad 41 corresponding to the bump structure 30 is formed on the surface of the second substrate 40. The second pad 41 can be directly soldered onto the second substrate 40. The function of the second pad 41 is heat dissipation. When the chip is working, it generates heat. At this time, the heat can be quickly radiated to the entire second substrate 40 through the second pad 41, increasing the heat dissipation area and accelerating the heat dissipation speed.

[0075] For example, such as Figure 4 and Figure 5 As shown, the bumps on the bump structure 30 are aligned and mounted with the second pads 41 on the second substrate 40. Then, the semiconductor device 10 to be packaged is inverted on the second substrate 40, so that the bump structure 30 and the second substrate 40 are facing each other. Finally, a solder reflow process is used to form solder balls 32 between the side of the semiconductor device 10 facing away from the substrate and the second substrate 40. Specifically, the bumps can be rounded into solder balls 32 by removing the photoresist layer, removing excess first metal layer on the surface of the PBO layer by wet etching, and then performing a reflow process.

[0076] S105. The semiconductor device to be packaged is plastically packaged using a second packaging material.

[0077] The second encapsulation material can be a plastic encapsulation material, and the semiconductor device 10 to be encapsulated is plastic encapsulated using the plastic encapsulation material to fill the gap between the first substrate 20 and the second substrate 40.

[0078] For example, the plastic encapsulation can be epoxy molding compound (EMC) encapsulation. EMC is a thermosetting plastic, a common encapsulation material for semiconductor packaging. Its main components include fillers, epoxy resin, curing agents, coupling agents, flame retardants, release agents, and modifying additives. The filler content is the highest, as it can improve the parameters and properties of the epoxy resin, such as reducing the coefficient of thermal expansion, increasing thermal conductivity, and increasing the elastic modulus.

[0079] In some embodiments, the thermal conductivity of the first encapsulation material is greater than that of the second encapsulation material.

[0080] The thermal conductivity of the molding compound is 50 W / mK, while the secondary encapsulation material is a material with low thermal conductivity, such as the molding compound itself. Current encapsulation technologies typically involve fixing the chip to a heat-dissipating chip carrier. While this allows for heat dissipation from the side of the chip that is in contact with the carrier, the side facing away from the carrier is encapsulated by the molding compound. This restricts heat dissipation on the opposite side, significantly reducing its effectiveness and resulting in low heat dissipation efficiency.

[0081] Since the thermal conductivity of the packaging material is very low, the problem of low heat dissipation effect and low heat dissipation efficiency in the existing packaging method can be solved by replacing the packaging material with a material with a higher thermal conductivity. That is, by adding the first packaging material to the surface of the first pad 21 to form an adhesive layer 22, and using the first substrate 20 and the second substrate 40, the heat generated by the chip is simultaneously conducted to the outside from above the chip (i.e., through the first substrate 20) and below the chip (i.e., through the second substrate 40), thereby improving the heat dissipation efficiency and effect of the chip and thus extending the chip's lifespan.

[0082] In some embodiments, the semiconductor device 10 to be packaged is injection molded using a second packaging material to fill the gap between the first substrate 20 and the second substrate 40; the injection-molded semiconductor device 10 is then cured to allow the semiconductor device 10 to be packaged to be injection molded.

[0083] Specifically, such as Figure 6 As shown, the injection molding process of the semiconductor device 10 to be packaged using the second encapsulation material specifically includes: filling the gap between the first substrate 20 and the second substrate 40 with bottom filler adhesive, that is, applying the filler adhesive to the edge of the assembled device, using the "capillary effect" of the liquid to allow the adhesive to penetrate and fill the bottom of the semiconductor device 10 to be packaged, and then heating to cure the semiconductor device 10 to be packaged after injection molding, so that the semiconductor device 10 to be packaged is injection molded, that is, the filler adhesive, the semiconductor device 10 to be packaged, the first substrate 20 and the second substrate 40 are integrated, and finally the electrical, thermal and mechanical connection between the chip and the first substrate 20 and the second substrate 40 is achieved, thereby obtaining the packaged semiconductor device 10, that is, the chip 100.

[0084] The chip packaging method provided in the above embodiment (i.e., steps S101-S105) first performs surface packaging on the semiconductor device 10 to be packaged, and then performs flip-chip packaging.

[0085] Please see Figure 7 , Figure 7 This is a schematic flowchart of a chip packaging method provided in another embodiment of this application.

[0086] like Figure 7 As shown, the chip packaging method specifically includes steps S201-S205.

[0087] S201. A semiconductor device to be packaged is provided, and a bump structure is formed on the side of the semiconductor device to be packaged away from the substrate.

[0088] S202. Provide a second substrate, attach the bump structure to the second substrate, and perform flip-chip packaging on the semiconductor device to be packaged and the second substrate.

[0089] S203. The semiconductor device to be packaged is plastically packaged using a second packaging material to enable injection molding of the semiconductor device to be packaged.

[0090] S204. A first substrate is provided, the first substrate including a first pad.

[0091] S205. Apply a first encapsulation material to the surface of the first pad to form an adhesive layer, attach the semiconductor device substrate to be encapsulated to the first pad through the adhesive layer, and perform surface encapsulation treatment on the semiconductor device to be encapsulated and the first pad.

[0092] The chip packaging method provided in this embodiment (i.e., steps S201-S205) involves first performing flip-chip packaging on the semiconductor device 10 to be packaged, and then performing surface-mount packaging. This application provides two chip packaging methods (i.e., steps S101-S105 and steps S201-S205), with different packaging steps but the same implementation details.

[0093] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of a chip provided in one embodiment of this application. Specifically, it can be obtained by packaging the semiconductor device 10 to be packaged using the chip packaging method described above. The heat emitted by the chip 100 can be conducted to the outside from both above and below the chip 100, thereby improving the heat dissipation efficiency and effect of the chip 100, and thus improving the service life of the chip 100.

[0094] The chip 100 includes a semiconductor device 10, a first substrate 20, a bump structure 30, a second substrate 40, and a filling medium 50. The first substrate 20 includes a first pad 21, which is connected to the substrate of the semiconductor device 10 via an adhesive layer 22. The bump structure 30 is disposed on the side of the semiconductor device 10 facing away from the substrate. The second substrate 40 is connected to the side of the semiconductor device 10 facing away from the substrate via the bump structure 30. The filling medium 50 is used to fill the gap between the first substrate 20 and the second substrate 40 and to encapsulate the semiconductor device 10.

[0095] The semiconductor device 10 can be a packaged wafer or die. Both the first substrate 20 and the second substrate 40 can be ceramic or printed circuit boards. The first substrate 20 includes a first pad 21, which can be a metal pad, specifically a copper pad or other metal pad with good thermal conductivity, used to dissipate heat from the packaged semiconductor device 10.

[0096] Specifically, the adhesive layer 22 can be formed by applying a first encapsulation material to the surface of the first pad 21, for attaching the substrate of the semiconductor device 10 to be encapsulated to the first pad 21. The first encapsulation material may include a soldering material for soldering the substrate of the semiconductor device 10 to be encapsulated onto the first pad 21.

[0097] The filling medium 50 can be obtained by plastic encapsulating the semiconductor device 10 using a second encapsulation material and then injection molding it, and is used to fill the gap between the first substrate 20 and the second substrate 40. The second encapsulation material can be a molding compound or the like.

[0098] In some embodiments, the thermal conductivity of the first encapsulation material is greater than that of the second encapsulation material.

[0099] The thermal conductivity of the molding compound is 50 W / mK, while the secondary encapsulation material is a material with low thermal conductivity, such as the molding compound itself. Current encapsulation technologies typically fix the chip 100 onto a corresponding heat-dissipating chip carrier. While this allows heat dissipation from the side of the chip 100 that is in contact with the heat-dissipating chip carrier, the side of the chip 100 facing away from the heat-dissipating chip carrier is encapsulated by the molding compound. Therefore, the heat dissipation effect is limited by the encapsulation material, resulting in a significantly reduced heat dissipation efficiency.

[0100] Since the thermal conductivity of the packaging material is very low, the problem of low heat dissipation effect and low heat dissipation efficiency in the existing packaging method can be solved by replacing the packaging material with a material with a higher thermal conductivity. That is, by adding the first packaging material to the surface of the first pad 21 to form an adhesive layer 22, and using the first substrate 20 and the second substrate 40, the heat generated by the chip 100 is simultaneously conducted to the outside from above the chip 100 (i.e., through the first substrate 20) and below the chip 100 (i.e., through the second substrate 40), improving the heat dissipation efficiency and effect of the chip 100, thereby increasing the service life of the chip 100.

[0101] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0102] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. It should be noted that, herein, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0103] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The above descriptions are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging method, characterized in that, The method includes: A semiconductor device to be packaged and a first substrate are provided, the first substrate including a first pad; A first encapsulation material is applied to the surface of the first pad to form an adhesive layer. The substrate of the semiconductor device to be encapsulated is attached to the first pad through the adhesive layer, and the semiconductor device to be encapsulated and the first pad are subjected to surface encapsulation treatment. A bump structure is formed on the side of the semiconductor device to be packaged that is away from the substrate; A second substrate is provided, the bump structure is attached to the second substrate, and the semiconductor device to be packaged and the second substrate are subjected to flip-chip packaging. The semiconductor device to be packaged is plastically encapsulated using a second encapsulation material. The step of applying a first encapsulation material to the surface of the first pad to form an adhesive layer, attaching the substrate of the semiconductor device to be encapsulated to the first pad through the adhesive layer, and performing surface encapsulation processing on the semiconductor device to be encapsulated and the first pad includes: The first packaging material is printed on the first pad to form an adhesive layer, and the substrate of the semiconductor device to be packaged is placed on the adhesive layer. The first packaging material includes soldering material. The substrate of the semiconductor device to be packaged is soldered onto the first pad, so that the substrate of the semiconductor device to be packaged is packaged on the first pad.

2. The method according to claim 1, characterized in that, The thermal conductivity of the first packaging material is greater than that of the second packaging material.

3. The method according to claim 1, characterized in that, The surface-mount package includes a QFN package or a DFN package; the flip-chip package includes a Flip-Chip package or an FC-BGA package.

4. The method according to claim 1, characterized in that, The step of attaching the bump structure to the second substrate and performing flip-chip packaging of the semiconductor device to be packaged and the second substrate includes: A second pad corresponding to the bump structure is formed on the surface of the second substrate; The bump structure is aligned with the corresponding second pad and then patched. The semiconductor device to be packaged is inverted on the second substrate, and the bump structure is soldered to the corresponding second pad so that the bump structure forms a solder ball, and is connected to the second substrate through the solder ball.

5. The method according to claim 1, characterized in that, The plastic encapsulation process of the semiconductor device to be encapsulated using a second encapsulation material includes: The semiconductor device to be packaged is injection molded using the second packaging material to fill the gap between the first substrate and the second substrate; The semiconductor device to be packaged is cured after injection molding to allow the semiconductor device to be packaged to be injection molded.

6. The method according to any one of claims 1-5, characterized in that, The first packaging material includes welding material, and the second packaging material includes molding material.

7. The method according to any one of claims 1-5, characterized in that, The first substrate and the second substrate are ceramic or printed circuit boards.

8. A chip packaging method, characterized in that, The method includes: A semiconductor device to be packaged is provided, wherein a bump structure is formed on the side of the semiconductor device to be packaged that is away from the substrate; A second substrate is provided, the bump structure is attached to the second substrate, and the semiconductor device to be packaged and the second substrate are subjected to flip-chip packaging. The semiconductor device to be packaged is plastically encapsulated using a second encapsulation material to enable injection molding of the semiconductor device to be packaged. A first substrate is provided, the first substrate including a first pad; A first encapsulation material is applied to the surface of the first pad to form an adhesive layer. The substrate of the semiconductor device to be encapsulated is attached to the first pad through the adhesive layer, and the semiconductor device to be encapsulated and the first pad are subjected to surface encapsulation treatment. The step of applying a first encapsulation material to the surface of the first pad to form an adhesive layer, attaching the substrate of the semiconductor device to be encapsulated to the first pad through the adhesive layer, and performing surface encapsulation processing on the semiconductor device to be encapsulated and the first pad includes: The first packaging material is printed on the first pad to form an adhesive layer, and the substrate of the semiconductor device to be packaged is placed on the adhesive layer. The first packaging material includes soldering material. The substrate of the semiconductor device to be packaged is soldered onto the first pad, so that the substrate of the semiconductor device to be packaged is packaged on the first pad.

9. A chip manufactured by the chip packaging method according to any one of claims 1-8, characterized in that, The chip includes: Semiconductor devices; A first substrate, the first substrate including a first pad, the first pad being connected to the substrate of the semiconductor device via an adhesive layer; A bump structure is disposed on the side of the semiconductor device that is away from the substrate; The second substrate is connected to the side of the semiconductor device away from the substrate via the bump structure; A filling medium is used to fill the gap between the first substrate and the second substrate and to encapsulate the semiconductor device.

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